JP2008278132A - Power interruption time detection device, broadcasting recording device and hdd recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power interruption time detection device for detecting a power interruption time with simple configuration. <P>SOLUTION: An HDD recorder is provided with: a main CPU 11; a sub-CPU 12; an RAM 18; a power source circuit 13 for generating a DC voltage from a power to be supplied from a commercial power source; a capacitor C1 functioning as a preliminary power source; and a power interruption detection circuit 142 for outputting a power interruption signal showing whether or not it is under power interruption. The RAM 18 is provided with a converted value storage part 181 for making the voltage value of the capacitor C1 correspond to a power interruption time and prestoring the voltage value of the capacitor C1. The sub-CPU 12 is provided with a voltage detection part 122 for detecting the voltage value of the capacitor C1 in a timing when the power interruption stops. The main CPU 11 is provided with a time calculation part 111 for calculating the power interruption time by reading a power interruption time corresponding to the detected voltage value from the converted value storage part 181 and a time display part 112 for displaying the calculated power interruption time on a display 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a power failure time detection device that detects a power failure time during which power supplied from a commercial power supply is stopped, and a monitor that is communicably connected to the monitor, receives a television broadcast, and receives the received video. The present invention relates to a broadcast recording apparatus that stores information in a recording medium. In particular, the present invention relates to an HDD recorder that is communicably connected to a monitor, receives a television broadcast, and stores received video information in an HDD.

  2. Description of the Related Art Conventionally, a broadcast recording apparatus including a main CPU and a sub CPU, such as an HDD recorder, is known in which the sub CPU controls power supply to the main CPU and peripheral devices.

For example, a DVD recorder in which a main microcomputer transmits power control data indicating a power supply control method to a sub-microcomputer by communication, and the sub-microcomputer controls power supply by a method indicated by the power control data transmitted from the main microcomputer Has been proposed (see Patent Document 1). According to this DVD recorder, the power control method by the sub-microcomputer can be changed.
JP 2007-41850 A

  On the other hand, in a HDD recorder or the like, if a power failure occurs during recording, recording is not performed during the power failure period, so the user needs to know the power failure time. However, the DVD recorder does not disclose a power supply control method during a power failure.

  The present invention has been made in view of the above problems, and an object thereof is to provide a power failure time detection apparatus and an HDD recorder that can detect a power failure time with a simple configuration.

  In order to achieve the above object, an HDD recorder according to claim 1 is an HDD recorder that is communicably connected to a monitor, receives a television broadcast, and stores the received video information in the HDD. A main CPU that controls the operation of the entire HDD recorder, a sub CPU that controls the operation during a power failure, a power supply circuit that generates a DC voltage of a predetermined magnitude set in advance from power supplied from a commercial power supply, The voltage side terminal is grounded, the DC voltage supplied from the power supply circuit is applied to the high voltage side terminal, the capacitor charged by the DC voltage and functioning as a standby power supply, and the DC voltage from the power supply circuit are input A power failure detection circuit for detecting a power failure and outputting a power failure signal indicating whether or not a power failure is present, and the voltage at the high-voltage side terminal of the capacitor Conversion value storage means for storing in advance in association with a power failure time, and the sub-CPU, based on a power failure signal from the power failure detection circuit, at the timing when the power failure is completed, Voltage calculating means for detecting a voltage value, and the main CPU calculates a power failure time by reading out the power failure time corresponding to the voltage value detected by the voltage detection means from the converted value storage means; and Time display means for displaying on the monitor the power failure time obtained by the time calculation means, wherein the capacitor is an electric double layer capacitor having a capacity of 0.1 F or more, and the power failure detection circuit Includes a transistor that is turned off when the emitter is grounded and a power failure occurs, and the collector voltage of the transistor is connected to the power failure signal. It is characterized in that to the output.

  The power failure time detection device according to claim 2 is a power failure time detection device that detects a power failure time that is a period in which the power supplied from the commercial power source is stopped, and is preset from the power supplied from the commercial power source. A power supply circuit that generates a DC voltage of a predetermined magnitude, a low voltage side terminal is grounded, a DC voltage supplied from the power supply circuit is applied to the high voltage side terminal, and the standby voltage is charged by the DC voltage. Capacitor that functions as a power failure detection circuit that receives a DC voltage from the power supply circuit, detects a power failure, and outputs a power failure signal that indicates whether a power failure occurs, and the power failure detection circuit Based on the power failure signal from the voltage detection means for detecting the voltage value of the high-voltage side terminal of the capacitor at the timing when the power failure ends, and the voltage value detected by the voltage detection means It is characterized by and a time calculation means for calculating a power failure time Zui.

  A power failure time detection device according to claim 3 is the power failure time detection device according to claim 2, wherein the capacitor is an electric double layer capacitor.

  A power failure time detection device according to claim 4 is the power failure time detection device according to claim 2 or claim 3, wherein the capacitor has a capacity of 0.1 F or more.

  The power failure time detection device according to claim 5 is the power failure time detection device according to any one of claims 2 to 4, wherein the power failure detection circuit is in a state where the emitter is grounded and a power failure occurs. A transistor which is in an OFF state is provided, and the collector voltage of the transistor is output as a power failure signal.

  The broadcast recording apparatus according to claim 6 is a broadcast recording apparatus that is communicably connected to a monitor, receives a television broadcast, and stores the received video information in a recording medium. The broadcast recording apparatus as a whole A main CPU that controls the operation of the power supply, a sub CPU that controls the operation at the time of a power failure, a power supply circuit that generates a preset DC voltage from power supplied from a commercial power supply, and a low-voltage side terminal Is grounded, a DC voltage supplied from the power supply circuit is applied to the high-voltage side terminal, a capacitor that is charged by the DC voltage and functions as a standby power supply, and the DC voltage from the power supply circuit is input, and a power failure occurs A power failure detection circuit that outputs a power failure signal indicating whether or not a power failure is occurring, and a voltage value of the high-voltage side terminal of the capacitor in association with a power failure time in advance And a converted value storage means for storing the voltage detection means for detecting the voltage value of the high-voltage side terminal of the capacitor at the timing when the power failure is completed based on the power failure signal from the power failure detection circuit. And the main CPU obtains a power outage time by reading out the power outage time corresponding to the voltage value detected by the voltage detection unit from the converted value storage unit, and is obtained by the time calculation unit. And a time display means for displaying a power failure time on the monitor.

  According to the HDD recorder of the first aspect, the power supply circuit generates a DC voltage having a predetermined magnitude from the power supplied from the commercial power supply, and the low voltage side terminal is grounded. A DC voltage supplied from the power supply circuit is applied to the voltage side terminal. The capacitor is charged with a DC voltage and functions as a standby power source. Further, a power failure detection circuit to which a DC voltage is input from the power supply circuit detects that a power failure has occurred, and outputs a power failure signal indicating whether or not a power failure has occurred. Further, in the sub CPU that controls the operation at the time of the power failure, the voltage value of the high-voltage side terminal of the capacitor is detected at the timing when the power failure is completed based on the power failure signal from the power failure detection circuit, and is detected by the main CPU. Since the power failure time is obtained based on the voltage value and the obtained power failure time is displayed on the monitor, an HDD recorder capable of detecting the power failure time with a simple configuration can be realized.

  That is, the voltage value of the high voltage side terminal of the capacitor that functions as a standby power supply is detected at the timing when the power failure ends (= timing when the power is restored), and the power failure time is obtained based on the detected voltage value. Since the power failure time can be obtained using a capacitor that functions as a standby power supply, the power failure time can be detected with a simple configuration.

  In addition, the sub CPU that controls the operation at the time of power failure detects the time of power failure because the voltage value of the high-voltage side terminal of the capacitor is detected at the timing when the power failure ends based on the power failure signal from the power failure detection circuit. Therefore, since the power consumed at the time of a power failure can be suppressed, an HDD recorder that can detect a power failure time with a simple configuration can be realized.

  Furthermore, since the capacitor is an electric double layer capacitor, the power failure time can be detected with a simpler configuration.

  In addition, since the capacity of the capacitor is 0.1 F or more, a power failure time of approximately 24 hours or more can be detected, so that the power failure time can be detected with a simple configuration.

  Also, the power failure detection circuit includes a transistor that is turned off when the emitter is grounded and a power failure occurs, and the collector voltage of this transistor is output as a power failure signal, thus realizing a power failure detection circuit with a simple configuration. Therefore, the power failure time can be detected with a simpler configuration.

  According to the power failure time detection device according to claim 2, the power source circuit generates a DC voltage having a predetermined magnitude from the power supplied from the commercial power source, and the low voltage side terminal is grounded. The DC voltage supplied from the power supply circuit is applied to the high voltage side terminal. The capacitor is charged with a DC voltage and functions as a standby power source. Further, a power failure detection circuit to which a DC voltage is input from the power supply circuit detects that a power failure has occurred, and outputs a power failure signal indicating whether or not a power failure has occurred. Furthermore, based on the power failure signal from the power failure detection circuit, the voltage value of the high-voltage side terminal of the capacitor is detected at the timing when the power failure is completed, and the power failure time is obtained based on the detected voltage value, so a simple configuration Can detect the power failure time.

  That is, the voltage value of the high voltage side terminal of the capacitor that functions as a standby power supply is detected at the timing when the power failure ends (= timing when the power is restored), and the power failure time is obtained based on the detected voltage value. Since the power failure time can be obtained using a capacitor that functions as a standby power supply, the power failure time can be detected with a simple configuration.

  According to the power failure time detection device of the third aspect, since the capacitor is an electric double layer capacitor, the power failure time can be detected with a simpler configuration.

  According to the power failure time detection device according to claim 4, since the capacity of the capacitor is 0.1 F or more, a power failure time of approximately 24 hours or more can be detected, so the power failure time is detected with a simple configuration. be able to.

  According to the power failure time detection apparatus of claim 5, the power failure detection circuit includes a transistor that is turned off when the emitter is grounded and the power failure occurs, and the collector voltage of the transistor is output as a power failure signal. Therefore, since the power failure detection circuit can be realized with a simple configuration, the power failure time can be detected with a simpler configuration.

  According to the broadcast recording apparatus of the sixth aspect, the power supply circuit generates a DC voltage having a predetermined magnitude set in advance from the power supplied from the commercial power supply, and the low-voltage side terminal of the capacitor is grounded. A DC voltage supplied from the power supply circuit is applied to the high voltage side terminal. The capacitor is charged with a DC voltage and functions as a standby power source. Further, a power failure detection circuit to which a DC voltage is input from the power supply circuit detects that a power failure has occurred, and outputs a power failure signal indicating whether or not a power failure has occurred. Further, in the sub CPU that controls the operation at the time of the power failure, the voltage value of the high-voltage side terminal of the capacitor is detected at the timing when the power failure is completed based on the power failure signal from the power failure detection circuit, and is detected by the main CPU. Since the power failure time is obtained based on the voltage value and the obtained power failure time is displayed on the monitor, a broadcast recording apparatus capable of detecting the power failure time with a simple configuration can be realized.

  That is, in the sub CPU that controls the operation at the time of a power failure, the voltage value of the high-voltage side terminal of the capacitor is detected at the timing when the power failure is finished (= timing when power is restored) based on the power failure signal from the power failure detection circuit. Therefore, since the power consumed at the time of a power failure can be suppressed in order to detect the power failure time, a broadcast recording device that can detect the power failure time with a simple configuration can be realized.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of an HDD recorder according to the present invention. The HDD recorder 1 (corresponding to a broadcast recording device) is connected to the output device 2 so as to be communicable.

  The HDD recorder 1 receives an operation input from a user via a remote controller (= Remote controller: hereinafter referred to as “remote controller”), and receives and receives a television broadcast based on the received operation input. Stores program information. The HDD recorder 1 reads and reproduces stored program information and outputs video and audio to the output device 2.

  The output device 2 includes a display 21 and a speaker 22, and outputs audio information and video information input from the HDD recorder 1. The display 21 (corresponding to a monitor) includes an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel), and the like, and displays video information input from the HDD recorder 1 so as to be visible from the outside. The speaker 22 outputs sound information input from the HDD recorder 1.

  The HDD recorder 1 includes a main CPU 11, a sub CPU 12, a power supply circuit 13, a power failure detection unit 14, a reception unit 15, an output processing unit 16, a RAM 18, and an HDD 19.

  A main CPU (Central Processing Unit) 11 controls the overall operation of the HDD recorder 1. The sub CPU 12 controls the operation at the time of power failure. The power supply circuit 13 generates a DC voltage having a predetermined magnitude (here, 5 V) from power supplied from a commercial power supply, and supplies the DC voltage to the main CPU 11 and the sub CPU 12 in the HDD recorder 1. is there. The power failure detection unit 14 performs various processes necessary for detecting the power failure time based on the DC voltage from the power supply circuit 13.

  The receiving unit 15 receives and demodulates a television broadcast, and includes an antenna unit 151, a tuner unit 152, an A / D conversion unit 153, a demodulation unit 154, and a TS demultiplexer 155.

  The antenna unit 151 receives a television broadcast wave. The tuner unit 152 selects a broadcast of a preset channel from the television broadcast wave received by the antenna unit 151. The A / D conversion unit 153 converts an output signal (= analog signal) from the tuner unit 152 into digital information. The demodulator 154 demodulates the output information from the A / D converter 153. A TS (Transport Stream) demultiplexer 155 separates and outputs the output information demodulated by the demodulator 154 for each type.

  The output processing unit 16 outputs an audio signal and a video signal corresponding to the television broadcast received by the receiving unit 15 to the speaker 22 and the display 21, respectively, and includes a D / A conversion unit 161, An audio signal output unit 162, an MPEG2 decoding unit 163, an NTSC encoding unit 164, and a video signal output unit 165 are provided.

  The D / A converter 161 converts the audio information (= digital information) output from the TS demultiplexer 155 into an analog signal. The audio signal output unit 162 outputs the audio signal converted into an analog signal by the D / A conversion unit 161 to the speaker 22.

  An MPEG (Motion Picture Experts Group) 2 decoding unit 163 decodes the video information output from the TS demultiplexer 155 into video information before compression.

  An NTSC (National Television Standards Committee) encoding unit 164 converts the video information decoded by the MPEG2 decoding unit 163 into an NTSC television signal. The video signal output unit 165 outputs the NTSC television signal output from the NTSC encoding unit 164 to the display 21.

  A RAM (Random Access Memory) 18 stores information such as audio information and video information in a readable and writable manner. An HDD (Hard Disk Drive) 19 (corresponding to a recording medium) stores various information such as video information and audio information in accordance with instructions from the MPU 11.

  Next, an operation when the HDD recorder 1 receives a broadcast will be described. First, the transmitted digital broadcast wave is received by the antenna unit 151. When a channel selection operation is accepted via a remote controller (not shown), the tuner unit 152 switches a transponder (Transponder) received. The received digital broadcast wave is converted into digital information by the A / D converter 153 and demodulated by the demodulator 154.

  The digital broadcast wave is transmitted as a TS (Transport Stream) packet from the transmission side (transmission station). This TS packet includes video information, audio information, control information, and the like, and these pieces of information are separated and output by the TS demultiplexer 155 and stored in the RAM 18. The audio information read from the RAM 18 is converted into an analog signal by the D / A conversion unit 161, and the audio is output from the speaker 22 via the audio signal output unit 162.

  Also, the video information read from the RAM 18 is decoded into video information before compression by the MPEG2 decoding unit 163, converted into an NTSC system television signal by the NTSC encoding unit 164, and passed through the video signal output unit 165. An image is displayed on the display 21.

  FIG. 2 is a block diagram showing an example of the configuration of the main part of the HDD recorder 1 according to the present invention. The power failure detection unit 14 includes a capacitor C1, a reset IC 141, and a power failure detection circuit 142. The capacitor C1 has a low-voltage side terminal grounded, a DC voltage (5V in this case) supplied from the power supply circuit 13 is applied to the high-voltage side terminal, is charged by this DC voltage, and functions as a standby power supply. is there. The capacitor C1 is composed of an electric double layer capacitor having a capacity of 0.1F or more (here, 1F).

  When the voltage value of the high-voltage side terminal of the capacitor C1 (= the operating voltage value of the sub CPU 12 during a power failure) becomes equal to or lower than a predetermined voltage (= the minimum operating voltage of the sub CPU 12), the reset IC 141 A reset signal is output to the RESET port of the CPU 12. When the reset signal is input from the reset IC 141, the sub CPU 12 cannot operate, so the operation is stopped and reset processing is performed when power is restored.

  The power failure detection circuit 142 is input with a DC voltage (here, 5 V) from the power supply circuit 13, detects that a power failure occurs, and sends a power failure signal to the sub CPU 12 indicating whether or not a power failure occurs. Output. The power failure detection circuit 142 includes a transistor TR2 that is turned off when the emitter is grounded and a power failure occurs, and outputs the collector voltage of the transistor TR2 to the PDWN port of the sub CPU 12 as a power failure signal. .

  The base of the transistor TR2 is applied with a divided voltage of a DC voltage (here, 5 V) from the power supply circuit 13 via a resistor R3 (for example, 1 kΩ). One end of the Zener diode D1 (for example, the Zener voltage is 3V) is applied with a DC voltage from the power supply circuit 13, and the other end of the Zener diode D1 is connected to the resistor R1 (for example, 100Ω) and the resistor R2 (for example, 100Ω). The resistors R2 are connected in series and one end of the resistor R2 is grounded. Therefore, when power is supplied from the commercial power supply to the power supply circuit 13, the base voltage of the transistor TR2 is approximately 1V, so that the transistor TR2 is turned on, and the collector voltage of the transistor TR2 is approximately 1V (= power failure signal). Is Low).

  Further, in the power failure detection circuit 142, a DC voltage (here, 5V) from the power supply circuit 13 is applied to the emitter, the base is connected to the collector of the transistor TR2 via the resistor R4 (for example, 10 kΩ), and the collector is a capacitor. A transistor TR1 connected to the high voltage side terminal of C1 is provided. Accordingly, when power is supplied from the commercial power supply to the power supply circuit 13, the base voltage of the transistor TR1 is approximately 1V, so that the transistor TR1 is turned on, and the VDD port of the sub CPU 12 and the capacitor C1 are supplied with power. Power is supplied from the circuit 13.

  When power is not supplied from the commercial power source to the power supply circuit 13 (= during power failure), the base voltage of the transistor TR2 is substantially 0 V, so that the transistor TR2 and the transistor TR1 are turned off, and the collector voltage of the transistor TR2 is The voltage value of the high-voltage side terminal of the capacitor C1 (= the power failure signal is High).

  That is, the power failure detection circuit 142 outputs a high power failure signal to the PDWN port of the sub CPU 12 when a power failure occurs, and when power is supplied from the commercial power source to the power supply circuit 13, A low power failure signal is output to the PDWN port.

  The main CPU 11 functionally includes a time calculation unit 111 and a time display unit 112, the sub CPU 12 functionally includes a power mode setting unit 121 and a voltage detection unit 122, and the RAM 18 is functional. In addition, a conversion value storage unit 181 is provided.

  Here, the main CPU 11 functions as functional units such as the time calculation unit 111 and the time display unit 112 by reading and executing a control program stored in advance in a ROM (Read Only Memory) or the like (not shown), The RAM 18 functions as a functional unit such as the converted value storage unit 181. The sub CPU 12 functions as functional units such as a power mode setting unit 121 and a voltage detection unit 122 by reading and executing a control program stored in advance in a ROM (not shown).

  Further, among various data stored in the RAM 12 shown in FIG. 1 and a ROM (not shown), data that can be stored in a removable recording medium includes, for example, a hard disk drive, an optical disk drive, a flexible disk drive, a silicon disk drive, and a cassette medium. In this case, the recording medium is, for example, a hard disk, an optical disk, a flexible disk, a CD (Compact Disc), a DVD (Digital Versatile Disk), a semiconductor memory, or the like.

  The conversion value storage unit 181 (corresponding to conversion value storage means) stores in advance the voltage value of the high-voltage side terminal of the capacitor C1 in association with the power failure time. Further, the power failure time is obtained by reading out the power failure time corresponding to the voltage value of the high voltage side terminal of the capacitor C1 from the power failure time stored in the converted value storage unit 181 by the time calculation unit 111.

  FIG. 3 is a graph showing an example of a change in voltage value at the high voltage side terminal of the capacitor C1. The horizontal axis of the figure is time (minutes), and the vertical axis is the voltage value (V) of the high-voltage side terminal of the capacitor C1. Here, a case where a power failure starts at time T0 and the power failure ends (= power recovery) at time T1 will be described.

  As shown in the graph G1, since the power is supplied from the capacitor C1 to the sub CPU 12 from the time T0 (= the electric charge of the capacitor C1 is discharged), the voltage value of the high voltage side terminal of the capacitor C1 gradually decreases. To do. Further, as shown in the graph G2, since power is supplied from the power supply circuit 13 to the capacitor C1 from time T1 (= charge is accumulated in the capacitor C1), the voltage at the high-voltage side terminal of the capacitor C1 The value gradually increases and reaches the voltage (here, 5 V) supplied from the power supply circuit 13.

  As shown in the graph G1, since the voltage value of the high voltage side terminal of the capacitor C1 is determined according to the elapsed period (= power failure time) after the power failure is started, the conversion value storage unit 181 includes a graph. Information indicating the relationship between the voltage value of the high-voltage side terminal of the capacitor C1 corresponding to G1 and the power failure time is stored.

  The functional configuration of the main CPU 11 and the sub CPU 12 will be described again using the configuration diagram of FIG. The power mode setting unit 121 sets a power mode for driving the HDD recorder 1 based on the power failure signal input from the power failure detection circuit 142 to the PDWN port of the sub CPU 12. That is, when power mode setting unit 121 determines that a power failure is not occurring due to a power failure signal, it sets the drive of HDD recorder 1 to a normal power mode, and when it is determined that a power failure occurs due to a power failure signal. In this case, the drive of the HDD recorder 1 is set to the “low power consumption mode”.

  Here, the “low power consumption mode” means that driving of devices other than the sub CPU 12 including the main CPU 11 is stopped (= power supply is stopped), and the sub CPU 12 is set to a low speed mode (for example, the driving frequency is 32.768 kHz). Drive in a certain mode), and power consumption through ports other than the RESET port, VDD port, and PDOWN port of the sub CPU 12 is prohibited. That is, the “low power consumption mode” is a mode in which only the reset signal from the reset IC 141 and the power failure signal from the power failure detection circuit 142 can be received.

  Based on the power failure signal from the power failure detection circuit 142, the voltage detection unit 122 (corresponding to the voltage detection means) determines the voltage value of the high voltage side terminal of the capacitor C1 at the timing when the power failure is completed (= recovered). While detecting via an A / D port, the detected voltage value is output to the time calculation part 111 of main CPU11. Note that, when a reset signal is input from the reset IC 141, the power failure signal from the power failure detection circuit 142 cannot be received, and therefore the voltage detection unit 122 does not perform the above processing.

  The time calculation unit 111 (corresponding to a time calculation unit) obtains the power outage time by reading out the power outage time corresponding to the voltage value detected by the voltage detection unit 122 from the converted value storage unit 181.

  The time display unit 112 (corresponding to a time display unit) displays the power failure time obtained by the time calculation unit 111 on the display 4. For example, the time display unit 112 displays the power outage time on the display 4 as an OSD (On-Screen Display) (for example, performs a character display of “There has been a power outage of about 10 minutes”).

  FIG. 4 is a flowchart showing an example of the operation of the HDD recorder 1 (mainly the main CPU 11 and the sub CPU 12). First, the power mode setting unit 121 determines whether or not a power failure has been detected based on the power failure signal input from the power failure detection circuit 142 to the PDWN port of the sub CPU 12 (S101). If it is determined that a power failure has not been detected (NO in S101), the process is set to a standby state. If it is determined that a power failure has been detected (YES in S101), the power mode setting unit 121 shifts to the low power consumption mode (S103). Then, based on the power failure signal input from the power failure detection circuit 142 to the PDWN port of the sub CPU 12, the voltage detection unit 122 determines whether or not the power failure has ended (= whether or not the power has been restored). S105).

  If it is determined that power has not been restored (= power outage is occurring) (NO in S105), the process is set to a standby state. When it is determined that power has been restored (YES in S105), the voltage detection unit 122 detects the voltage value of the high-voltage side terminal of the capacitor C1 via the A / D port (S107). And the power failure time is calculated | required by the time calculation part 111 being read from the conversion value memory | storage part 181 corresponding to the voltage value detected in step S107 (S109). Next, the power failure time obtained in step S109 is displayed on the display 4 by the time display unit 112 (S111), and the process ends.

  In this way, the power supply circuit 13 generates a DC voltage of a predetermined magnitude (here, 5 V) from the power supplied from the commercial power supply, and the low-voltage side terminal of the capacitor C1 is grounded. A DC voltage supplied from the power supply circuit 13 is applied to the high voltage side terminal. The capacitor C1 is charged with a DC voltage and functions as a standby power source. Further, the power failure detection circuit 142 to which a DC voltage is input from the power supply circuit 13 detects that a power failure is occurring, and outputs a power failure signal indicating whether or not a power failure is occurring. Further, in the sub CPU 12 that controls the operation at the time of a power failure, the voltage value of the high-voltage side terminal of the capacitor C1 is detected at the timing when the power failure is completed based on the power failure signal from the power failure detection circuit 142. Since the power failure time is obtained based on the obtained voltage value and the obtained power failure time is displayed on the display 4, the HDD recorder 1 capable of detecting the power failure time with a simple configuration can be realized.

  That is, because the voltage value of the high-voltage side terminal of the capacitor C1 functioning as a standby power supply is detected at the timing when the power failure ends (= the timing when power is restored), the power failure time is obtained based on the detected voltage value. Since the power failure time can be obtained using the capacitor C1 functioning as a standby power supply, the power failure time can be detected with a simple configuration.

  Further, in the sub CPU 12 that controls the operation at the time of the power failure, the voltage value of the high-voltage side terminal of the capacitor C1 is detected at the timing when the power failure ends based on the power failure signal from the power failure detection circuit 142. Since the power consumed at the time of a power failure for detection can be suppressed, the HDD recorder 1 that can detect the power failure time with a simple configuration can be realized.

  Furthermore, since the capacitor C1 is an electric double layer capacitor, the power failure time can be detected with a simpler configuration.

  In addition, since the capacity of the capacitor C1 is 0.1F or more (here, 1F), a power failure time of approximately 24 hours or more can be detected, so that the power failure time can be detected with a simple configuration.

  The power failure detection circuit 142 includes a transistor TR2 that is turned off when the emitter is grounded and a power failure occurs, and the collector voltage of the transistor TR2 is output as a power failure signal. 142 can be realized, the power failure time can be detected with a simpler configuration.

The present invention can also be applied to the following forms.
(A) In the present embodiment, the case where the broadcast recording apparatus is the HDD recorder 1 has been described. However, the broadcast recording apparatus is connected to a monitor so as to be communicable, receives a television broadcast, and receives received video information. May be used as long as the device stores the information in the recording medium. For example, the broadcast recording device may be a DVD recorder.

  (B) In the present embodiment, the case where the HDD recorder 1 includes two CPUs (main CPU 11 and sub CPU 12) has been described. However, the HDD recorder 1 may include one CPU.

  (C) In this embodiment, the case where the main CPU 11 functions as the time calculation unit 111 and the time display unit 112 has been described. However, at least one of the time calculation unit 111 and the time display unit 112 serves as a function unit of the sub CPU 12. It may be realized.

  (D) In the present embodiment, the case where the power failure detection circuit 142 includes the transistor TR2 that is turned off when the emitter is grounded and the power failure occurs is described. Any circuit may be used as long as it detects that a power failure has occurred and a power failure signal indicating whether or not a power failure has occurred, and outputs a power failure signal to the sub CPU 12.

These are block diagrams which show an example of a structure of the HDD recorder which concerns on this invention. These are functional block diagrams which show an example of a structure of the principal part in the HDD recorder which concerns on this invention. These are graphs which show an example of the change of the voltage value in the high voltage side terminal of a capacitor | condenser. These are the flowcharts which show an example of operation | movement of HDD recorder (mainly main CPU, sub CPU).

Explanation of symbols

1 HDD recorder (broadcast recording device)
11 Main CPU
111 Time calculation unit (time calculation means)
112 Time display section (Time display means)
12 Sub CPU
121 power mode setting unit 122 voltage detection unit (voltage detection means)
13 Power supply circuit 14 Power failure detection unit 141 Reset IC
142 Power failure detection circuit TR1, TR2 Transistor 15 Receiver 18 RAM
181 Conversion value storage unit (conversion value storage means)
19 HDD (recording medium)
2 Output device 21 Display (monitor)

Claims (6)

An HDD recorder that is communicably connected to a monitor, receives a television broadcast, and stores received video information in an HDD,
A main CPU for controlling the operation of the entire HDD recorder;
A sub CPU that controls the operation during a power failure;
A power supply circuit that generates a DC voltage of a predetermined magnitude set in advance from power supplied from a commercial power supply;
A low-voltage side terminal is grounded, a DC voltage supplied from the power supply circuit is applied to the high-voltage side terminal, and a capacitor that is charged by the DC voltage and functions as a standby power supply;
A power failure detection circuit that receives a direct current voltage from the power supply circuit, detects that a power failure is occurring, and outputs a power failure signal that indicates whether or not a power failure occurs.
Conversion value storage means for storing in advance the voltage value of the high voltage side terminal of the capacitor in association with the power failure time;
With
The sub CPU is
Based on the power failure signal from the power failure detection circuit, the voltage detection means for detecting the voltage value of the high voltage side terminal of the capacitor at the timing when the power failure ends,
The main CPU is
A time calculation means for obtaining a power failure time by reading out the power failure time corresponding to the voltage value detected by the voltage detection means from the converted value storage means;
Time display means for displaying the power failure time obtained by the time calculation means on the monitor;
With
The capacitor is an electric double layer capacitor having a capacity of 0.1 F or more,
The HDD recorder characterized in that the power failure detection circuit includes a transistor whose emitter is grounded and is turned off when a power failure occurs, and outputs a collector voltage of the transistor as a power failure signal. A power failure time detection device that detects a power failure time during which power supplied from a commercial power supply is stopped,
A power supply circuit that generates a DC voltage of a predetermined magnitude set in advance from power supplied from a commercial power supply;
A low-voltage side terminal is grounded, a DC voltage supplied from the power supply circuit is applied to the high-voltage side terminal, and a capacitor that is charged by the DC voltage and functions as a standby power supply;
A power failure detection circuit that receives a direct current voltage from the power supply circuit, detects that a power failure is occurring, and outputs a power failure signal that indicates whether or not a power failure occurs.
Based on the power failure signal from the power failure detection circuit, voltage detection means for detecting the voltage value of the high voltage side terminal of the capacitor at the timing when the power failure is completed,
Time calculation means for obtaining a power failure time based on the voltage value detected by the voltage detection means;
A power failure time detection device comprising:   The power failure time detection device according to claim 2, wherein the capacitor is an electric double layer capacitor.   4. The power failure time detection device according to claim 2, wherein the capacitor has a capacity of 0.1 F or more. 5.   5. The power failure detection circuit includes a transistor that is turned off when a power failure occurs while the emitter is grounded, and outputs a collector voltage of the transistor as a power failure signal. The power failure time detection device described in Crab. A broadcast recording device that is communicably connected to a monitor, receives a television broadcast, and stores the received video information in a recording medium,
A main CPU that controls the operation of the entire broadcast recording apparatus;
A sub CPU that controls the operation during a power failure;
A power supply circuit that generates a DC voltage of a predetermined magnitude set in advance from power supplied from a commercial power supply;
A low-voltage side terminal is grounded, a DC voltage supplied from the power supply circuit is applied to the high-voltage side terminal, and a capacitor that is charged by the DC voltage and functions as a standby power supply;
A power failure detection circuit that receives a direct current voltage from the power supply circuit, detects that a power failure is occurring, and outputs a power failure signal that indicates whether or not a power failure occurs.
Conversion value storage means for storing in advance the voltage value of the high voltage side terminal of the capacitor in association with the power failure time;
With
The sub CPU is
Based on the power failure signal from the power failure detection circuit, the voltage detection means for detecting the voltage value of the high voltage side terminal of the capacitor at the timing when the power failure ends,
The main CPU is
A time calculation means for obtaining a power failure time by reading out the power failure time corresponding to the voltage value detected by the voltage detection means from the converted value storage means;
Time display means for displaying the power failure time obtained by the time calculation means on the monitor;
A broadcast recording apparatus comprising:

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