JP2008277809A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a capacitor type antifuse which can be set to a blow state efficiently and securely, and has desired breakdown voltage characteristics for holding program information securely at a normal operating mode. <P>SOLUTION: Impurity regions 71a and 71b are formed on the surface of a semiconductor substrate region 70. A gate electrode layer 73 is formed on a channel region between these impurity regions 71a and 71b through a gate insulating film 72. The gate electrode layer 73 is electrically connected with a conductive layer 74 of its upper layer on the channel region. A field insulating film 75 for isolation is formed so that the field insulating film may surround the impurity regions 71a and 71b. A contact hole 76 is formed on the channel region to the gate electrode layer 73 of a MOS capacitor which constitutes a fuse. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a capacitor as a program element. More specifically, the present invention relates to a configuration of a program circuit in a dynamic semiconductor memory device in which a memory cell has a capacitor.

  In a semiconductor device, a program circuit is used for various purposes. For example, in the case of a semiconductor memory device, this program circuit has an operation mode setting (for example, first page mode in DRAM (Dynamic Random Access Memory) and EDO (Extended Data Output) mode), word configuration It is used for setting (setting of x8 and x16). Further, in order to finely adjust the resistance value for generating the reference voltage, a fusible link element is used as a program element.

  In a semiconductor memory device, a defective address program circuit for storing a defective address is used to relieve a defective memory cell. When a defective address is designated, a normal memory cell corresponding to the defective address is replaced with a redundant memory cell.

  In such a program circuit, a fusing link element (fuse element) is conventionally used. An energy beam such as a laser beam is used for programming the fuse element (melting / non-melting). When such a fuse element is used, a post-process such as cleaning is required after fusing (after laser blow) to prevent a short circuit due to scattering of molten fragments in the vicinity of the irradiated region, which is relatively long for programs. It takes time.

  Further, in a high density / highly integrated semiconductor device, when fuse elements are arranged at high density, the adjacent fuse elements are partially damaged due to misalignment of the laser beam, making it difficult to perform accurate programming. .

  Further, due to the positional deviation between the laser beam and the fuse element to be blown, the fuse element to be blown is blown incompletely and cannot be accurately programmed.

  When such a fuse element is a defective address program element for relieving a defective memory cell, the number of fuse elements to be blown increases and the possibility of erroneous programming is increased. Such an incorrect program reduces the product yield.

  In addition to the fusible link element as described above, there is a program element called an “antifuse”. In this antifuse, the capacitor insulating film is subjected to dielectric breakdown (breakdown) according to information to be stored, and programming is performed by conduction / non-conduction of the capacitor.

  FIG. 35 schematically shows a structure of a conventional antifuse circuit. 35, the antifuse circuit includes a programmable capacitor (antifuse) 900 having one electrode node coupled to node 902, a decoupling transistor 903 that couples the other electrode node of programmable capacitor 900 to node 904, In accordance with the signal potential on 904, the programmable state of programmable capacitor (hereinafter simply referred to as antifuse) 900 is determined, inverter 906 that outputs signal FR indicating the determination result, and node 904 in response to trigger signal ZT. P channel MOS transistor 908 charging to power supply voltage Vcc level, and n channel MOS transistors 910 and 912 connected in series between node 904 and the ground node are included. MOS transistor 910 receives program signal AD at its gate, and MOS transistor 912 receives output signal FR of inverter 906 at its gate.

  This antifuse circuit further includes a p-channel MOS transistor 914 for charging node 904 to the power supply voltage Vcc level according to output signal FR of inverter 906, and an n-channel MOS transistor 916 for discharging node 904 to the ground voltage level according to reset signal RST. including.

  Node 902 is applied with a high voltage (for example, 12 V) in the program mode, and is applied with the ground voltage in the normal operation mode (the mode for performing the determination operation and the standby state). MOS transistor 903 receives power supply voltage Vcc at its gate, and prevents high voltage applied to node 902 from being applied to other circuit elements when antifuse 900 is programmed. Next, the operation of the antifuse circuit shown in FIG. 35 will be briefly described.

  First, the program operation of the antifuse 900 will be described with reference to FIG. In this program operation mode, trigger signal ZT is set to H level, and MOS transistor 908 is held in a non-conductive state. According to the information to be programmed, the signal AD is set to a predetermined voltage level. In FIG. 36A, signal AD is set to H level in order to set antifuse 900 to a conductive state (blow). In the initial state, node 904 is precharged to H level by the initial setting of trigger signal ZT, and signal FR from inverter 906 is set to L level. In response to L level signal FR, MOS transistor 914 is rendered conductive, and node 904 is held at H level.

  In the program operation mode, the reset signal RST is first set to H level, and the MOS transistor 916 is turned on. Node 904 is discharged to the ground voltage level, and signal FR falls to the H level. In response to the fall of signal FR, MOS transistor 914 is rendered non-conductive, while MOS transistor 912 is rendered conductive, and node 904 is coupled to the ground node via MOS transistors 910 and 912. While the reset signal RST is at the H level, the voltage level applied to the node 902 is raised. Since the reset signal RST is at the H level, when the voltage to the node 902 rises, the voltage level of the node 904 is prevented from rising due to capacitive coupling of the antifuse 900, and the signal FR maintains the H level.

  When reset signal RST is set to L level, it is then applied to node 902 with a high voltage for programming. Due to the voltage of the node 902, a high voltage is applied to the antifuse 900, causing dielectric breakdown of the capacitor insulating film (the signal AD is at H level). Due to the dielectric breakdown in antifuse 900, the voltage applied to node 902 is transmitted to node 904, and the voltage level on node 904 rises. The voltage at node 904 is determined by the ratio of the resistance of antifuse 900 to the combined channel resistance of transistors 910 and 912. When the voltage at node 904 exceeds the input logic threshold value of inverter 906, signal FR falls from H level to L level, MOS transistor 912 is turned off, and MOS transistor 914 is turned on. Node 904 is charged to power supply voltage Vcc level through MOS transistor 914. Decoupling transistor 903 transmits voltage Vcc-Vth. Here, Vth indicates the threshold voltage of the decoupling transistor 903. Therefore, the flow of current through the antifuse 900 from the node 902 to the node 904 is interrupted, and the program of the antifuse 900 is completed.

  In this program operation mode, when signal AD is set to L level, MOS transistor 910 is held in a non-conductive state. When node 904 is discharged to ground voltage level via MOS transistor 916 by reset signal RST, signal FR rises to H level and MOS transistor 914 is driven to a non-conductive state. Therefore, when reset signal RST falls to the L level, MOS transistors 908, 910, 914, and 916 are all turned off, so that node 904 is in a floating state. In this state, when a high voltage for programming is applied to the node 902, the high voltage for programming at this node 902 is transmitted to the node 904 via the anti-fuse 900 and capacitively coupled to the node 904 via the MOS transistor 903. Therefore, since a high voltage is not applied between the electrodes of the antifuse 900, the dielectric breakdown does not occur in the antifuse 900. When the antifuse 900 is not blown, the voltage level of the node 904 rises due to capacitive coupling of the antifuse 900, and as shown by the broken line waveform, the signal FR from the inverter 906 falls to the L level, and the MOS transistor Node 904 is charged to the level of power supply voltage Vcc.

Next, the stored information reading operation will be described with reference to FIG.
When trigger signal ZT is inactivated, reset signal RST is driven to the H level, and node 904 is discharged to the ground voltage level. In response, signal FR from inverter 906 is driven to the H level.

  In this stored information read mode, ground voltage is applied to node 902 and signal AD is also set to L level.

  In this state, when the trigger signal ZT falls to the L level, the MOS transistor 908 becomes conductive. When the antifuse 900 is set to the conductive state, the current from the MOS transistor 908 is discharged to the node 902 through the antifuse 900, the node 904 maintains the L level, and the signal FR is at the H level. maintain.

  On the other hand, when antifuse 900 is programmed to a non-blown state, when MOS transistor 908 is turned on, node 904 is charged to power supply voltage Vcc level, and signal FR is lowered to L level accordingly. The information stored in the anti-fuse circuit is read according to the H level / L level of the signal FR.

  When the antifuse circuit is used for specifying an operation mode, this signal FR is used as an operation mode designation signal.

  When this antifuse circuit is used as a defective address program circuit for repairing a defective cell in a memory cell, the signal FR corresponds to each defective address bit, and the applied address signal and the signal FR are compared bit by bit. Whether or not a defective address has been designated is determined according to the comparison result. Based on the determination result, replacement of a redundant cell or access to a normal cell is performed.

  Antifuses as described above do not require the use of a laser beam or the like and can be electrically programmed, so that they are widely used as programming circuits for high-density / highly integrated semiconductor devices. .

  In the antifuse circuit as described above, a capacitor is used. At the time of programming the capacitor, it is necessary to apply a relatively high voltage (for example, 12 V) to cause dielectric breakdown. In order to apply such a high voltage, a MOS transistor (insulated gate field effect transistor) that is a component of a program control circuit that applies the high voltage needs to have a sufficiently high breakdown voltage. However, in recent high-density and highly-integrated semiconductor memory devices, the size of MOS transistors has been reduced, and the breakdown voltage has been reduced. Therefore, in order to apply such a high voltage for programming, it is necessary to use a MOS transistor having a sufficiently high breakdown voltage as a constituent element compared to other peripheral circuits, and its size increases (usually in accordance with the scaling law). When the MOS transistor is formed and the gate insulating film is thickened, the size increases accordingly). Therefore, there arises a problem that the area occupied by the program control circuit increases.

  As described above, US Pat. No. 5,110,754 shows a configuration in which a capacitor having the same structure as a three-dimensional capacitor of a DRAM cell is used as an antifuse in order to program a capacitor antifuse without using a program high voltage. . In this prior art, a single capacitor is used as an antifuse. When a single capacitor having the same characteristics as the memory cell capacitor is formed in the peripheral circuit region, a repetitive pattern in the memory cell array region is not formed. Therefore, the capacitor pattern / shape in the peripheral region is different from that of the memory cell capacitor. There arises a problem that it is difficult to form an antifuse capacitor having the same characteristics as the capacitor.

  In order to read the program information, it is necessary to pass a relatively large current through the antifuse (capacitor), and the electrode area needs to be sufficiently large (to read the stored data at high speed). For this reason, the area occupied by the antifuse circuit is increased, and there is a problem that high integration cannot be achieved.

  Therefore, an object of the present invention is to provide a highly reliable antifuse circuit with a small occupation area.

  Another object of the present invention is to provide a semiconductor device in which a capacitor having exactly the same characteristics as a memory cell capacitor can be used as an antifuse element.

A semiconductor device according to a first aspect of the present invention is a MOS capacitor including an insulated gate field effect transistor having a gate and first and second impurity regions formed on the surface of the semiconductor substrate region. including. The gate of the MOS capacitor is electrically connected to the conductive wiring through a contact hole formed on the channel region between the first and second impurity regions, and the first and second impurity regions are shared. And the conductive wiring becomes the other electrode of the capacitor.

The semiconductor device according to the first aspect, further comprising programming operation mode, a program control circuit for applying a program voltage to the one and the other electrodes.

According to a second aspect of the present invention , in the MOS capacitor of the semiconductor device according to the first aspect, the first and second impurity regions have the same conductivity type as the semiconductor substrate region.

The semiconductor device according to claim 3, having a first and second electrode nodes, the program capacitor element having a high breakdown voltage and low-voltage by applying voltage polarity between the first and second electrode nodes, In the program operation mode, a program voltage is applied to the program capacitor element with a voltage polarity that gives this high withstand voltage, and the program capacitor element is programmed. In the normal operation mode, the voltage is given with a voltage polarity that gives a low withstand voltage. A program control circuit for applying to

According to a fourth aspect of the present invention, there is provided a semiconductor device having first and second electrode nodes, a program capacitance element having a high withstand voltage and a low withstand voltage according to an applied voltage polarity between the first and second electrode nodes, and a program In the operation mode, a program voltage is applied between the first and second electrodes with a voltage with low withstand voltage, and in the normal operation mode, a voltage is applied between the first and second electrodes with a voltage with low withstand voltage. A program control circuit is provided.

According to a fifth aspect of the present invention, there is provided a semiconductor device having first and second electrode nodes, a program capacitance element having a high withstand voltage and a low withstand voltage according to a voltage polarity applied between the first and second electrode nodes, and a program A program control circuit is provided for applying a voltage between the first and second electrodes with the same voltage polarity in the operation mode and the normal operation mode.

According to a sixth aspect of the present invention, the semiconductor device according to any of the third to fifth aspects further includes a plurality of memory cells each having a capacitor for storing information, and the program capacitor element has the same structure as the capacitor. Including the capacitive element.

According to a seventh aspect of the present invention, there is provided a semiconductor device comprising: a capacitor; and a program voltage applied to the capacitor in a program operation mode to selectively cause a dielectric breakdown in the capacitor according to stored information. A control circuit is provided for applying a one-shot pulse signal between the capacitor electrodes in response to the state determination instruction signal for determining the storage information of the capacitor.

In the semiconductor device according to claim 8 , the program control circuit according to claim 7 sets the first electrode of the capacitor to the first voltage level in the determination operation mode, and responds to the activation of the state determination instruction signal. The second electrode of the capacitor is driven to the second voltage level in the form of a one-shot pulse, and the second electrode node of the capacitor is pre-set to the first voltage level in response to the deactivation of the state determination instruction signal. Including means for charging.

The semiconductor device according to claim 9 is arranged corresponding to each of a plurality of normal elements, a plurality of program circuits each programmed with information specifying a defective normal element by dielectric breakdown of a capacitor, and a plurality of programs. And a plurality of redundant elements for replacing and repairing defective normal elements of the plurality of normal elements. The plurality of program circuits and the plurality of redundant elements can relieve the defective program circuit and / or the defective redundant element.

  By setting the program high voltage and the polarity of the applied voltage in the normal operation mode according to the direction of the withstand voltage characteristics of the capacitor, dielectric breakdown is surely generated in the program operation mode and conduction is ensured in the normal operation mode. / A non-conduction (melting / non-melting) state can be set, and a highly reliable antifuse circuit can be realized.

In other words, according to the first aspect of the present invention, a contact hole for making an electrical contact is formed in the gate on the channel region of the MOS capacitor to electrically connect the upper conductive layer and its gate electrode layer. Therefore, the withstand voltage of the MOS capacitor can be lowered, and the capacitor type antifuse including the MOS capacitor can be easily programmed.

According to the invention of claim 2, the MOS capacitor has the impurity region and the substrate region of the same conductivity type, so that a plurality of MOS capacitors can be reliably electrically connected in parallel, and the substrate region Due to the parasitic capacitance, the capacitance value of the MOS capacitor can be increased.

According to the invention of claim 3, in a capacitor having a low withstand voltage polarity and a high withstand voltage polarity, a program high voltage is applied with a high withstand voltage polarity in the program operation mode, and in a normal operation mode, Since the voltage is applied with the voltage polarity of low withstand voltage characteristics, it is possible to surely cause dielectric breakdown and to ensure that the programmed capacitor type antifuse is blown / unblown in normal operation mode. Can be held.

According to the invention of claim 4, in a capacitor having a voltage polarity with a high withstand voltage characteristic and a low withstand voltage characteristic, the program high voltage is applied with a voltage polarity with a low withstand voltage in the program operation mode, and the normal operation mode Since the voltage is applied to the capacitor in the voltage polarity direction with a low withstand voltage, dielectric breakdown occurs at a low program high voltage, and the non-blown capacitor type antifuse is reliably prevented by applying the voltage of the same voltage polarity. It can be kept in a blown state.

According to the fifth aspect of the present invention, a capacitor having a high breakdown voltage and a low breakdown voltage according to the voltage polarity is configured to apply a voltage with the same polarity in the program operation mode and in the normal operation mode. Therefore, the configuration of these control circuits is simplified (since it is not necessary to reverse the voltage polarity). Further, the non-blown / blown state of the capacitor can be reliably maintained even in the normal operation mode.

According to the invention of claim 6, since the capacitor having the same structure as the memory cell capacitor is used as the capacitor having asymmetric withstand voltage characteristics, the capacitor having the complete structure can be easily formed with a small occupied area. Can be realized.

According to the invention of claim 7, since the voltage is applied to the capacitor in the form of a one-shot pulse when determining the stored information of the capacitor, it is possible to reduce the voltage stress application time applied to the capacitor. Thus, it is possible to prevent the breakdown voltage characteristics of the capacitor from being deteriorated and to realize a highly reliable program circuit.

According to the invention of claim 8, in the standby cycle, the determination node (first electrode node) of the capacitor is set to the first level, and in the determination operation mode, the determination mode is in the form of a one-shot pulse. Since the second level voltage is applied, the time during which voltage stress is applied to the capacitor can be reduced.

According to the ninth aspect of the present invention, a program circuit is provided for each spare element, and when a defect exists in the combination of the program circuit and the spare element, another set is used without using the combination of the program circuit and the spare element. Since the program circuit is configured to perform a defect relief program, even when a defect exists in the program circuit and the spare element for defect relief, it is relieved by another program circuit and a spare element. Chip yield can be improved.

[Overall configuration]
FIG. 1 schematically shows a whole structure of a semiconductor device according to the present invention. In FIG. 1, a dynamic semiconductor memory device is shown as a semiconductor device to which the present invention is applied.

  In FIG. 1, a semiconductor memory device 1 includes a normal array 2 having a plurality of normal cells arranged in a matrix, and a spare array in which redundant cells for relieving defective normal cells in the normal array 2 are arranged in a matrix. 3, an address input circuit 4 that generates an internal address signal in response to an external address signal ADD, and, when activated, selects an addressed normal cell in the normal array 2 according to the internal address signal from the address input circuit 4 A normal cell selection circuit 5 to perform, an internal address signal from the address input circuit 4 to determine whether or not a defective normal cell in the normal array 2 is designated, and a redundant replacement control circuit 6 A redundant cell selection circuit 7 for selecting a spare cell of the spare array 3 in accordance with a defective normal cell designation instruction signal, and an external control signal φ A peripheral control circuit 8 for generating an internal control signal φin according x.

  In normal array 2 and spare array 3, 1-transistor / 1-capacitor type memory cells are arranged in a matrix. The spare array 3 may be configured to relieve defective normal cells of the normal array 2. Spare array 3 includes a spare row for relieving a defective normal cell row of normal array 2 and a spare column for relieving a defective memory cell column of normal array 2. Normal cell selection circuit 5 includes a row selection circuit for selecting a normal cell row of normal array 2 and a column selection circuit for selecting a normal cell column of normal array 2. Redundant cell selection circuit 7 also includes a row selection circuit for selecting redundant cell rows of spare array 3 and a column selection circuit for selecting redundant cell columns of spare array 3. However, redundant cell selection circuit 7 may be configured to include only one of a row selection circuit for selecting a redundant cell row and a column selection circuit for selecting a redundant cell column.

  The redundant replacement control circuit 6 deactivates the normal cell selection circuit 5 and activates the redundant cell selection circuit 7 when the internal address signal from the address input circuit 4 designates a defective normal cell. Redundant replacement control circuit 6 includes a program circuit for programming a defective normal cell row / column, and has a configuration in which a row / column selection circuit is provided in redundant cell selection circuit 7 corresponding to each program circuit. Also good. Redundant cell selection circuit 7 may be activated in accordance with a defective normal cell designation instruction signal from redundant replacement control circuit 6 to decode an address signal from address input circuit 4.

  FIG. 2 schematically shows a configuration of redundant replacement control circuit 6 shown in FIG. In FIG. 2, a redundant replacement control circuit 6 includes a program control circuit 6a for generating a control signal designating a normal operation mode and a program operation mode, and a program and program data for a defective normal cell address according to the control signal from the program control circuit 6a. The program circuit 6b for reading data is operated under the control of the program control circuit 6a, and the programmed defective normal cell address signal from the program circuit 6b is compared with the internal address signal ADD from the address input circuit 4, Comparing / determining circuit 6c for generating signal M indicating whether or not to perform redundant replacement (operation of delaying a defective normal cell with a redundant cell) according to the comparison result is included.

  Program circuit 6b preferably includes a capacitor-type anti-fuse composed of a plurality of capacitive elements having the same structure as the memory cell capacitors arranged in accordance with the same pattern as the memory cell array pattern in normal array 2 and spare array 3, as a defective normal It is included as a program element for programming a cell address.

[Embodiment 1]
FIG. 3 shows a structure of a main portion of the semiconductor memory device according to the first embodiment of the present invention. FIG. 3 shows a configuration of program circuit 6b corresponding to memory array MA and 1-bit address signal. Memory array MA may be either normal array 2 or spare array 3 shown in FIG. In the normal array 2 and the spare array 3, memories having the same pattern are repeatedly arranged.

  The memory array MA includes a plurality of memory cells MC arranged in a matrix, word lines WL0, WL1,... Arranged corresponding to the memory cell rows, and bit lines arranged corresponding to the memory cell columns. The pairs BL0, / BL0, BL1, / BL1,. Memory cell MC includes a capacitor MS for storing information and an access transistor MT formed of an n-channel MOS transistor for connecting memory cell capacitor MS to a corresponding bit line according to a signal potential on the corresponding word line.

  Program circuit 6b includes a plurality of program unit elements PRa-PRn arranged in alignment along the row direction. Each of program unit elements PRa to PRn has the same structure as memory cell MC, and includes a capacitive element S and a MOS transistor T. Capacitance element S has the same structure as memory cell capacitor MS, and MOS transistor T has the same structure as access transistor MT. Here, “same structure” indicates a state in which the size and shape are the same. Therefore, the capacitive element S has the same electrical characteristics as the memory cell capacitor MS.

  Program circuit 6b further extends in the row direction, and is connected to conductive wire 10 commonly connected to the gate of MOS transistor T, and conductive wire commonly connected to one electrode node of capacitive element S. 13, conductive lines 11a to 11n connected to the first electrode nodes of the MOS transistor T, and a conductive line 12 connected in common to the conductive lines 11a to 11n, respectively. Conductive wiring 10 is formed in the same process as word lines WL (WL0, WL1,...) In memory array MA, is formed of the same material as word lines WL, and transmits power supply voltage Vcc. The conductive wiring 13 corresponds to the cell plate electrode layer of the memory cell capacitor MS in the memory array MA, and is formed in the same manufacturing process as this cell plate electrode layer. Conductive wirings 11a to 11n correspond to bit line BL (or / BL) in memory array MA. The conductive wiring 12 becomes the first electrode C1 of the program element (capacitor type antifuse), and the conductive wiring 13 becomes the other electrode C2 of the program element.

  Conductive line 10 transmits power supply voltage Vcc, MOS transistor T becomes conductive, and capacitive element S is coupled to conductive line 12 through conductive lines 11a to 11n. Therefore, a plurality of capacitive elements S are connected in parallel between the electrode nodes C1 and C2 of the program element, and a program element having a relatively large capacitance value with a small occupation area can be realized. In particular, the memory cell capacitor is required to have a necessary minimum capacitance value even if the area is reduced for storing information. Therefore, the memory cell capacitor is the capacitor with the most excellent area utilization efficiency. By connecting a plurality of capacitive elements having the same structure as this memory cell capacitor in parallel, a program element composed of a capacitor with excellent area utilization efficiency can be realized.

  FIG. 4 schematically shows a cross-sectional structure of memory cell MC and program unit element PR (PRa to PRn). In FIG. 4, since these memory cells MC and program unit elements PR (PRa to PRn) have the same structure, the sectional structure of the program unit element PR is shown. In FIG. 4, the program unit element PR has n-type impurity regions 16a, 16b and 16c formed on the surface of the semiconductor substrate region 15 and a gate insulation (not shown) on the channel region between the impurity regions 16a and 16b. A conductive layer 17 formed through the film, a conductive layer 18 electrically connected to the impurity region 16b and extending on the conductive layer 17, a conductive layer 18, and a thin capacitor insulating film (not shown) And a conductive layer 20 electrically connected to the impurity region 16a and formed under the conductive layer 18 and extending in a direction intersecting the conductive layer 17.

  The conductive layer 17 corresponds to the conductive wiring 10 shown in FIG. 3, the conductive layer 19 corresponds to the conductive wiring 13, and the conductive layer 20 corresponds to the conductive wiring 11 (11a to 11n). A thick insulating film 21 for element isolation is formed between the impurity region 16b and the impurity region 16c.

  This program unit element has a three-dimensional structure, and the capacitive element S has a so-called stacked capacitor structure. When such a three-dimensional capacitor is formed independently in the peripheral circuit region, since such a three-dimensional structure is not provided in the peripheral circuit, there is no pattern / step difference between the peripheral circuit region and this capacitive element. Different. Therefore, when a capacitor having the same three-dimensional structure as the memory cell capacitor is arranged alone in the peripheral circuit region, patterning shift due to halation due to a step of the peripheral circuit at the time of exposure, and peripheral circuit at the time of manufacture Deformation of the shape due to stress or the like due to the level difference of the constituent elements of the region occurs, and a capacitor having desired characteristics cannot be realized. However, as in the first embodiment, by repeatedly arranging the program unit elements along the row direction, the repetition of the pattern can be obtained, and the program unit elements can be obtained without being affected by the components of the peripheral circuit. It can be formed in the same shape as the memory cell MC, whereby a capacitor type antifuse having desired characteristics can be realized.

  When the program unit element PR is used as an antifuse, the number of unit elements PR may be about several tens.

  In this case, when the program unit elements PRa to PRn are connected in parallel and used as one program element, if the dielectric breakdown of at least one capacitive element S occurs, the program element may be used as an antifuse. it can. Therefore, even if the dielectric breakdown voltage in the capacitive element S varies, programming can be performed reliably without being affected by the variation, and a program circuit with a high yield can be realized.

[Modification 1]
FIG. 5 schematically shows a configuration of a first modification of the first embodiment of the present invention. In FIG. 5, program unit elements PRp to PRu are arranged in the same repeating pattern as the array pattern in the memory array column direction. Program unit elements PRp to PRu have the same structure as memory cell MC, and include MOS transistor T and capacitive element S.

  The first electrode node of MOS transistor T is coupled in common to conductive line 26, and the first electrode node of capacitive element S (corresponding to the cell plate electrode node of the memory cell capacitor) is commonly connected to conductive line 25. The MOS transistor T has its gate coupled to receive power supply voltage Vcc through conductive lines 27p-27u, respectively. These conductive wirings 27p to 27u may be formed so as to be coupled to one wiring in common and receive power supply voltage Vcc as shown by a broken line in FIG. 5, and when there is a power supply wiring in the vicinity, The power supply wiring may be individually connected.

  In the program element shown in FIG. 5 as well, the same pattern is repeated in the column direction, and the capacitive element S having the same structure as the memory cell capacitor is accurately connected to the peripheral circuit without being affected by the pattern of the constituent elements of the peripheral circuit. Can be formed in the region. Also in the arrangement shown in FIG. 5, the conductive wiring 26 becomes one electrode node C1 of the program element, and the conductive wiring 25 becomes the other electrode node C2 of the program element. Therefore, capacitive element S is coupled in parallel between electrode nodes C1 and C2. In this way, a capacitor type antifuse with excellent area utilization efficiency can be formed. Further, the same effect as the capacitor type antifuse shown in FIG. 3 can be obtained.

[Modification 2]
FIG. 6 (A) schematically shows a configuration of a second modification of the first embodiment of the present invention. In FIG. 6A, this capacitor type antifuse is formed in an N well 31 formed on the surface of the semiconductor substrate region 30. N-type impurity regions 32a, 32b, 32c, and 32d are formed on the surface of N well 31 with a gap. Conductive layer 33a is formed on the channel region between impurity regions 32a and 32b via a gate insulating film (not shown), and conductive layer 33b is formed on the channel region between impurity regions 32b and 32c. Impurity regions 32a and 32c are electrically connected to conductive layers 34a and 34b that are separated from each other, respectively. Conductive layer 35 is commonly formed on conductive layers 34a and 34b corresponding to these memory cell storage nodes via a capacitor insulating film (not shown).

  FIG. 6B is a diagram showing an electrical equivalent circuit of the program element shown in FIG. In FIG. 6B, the storage node SN (corresponding to the impurity regions 32a and 32c) of the unit element is coupled through the wiring 38 in common, and the other electrode node of the capacitor S is coupled to the electrode node C1 through the wiring 37. Is done. This wiring 38 corresponds to the N well 31 in FIG. The storage node SN is a connection node between the MOS transistor T and the capacitive element S. As shown in FIG. 6B, since N well 31 functions as wiring 38 and electrode node C2 of the program element, capacitive element S is connected in parallel between electrode nodes C1 and C2. Conductive layers 33a and 33b serving as gates of MOS transistor T are provided as a dummy for forming the same pattern as that of the memory cell array. Therefore, the voltage levels of conductive layers 33a and 33b are arbitrary and may be in an electrically floating state. When conductive layers 33a and 33b are connected to power supply voltage Vcc, N-type impurities are attracted to the region between impurity regions 32a and 32b and the region between impurity regions 32b and 32c. The resistance can be reduced, and the resistance of the capacitor electrode can be reduced.

  In FIG. 6A, a conductive layer corresponding to a bit line is not shown. However, a conductive layer corresponding to the bit line may be formed so as to be electrically connected to the impurity region 32b in order to maintain the sameness as the pattern of the memory array. Also in this case, the conductive layer corresponding to the bit line is simply provided as a dummy (in order to maintain pattern identity).

  The unit elements shown in FIG. 6A may be arranged in alignment along either the row direction or the column direction of the memory array.

[Modification 3]
FIG. 7 schematically shows a configuration of a third modification of the first embodiment of the present invention. In FIG. 7, program unit elements PR0 to PRn are arranged so as to have the same arrangement pattern as the arrangement pattern in the row direction or the column direction of the memory array. Dummy elements DPRa and DPRb are arranged in alignment on both sides of these unit elements PR0 to PRn. These dummy elements DPRa and DPRb have the same layout pattern as unit elements PR0 to PRn. Unit elements PR0 to PRn are connected in parallel between electrode nodes C1 and C2. Dummy elements DPRa and DPRb are held in a floating state. Therefore, unit elements PR0 to PRn are used as capacitor type antifuses, and dummy elements DPRa and DPRb are not used. These dummy elements DPRa and DPRb are provided in order to maintain the continuity of the repeated pattern in the alignment direction of the unit elements PR0 to PRn. The end unit elements PR0 and PRn also have the same repeating pattern on both sides thereof, and can be formed under the same conditions as the other unit elements PR1,..., And are included in these unit elements PR0 and PRn. The capacitor element is also formed under the same conditions as the other unit elements, and a capacitor element having the same structure and characteristics as the memory cell capacitor can be reliably formed.

  In the above description, the unit elements are arranged in the row or column direction. However, the unit elements PR may be arranged in two-dimensional alignment in the row and column directions. In this case, a node corresponding to the cell plate electrode node of the memory cell capacitor is connected in common to serve as one electrode of the program element. When the substrate region is used as an electrode of the program element, the conductive layer corresponding to the bit line is in a floating state, and the conductive layer corresponding to the word line is arbitrarily connected. When the capacitive elements are connected to each other via a MOS transistor (a transistor corresponding to an access transistor), power supply voltage Vcc is applied to a conductive layer corresponding to a word line. Even if such unit elements are arranged in a two-dimensional manner, a capacitor type antifuse with excellent area utilization efficiency can be realized.

[Modification 4]
FIG. 8 schematically shows a configuration of a fourth modification of the first embodiment of the present invention. In FIG. 8, an antifuse arrangement region 6ba is provided adjacent to memory array MA, and program peripheral circuit 6bb is arranged adjacent to or adjacent to antifuse arrangement region 6ba. The antifuse arrangement region 6ba and the program peripheral circuit 6bb correspond to the program circuit 6b shown in FIG. In memory array MA, memory cells MC are arranged in a matrix. The memory cell arrangement pattern of the memory array MA is repeated to extend to the antifuse arrangement region 6ba. As a result, the capacitive element can be formed in the antifuse arrangement region 6ba with the same pattern as the repeated pattern of the memory array MA. By repeating the repeating pattern in the memory array MA continuously, a unit element composed of a capacitive element and a MOS transistor can be easily formed in the antifuse arrangement region 6ba. As a result, the structure for preventing the discontinuity of the pattern in the end region in the memory array MA can be used as it is in the antifuse arrangement region 6ba, and exactly the same structure as the memory cell MC in the memory array MA ( Unit elements having the same pattern) can be formed.

  Program peripheral circuit 6bb includes a circuit portion for programming a capacitor type antifuse included in antifuse arrangement region 6ba and reading the stored data.

  Further, in FIG. 7, dummy elements DPRa and DPRb are arranged on both sides of the unit elements PR0 to PRn. However, the number of these dummy elements is arbitrary, and repetition of the same pattern results in these unit elements PR0 to PRn. As long as they have the same effect.

  As described above, according to the first embodiment of the present invention, when a memory cell capacitor structure is used as a capacitor type antifuse, an antifuse can be easily realized by repeatedly arranging and arranging the memory cell structures. be able to. Even if a capacitor-type antifuse is disposed in the peripheral circuit region, a capacitor-type antifuse having desired characteristics can be formed. Further, it is possible to prevent formation of a capacitor type antifuse having an incomplete structure, and it is possible to realize a highly reliable capacitor type antifuse.

[Embodiment 2]
FIG. 9A schematically shows a structure of an antifuse circuit according to the second embodiment of the present invention. FIG. 9A shows the structure of one capacitor type antifuse. In FIG. 9A, unit elements composed of a serial body of a MOS transistor T and a capacitive element S are connected in parallel between nodes C3 and C4. The gates of the MOS transistors T are commonly connected to the node NG. The MOS transistor T is used as the decoupling transistor 903 shown in FIG. 36, and the capacitive element S is used as the capacitor type antifuse 40. These capacitive elements S may be aligned in either row or column direction, and may be aligned according to the first embodiment.

  FIG. 9B is a diagram showing an electrical equivalent circuit of the arrangement of unit elements shown in FIG. In FIG. 9B, a MOS transistor 41 and a capacitor type antifuse 40 are connected in series between nodes C3 and C4. The MOS transistor 41 is formed of a parallel body of a plurality of MOS transistors T. Therefore, the channel width is widened and a sufficiently large current can be supplied, and the current when the capacitor type antifuse 40 is blown / not blown can be sufficiently driven. In addition, the MOS transistor 41 can drive a sufficiently large current even when the antifuse 40 is blown / not blown, so that the capacitor antifuse 40 can be blown / not blown at high speed.

  FIG. 10A schematically shows a structure of a circuit using the capacitor type antifuse according to the second embodiment of the present invention. FIG. 10 shows a 1-bit configuration of the antifuse circuit in the program circuit.

  10A, the antifuse circuit is turned on in response to deactivation (L level) of memory cycle start instruction signal RAS, and p channel MOS transistor 50 charges node C3 to power supply voltage Vcc level. In the program operation mode (fuse blow cycle), the n-channel MOS transistor 51 that is selectively set in a conducting state according to the signal Ad and the voltage level of the node C3 in the normal operation mode are determined, and the antifuse 40 is blown / An inverter circuit 52 that generates a signal BLOW indicating non-blown is included. The antifuse 40 has the configuration shown in FIG. 9A, and is shown in FIG. 9A as a decoupling transistor in order to prevent a high voltage from being applied to the node C3 during the fuse blow cycle. A MOS transistor 41 is used. MOS transistor 41 has a gate node NG coupled to receive power supply voltage Vcc. Next, the operation of the antifuse circuit shown in FIG. 10A will be described with reference to the operation waveform diagram shown in FIG.

  In the fuse blow (program) cycle, the signal RAS is first set from L level to H level. When memory cycle start instruction signal RAS is inactivated, MOS transistor 50 is in a conductive state, and node C3 is held at the H level. The antifuse 40 has a relatively large resistance (for example, 5 KΩ or more) even during conduction (when blown). Therefore, instruction signal BLOW is at the H level.

  In the fuse blow cycle, first, memory cycle start instruction signal RAS is raised to H level, and MOS transistor 50 is set in a non-conductive state. Thereby, the H level precharge operation to the node C3 is completed. Next, the signal Ad is set to the H level or the L level according to the program data, and a high voltage for programming is applied to the node C4. When MOS transistor 51 becomes conductive, node C3 falls to the ground voltage level, and a high voltage is applied to antifuse 40. When the voltage applied to the capacitor type antifuse 40 exceeds the withstand voltage of the antifuse 40, the antifuse 40 undergoes dielectric breakdown, and a current flows from the node C4 to the ground node via the node C3. MOS transistor 51 has a relatively large channel resistance, and the voltage level of node C3 increases according to the resistance value of antifuse 40 and the resistance value of MOS transistor 51. When voltage level of node C3 exceeds the input logic threshold value of inverter circuit 52, fusing instruction signal BLOW rises to H level. The decoupling transistor 41 can only transmit the voltage Vcc-Vth to the high voltage applied to the node C4, and transmission to the node C3 is prevented.

  On the other hand, when signal Ad is at L level, MOS transistor 51 is turned off. Node C3 is in a state precharged to the level of power supply voltage Vcc by MOS transistor 50. Therefore, even if a high voltage is applied to the node C4, the voltage applied between the electrodes of the antifuse 40 does not exceed the withstand voltage of the antifuse 40, so that the antifuse 40 is held in an unblown state. Therefore, the signal BLOW maintains the L level as shown by the broken line in FIG.

  When a predetermined time elapses, the fuse blow cycle is completed, the memory cycle start instruction signal RAS is driven to the L level, and the high voltage application to the node C4 is stopped.

  In the normal operation mode, the signal Ad is set to L level. When memory cycle start instruction signal RAS rises to the H level, MOS transistor 50 is turned off. In the normal operation mode, MOS transistor 51 is always in a non-conductive state. Therefore, the voltage level of node C3 is determined according to the blown / non-blown state of the antifuse. When the antifuse 40 is blown (fuse blown), the node C3 is discharged through the MOS transistor 41 and the antifuse 40. Here, node C4 is held at the ground voltage level in the normal operation mode. Therefore, signal BLOW rises to the H level, and data stored in the antifuse circuit is read out. On the other hand, when antifuse 40 is not blown, there is no path for discharging current to node C3. Therefore, node C3 maintains H level and signal BLOW from inverter circuit 52 maintains L level.

The antifuse 40 can be blown by the above-described operation.
Note that the configuration of the program circuit (anti-fuse circuit) shown in FIG. 10A is an example, and other configurations may be used.

  As described above, the number of components of the program circuit is reduced by using the MOS transistor T of the unit element as a decoupling transistor for preventing the transmission of a high voltage during the program operation (during the fuse blow cycle). And the area occupied by the circuit can be reduced.

  As described above, according to the second embodiment of the present invention, the MOS transistor of the unit element is used not as an antifuse but as a constituent element of a program circuit (antifuse circuit). The area can be reduced.

[Embodiment 3]
FIG. 11A schematically shows a cross-sectional structure of the program element according to the third embodiment of the present invention. FIG. 11A shows a cross-sectional structure of a capacitor in one unit element. In FIG. 11A, the capacitor is formed with a conductive layer 57 electrically connected to an impurity region 56 formed on the surface of the semiconductor substrate region 55 and a capacitor insulating film 58 on the conductive layer 57. And a low resistance conductive layer 60 formed on and electrically connected to the conductive layer 59. Conductive layer 57 corresponds to a storage node of the memory cell capacitor, and conductive layer 59 corresponds to a cell plate electrode of the memory cell capacitor. The conductive layer 59 corresponding to the cell plate electrode is provided in common for the plurality of capacitor elements. A low resistance conductive layer 60 is formed through a contact hole at a position facing the conductive layer 57 for each of the capacitive elements.

  FIG. 11B is a diagram schematically showing a planar layout of the capacitor having the cross-sectional structure shown in FIG. As shown in FIG. 11B, a contact hole 61 is formed so as to overlap with the conductive layer 57 in plan view, and the low resistance conductive layer 60 and the conductive layer 59 are electrically connected through the contact hole 61. Connected.

  In the memory cell capacitor, the cell plate electrode layer and the electrode layer serving as a storage node are formed of polysilicon. This polysilicon layer is doped with impurities at a high concentration in order to reduce the resistance. Since the capacitor element of the capacitor type antifuse has the same structure as the memory cell capacitor, these conductive layers 57 and 59 are also formed of a polysilicon layer doped with impurities at a high concentration. The low resistance conductive layer 60 is made of aluminum, for example. When the low resistance conductive layer 60 is electrically connected to the conductive layer 59, the low resistance conductive layer 60 is formed and patterned under a certain temperature condition. In the conductive layer 59, when the contact is formed, the doped impurities move to the capacitor insulating film 58, and the characteristics of the capacitor insulating film 58 change. Normally, when impurities move to the capacitor insulating film 58, electron / hole traps are formed in the capacitor insulating film 58, and the insulating characteristics of the capacitor insulating film 58 deteriorate. Therefore, the contact hole 61 is formed opposite to the conductive layer 57 corresponding to the storage node and electrically connected to the upper low-resistance conductive layer 60, so that the withstand voltage characteristic of the capacitive element can be lowered. The voltage level applied during programming can be lowered. As a result, even in a semiconductor device driven at a low voltage, it is possible to program the program element with a relatively low voltage.

  In the structure shown in FIG. 11A, low resistance conductive layer 60 may be used as one electrode node of the program element, and conductive layer 59 corresponding to the cell plate electrode layer is an electrode node of the program element. May be used as However, the low-resistance conductive layer 60 may simply be provided corresponding to each capacitive element in order to reduce the breakdown voltage of the capacitive element.

[Modification 1]
FIG. 12A schematically shows a configuration of the first modification of the third embodiment of the present invention. In FIG. 12A, the cross-sectional structure of one MOS capacitor is schematically shown. 12A, impurity regions 71a and 71b are formed on the surface of semiconductor substrate region 70. In FIG. A gate electrode layer 73 is formed on the channel region between impurity regions 71a and 71b with gate insulating film 72 interposed. The gate electrode layer 73 is electrically connected to the upper conductive layer 74 on the channel region. A field insulating film 75 for element isolation is formed so as to surround impurity regions 71a and 71b.

  FIG. 12B schematically shows a planar layout of the MOS capacitor shown in FIG. In FIG. 12B, impurity regions 71 (71a, 71b) are formed so as to surround the gate electrode layer 73. The gate electrode layer 73 is electrically connected to the upper conductive layer 74 through a contact hole 76 formed so as to overlap with the channel region in plan view. In FIG. 12B, the upper conductive layer 74 is not shown in order to simplify the drawing.

  As shown in FIGS. 12A and 12B, a contact hole 76 is formed on the channel region in the MOS capacitor structure. Therefore, when forming the contact hole and forming the electrical contact between the upper conductive layer 74 and the gate electrode layer 73, the impurity doped in the gate electrode layer 73 diffuses into the gate insulating film 72, and the breakdown voltage of the gate insulating film 72 is increased. Decreases. Therefore, the withstand voltage of the MOS capacitor can be lowered, and the MOS capacitor can be used as an antifuse.

  In a normal MOS transistor structure, the breakdown voltage of the gate insulating film is set high in order to ensure the reliability, and the PN junction breakdown voltage (the breakdown breakdown voltage of the junction between the impurity region 71 and the substrate region 70) is set. And higher than the source-drain breakdown voltage. This is because a high electric field tends to be generated in the vicinity of the drain or the like when the MOS transistor is normally operated, and the high electric field is stably operated. Therefore, when such a normal MOS transistor structure is used as a capacitor-type antifuse, when a high voltage is applied for programming, junction breakdown or a source-drain short-circuit occurs, which can be used as a programming element. become unable. However, as shown in FIGS. 12A and 12B, a contact hole is formed in the channel region, and the gate electrode layer is electrically connected to the conductive layer thereabove, thereby reducing this withstand voltage. can do. As a result, in the peripheral circuit region, a MOS transistor having the same structure as a normal peripheral circuit MOS transistor can be used as a capacitor-type antifuse, and an extra manufacturing process for forming the antifuse is not required.

  In the MOS capacitor structure shown in FIGS. 12A and 12B, conductive layer 74 serves as one electrode node C1 of the program element, and impurity region 71 (71a, 71b) serves as the other electrode node C2 of the program element. Become.

[Modification 2]
FIG. 13 schematically shows a configuration of a second modification of the third embodiment of the present invention. In FIG. 13, the program element is formed in an N well 77 formed on the surface of the semiconductor substrate 76. Impurity regions 71a and 71b are formed using N well 77 as a substrate region. Other configurations are the same as those shown in FIGS. 12A and 12B, and corresponding portions are denoted by the same reference numerals. In the configuration shown in FIG. 13, N well 77 having the same conductivity type as impurity regions 71a and 71b is used as a substrate region. Therefore, a capacitor type antifuse having the same structure as a normal parallel electrode type capacitor is realized. Also in this case, a contact hole is formed on the region between impurity regions 71a and 71b, and gate electrode layer 73 and conductive layer 74 are electrically connected through this contact hole. Therefore, the breakdown voltage of the gate insulating film 72 can be lowered.

  In this N well 77, one MOS transistor may be formed or a plurality of MOS transistors may be formed. In this case, in the DRAM cell, a desired number of MOS transistors having the same size as the access transistor can be formed in the same process as the access transistor manufacturing process. Even in cell structures where capacitors are not used for information storage, such as SRAM (Static Random Access Memory) and Flash Memory (Batch Erase EEPROM), memory cell manufacturing process or peripheral MOS transistor manufacturing The MOS transistor for this capacitor type antifuse can be formed in the same process as the process. As a result, a capacitor type antifuse having a low breakdown voltage can be realized without increasing the number of manufacturing steps. A plurality of MOS capacitors may be connected in parallel as antifuses.

  As described above, according to the third embodiment of the present invention, the other electrode node is electrically connected to another conductive layer through the contact hole in the region facing one electrode of the capacitive element used as the program element. With this configuration, the withstand voltage of the capacitive element can be reduced, and accurate programming can be performed using a low program voltage. Further, the capacitor element can be formed in the same process as the memory cell or peripheral circuit manufacturing process, and the program element can be easily manufactured without increasing the number of manufacturing process steps.

[Embodiment 4]
FIG. 14 is a diagram illustrating the configuration of the program circuit according to the fourth embodiment of the present invention. FIG. 14 shows a configuration of a portion of the antifuse circuit related to a 1-bit address signal. In FIG. 14, the antifuse circuit includes first and second capacitor type antifuses 80a and 80b. Each of these capacitor type antifuses 80a and 80b includes a capacitive element having the same structure as the memory cell capacitor, similarly to the structure in the first or second embodiment. In the first capacitor type antifuse 80a, one electrode node is coupled to the node ND1, and the other electrode node is connected to the node ND3 through the MOS transistor 81a. In the second capacitor type antifuse 81b, one electrode node is connected to the node ND3, and the other electrode node is connected to the node ND1 through the MOS transistor 80b. MOS transistor 81a receives control signal φ1 at its gate, and MOS transistor 80b receives control signal φ3 at its gate. These MOS transistors 81a and 81b include MOS transistor elements having the same structure as that of the access transistor of the memory cell (see the first embodiment).

  The antifuse circuit further determines whether the capacitor type antifuse is blown or not blown according to the MOS transistor 82 connected between the nodes ND2 and ND4 and receiving the control signal φ2 at its gate, and the signal potential of the node ND2. The determination part 85 which outputs the signal to perform is included. Determination unit 85 includes a precharge element that precharges node ND2 to a predetermined potential, and an inverter circuit that determines the voltage level of node ND2.

  In an integrated DRAM, the memory cell size is reduced. In accordance with this miniaturization, the capacitor insulating film of the memory cell capacitor is also thinned to ensure a sufficient capacitance value with a small occupation area. Even in this thin capacitor insulating film, in order to guarantee the withstand voltage characteristics, an intermediate voltage Vcc / 2 is normally applied to the cell plate electrode node in the memory cell capacitor. A power supply voltage Vcc or a ground voltage level voltage is transmitted to the storage node of the memory cell capacitor. As a result, in the memory cell capacitor, only the maximum voltage Vcc / 2 is applied in the normal operation mode, and an excessive voltage is applied to the thin capacitor insulating film to prevent the dielectric breakdown.

  When a capacitive element having the same characteristics as this memory cell capacitor is used as an antifuse, in the normal operation mode, the power supply voltage Vcc is applied between the capacitors in the conventional configuration. For this reason, an excessive voltage is applied to the capacitor-type antifuse in a non-blown state, reliability cannot be guaranteed, and program data cannot be stored accurately (when dielectric breakdown occurs).

  Therefore, in the antifuse circuit shown in FIG. 14, in the fuse blow cycle (in the program operation mode), the first and second antifuses are connected in parallel and the stored information is programmed with a low program voltage. In the normal operation mode, these antifuses 80a and 80b are connected in series, and a maximum voltage of Vcc / 2 is applied to each of antifuses 80a and 80b. Next, the operation of the antifuse circuit shown in FIG. 14 will be described.

(I) Fuse blow program:
First, with reference to FIG. 15A, the applied voltage during the fuse blow program of the antifuse circuit will be described. As shown in FIG. 15A, in the fuse blow program, control signals φ1 and φ3 are set at the H level, and control signal φ2 is set at the L level. Node ND1 is coupled to receive ground voltage GND, and high voltage HV for programming is transmitted to node ND3. Since the control signal φ2 is at the L level, the MOS transistor 82 becomes non-conductive, and the voltage level of the node ND2 is arbitrary (don't care state).

  In the voltage application shown in FIG. 15A, capacitor type antifuses 80a and 80b are connected in parallel between nodes ND1 and ND3, as shown in FIG. 15B. High voltage HV for programming is applied to node ND3, and node ND1 is at the GND level of the ground voltage level. Therefore, dielectric breakdown occurs in these capacitor type antifuses 80a and 80b, and the capacitor type antifuses 80a and 80b become conductive.

(Ii) Fuse non-blow program:
In the fuse non-blow program, all the control signals φ1 to φ3 are set to the L level as shown in FIG. High voltage HV for programming is transmitted to node ND3, and ground voltage GND is transmitted to node ND1. In this state, MOS transistors 81a, 81b and 82 are all non-conductive. Therefore, as shown in FIG. 16B, capacitor type antifuse 80a has one electrode node coupled to node ND1 and the other electrode node in a floating state. Capacitor type antifuse 80b has one electrode node coupled to node ND3 and the other electrode node in a floating state. Therefore, even when the high programming voltage HV is applied to the node ND3, no high voltage is applied between the electrodes of the antifuses 80a and 80b, and dielectric breakdown does not occur. Thereby, capacitor type antifuses 80a and 80b are programmed to a non-conductive state.

(Iii) In normal operation mode:
As shown in FIG. 17A, in the normal operation mode, control signal φ1 is set to L level, and control signals φ2 and φ3 are set to H level. In this state, MOS transistor 81a is turned off, and MOS transistors 81b and 82 are turned on. Ground voltage GND is transmitted to node ND3, and node ND1 is set in an open state (floating state). In this state, as shown in FIG. 17B, capacitor type antifuses 80a and 80b are connected in series between nodes ND4 and ND3. Node ND4 is precharged to power supply voltage Vcc level by precharging node ND2 in the normal operation mode. Therefore, the capacitance values of these capacitor type antifuses 80a and 80b are equal. Due to the capacitance division of the capacitor type antifuses 80a and 80b, the voltage level of the node ND1 becomes approximately Vcc / 2. Therefore, only the maximum voltage Vcc / 2 is applied to capacitor type antifuses 80a and 80b. Even if a capacitor element having the same structure as that of the memory cell capacitor is used for the capacitor type antifuses 80a and 80b, only a voltage having the same magnitude as the voltage that is constantly applied to the memory cell capacitor is applied. The characteristics are guaranteed, and stored information can be held stably without causing dielectric breakdown.

  The configuration of determination unit 85 only needs to include an inverter circuit that inverts the voltage level of node ND2 and a precharge circuit that precharges node ND2 to power supply voltage Vcc level. Since the programming operation is performed with MOS transistor 82 in a non-conductive state, MOS transistor (MOS transistor 51 shown in FIG. 10) for forming a current path is not particularly used in determination unit 85.

  FIG. 18 is a diagram schematically showing a configuration of a control unit of a 1-bit antifuse circuit. In FIG. 18, the anti-fuse circuit is turned on when receiving a program address signal bit Ad and generating a control signal φ1, a node 86 receiving a power supply voltage Vcc, and a program mode instruction signal PM. N channel MOS transistor 88 transmitting upper address signal bit Ad to generate control signal φ3 and conductive when program mode instructing signal PM is inactive, transmit power supply voltage Vcc on power supply node 86 to control signal p channel MOS transistor 89 for generating φ3 and inverter circuit 90 for inverting program mode instruction signal PM to generate control signal φ2.

  These MOS transistors 88 and 89 may be composed of CMOS transmission gates. A set of MOS transistors 87, 88, 89 is provided corresponding to each antifuse circuit. The control signal φ2 from the inverter circuit 90 is generated in common to the antifuse circuits for one address, and is commonly supplied to the antifuse circuits related to these one address (each receiving different address signal bits).

  Antifuse circuit further conducts when program mode instruction signal PM is activated, and conducts in response to n channel MOS transistor 91 transmitting ground voltage GND to node ND1 and activation (H level) of control signal φ2. N channel MOS transistor 92 transmitting ground voltage GND to node ND3, and p channel MOS transistor 93 conducting when control signal φ2 is inactive (L level) and transmitting high voltage HV to node ND3. .

  In the program operation mode, address signal bit Ad of node 85 is set to H level or L level according to the defective address. MOS transistor 88 is rendered conductive, and control signals φ1 and φ3 are set to H level or L level according to address signal bit Ad.

  In the normal operation mode, address signal bit Ad on node 85 is fixed at the L level. Therefore, control signal φ1 is fixed at the L level, and MOS transistor 81a of the antifuse circuit is held in a non-conductive state. On the other hand, MOS transistor 89 is turned on, control signal φ3 is fixed to H level, and MOS transistor 81b of the antifuse circuit is fixed to the conductive state.

  In the program operation mode, node ND3 receives program high voltage HV through MOS transistor 93, and in the normal operation mode, node ND3 receives ground voltage GND through MOS transistor 92. Node ND1 receives ground GND through MOS transistor 91 in the program operation mode, and is maintained in the floating state in MOS operation mode 91 in the normal operation mode.

  By utilizing the configuration shown in FIG. 18, the capacitor type antifuse can be programmed in accordance with the address signal bit Ad to be programmed in each antifuse circuit.

The node 86 may be a node connected to a normal power supply line.
Alternatively, the program high voltage HV and the ground voltage GND may be selectively transmitted from the program control circuit 6a shown in FIG. 2 to the node ND3 according to the operation mode. As a circuit for generating high voltage HV for programming, for example, in a DRAM, an output signal of a high voltage generation circuit for driving a word line boosted voltage used for boosting a word line can be used. Further, a configuration in which this high voltage HV is externally applied in the program operation mode may be used.

  In the configuration described above, control signals φ1 and φ3 are set to the H level or the L level according to the address signal bit to be programmed in the program operation mode. Instead, in the program operation mode, the control signals φ1 and φ3 are always in the H level state, and the high voltage HV or the ground voltage GND is selectively transmitted to the node ND3 according to the address signal bit Ad to be programmed. A configuration may be used. For this purpose, it is only necessary to use a configuration in which MOS transistors 92 and 93 shown in FIG. 18 are supplied with an inverted signal (shown in parentheses) of address signal bit Ad to be programmed. The number of capacitive elements constituting the antifuse may be one.

  As described above, according to the fourth embodiment of the present invention, the capacitor type antifuse having the same structure as the memory cell capacitor structure is connected in parallel in the program operation mode and connected in series in the normal operation mode. Therefore, in the normal operation mode, only a voltage of Vcc / 2 is applied between the capacitor type anti-fuse electrodes, and it is possible to prevent the breakdown voltage characteristics from being deteriorated and to accurately program. An antifuse circuit capable of holding information can be realized.

[Embodiment 5]
FIG. 19 is a diagram illustrating the relationship between the voltage between electrodes of a capacitor and the current. In FIG. 19, when the voltage between the electrodes is V1, dielectric breakdown occurs, and a large current I flows. On the other hand, when a voltage is applied in the reverse direction, dielectric breakdown occurs at the voltage −V2. In general, a capacitor has asymmetry in dielectric strength characteristics, as shown in FIG. The general reason why this withstand voltage characteristic is asymmetric in the positive and negative directions of the interelectrode voltage will be described below.

  FIG. 20A shows a cell plate electrode layer 95 and a storage node electrode layer 96 of the memory cell capacitor. Usually, since a constant voltage is transmitted to the cell plate electrode layer 95, an impurity (n-type impurity) is doped at a high concentration in order to sufficiently reduce its resistance. On the other hand, the conductive node of storage node electrode layer 96 has a relatively small doping amount (however, the resistance is reduced) in order to prevent adverse effects due to diffusion to the substrate region. Therefore, the cell plate electrode layer 95 and the storage node electrode layer 96 have different impurity doping amounts. The cell plate electrode layer 95 and the storage node electrode layer 96 are formed of a polysilicon layer and have characteristics as semiconductors. When the impurity concentration is different in such a semiconductor layer, the energy band is bent in the interface region.

  A capacitor element having both the cell plate electrode layer 95 and the storage node electrode layer 96 as electrodes is used as a capacitor. The voltage of conductive layer 95 corresponding to the cell plate electrode is set higher than that of conductive layer 96 corresponding to the storage node electrode. In this case, in the capacitor insulating film, the same amount of charge as that induced by the conductive layer 95 is generated at the interface with the conductive layer 96.

  When the voltage of the conductive layer 96 is positively biased with respect to the conductive layer 95, a so-called n + / i / n junction becomes a “reverse bias state”, and a depletion layer spreads in the conductive layer 96. This depletion layer is usually formed in the conductive layer 96. This depletion layer is a region where no electric charge exists and acts as a capacitance. Therefore, in this state, the electric field applied to the capacitor insulating film is reduced by this depletion layer, so that the withstand voltage is increased. In the opposite case, the depletion layer does not expand, and the withstand voltage is determined by the withstand voltage of the insulating film itself.

  Further, consider a case where a MOS capacitor is used as shown in FIG. In this case, the MOS capacitor includes high-concentration impurity regions 98a and 98b formed on the surface of semiconductor substrate region 97, and gate electrode layer 99 formed on a channel region between impurity regions 98a and 98b. In the MOS capacitor, a depletion type MOS capacitor is usually used. In order to prevent the influence of the threshold voltage of the MOS transistor and to efficiently form a channel layer, the surface of the channel region is doped with n-type impurities. In this state, when the gate electrode layer 99 is biased to a positive voltage with respect to the substrate region 97, electrons are attracted to the surface of the channel region by the gate electrode layer 99, so that a so-called accumulation state is obtained, and a normal capacitor is formed. The

  Conversely, when the gate electrode layer 99 is biased to a negative voltage with respect to the substrate region 97, electrons are repelled from the interface by the negative voltage of the gate electrode layer 99, and the channel region is depleted. And the formed depletion layer spreads. Therefore, when the substrate region 97 is biased to a positive voltage with respect to the gate electrode layer 99, the depletion layer expands, and equivalently, the applied electric field between the gate electrode layer 99 and the substrate region 97 is reduced, and the dielectric breakdown voltage is reduced. Becomes higher.

  Further, in a normal capacitor insulating film or gate insulating film, a multilayer film such as an OMO film (oxide film-nitride film-oxide film) is used. In such a multilayer film, the thickness of each layer is different, so the electric field applied to each insulating film differs depending on the voltage application direction. Such asymmetry of the film thickness of the multilayer film is also one of the causes of the asymmetry of the pressure resistance characteristics.

  Utilizing such asymmetry of the withstand voltage characteristic of the capacitor, in the fifth embodiment, dielectric breakdown is caused in the direction of higher withstand voltage, and in the normal operation, it is used in the opposite direction.

  That is, as shown in FIG. 21A, at the electrode nodes C5 and C6 of the capacitor type antifuse 100, the high voltage HV is applied to the electrode C6 in the program operation mode. The capacitor type antifuse 100 has a high breakdown voltage when the electrode node C6 is positively biased with respect to the electrode node C5. In the direction in which the withstand voltage is higher, the program high voltage HV is applied, and the capacitor-type antifuse 100 is blown. Therefore, the capacitor-type antifuse 100 is reliably blown.

  In the normal operation mode, as shown in FIG. 21B, the electrode node C5 is biased to a positive voltage with respect to the electrode node C6. In the normal operation mode, the electrode node C5 is precharged to the power supply voltage Vcc. Electrode node C6 is coupled to receive ground voltage GND. When the electrode node C5 is biased to a positive voltage with respect to the electrode node C6, the withstand voltage of the capacitor type antifuse 100 is lowered. A voltage lower than the low breakdown voltage is applied between the electrode nodes C5 and C6. Therefore, the capacitor type anti-fuse whose breakdown has been destroyed (fuse blown) is surely in the fuse blow state, and the determination of fuse blow / non-blow can be made accurately.

  Consider a case where a program is executed in the reverse direction, that is, the direction shown in FIG. 21B, and a normal operation is performed by applying a voltage in the direction shown in FIG. In this case, in FIG. 19, the breakdown occurs when the voltage −V2 is applied, but the breakdown does not occur when the voltage V1 is applied. Therefore, it is impossible to accurately determine the blow / non-blow determination of the fuse (the blown fuse may be determined as the non-blow fuse).

  As shown in FIGS. 21A and 21B, by applying a program high voltage in a direction in which the withstand voltage is high, the antifuse to be blown is surely brought into a blown state regardless of the direction of the voltage between the electrodes. can do.

  For the voltage application of the capacitor type antifuse shown in FIGS. 21A and 21B, the configuration shown in FIGS. 10A and 14 can be used. The electrode nodes may be appropriately connected according to the characteristics of the formed program element (antifuse).

  Note that the capacitor characteristics shown in FIGS. 20A and 20B are general characteristics. In an actual manufacturing process, a capacitor having different characteristics may be formed. In this case, in the prototype production stage, general characteristics of the capacitor (memory cell capacitor or MOS capacitor) are measured, and the direction in which the withstand voltage is high may be determined based on the measured parameters. When manufacturing an actual product, a monitor chip may be formed together, the characteristics of the capacitor of the monitor chip may be measured, and confirmation of the direction of the withstand voltage characteristic of the capacitor may also be performed.

  As described above, according to the fifth embodiment of the present invention, the applied voltage polarity of the capacitor type antifuse is set according to the asymmetry of the withstand voltage characteristic of the capacitor during program operation (fuse blow operation) and normal operation. Therefore, it is possible to confirm whether the capacitor antifuse is blown or not blown reliably, and it is possible to accurately maintain the blown state of the capacitor antifuse even during normal operation. Furthermore, it is possible to determine whether the antifuse is blown or not blown.

[Embodiment 6]
FIGS. 22A and 22B are diagrams showing voltage application modes of the capacitor type antifuse according to the sixth embodiment of the present invention. 22A shows a voltage application mode during the program operation, and FIG. 22B shows a voltage application mode during the normal operation mode.

  In FIG. 22A, the capacitor type antifuse 100 has a memory cell capacitor structure or a MOS capacitor structure, and a program high voltage HV is applied to electrodes C7 and C8 with a voltage polarity in a direction with a lower withstand voltage. . Now, it is assumed that the capacitor type antifuse 100 has a low breakdown voltage when the electrode node C8 is positively biased with respect to the electrode node C7. In this state, the program high voltage HV is applied to the electrode node C8.

  In the normal operation mode, as shown in FIG. 22B, power supply voltage Vcc is applied to electrode node C8, and electrode node C7 is coupled to the ground voltage level. That is, a voltage of the same polarity is applied to the capacitor type antifuse 100 in the program operation mode and the normal operation mode. Since the program high voltage is applied in the direction of lower withstand voltage characteristics, the voltage level of the program high voltage HV can be lowered, and dielectric breakdown can easily occur.

  In order to realize the voltage application shown in FIGS. 22A and 22B, there is a method of switching the connection of the antifuse electrode nodes in the normal operation mode in the configuration of the antifuse circuit shown in FIG. is there. However, in this case, the circuit configuration becomes complicated.

  FIG. 23A schematically shows a structure of an antifuse circuit used in the sixth embodiment of the present invention. 23A, the antifuse circuit includes a decoupling transistor 104 connected between the electrode node C7 and the node 108 of the capacitor type antifuse 102, a signal potential on the node 108 inverted, and a fusing instruction signal / Inverter circuit 105 that outputs BLOW, p-channel MOS transistor 106 that conducts when control signal / TPM is activated, precharges node 108 to the level of power supply voltage Vcc, and node 108 is selectively grounded according to control signal φPA. An n-channel MOS transistor 107 that discharges to a level is included. Next, operation of the antifuse circuit illustrated in FIG. 23A will be described with reference to a signal waveform diagram illustrated in FIG.

  In the program operation mode, first, control signal / TPM is set to L level, and node 108 is precharged to power supply voltage Vcc level via MOS transistor 106.

  When the program cycle starts, control signal / TPM becomes H level and MOS transistor 106 is turned off. Control signal φPA is set to H level or L level in accordance with address signal bit Ad to be programmed to be stored. A high voltage HV for programming is applied to the electrode node C8.

  If control signal φPA is at H level, MOS transistor 107 is turned on, node 108 is driven to the ground voltage level, a high voltage is applied between electrode nodes C8 and C7 of capacitor type antifuse 102, and capacitor type antifuse. 102 is set to a blow (melting) state. When control signal φPA is at L level, MOS transistor 107 is non-conductive, node 108 maintains power supply voltage Vcc level, and no high voltage is applied between electrodes C7 and C8 of capacitor type antifuse 102. Therefore, the capacitor type antifuse 102 is held in a non-blow state (non-blown state).

  When the program cycle is completed in FIG. 23B, control signal / TPM is set to L level, and node 108 is precharged to power supply voltage Vcc level.

  In the normal operation mode, control signal / TPM is held at the H level, and power supply voltage Vcc is applied to node C8. Control signal φPA functions as an operation cycle defining signal and changes in synchronization with memory cycle start instruction signal RAS. Therefore, in the normal operation mode, node 108 is precharged to the ground voltage level in accordance with control signal φPA, and blowing instruction signal / BLOW from inverter circuit 105 is set to the H level. When the normal operation cycle (active cycle) starts, the control signal φPA becomes L level, and the MOS transistor 107 is turned off. If antifuse 102 is in a conductive state, power supply voltage Vcc applied to node C8 is transmitted to node 108, and fusing instruction signal / BLOW falls to the L level. When capacitor type antifuse 102 is in a non-blown state, no current flows from electrode node C8 to node 108, so that node 108 maintains the L level and blowing instruction signal / BLOW maintains the H level. In this control operation mode, the program state of the antifuse circuit can be read by looking at the H level / L level of the fusing instruction signal / BLOW.

  The state of the fusing instruction signal / BLOW differs between the program cycle and the normal operation mode. However, in the program cycle, it is only required to program whether the capacitor type antifuse 102 is blown or not blown, and even if the state differs from the blow instruction signal / BLOW in the normal operation mode, there is a particular problem. Does not occur.

  FIG. 24 schematically shows a structure of a portion for generating the control signal shown in FIG. In FIG. 24, the control signal generating portion is turned on when the program mode instruction signal PM is activated (at the H level), and the n-channel MOS transistor 110 for passing the program address signal bit Ad and the inactivation of the program mode instruction signal PM. P channel MOS transistor 112 that conducts when activated and passes memory cycle start instruction signal RAS, n channel MOS transistor 114 that conducts when program mode instruction signal PM is activated and passes memory cycle start instruction signal RAS, and program It includes a p-channel MOS transistor 116 which is rendered conductive when mode instruction signal PM is activated and allows power supply voltage Vcc to pass therethrough. First conduction nodes of MOS transistors 110 and 112 are commonly coupled to output control signal / φPA. MOS transistors 114 and 116 have a first conduction node coupled in common to output control signal / TPM. In each antifuse circuit, MOS transistors 110 and 112 are provided. MOS transistors 114 and 116 are provided in common to the plurality of antifuse circuits, and transmit control signal / TPM to the plurality of antifuse circuits in common.

  In program mode (program cycle), control signal φPA is generated in accordance with program control address signal bit Ad, and control signal / TPM is generated in accordance with memory cycle start instruction signal RAS. On the other hand, since program mode instruction signal PM is at the L level in the normal operation mode, control signal φPA is generated in accordance with the inverted signal of memory cycle start signal RAS, and control signal / TPM is fixed at power supply voltage Vcc level. Is done.

  In the configuration of the control signal generator shown in FIG. 24, the address bit to be stored is a row address signal bit. When the address signal bit to be stored is a column address signal bit, a column selection operation start instruction signal CAS is used instead of the memory cycle start instruction signal RAS. This signal RAS may be converted into an appropriate signal according to the contents of stored information to be programmed.

  The configuration shown in FIG. 18 can be used as the configuration for selectively transmitting high voltage HV and ground voltage GND to electrode node C8 shown in FIG. The electrode node C8 may be fixedly set at the ground voltage level during a bonding process before package mounting.

  If the ratio between the resistance value of the blown antifuse 102 and the channel resistance of the MOS transistor 107 is set so that the voltage at the node 108 is higher than the input logic threshold value of the inverter 105 during the normal cycle, the signal φPA may be set to H level during a normal cycle (φPA = RAS).

  As described above, according to the sixth embodiment of the present invention, the applied voltage polarity of the capacitor type antifuse is the same in the program operation mode and the normal operation mode. The state can be confirmed easily and reliably (because the polarity of the withstand voltage characteristic of the capacitor does not change). Further, by programming in the direction of lower withstand voltage characteristics, the capacitor-type antifuse can be easily blown (blown), and a relatively low voltage can be used as the program high voltage.

[Embodiment 7]
FIG. 25A schematically shows a structure of an antifuse circuit according to the seventh embodiment of the present invention. In the configuration of the antifuse circuit shown in FIG. 25A, a latch circuit 120 that latches the output signal of the inverter circuit 105 in response to the activation of the latch trigger instruction signal TLR is provided at the output portion of the inverter circuit 105. . A trigger signal / TTR that is activated in the form of a one-shot pulse at the start of the memory cycle is applied to the node of p channel MOS transistor 106 that precharges node 108. Node C8 is at the ground voltage level. Other structures are the same as those shown in FIG. 23A, and corresponding portions bear the same reference numerals.

  The latch circuit 120 inverts the output signal of the inverter 105 and outputs a fusing instruction signal BLOW, and is activated when the latch instruction signal TLR is activated. The latch circuit 120 inverts the output signal of the inverter 120a and A tri-state inverter 120b for transmitting to the input unit is included. Next, the operation of the antifuse circuit shown in FIG. 25A will be described with reference to the operation waveform diagram shown in FIG.

  In the program operation, an operation similar to the operation waveform shown in FIG. During normal operation, the operation cycle of the antifuse circuit is defined by read cycle start signal / RAS.

  In the standby state where memory cycle start instruction signal / RAS is in an inactive state of H level, control signal φPA is at H level, signal / TTR is at H level, and latch trigger instruction signal TLR is at L level. In this state, node 108 is discharged to the ground voltage level via MOS transistor 107, and fusing instruction signal BLOW is also held at the L level.

  When the read cycle starts, in response to the activation of the memory cycle start instruction signal (row address strobe signal), control signal φPA is inactivated to L level, and then trigger signal / TTR is set to L level for a predetermined period. The Thereby, node 108 is charged to power supply voltage Vcc level through MOS transistor 106. When the capacitor type antifuse 102 is in a blown state, the charging voltage of the node 108 is discharged to the electrode node C8 receiving the ground voltage via the capacitor type antifuse 102.

  On the other hand, when capacitor-type antifuse 102 is in a non-blown state, there is no path through which current flows, so that node 108 is held at power supply voltage Vcc level. When the charging operation of node 108 is completed and the voltage level of node 108 is stabilized, latch instruction signal TLR is activated, tristate inverter 120b is activated, and latch circuit 120 inverts the output signal of inverter 105. And latch. Therefore, when the capacitor type antifuse 102 is in a blown state, the blown instruction signal BLOW is held at the L level as in the standby state. On the other hand, when the capacitor type antifuse 102 is in a non-blown state, the blown instruction signal BLOW is Driven to H level. When the memory cycle is completed, memory cycle start instruction signal / RAS is driven to the H level, control signal φPA is again set to the H level, and latch trigger instruction signal TLR is set to the L level. Thereby, node 108 is discharged to the ground voltage level. Further, the fusing instruction signal BLOW returns to the L level.

  As shown in FIG. 25A, by charging the node 108 to the power supply voltage Vcc level in the form of a one-shot pulse, there is a short period between the electrodes C7 and C8 of the non-blown capacitor type antifuse. The power supply voltage Vcc is applied only during the interval. As a result, the power supply voltage Vcc is not continuously applied during the memory cycle, the voltage stress of the capacitor type antifuse can be alleviated, and the insulation characteristics of the unfused capacitor type antifuse are deteriorated. Can be prevented, and a highly reliable program circuit can be realized.

  In the configuration shown in FIG. 25A, the fusing instruction signal BLOW may be extracted from the output of the inverter circuit 105.

  Alternatively, a configuration may be used in which precharge instruction control signal φPA is activated after latch circuit 120 is in a latched state. This is easily realized by making the driving force of the tri-state inverter 120b larger than the driving force of the inverter circuit 105. In this configuration, a configuration may be used in which inverter circuit 105 is activated / deactivated in a complementary manner to tristate inverter 120b in response to latch instruction signal TLR.

  According to this configuration, the period during which the power supply voltage is applied between the electrodes of the capacitor-type antifuse in the non-blown state can be further shortened. In the standby cycle, the voltage between the electrodes of the capacitor type antifuse is 0 V, and the voltage stress applied to the capacitor type antifuse can be greatly reduced.

  In the configuration shown in FIG. 25A, the power supply voltage of the electrode node C8 is applied as shown by the broken line waveform in FIG. 25B, and the precharge voltage of the node 108 is changed between the standby cycle and the normal memory cycle. An opposite configuration may be used (H-level precharge, one-shot L-level precharge, fusing / non-blown operation sequence). During standby, signal / TTR is at L level, and node 108 is precharged to power supply voltage Vcc level. The voltage between the electrodes of the antifuse 102 is 0V. In the active cycle, signal / TTR is set to H level and signal φPA is driven to H level in the form of a one-shot pulse, and node 108 is discharged to the ground voltage level.

  FIG. 26 schematically shows a structure of a portion for generating the control signal shown in FIG. In FIG. 26, the control signal generation unit buffers the memory cycle start instruction signal / RAS to generate the precharge instruction control signal φPA, and responds to the fall of the output signal of the buffer circuit 130. One shot pulse generation circuit 131 that outputs a trigger signal / TTR that is L level for a predetermined period of time, a rise delay circuit 133 that delays the rise of the trigger signal / TTR output from the one shot pulse generation circuit 131, and a memory cycle start instruction Inverter 132 that receives signal / RAS, and an AND circuit 134 that receives the output signal of inverter 132 and the output signal of rise delay circuit 133 and outputs latch instruction signal TLR are included.

  When memory cycle start instruction signal / RAS is in the active state at the L level, precharge instruction control signal φPA is in the inactive state at the L level. In response to the deactivation of precharge instruction control signal φPA, one-shot pulse generation circuit 131 generates a one-shot pulse signal that is at L level for a predetermined period. The output signal of this one-shot pulse generation circuit 131 is used as a trigger instruction signal / TTR. Thereby, node 108 is precharged to power supply voltage Vcc level for a predetermined period. When the precharge operation is completed, the output signal from rising delay circuit 133 rises to H level after a predetermined period. On the other hand, the output signal of inverter 132 becomes H level in response to activation of memory cycle start instruction signal / RAS. Therefore, after completion of the precharge operation to the power supply voltage Vcc level, the AND circuit 134 activates the latch instruction signal TLR after the voltage level of the determination node (node 108) is stabilized, and this state is the memory cycle. It is held while the start instruction signal / RAS is active.

  Note that by appropriately changing the configuration of the control signal generator shown in FIG. 26, it is possible to adopt a configuration in which node 108 is precharged to the ground voltage level after activation of latch instruction signal TLR (precharge instruction signal). Activation of φPA). This is realized by using a signal obtained by OR (logical sum) of the precharge instruction signal φPA and the inverted signal of the latch instruction signal PLR as the precharge instruction signal to the ground voltage level in the configuration shown in FIG. Is done. Also, the broken line waveform sequence of FIG. 25B can be easily realized.

  As described above, according to the seventh embodiment of the present invention, the power supply voltage is applied to the capacitor type antifuse in the form of a one-shot pulse in the normal operation mode. The voltage stress applied to the capacitor-type antifuse in the state can be greatly reduced, and the deterioration of the insulation characteristics can be prevented.

[Embodiment 8]
Corresponding to each of address program circuits 142 # 1-142 # n, in accordance with test mode instruction signal TEST, each of spare activation signals SAT # 1-SAT # n and corresponding address program circuits 142 # 1-142 # n outputs Switching circuit 144 # 1-144 # n that selectively passes one of signals MA # 1-MA # n, and corresponding spare element 140 # 1 according to output signals SS1-SSn of switching circuits 144 # 1-144 # n Spare element selection circuits 146 # 1-146 # n for driving .about.140 # n to the selected state are provided.

  Test mode instructing signal TEST is activated during the failure / good detection operation of the spare element of the failure relief circuit or the address program circuit.

  In the defect relief circuit shown in FIG. 27, a defective address program is programmed by address program circuit 142 # 1. It is determined whether or not the spare element 140 # 1 operates normally. When spare element 140 # 1 is defective, use of spare element 140 # 1 is stopped and another spare element and address program circuit are used. Even if spare element 140 # 1 operates normally, address program circuit 142 # 1 is not used when address program circuit 142 # 1 is defective (for example, when a capacitor type antifuse is defective). Therefore, a set of a plurality of address program circuits and spare elements can be prepared for one defective element (normal cell row or normal cell column). As a result, the spare element can be further relieved in the redundant configuration, so that the chip yield can be improved.

  FIG. 28 is a flowchart showing a program operation of the defect relief circuit shown in FIG. Hereinafter, the programming procedure of the defect relief circuit shown in FIG. 27 will be described with reference to FIG.

  First, first spare element 140 # 1 and corresponding address program circuit 142 # 1 are designated (i is set to 1) (step ST1). A defective address to be relieved is programmed to address program circuit 142 # i (step ST2). Then, test mode instruction signal TEST is activated to cause switching circuit 144 # i to select spare activation signal SAT # i and activate spare element 140 # i corresponding to spare element selection circuit SSi. A functional test (such as a short circuit) of activated spare element 140 # i is performed to determine whether or not the spare element is defective (steps ST3 and ST4). If the function test result of spare element 140 # i indicates the presence of a defect, the process proceeds to step ST5. Address program circuit 142 # i and spare element 140 # i cannot be used. Therefore, i is incremented by one and the program operation for next address program circuit 142 # i + 1 is performed again. On the other hand, when spare element 140 # i is normal, an address signal is applied to address program circuit 142 # i to select spare element 140 # i and a functional test of spare element 140 # i is performed (step) ST6).

  In this case, since spare element 140 # i is operating normally, it is only necessary to determine whether or not spare element 140 # i is driven to the selected state, so that data writing / reading is performed. This normal / bad can be identified. If the result of the functional test in step ST6 indicates that a defect exists, the address program circuit 142 # i has a defect. If it is determined in defect determination step ST7 that there is a defect in address program circuit 142 # i, i is incremented by 1 in step ST5, and the program operation is performed for the next address program circuit 142 # i + 1. The operations after step ST2 are repeatedly executed.

  If it is determined in step ST7 that it is normal, address program circuit 142 # i and spare element 140 # i are operating normally, so that address programming is performed normally and normal operation is performed. Even in the mode, it is possible to surely repair a defective element. This operation is executed for each defective address.

  Steps ST1, ST3 and ST4 are performed, normal / abnormal of spare element 140 # i is performed according to spare activation signal SAT # i, and when spare element 140 # i is determined to be normal, the corresponding address A technique in which program circuit 142 # i is programmed may be used.

  FIG. 29 schematically shows a configuration of address program circuits 142 # 1-142 # n shown in FIG. FIG. 29 representatively shows address program circuit 142 # i.

  29, address program circuit 142 # i is provided corresponding to each of address signal bits A0-Ak, and provided corresponding to each of antifuse circuits 150-0-150-k and address signal bits A0-Ak. Are coupled in parallel to the mismatch signal detection circuit 152-0 to 152-k receiving the output signals of the antifuse circuits 150-0 to 150-k corresponding to the address bits A0 to Ak, and the output signal line 156, respectively. N-channel MOS transistors 154-0 to 154-k receiving the output signals of mismatch detection circuits 152-0 to 152-k, and P-channel MOS for precharging output signal line 156 to power supply voltage Vcc level in accordance with precharge instruction signal φPRG A precharge circuit 158 including a transistor is included.

  Each of the antifuse circuits 150-0 to 150-k includes a capacitor type antifuse, and a corresponding address signal bit is programmed by blowing or not blowing the capacitor type antifuse. In the normal operation mode, a signal (BLOW or / BLOW) indicating blowing / non-melting is output. Next, the operation of address program circuit 142 # i shown in FIG. 29 will be described.

  When address signal ADD is applied, address signal bits A0 to Ak are first applied to respective first inputs of mismatch detection circuits 152-0 to 152-k. The antifuse circuits 150-0 to 150-k output signals according to the state of the capacitor type antifuse. When the output signal patterns from the antifuse circuits 150-0 to 150-k match the address signal bit patterns A0 to Ak, the output signals of the mismatch detection circuits 152-0 to 152-k all become L level, and the MOS Transistors 154-0 to 154-k are non-conductive, and signal MA from output signal line 156 is held at the H level.

  On the other hand, when there is a mismatch even with one bit, at least one output signal of the mismatch detection circuits 150-0 to 150-k becomes H level. Accordingly, at least one of MOS transistors 154-0 to 154-k is turned on, output signal line 156 is discharged to the ground voltage level, and signal MA goes to L level. When this signal MA is at the H level, the defective address is addressed, so that the corresponding spare element is activated and the defective address is relieved.

  The antifuse circuits 150-0 to 150-k only have to have a configuration in which each output signal matches the bit of the defective address, and any of the previous embodiments may be used.

  FIG. 30 is a diagram showing an example of the configuration of the switching circuit shown in FIG. In FIG. 30, switching circuit 144 # i (144 # 1-144 # n) conducts in response to inverter 160 for inverting test mode instruction signal TEST, and output signals of test mode instruction signal TEST and inverter 150, Responsive to CMOS transmission gate 162 that passes spare activation signal SAT # i, test mode instruction signal TEST, and the output signal of inverter 160, and complementary to CMOS transmission gate 162, the corresponding address program circuit A CMOS transmission gate 164 that passes the output signal MAi is included. Output signals of these CMOS transmission gates 162 and 164 are applied as spare selection signal SSi to the spare element selection circuit.

  In the structure shown in FIG. 30, one of test spare activation signal SAT # i generated externally or internally and one of output signal MAi from the corresponding address program circuit is generated according to the operation mode by the CMOS transmission gate. Is selected and transmitted to the spare element selection circuit. Thus, the signal path for moving the spare element selection circuit can be switched according to the operation mode.

  FIG. 31A shows an example of the configuration of the spare element selection circuit shown in FIG. FIG. 31A shows a configuration of a spare element selection circuit when the spare element is a spare word line SWL.

  In FIG. 31A, spare element selection circuit 146 # i is connected between inverter circuit 170 receiving spare element activation signal SSi provided from the corresponding switching circuit, between the high voltage node and spare word line SWL, Conductive when the output signal of inverter circuit 170 is at L level and conductive when P channel MOS transistor 171 charges spare word line SWL to high voltage Vpp level, and when the output signal of inverter circuit 170 is at H level, spare word line N channel MOS transistor 172 for discharging SWL to the ground voltage level is included. Spare word line SWL is driven to the high voltage Vpp level in the selected state.

  When a match is detected in the corresponding address program circuit, output signal MAi of the corresponding address program circuit is at the H level. Therefore, the output signal of inverter circuit 170 becomes L level, and spare word line SWL is driven to the selected state. Thereby, defect repair by redundant replacement is performed.

  Inverter circuit 170 may have a level conversion function, and when the spare word line SWL is at L level, a so-called P channel MOS transistor is provided for charging the output part of the inverter circuit 170 to the high voltage Vpp level. A “half latch” type word line drive circuit may be used. The configuration of the spare element selection circuit is arbitrary. Spare word line SWL may have a hierarchical structure, and further, a spare decoder is provided, and a configuration in which one spare sub word line of a plurality of spare word lines is driven to a selected state is used. Good.

  The corresponding spare element may be driven to the selected state by the spare selection circuit in accordance with the coincidence detection signal from the corresponding address program circuit.

  FIG. 31B is a diagram showing another configuration of the spare element selection circuit. FIG. 31B shows a configuration of a spare element selection circuit when the spare element is a spare memory cell column.

  In FIG. 31B, spare element selection circuit 146 # i operates by receiving inverter circuit 173 receiving spare selection signal SSi, power supply voltage Vcc and ground voltage as operating power supply voltages, and inverting the output signal of inverter 173. And a CMOS inverter for outputting spare column selection signal SCSL. This CMOS inverter includes a P-channel MOS transistor 174 and an n-channel MOS transistor 175 connected in series between an output node and a ground node and receiving the output signal of inverter circuit 173 at each gate.

  In the configuration shown in FIG. 31B, when spare selection signal SSi is at H level (when coincidence detection signal MAi is at H level), the output signal of inverter circuit 173 is at L level, and accordingly, spare column selection is performed. Signal SCSL is driven to the H level. Thus, the repair is performed by replacing the defective column with the spare column.

  When spare selection signal SSi is at L level, spare column selection signal SCSL is at L level and redundant replacement is not performed.

[Example of change]
FIG. 32 is a flowchart showing the operation of the modification of the eighth embodiment of the present invention. The operation of the modification of the eighth embodiment of the present invention will be described below with reference to the flowchart shown in FIG.

  In this modification, an address program circuit is provided for each spare element. Similarly, a spare selection circuit is provided for a spare element, but no switching circuit is provided.

  First, initialization is performed (i is set to 1) (step ST11). Then, a defective address is programmed for address program circuit 142 # i (step ST12). Next, this address program circuit is operated, the corresponding spare element is driven to the selected state, and a function test of the spare element is executed (step ST13).

  Based on this functional test, it is determined in step ST14 whether or not there is a defect in the spare element. When a defect exists, at least one of address program circuit 142 # i and spare element 140 # i is defective. In this case, address program circuit 142 # i and spare element 140 # i are not used, and i is incremented by 1 to select the next set of address program circuit and spare element (step ST1). Next, the processes after step ST12 are performed again.

  If it is determined in step ST14 that it is normal, address program circuit 142 # i and corresponding spare element 140 # i are functioning normally, and the defective address programming operation is completed. Next, the next defective address is programmed. When all the defective address programs are completed, the program processing for defect repair is completed.

  In the processing procedure of this modification, it is not necessary to use the switching circuit using the test mode instruction signal TEST. Simply, it is determined whether the address program circuit and spare element set is good or bad, and if it is defective, the defective set is replaced with another address program circuit and spare element. Thereby, the time required for the program can be shortened.

  As described above, according to the eighth embodiment of the present invention, since the defect relief circuit for relieving a defective normal element has a redundant configuration, for example, even if a program failure occurs due to a failure of a capacitor type antifuse, It can be replaced by an address program circuit, and a reduction in chip yield can be reduced.

  In the eighth embodiment, it is preferable that the capacitor type antifuse used in the antifuse circuit is composed of a capacitor element having the same structure as the memory cell capacitor or transistor. However, the eighth embodiment can be applied even if it is constituted by a normal capacitor or a MOS capacitor.

[Embodiment 9]
FIG. 33 shows a structure of a main portion of the semiconductor device according to the ninth embodiment of the present invention. 33, the semiconductor device includes a constant current source 180 that supplies a constant current from a power supply node 179, a programmable resistance circuit 182 that converts a current from the constant current source 180 into a voltage and generates a reference voltage Vref, Anti-fuse circuits 185-1 to 158-m for adjusting the resistance value of this programmable resistance circuit 182 are included. The programmable resistance circuit 182 is provided in parallel with each of the resistance elements R0 to Rm connected in series between the output node and the ground node, and the resistance elements R1 to Rm, and anti-fuse circuits 185-1 to 185 are provided at the respective gates. N-channel MOS transistors TR1 to TRm that receive an output signal of −m are included.

  Antifuse circuits 185-1 to 185-m have the capacitor type antifuses of the first to seventh embodiments, and the capacitor type antifuses are programmed according to the conduction / non-conduction state of the corresponding transistor.

  If the number of conducting transistors among the transistors TR1 to TRm decreases, the resistance value of the programmable resistance circuit 182 increases and the voltage level of the reference voltage Vref increases. On the other hand, if the number of conducting transistors among the transistors TR1 to TRm decreases, the resistance value of the programmable resistance circuit 182 decreases, and the voltage level of the reference voltage Vref decreases. Therefore, the resistance value of the programmable resistor circuit 182 can be adjusted by programming the capacitor type antifuse included in the antifuse circuits 185-1 to 185-n to generate the reference voltage Vref at the optimum level. it can.

  When the antifuse circuits 185-1 to 185-m are used, an appropriate switching signal (AD) is applied to the antifuse circuits 185-1 to 185-m in the test operation mode, and the transistors TR1 to TRm are applied. Of these, the transistors to be turned off can be programmed equivalently. Based on the data obtained in the test mode, the antifuse circuits 185-1 to 185-m are executed. When optimizing the resistance value of the programmable resistance circuit 182, the capacitor type antifuse is set in a non-conductive state without applying a high voltage, and the output signal of the antifuse circuit is set by the switching signal (AD) in the test operation mode. A control signal can be generated from the antifuse circuits 185-1 to 185-m. At the time of programming, a high voltage is applied and a signal pattern corresponding to the optimum value is applied to the antifuse circuits 185-1 to 185-m. Thereby, both the antifuse circuits 185-1 to 185-m can be used in the test operation mode and the program operation mode, and the circuit configuration is simplified.

[Example of change]
FIG. 34 shows a structure of a modification of the ninth embodiment of the present invention. In the configuration shown in FIG. 34, output signal φop from antifuse circuit 190 is used as an operation mode designation signal. The operation mode of the semiconductor device is designated according to this signal φop. This signal φop may also be used to set the word configuration (number of data bits). A so-called “bonding option” function such as a word configuration and an operation mode that has been conventionally set by bonding or mask arrangement can be set in accordance with the output signal φop of the antifuse circuit 190. In this case, a pad for switching the mode or word configuration becomes unnecessary.

  Further, the antifuse circuit can be used in place of a fuse element used in a laser trimming process that has conventionally been blown / not blown by a laser beam or the like. In this case, a combination of an anti-fuse circuit and a switching transistor that becomes conductive / non-conductive in response to the output signal is used in place of the fuse element.

  When a memory cell capacitor is used, the memory cell capacitor only needs to have a three-dimensional structure. In the case of a stacked capacitor, the capacitor structure may have any configuration such as a cylindrical shape, a T-shape, or a fin shape. Further, the present invention can be applied even to a capacitor having a trench structure.

  In particular, in the case of a MOS capacitor configuration that does not use a memory cell capacitor, the present invention can be applied to any MOSIC.

1 schematically shows an entire configuration of a semiconductor device according to the present invention. FIG. FIG. 2 is a diagram schematically showing a configuration of a redundant replacement control circuit shown in FIG. 1. FIG. 3 is a diagram showing a configuration of a program circuit shown in FIG. 2. FIG. 4 schematically shows an internal structure of the program circuit shown in FIG. 3. It is a figure which shows the structure of the modification 1 of Embodiment 1 of this invention. (A) shows a configuration of a second modification of the first embodiment of the present invention, and (B) shows an electrical equivalent circuit of the configuration shown in (A). It is a figure which shows schematically the structure of the modification 3 of Embodiment 1 of this invention. It is a figure which shows schematically the structure of the modification 4 of Embodiment 1 of this invention. (A) shows a configuration of a program element according to the second embodiment of the present invention, and (B) shows an electrical equivalent circuit of the configuration shown in (A). (A) schematically shows a configuration of an antifuse circuit according to the second embodiment of the present invention, and (B) is a signal waveform diagram showing an operation of the antifuse circuit shown in (A). (A) shows a cross-sectional structure of a program element according to the third embodiment of the present invention, and (B) schematically shows a planar layout of the configuration shown in (A). (A) shows a cross-sectional structure of a modified example of Embodiment 3 of the present invention, and (B) schematically shows a planar layout of the configuration shown in (A). It is a figure which shows schematically the structure of the modification 2 of Embodiment 3 of this invention. It is a figure which shows schematically the structure of the antifuse circuit according to Embodiment 4 of this invention. (A) shows the applied voltage in the program operation mode of the antifuse circuit shown in FIG. 14, and (B) is a diagram showing an electrical equivalent circuit of the configuration shown in (A). (A) is a figure which shows the applied voltage at the time of the blow of a fuse of the circuit shown in FIG. 14, (B) is a figure which shows the electrical equivalent circuit of the circuit shown to (A). (A) shows the applied voltage in the normal operation mode shown in FIG. 14, and (B) shows an electrical equivalent circuit of the circuit shown in (A). It is a figure which shows the structure of the part which generate | occur | produces the control signal shown in FIG. It is a figure which shows the pressure | voltage resistant characteristic of the capacitor in Embodiment 5 of this invention. (A) And (B) is a figure for demonstrating an asymmetric pressure | voltage resistant characteristic. (A) shows the direction of applied voltage at the time of programming in the fifth embodiment of the present invention, and (B) is a diagram showing the direction of capacitor applied voltage in the normal operation mode in the fifth embodiment of the present invention. . (A) shows the direction of voltage application during programming according to the sixth embodiment of the present invention, and (B) shows the direction of voltage applied to the capacitor during the normal operation mode according to the sixth embodiment of the present invention. It is. (A) is a diagram schematically showing a configuration of an antifuse circuit for applying a voltage shown in FIGS. 22 (A) and (B), and (B) is a signal showing an operation of the circuit shown in (A). It is a waveform diagram. It is a figure which shows schematically the structure of the part which generate | occur | produces the control signal shown to FIG. 23 (A). (A) is a figure which shows roughly the structure of the antifuse circuit according to Embodiment 7 of this invention, (B) is a signal waveform diagram which shows operation | movement of the circuit shown to (A). FIG. 26 is a diagram schematically showing a configuration of a control signal generation unit shown in FIG. It is a figure which shows roughly the structure of the defect relief circuit according to Embodiment 8 of this invention. It is a flowchart which shows the program procedure in the structure shown in FIG. FIG. 28 schematically shows a configuration of an address program circuit shown in FIG. 27. It is a figure which shows an example of a structure of the switching circuit shown in FIG. (A) and (B) are diagrams showing a configuration of a spare element selection circuit shown in FIG. It is a flowchart which shows the operation | movement of the example of a change of Embodiment 8 of this invention. It is a figure which shows roughly the structure of the semiconductor device of Embodiment 9 of this invention. It is a figure which shows the example of a change of Embodiment 9 of this invention. It is a figure which shows an example of a structure of the conventional antifuse circuit. (A) is a signal waveform diagram showing the operation of the circuit shown in FIG. 35 during programming, and (B) is a signal waveform diagram showing the operation of the circuit shown in FIG. 35 in the normal operation mode.

Explanation of symbols

  2 normal array, 3 spare array, 5 normal cell selection circuit, 6 redundant replacement control circuit, 7 redundant cell selection circuit, 6a program control circuit, 6b program circuit, 6c comparison / determination circuit, WL0 to WL1 word line, BL0, / BL0, BL1, / BL1 bit line, MC memory cell, MT access transistor, MS memory cell capacitor, PRa to PRn program unit element, TMOS transistor, S capacitor element, 10 word line equivalent conductive layer, 11a to 11n bit line equivalent Conductive layer, 12 conductive wiring, 13 cell plate line equivalent conductive wiring, PRp to PRu program unit element, 25 cell plate line equivalent conductive wiring, 26 bit line equivalent conductive wiring, 27p to 27u word line equivalent conductive wiring, 31 N well, 32a to 32d impurity regions , 34a, 34b, 135 conductive layer, DPRa, DPRb dummy program unit element, 6ba antifuse placement region, 6bb program peripheral circuit, MA memory array, 40 capacitor type antifuse, 41 decoupling transistor, 57 storage node equivalent conductive layer, 59 cell plate line equivalent conductive layer, 60 upper layer wiring, 61 contact hole, 73 gate electrode layer, 74 upper layer conductive wiring, 76 contact hole, 71a, 71b impurity region, 77 N well, 80a, 80b capacitor type antifuse, 81a, 81b MOS transistor, 82 decoupling transistor, 85 determination unit, 100 capacitor type antifuse, 104 decoupling transistor, 106 P channel MOS transistor, 10 7 n-channel MOS transistor, 105 inverter circuit, 120 latch circuit, 140 # 1-140 # m spare element, 142 # 1-142 # m address program circuit, 144 # 1-144 # m switching circuit, 146 # 1-146 #M Spare element selection circuit, 150-0 to 150-k antifuse circuit, 152-0 to 152-k mismatch detection circuit, 154-0 to 154-k MOS transistor, 156 output signal line, 158 precharge circuit, 185 -1 to 185-m, 190 Antifuse circuit, 182 Programmable resistance circuit.

Claims (9)

A gate and a MOS capacitor formed of an insulated gate field effect transistor having a first and a second impurity region formed on the surface of the substrate region and connected to each other; And electrically connected to the upper conductive wiring via a contact hole formed on the channel region between the first and second impurity regions, and the first and second impurity regions serve as one electrode of the MOS capacitor. And a conductive control line serving as the other electrode of the MOS capacitor, and a program control circuit for applying a program voltage between one electrode and the other electrode of the MOS capacitor in a program operation mode.   The semiconductor device according to claim 1, wherein the first and second impurity regions of the MOS capacitor have the same conductivity type as the substrate region. A program capacitor element having first and second electrode nodes and having a high breakdown voltage and a low breakdown voltage according to the applied voltage polarity of the first and second electrode nodes, and a voltage that provides the high breakdown voltage in the program operation mode A semiconductor comprising: a program control circuit for applying a program voltage to the program capacitor element with polarity to program the program capacitor element and applying a voltage with a voltage polarity that gives the low breakdown voltage to the program capacitor element in a normal operation mode apparatus. A program capacitor element having first and second electrode nodes and having a high withstand voltage and a low withstand voltage according to the applied voltage polarity between the first and second electrode nodes, and a voltage polarity with a low withstand voltage in the program operation mode A semiconductor device comprising: a program control circuit that applies a program voltage between the first and second electrodes and applies a voltage between the first and second electrodes with a voltage polarity having a low withstand voltage in a normal operation mode. A program capacitor element having first and second electrode nodes and having a high withstand voltage and a low withstand voltage according to a polarity of an applied voltage between the first and second electrode nodes; and in a program operation mode and a normal operation mode, A semiconductor device comprising a program control circuit for applying a voltage with the same polarity between a first electrode and a second electrode. A plurality of memory cells each having a capacitor for storing information;
The semiconductor device according to claim 3, wherein the program capacitor element includes an element having the same structure as the capacitor. Capacitors,
Applying a program voltage to the capacitor in the program operation mode, causing dielectric breakdown to the capacitor selectively according to the stored information, and determining the stored information of the capacitor in the determination operation mode A semiconductor device comprising a program control circuit for applying a one-shot pulse signal between the electrodes of the capacitor in response to a signal.   In the determination operation mode, the program control circuit sets the first electrode of the capacitor to a first voltage level and sets the second electrode of the capacitor to a second voltage level in response to the state determination instruction signal. 8. The semiconductor device according to claim 7, further comprising means for making a determination in the form of a one-shot pulse and precharging the second electrode of the capacitor to the first voltage level when the determination operation mode is completed. Multiple regular elements,
A plurality of redundant elements for replacing and repairing defective normal elements of the plurality of normal elements, and a plurality of program circuits provided corresponding to each of the plurality of redundant elements, each programmed by dielectric breakdown of a capacitor The plurality of program circuits are programmed with information for specifying the defective normal element, and the plurality of program circuits and the plurality of redundant elements are used to relieve a defective program circuit and / or a corresponding defective redundant element. Can be a semiconductor device.

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