JP2008277747A - Nonvolatile semiconductor storage device and its data rewriting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device and a data rewriting method capable of suppressing a decrease in threshold voltage after rewriting with an increase in the number of rewritings. <P>SOLUTION: The electrically rewritable nonvolatile semiconductor storage device conducts an erasing with a hot carrier generated in a drain adjacent end part of a channel forming region by an avalanche breakdown. The channel forming region comprises a first channel forming region of the predetermined region from a drain, and a second channel forming region adjacent to the first channel forming region. Further, an impurity concentration of the second channel forming region is higher than that of the first channel forming region, and a boundary of the two channel forming regions is different from the drain adjacent end part but in an intermediate part between the drain adjacent end part and the source adjacent end part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a data rewriting method thereof.

In recent years, in a nonvolatile semiconductor memory device having a floating gate electrode and a control gate electrode, an avalanche breakdown is caused between a drain and a semiconductor substrate because data can be erased at a low voltage. Attention has been focused on a hot hole method in which data is erased by injecting into the floating gate electrode (see, for example, Patent Document 1).
JP-A-56-129374

  In the nonvolatile semiconductor memory device having a so-called stacked gate structure in which a floating gate electrode and a control gate electrode are stacked, the inventor drains electrons (hot electrons) in a high energy state among electrons from the source to the drain. The change in the threshold voltage Vt due to the number of rewrites was confirmed for the data writing by hot electrons to be in a data writing state by injecting the floating gate electrode in the vicinity and the data erasing by the hot hole accompanying the avalanche breakdown. It should be noted that the number of data in each number of rewrites was n = 5, and the rewrite temperature was 25 ° C. As a result, it was found that the threshold voltage Vt after writing (after electron injection) decreases as the number of rewrites increases. That is, there is a concern that the number of rewritable times is small.

  In view of the above problems, an object of the present invention is to provide a nonvolatile semiconductor memory device and a data rewriting method thereof that can suppress a decrease in threshold voltage after writing accompanying an increase in the number of times of rewriting.

  The inventor of the present invention is that the main factor of the decrease in the threshold voltage Vt after writing accompanying the increase in the number of rewrites is that a trap occurs in the insulating film due to avalanche breakdown at the time of data erasure, and the amount of electrons trapped in this trap is We found that it is to increase with the increase. The following invention is based on this finding.

  In order to achieve the above object, a non-volatile semiconductor memory device according to claim 1 is formed by separating a first conductivity type semiconductor substrate and a surface layer portion of a main surface of the semiconductor substrate from each other, Is a floating gate electrode as a gate electrode disposed via an insulating film on a channel formation region between the source and drain of the semiconductor substrate and the source and drain which are regions where the opposite second conductivity type impurities are diffused And an electrically rewritable non-volatile semiconductor comprising at least a part of the control gate electrode capacitively coupled to the floating gate electrode and erasing by hot carriers generated at the end near the drain of the channel formation region by avalanche breakdown The position of the electric field concentration portion (so-called pinch-off point) where the electric field strength in the channel formation region is the maximum at the time of writing is a storage device. Unlike proximal end portion, characterized in that it is within the middle portion between the source near the end and the vicinity of the drain end portion opposite to the vicinity of the drain end.

  According to the present invention, at the time of writing, electrons directed from the source to the drain can be brought into a high energy state at the electric field concentration portion in the intermediate portion between the end portion near the source and the end portion near the drain. That is, electrons in a high energy state can be injected into the floating gate electrode mainly in the electric field concentration portion in the channel formation region. Thus, since the electron injection position at the time of writing is different from the hot carrier injection position at the time of erasing, the amount of electrons captured by the trap of the insulating film at the time of writing can be reduced. And the fall of the threshold voltage after writing accompanying the increase in the frequency | count of rewriting can be suppressed.

  Note that the end of the channel formation region near the drain is a predetermined range from the end of the drain where hot carriers are generated during erasing, in other words, a range where traps are generated in the insulating film due to avalanche breakdown. Further, the source vicinity end portion is in the same width range as the drain vicinity end portion on the source side.

  Specifically, as described in claim 2, the distance between the electric field concentration portion and the drain vicinity end portion is preferably 0.06 μm or more. With such a configuration, it is possible to more effectively suppress a decrease in threshold voltage after writing accompanying an increase in the number of rewrites.

  Specifically, the first transistor including the first channel forming region from the source side end of the electric field concentration portion to the drain in the channel forming region, and the first channel as defined in claim 3 A second transistor including a second channel formation region adjacent to the formation region, and the floating gate electrode is in a neutral state; the absolute value of the threshold voltage of the second transistor is equal to the threshold voltage of the first transistor; It is preferable to make the configuration larger than the absolute value.

  With such a configuration, of the first channel formation region and the second channel formation region, both of which are of the first conductivity type, the second channel formation region has a second conductivity type rather than the first channel formation region. It becomes difficult to reverse. Therefore, the electric field concentration portion (pinch-off point) can be set near the source side end of the first channel formation region (near the second channel formation region side end).

  In the invention described in claim 3, for example, as described in claim 4, the control gate electrode is stacked between the floating gate electrode and capacitively coupled, and the floating gate electrode is formed on the channel formation region. In the middle of the channel forming region, the electric field concentration portion is located on the source side with respect to the portion facing the floating gate electrode or the portion facing the floating gate electrode. It is good also as a structure made into the vicinity site | part.

  As described above, in the so-called split gate structure nonvolatile semiconductor memory device in which the floating gate electrode is biased to the drain side of the channel formation region, the electron injection position at the time of writing is the hot carrier injection position at the time of erasing. Different positions can be used.

  For example, as described in claim 5, it is preferable that the first transistor includes a stack portion of the control gate electrode. With such a configuration, in the channel formation region, the source side end portion of the facing portion facing the floating gate electrode, or the vicinity portion adjacent to the source side end portion of the facing portion can be an electric field concentration portion. . In addition, since the gap between the juxtaposed portion of the control gate electrode and the floating gate electrode becomes a resistance component at the time of channel formation, this also causes the source side of the facing portion of the channel formation region facing the floating gate electrode. An end portion or a neighboring portion adjacent to the source-side end portion of the opposite portion can be easily set as an electric field concentration portion.

  In the invention described in claim 5, for example, as described in claim 6, the region from the boundary with the first channel formation region to the source is the second channel formation region, and the juxtaposed portion is the second channel formation region. A structure included in the transistor may be employed. With such a configuration, the configuration can be simplified. In addition, only a part of the source side region from the boundary with the first channel formation region can be used as the second channel formation region.

  According to a third aspect of the invention, as in the seventh aspect, the control gate electrode has only a laminated portion laminated with the floating gate electrode and capacitively coupled on the channel formation region. Also good.

  Even in a nonvolatile semiconductor memory device having such a structure (for example, a so-called stacked gate structure), the electron injection position at the time of writing can be set to a position different from the hot carrier injection position at the time of erasing.

  In the invention according to any one of claims 3 to 7, for example, as described in claim 8, the impurity concentration of the second channel formation region is made higher than the impurity concentration of the first channel formation region And good.

  Since the higher the impurity concentration, the more difficult the conductivity type is inverted to the opposite (opposite) conductivity type. With this configuration, the first channel formation region and the second channel formation region, both of which are the first conductivity type, are used. The second channel formation region is less likely to be inverted to the second conductivity type than the first channel formation region. Therefore, when the floating gate electrode is in a neutral state, the absolute value of the threshold voltage of the second transistor can be made larger than the absolute value of the threshold voltage of the first transistor.

  In the invention according to any one of claims 3 to 8, as described in claim 9, the insulating film interposed between the main surface of the semiconductor substrate and the floating gate electrode on the second channel formation region The thickness of the first channel formation region may be greater than the thickness of the insulating film interposed between the main surface of the semiconductor substrate and the floating gate electrode.

  Since the electric field decreases with respect to a constant control gate voltage as the insulating film is thicker, with this configuration, the first channel formation region and the second channel formation region, both of which are of the first conductivity type, are used. The second channel formation region is less likely to be inverted to the second conductivity type than the first channel formation region. Therefore, when the floating gate electrode is in a neutral state, the absolute value of the threshold voltage of the second transistor can be made larger than the absolute value of the threshold voltage of the first transistor.

  In the invention according to any one of claims 3 to 9, as described in claim 10, the floating gate electrode is provided on the first channel formation region and is interposed between the main surface of the semiconductor substrate. A first floating gate electrode portion in contact with the insulating film, and a first floating gate electrode portion provided on the second channel formation region and in contact with the insulating film interposed between the main surface of the semiconductor substrate and the first floating gate electrode portion A structure may be employed in which the first floating gate electrode portion and the second floating gate electrode portion are formed using materials having different work functions.

  As described above, even if the work functions of the constituent materials are different between the first floating gate electrode portion and the second floating gate electrode portion in the portion of the floating gate electrode on the channel formation region, the floating gate electrode In the neutral state, the absolute value of the threshold voltage of the second transistor can be made larger than the absolute value of the threshold voltage of the first transistor.

  For example, when the second conductivity type is an N conductivity type (the inversion layer is an N conductivity type) as in claim 11, the second floating gate electrode portion is configured as the first floating gate electrode portion. What is necessary is just to set it as the structure formed using the material whose work function is larger than material.

  In the invention according to any one of claims 3 to 11, as described in claim 12, the semiconductor substrate has a height higher than that of the first transistor on the main surface thereof from the back surface of the main surface. The transistor 2 may have a higher step, and the step may be made larger than the thickness of the inversion layer formed in the second channel formation region by applying a predetermined voltage to the control gate electrode. .

  With such a configuration, at the time of writing, electrons from the source to the drain are changed to a high energy state in the electric field concentration portion near the source side end portion of the first channel formation region, while being in a high energy state (hot Electrons) can be injected into the floating gate electrode without changing the traveling direction. Therefore, the writing efficiency can be further improved in combination with the effect described in any one of claims 3 to 11.

  Next, according to a thirteenth aspect of the present invention, a source and a drain which are second conductivity type impurity diffusion regions opposite to the first conductivity type are formed on the main surface of the first conductivity type semiconductor substrate so as to be separated from each other. In a non-volatile semiconductor memory device in which a floating gate electrode and a control gate electrode having a split gate structure are disposed on a channel formation region between a source and a drain of a semiconductor substrate via an insulating film, the source can be Among electrons toward the drain, electrons in a high energy state are injected into the floating gate electrode to make a data write state, and at the time of erasure, an avalanche breakdown is generated between the drain and the semiconductor substrate, and hot carriers associated therewith are generated. Is a method for rewriting data in a nonvolatile semiconductor memory device in which data is erased by injecting into the floating gate electrode. Among the control gate electrodes, the absolute value of the threshold voltage of the transistor including the stacked portion that is stacked and capacitively coupled with the floating gate electrode has a predetermined gap between the channel formation region and the floating gate electrode. Data is erased so as to be smaller than the absolute value of the threshold voltage of the transistors including the juxtaposed portions arranged side by side, and writing is performed from a state in which this threshold voltage relationship is satisfied.

  As described above, according to the present invention, in the initial stage of writing, an inversion layer (channel) is formed in the channel formation region at a portion facing the floating gate first, and the vicinity of the end of the inversion layer near the source side is It can be set as the electric field concentration part of the invention. That is, the electron injection position at the time of writing can be set to a position different from the hot carrier injection position at the time of erasing. Therefore, the amount of electrons trapped in the trap of the insulating film at the time of writing can be reduced, and a decrease in threshold voltage after writing accompanying an increase in the number of rewrites can be suppressed.

  In addition, as described in claim 14, when the potential of the control gate electrode is fixed at the same potential as the semiconductor substrate or a negative potential with respect to the semiconductor substrate at the time of erasing, the channel formation region is in a state before writing. Of these, it is more preferable because a facing portion facing the floating gate can be selectively brought into a depletion state (a state in which a channel is formed).

  First, before describing the embodiment of the present invention, the background of the inventor's creation of the present invention will be described. The present inventor investigated the cause of the decrease in the threshold voltage Vt after writing in the electrically rewritable nonvolatile semiconductor memory device with the increase in the number of rewrites. Specifically, the charge trapping method was used to measure the amount of charge trapped in the insulating film (oxide film) between the semiconductor substrate and the floating gate electrode in the so-called stacked gate nonvolatile semiconductor memory device. . As a result, as shown in FIG. 1, it was confirmed that the amount of electron capture after writing (after electron injection) increased as the number of rewrites increased. FIG. 1 is a diagram showing the relationship between the number of rewrites and the charge accumulation amount of the insulating film.

  This is because an electron trap is formed in the insulating film due to damage caused by avalanche breakdown during data erasing (hot hole injection), and an insulating film trap during data writing (electron injection into the floating gate electrode). Suggests that electrons are captured. The number of electrons trapped in the insulating film increases as the number of times of rewriting increases. As a result, the potential of the insulating film with respect to electrons increases, and the amount of electrons injected into the floating gate electrode decreases.

As described above, the present inventor found that the main cause of the decrease in the threshold voltage Vt after writing accompanying the increase in the number of rewrites is that a trap occurs in the insulating film due to avalanche breakdown at the time of data erasing, and the amount of electrons trapped in this trap And found that the number of rewrites increases with the increase in the number of rewrites. The present invention is based on this finding, and hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 2 is a cross-sectional view showing a schematic configuration of a main part of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. Note that the nonvolatile semiconductor memory device of the present invention has two gate electrodes, a floating gate electrode and a control gate electrode, and performs electrical erasure by hot carriers generated at the end near the drain of the channel formation region by avalanche breakdown. It is a rewritable nonvolatile semiconductor memory device. In the present embodiment, a nonvolatile semiconductor memory device having a so-called split gate structure will be described as an example.

  As shown in FIG. 2, the nonvolatile semiconductor memory device 1 includes a P-conductivity type (P) semiconductor substrate 10, and an impurity concentration of, for example, 1 × 10 20 cm is formed on the surface layer portion of the main surface of the semiconductor substrate 10. A source 20 and a drain 30 which are impurity diffusion regions of N conductivity type (N +) of about −3 are formed apart from each other. A region sandwiched between the source 20 and the drain 30 in the surface layer portion of the semiconductor substrate 10 is a channel formation region 11 of the nonvolatile semiconductor memory device 1.

  The channel formation region 11 causes electrons traveling from the source 20 to the drain 30 at the time of writing to be high not at the vicinity of the drain 30 where hot holes are generated at the time of erasing, but at an intermediate portion between the end near the drain and the end near the source. An energy state is set, and electrons (hot electrons) can be injected into the floating gate electrode 40 at the position. Specifically, in the channel formation region 11, the first channel formation region 12, which is a region from the source side end portion of the electric field concentration portion where the electric field intensity becomes maximum at the time of writing to the drain 30, and adjacent to the first channel formation region 12 And at least a second channel formation region 13 which is a region to be formed. The first channel forming region 12 corresponds to the first channel forming region described in the claims, and the second channel forming region 13 corresponds to the second channel forming region described in the claims. Note that the end of the channel forming region 11 near the drain is a region within a predetermined range from the end of the drain where hot carriers are generated during erasure, in other words, a region where a trap occurs in the first gate insulating film 60 due to avalanche breakdown. . The source vicinity end portion is a region having the same width as the drain vicinity end portion on the source 20 side.

  In the present embodiment, the channel formation region 11 is composed of the first channel formation region 12 and the second channel formation region 13, and the second channel formation region 13 extends to the source 20. Specifically, the regions surrounded by broken lines in FIG. 2 indicate the first channel forming region 12 and the second channel forming region 13, respectively, and a side-by-side portion 52 of the floating gate electrode 40 and the control gate electrode 50, which will be described later, The boundary between the two channel forming regions 12 and 13 is set within a range corresponding to the gap 90 between the two channel forming regions 12 and 13. The first channel formation region 12 has its impurity concentration adjusted to about 5 × 10 16 cm −3, and the second channel formation region 13 has its impurity concentration adjusted to about 1.5 × 10 17 cm −3. Yes. That is, the second channel formation region 13 has a higher concentration than the first channel formation region 12. The configuration of the channel formation region 11 is a characteristic part of the nonvolatile semiconductor memory device 1 of the present embodiment. The effect will be described later. The impurity concentration of the first channel formation region 12 may be the same as that of the semiconductor substrate 10 or may be higher than that of the semiconductor substrate 10. In the present embodiment, P-conductivity type impurities are implanted so that the concentration is higher than that of the semiconductor substrate 10.

  In the present embodiment, an example in which the source 20 and the drain 30 are formed in the semiconductor substrate 10 has been shown. However, the P substrate of the P conductivity type (P) having a higher concentration than the semiconductor substrate 10 is formed on the main surface of the semiconductor substrate 10. A well region may be formed, and the source 20 and the drain 30 may be formed in the well region.

  On the main surface of the semiconductor substrate 10, two gate electrodes 40 and 50, for example, a floating gate electrode 40 and a control gate electrode 50 formed by introducing impurities into a polycrystalline silicon film are disposed. As shown in FIG. 2, the floating gate electrode 40 is disposed on the channel formation region 11 so as to be biased toward the drain 30 side. Specifically, it is disposed on the first channel formation region 12 so as to influence the potential of the channel formation region 11 with the first gate insulating film 60 having a thickness of about 10 nm interposed therebetween. Therefore, the potential of the first channel formation region 12 can be changed in accordance with the charge accumulation state of the floating gate electrode 40 to form, for example, a channel in the region. In addition, the floating gate electrode 40 is also disposed opposite to the drain 30 and its vicinity, and a high energy state hole (hot hole) generated near the drain 30 is injected into the floating gate electrode 40 when erasing data. Can be made.

  A part of the control gate electrode 50 is stacked on the floating gate electrode 40 via the intermediate insulating film 70. The intermediate insulating film 70 electrically insulates the floating gate electrode 40 and the control gate electrode 50 and employs, for example, an insulating film (so-called ONO film) having a three-layer structure of oxide film-nitride film-oxide film. be able to. Of the control gate electrode 50, a stacked portion 51 stacked on (and in the vicinity of) the floating gate electrode 40 via the intermediate insulating film 70 and capacitively coupled to the floating gate electrode 40 is opposed to the first channel formation region 12. And serves as the gate electrode of the first transistor 2. The first transistor 2 corresponds to the first transistor recited in the claims, and is a memory cell transistor in the present embodiment.

  In addition, the control gate electrode 50 has a juxtaposed portion 52 that is arranged on the channel formation region 11 side by side with the floating gate electrode 40 with a predetermined gap 90. The juxtaposed portion 52 faces the second channel formation region 12 and serves as the gate electrode of the second transistor 3. The second transistor 3 corresponds to the second transistor described in the claims, and is a selection transistor in this embodiment. The juxtaposed portion 52 has a channel formation region 11 (second channel formation region 13) in which the floating gate electrode 40 is not disposed via a second gate insulation film 80 (for example, about 20 to 30 nm) thicker than the first gate insulation film 60. ) Opposed to the top. That is, the juxtaposed portions 52 are arranged in a biased manner toward the source 20 in the channel formation region 11. Therefore, in the vicinity of the source 20 in the channel formation region 11, the control gate electrode 50 can perform a current control function independently of the channel formation region 11.

  As described above, the nonvolatile semiconductor memory device 1 according to this embodiment has a split gate structure in which one control gate electrode 50 also functions as the gate electrode of the second transistor 3. In the present embodiment, when the floating gate electrode 40 is in a neutral state, the threshold voltage Vt1 viewed from the control gate electrode 50 of the first transistor 2 is about 0.8 V, as viewed from the control gate electrode 50 of the second transistor 3. The threshold voltage Vt2 is about 1V.

  The nonvolatile semiconductor memory device 1 having such a configuration can be formed by a known semiconductor process. As an example, first, a surface of a P-conductivity type (P) semiconductor substrate 10 is thermally oxidized to form a silicon oxide film that becomes the first gate insulating film 60, and a P-conductivity type such as boron is formed in the channel formation region 11. Impurities are implanted to form the first channel formation region 12 and the second channel formation region 13. Next, a polycrystalline silicon layer (first poly) to be the floating gate electrode 40 is formed on the silicon oxide film by a CVD method. Then, after an ONO film to be the intermediate insulating film 70 is formed on the polycrystalline silicon layer, selective etching is performed to form the first gate insulating film 60, the floating gate electrode 40, and the intermediate insulating film 70. Next, the surface of the semiconductor substrate 10 is thermally oxidized to form a silicon oxide film to be the second gate insulating film 80, and a polycrystalline silicon layer (second poly-silicon layer) to be the control gate electrode 50 is formed on the silicon oxide film by a CVD method. ). Then, the second gate insulating film 80 and the control gate electrode 50 are formed by selective etching. Thereafter, an N conductivity type impurity such as phosphorus is implanted into the semiconductor substrate 10 using the floating gate electrode 40 and the control gate electrode 50 as a mask, whereby the source 20 and the drain 30 are formed. For example, the nonvolatile semiconductor memory device 1 can be formed in this way. Other manufacturing methods can also be employed.

  Next, write / erase operations (data rewrite operations) of the nonvolatile semiconductor memory device 1 will be described with reference to FIG. 3A and 3B are diagrams for explaining the write / erase operation, where FIG. 3A shows writing and FIG. 3B shows erasing.

  Data is written by a channel hot electron (CHE) method which is a well-known method. Specifically, as shown in FIG. 3A, the source 20 is set to the same potential as the substrate potential, and the positive gate voltage (preferably 9 V or less) is applied to the drain 30 with respect to the substrate potential. A positive voltage larger than the voltage applied to the drain 30 (preferably 12 V or less) is applied to 50. In the present embodiment, as shown in FIG. 3A, the source 20 and the semiconductor substrate 10 are grounded, and 5 V is applied to the drain 30 and 8 V is applied to the control gate electrode 50.

  Here, in the present embodiment, the channel forming region 11 is composed of the first channel forming region 12 and the second channel forming region 13 of P conductivity type, and the impurity concentration of the second channel forming region 13 is set to the first channel forming region. It is higher than the area 12. That is, the second channel formation region 13 is configured to form a channel (N conductivity type inversion layer) less easily than the first channel formation region 12. In other words, the absolute value of the threshold voltage Vt2 viewed from the control gate electrode 50 of the second transistor 3 including the second channel formation region 13 is calculated from the control gate electrode 50 of the first transistor 2 including the first channel formation region 12. It is larger than the absolute value of the threshold voltage Vt1 seen.

  Therefore, at the time of writing, when the voltage applied to the control gate electrode 50 first exceeds the threshold voltage Vt 1 of the first transistor 2, an N conductivity type channel is formed in the first channel formation region 12. This state can be regarded as equivalent to a configuration in which the drain 30 extends to the end portion on the source side of the first channel formation region 12. Next, when the voltage applied to the control gate electrode 50 exceeds the threshold voltage Vt <b> 2 of the second transistor 3, an N conductivity type channel is also formed in the second channel formation region 13. At this time, since the channel is already formed in the first channel formation region 12, the source side end portion of the first channel formation region 12 is the electric field concentration portion (in other words, the electric field concentration portion having the maximum electric field strength in the channel formation region 11. Pinch-off point). Therefore, when electrons supplied from the source 20 move at high speed in the channel formation region 11 toward the drain 30 (that is, a channel current flows), high energy is generated in the vicinity of the source side end portion of the first channel formation region 12. State. Then, in the vicinity of the source side end portion of the first channel formation region 12, electrons (hot electrons) in a high energy state jump over the first gate insulating film 60 and are injected into the floating gate electrode 40. Thereby, data is written.

  If the threshold voltage Vt1 of the first transistor 2 including the first channel formation region 12 is too low, it takes a long time for electron injection during writing. Therefore, it is preferable to adjust the impurity concentration of the first channel formation region 12 and the thickness of the first gate insulating film 60 so as to be −4 V or higher.

  Data is erased by a hot hole (HH) method which is a well-known method. Specifically, a voltage equal to or negative with respect to the substrate potential is applied to the control gate electrode 50, the source 20 is set to a floating potential, and the drain 30 is connected to the semiconductor substrate 10 with respect to the substrate potential. A positive voltage (for example, about 5 to 12 V) that causes avalanche breakdown is applied. In this embodiment, as shown in FIG. 3B, the semiconductor substrate 10 is grounded, the source 20 is applied with the floating potential, the drain 30 is applied with 8V, and the control gate electrode 50 is applied with −2V. .

  Under the above-described conditions, as shown in FIG. 3B, an avalanche breakdown occurs between the drain 30 and the semiconductor substrate 10, and an avalanche current flows. A certain hole (hot hole) is injected into the vicinity of the drain of the floating gate electrode 40. As a result, the electrons injected into the floating gate electrode 40 are neutralized and data is erased.

  In addition, this inventor has confirmed said effect by simulation and actual measurement. The results are shown in FIGS. 4 to 6 are diagrams illustrating simulation results, and FIG. 7 is a diagram illustrating actual measurement results. FIG. 4 is a diagram showing the concentration distribution. 5A and 5B are diagrams showing the electric field strength distribution at the time of data writing. FIG. 5A shows the electric field strength distribution of the region 100 surrounded by the broken line in FIG. 4, and FIG. 5B shows the region 101 surrounded by the broken line in FIG. The electric field strength distribution is shown. 6A and 6B are diagrams showing the electric field intensity distribution at the time of erasing data. FIG. 6A shows the electric field intensity distribution of the region 100 surrounded by the broken line in FIG. 4, and FIG. 6B shows the region 101 surrounded by the broken line in FIG. The electric field strength distribution is shown. FIG. 7 is a diagram showing the relationship between the number of rewrites and the threshold voltage Vt. In FIG. 7, the result of the nonvolatile semiconductor memory device 1 according to the present embodiment is shown by a solid line. As a comparative example, a conventional nonvolatile semiconductor memory device in which the hot electron injection position and the hot carrier injection position are the same is used. The result is shown by a broken line. In addition, at the rewrite temperature of 25 ° C., five threshold voltage data were acquired for each rewrite count.

  As shown in FIG. 4, in the configuration in which the impurity concentration of the second channel formation region 13 is higher than the impurity concentration of the first channel formation region 12, the first channel formation region 11 is not adjacent to the drain 30 at the time of writing. It is clear from FIGS. 5 (a) and 5 (b) that the electric field concentration occurs in the vicinity of the source-side end portion. Further, it is clear from FIGS. 6A and 6B that electric field concentration occurs in the vicinity of the drain 30 during erasing. This result suggests that hot electrons are injected into the floating gate electrode 40 near the source side end of the first channel formation region 11 and hot carriers are injected into the floating gate electrode 40 near the drain 30. .

  Further, as shown in FIG. 7, it is clear that the nonvolatile semiconductor memory device 1 according to the present embodiment can suppress a decrease in the threshold voltage Vt after writing as compared with the conventional nonvolatile semiconductor memory device. .

  As described above, in this embodiment, the electrically rewritable nonvolatile semiconductor memory device 1 has a split gate structure and is erased by hot carriers generated at the end near the drain of the channel formation region 11 due to avalanche breakdown. 2, the channel forming region 11 is constituted by a first channel forming region 12 in a predetermined region from the drain 30 and a second channel forming region 13 adjacent to the first channel forming region 12. Then, the impurity concentration of the second channel formation region 13 is made higher than the impurity concentration of the first channel formation region 12, and the boundary between the two channel formation regions 12 and 13 is different from the end portion near the drain, unlike the end portion near the drain. And in the middle part between the source and the vicinity of the source. Therefore, at the time of writing, in the channel forming region 11, electrons from the source 20 to the drain 30 can be in a high energy state at an intermediate portion between the end portion near the source and the end portion near the drain. As a result, since the electron injection position at the time of writing and the hot carrier injection position at the time of erasing are different, the amount of electrons trapped in the trap of the first gate insulating film 60 at the time of writing is reduced, and the number of rewrites is increased. A decrease in threshold voltage Vt after writing can be suppressed. In other words, even if the number of rewrites increases, the threshold voltage Vt after writing can be set to a predetermined value in a short time.

  Further, in the present embodiment, the boundary between the first channel formation region 12 and the second channel formation region 13 is arranged so that the floating gate electrode 40 and the control gate electrode 50 arranged in parallel are arranged on the channel formation region 11. In the region corresponding to the gap 90. In the channel formation region 11, the portion corresponding to the gap 90 becomes a resistance component at the time of channel formation, so that the electric field can be easily concentrated near the source side end portion of the first channel formation region 12. In particular, in the above configuration, the same potential as the substrate potential or a negative potential can be applied to the control gate electrode 50 during erasing. In this case, since the charge accumulation state of the floating gate electrode 40 becomes a state with fewer electrons, the erasing time can be shortened.

  Further, in this embodiment, the electron injection position at the time of writing can be controlled by the impurity concentration of the two channel formation regions 12 and 13, so that the configuration can be simplified.

  In the present embodiment, in the channel formation region 11, the distance between the source side end portion of the first channel formation region 12 that is the electric field concentration portion and the drain vicinity end portion is not particularly mentioned. However, the distance between the electric field concentration portion and the end near the drain is preferably 0.06 μm or more. As described above, when the electric field concentration portion and the drain vicinity end portion are separated from each other, a decrease in the threshold voltage Vt after writing accompanying an increase in the number of rewrites can be more effectively suppressed. This point is clear from the simulation results by the present inventors.

  In the present embodiment, the boundary between the first channel formation region 12 and the second channel formation region 13 is within a portion corresponding to the gap 90 between the floating gate electrode 40 and the juxtaposed portion 52 of the control gate electrode 50. An example is shown. However, unlike the vicinity of the drain end, a configuration in which electrons (hot electrons) in a high energy state can be injected into the floating gate electrode 40 in the intermediate portion between the end of the drain vicinity and the end near the source. If it can be adopted. For example, as shown in FIG. 8, the boundary between the first channel forming region 12 and the second channel forming region 13 may be a region directly below the floating gate electrode 40. In this case, the effect of the portion corresponding to the gap 90 disappears if it is away from the gap 90, but the threshold voltages Vt1 and Vt2 based on the difference in impurity concentration between the first channel formation region 12 and the second channel formation region 13 are eliminated. From the relationship, the source-side end portion of the first channel formation region 12 can be an electric field concentration portion. FIG. 8 is a cross-sectional view showing a modification.

  Further, as shown in FIG. 9, in the surface layer portion of the main surface of the semiconductor substrate 10, a P-conductivity type high concentration region 14 (for example, the concentration is about 1 × 10 18 cm −3) adjacent to the source side end portion of the drain 30. It is good also as a structure which provided. With such a configuration, an avalanche breakdown is likely to occur between the drain 30 and the semiconductor substrate 10, and holes (hot holes) that are in a high energy state with a low voltage at the time of erasing can be injected into the floating gate electrode 40. it can. In other words, the nonvolatile semiconductor memory device 1 can be driven at a low voltage. FIG. 9 is a cross-sectional view showing a modification. Such a high concentration region 14 may be provided so as to enclose the drain 30, or may be provided not only on the drain side but also on the source 20 side.

  In the present embodiment, the example in which the potential of the control gate electrode 50 is fixed to the same potential as the substrate potential or a negative potential with respect to the substrate potential at the time of erasing data is shown. However, the potential may be higher than the substrate potential. However, if the potential is fixed higher than the substrate potential, it becomes difficult for holes to be injected into the floating gate electrode 40, and the erasing time becomes longer accordingly.

  In the present embodiment, an example of the N channel type is shown as the nonvolatile semiconductor memory device 1. However, the P channel type can also be adopted. Also in the case of the P channel type, the absolute value of the threshold voltage Vt2 viewed from the control gate electrode 50 of the second transistor 3 including the second channel formation region 13 includes the first channel formation region 12 as in the NN channel type. What is necessary is just to make it larger than the absolute value of the threshold voltage Vt1 seen from the control gate electrode 50 of the first transistor 2. Specifically, when the impurity concentration of the second channel formation region 13 is higher than that of the first channel formation region 12, the second channel formation region 13 has a channel (P conductivity type inversion layer) rather than the first channel formation region 12. Is difficult to form, and the threshold voltages Vt1 and Vt2 satisfy the above relationship.

(Second Embodiment)
Next, a second embodiment of the present invention will be described based on FIG. FIG. 10 is a cross-sectional view showing a schematic configuration of the nonvolatile semiconductor memory device according to the second embodiment.

  Since the non-volatile semiconductor memory device according to the second embodiment is in common with the non-volatile semiconductor memory device shown in the first embodiment, a detailed description of the common parts will be omitted below, and different parts will be emphasized. explain. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In the present embodiment, for example, as shown in FIG. 10, the channel forming region 11 is constituted by three channel forming regions 12, 13, and 15, and one end is the first channel forming region 12 up to the drain 30 and one end is the source 20. The second channel forming region 13 is sandwiched between the third channel forming regions 15 up to this point. Then, the impurity concentration of the second channel formation region 13 is made higher than that of the other channel formation regions 12 and 15, and the threshold voltage Vt 2 of the second transistor 3 including the second channel formation region 13 becomes the other channel formation region 12, 15 is characterized by being higher than the threshold voltages Vt1 and Vt3 of the transistors 2 and 4 including 15.

  Even in such a configuration, the end portion on the source side of the first channel formation region 12 can be an electric field concentration portion. The impurity concentration of the first channel formation region 12 and the third channel formation region 15 may be the same or different. In this embodiment, the same concentration is used.

  In FIG. 10, the boundary between the first channel formation region 12 and the second channel formation region 13 is a region immediately below the floating gate electrode 40, and the boundary between the second channel formation region 13 and the third channel formation region 15 is The region is directly below the gap 90. However, the position of each boundary is not limited to the above example. As shown in FIG. 10, when the boundary between the first channel formation region 12 and the second channel formation region 13 is a region immediately below the floating gate electrode 40, for example, in an unnecessary portion by ion implantation in an oblique direction and ion implantation. The second channel formation region 13 can be selectively formed by the sum.

  Note that the high-concentration region 14 shown as a modification of the first embodiment can be combined with the configuration shown in the present embodiment. Also, a P channel type can be adopted.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 11 is a cross-sectional view showing a schematic configuration of the nonvolatile semiconductor memory device according to the third embodiment.

  Since the non-volatile semiconductor memory device according to the third embodiment is common in common with the non-volatile semiconductor memory device shown in the first embodiment, the detailed description of the common parts will be omitted below, and different parts will be emphasized. explain. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In the present embodiment, in the configuration shown in the first embodiment, as shown in FIG. 11, the semiconductor substrate 10 has a main transistor whose height from the back surface of the main surface is the first transistor 2 (first channel). The second transistor 3 (second channel formation region 13) has a stepped portion 16 that is higher than the formation region 12), and is formed in the second channel formation region 13 by applying a predetermined voltage to the control gate electrode 50. The step L2 of the step portion 16 is made larger than the thickness L3 of the channel (N conductivity type inversion layer).

  With such a configuration, at the time of writing, electrons from the source 20 to the drain 30 are in a high energy state in the vicinity of the source side end of the first channel formation region 12 and are in a high energy state (hot electrons). Can be injected into the floating gate electrode 40 without changing the traveling direction. Therefore, the writing efficiency can be further improved. That is, the writing time can be shortened. Further, it is possible to suppress a decrease in the threshold voltage Vt after writing.

  Further, in the present embodiment, an example in which the step L2 of the stepped portion 16 is larger than the thickness L3 of the channel (N conductivity type inversion layer) formed in the second channel forming region 13 has been described. However, the step L2 of the step portion 16 is not limited to the above example. It is only necessary to have a level difference (ie, L2> 0). When the level difference L2 is large, electrons in a high energy state can be efficiently injected into the floating gate electrode 40. However, the level difference part 16 and the site formed on the main surface of the semiconductor substrate 10 are formed. It becomes difficult. Therefore, the thickness is 0.2 μm or less, preferably about 0.06 μm.

  Moreover, in this embodiment, the example which combined the structure shown in FIG. 2 and the level | step-difference part 16 among 1st Embodiment was shown. However, the configuration shown in the first embodiment and the configuration shown in the second embodiment and the stepped portion 16 may be combined.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG. 12A and 12B are schematic cross-sectional views for explaining the data rewriting method of the nonvolatile semiconductor memory device according to the fourth embodiment. FIG. 12A shows the end of erasing, and FIG. 12B shows the initial stage of writing. .

  Since the data rewriting method for the nonvolatile semiconductor memory device according to the fourth embodiment is in common with the nonvolatile semiconductor memory device and its rewriting operation (method) shown in the first embodiment, the common parts will be described in detail below. The explanation is omitted, and different parts are explained mainly. In addition, the same code | symbol shall be provided to the element same as the element shown in 1st Embodiment.

  In the first embodiment, the threshold voltage Vt2 of the second transistor 3 is set to the threshold voltage Vt1 of the first transistor 2 by making the impurity concentration of the second channel formation region 13 higher than the impurity concentration of the first channel formation region 12. An example is shown in which the electric field is concentrated at the source side end of the first channel formation region 12 during writing. On the other hand, the present embodiment is characterized in that a channel is partially formed in the channel formation region 11 so that the electric field is concentrated at the source side end of this channel at the initial stage of writing.

  The nonvolatile semiconductor memory device 1 shown in FIGS. 12A and 12B has the same configuration as that of the first embodiment except that the channel formation region 11 is not divided into a plurality of channel formation regions due to a difference in impurity concentration. This is the same as the nonvolatile semiconductor memory device 1 shown in FIG. 2 (that is, the conventional nonvolatile semiconductor memory device having a split gate structure). In the nonvolatile semiconductor memory device 1 having such a configuration, the stacked portion 51 that is stacked on (and in the vicinity of) the floating gate electrode 40 of the control gate electrode 50 and is capacitively coupled to the floating gate electrode 40 includes the first portion. The gate electrode of the transistor 2 is used. In addition, the juxtaposed portion 52 arranged side by side with the floating gate electrode 40 on the channel formation region 11 is used as the gate electrode of the second transistor 3. At the time of erasing, for example, hot holes are sufficiently injected into the floating gate electrode 40, thereby making the absolute value of the threshold voltage Vt1 of the first transistor 2 smaller than the absolute value of the threshold voltage Vt2 of the second transistor 3. The same effects as those of the nonvolatile semiconductor memory device 1 shown in the first embodiment and other embodiments can be obtained.

  In this embodiment, as shown in FIG. 12A, at the time of erasing, the potential of the control gate electrode 50 is fixed to the same potential as the substrate potential or a negative potential with respect to the substrate potential. In this embodiment, at the time of erasing, the semiconductor substrate 10 is grounded, the source 20 is applied with a floating potential, the drain 30 is applied with 8V, and the control gate electrode 50 is applied with −2V.

  Thus, when the potential of the control gate electrode 50 is fixed to the same potential as the substrate potential or a negative potential with respect to the substrate potential, the charge accumulation state of the floating gate electrode 40 can be reduced to a state with fewer electrons. Then, as shown in FIG. 12A, at the end of erasing, the inversion layer 17 (indicated by a broken line in the drawing) is selectively formed in the opposite portion of the channel formation region 11 facing the floating gate electrode 40. Region) can be formed. That is, the channel formation region 11 can be partially brought into a depletion state. Since the inversion layer 17 is not formed at the start of erasing, hot carriers can be injected into the floating gate electrode 40 in the vicinity of the drain 30.

  Therefore, at the moment of switching to writing (initial stage of writing), as shown in FIG. 12B, the vicinity of the source side end of the inversion layer 17 in the channel formation region 11 becomes an electric field concentration portion. Of the electrons traveling from the source 20 to the drain 30, electrons (hot electrons) in a high energy state near the source side end of the inversion layer 17 can be injected into the floating gate electrode 40. Although the inversion layer 17 disappears with time, hot electrons are more likely to be injected into the floating gate electrode 40 in the initial stage of writing with fewer electrons in the floating gate electrode 40, and can occupy the main part of electron injection. In this embodiment, at the time of writing, the semiconductor substrate 10 and the source 20 are grounded, and 5 V is applied to the drain 30 and 8 V is applied to the control gate electrode 50.

  Thus, according to the data rewriting method shown in the present embodiment, the electron injection position at the time of writing can be set to a position different from the hot carrier injection position at the time of erasing. Therefore, the amount of electrons trapped in the trap of the first gate insulating film 60 at the time of writing can be reduced, and a decrease in the threshold voltage Vt after writing accompanying an increase in the number of rewrites can be suppressed.

  Further, since data erasure is performed by fixing the potential of the control gate electrode 50 to the same potential as the substrate potential or a negative potential with respect to the substrate potential, compared to a configuration in which the potential is controlled to be positive with respect to the substrate potential, The erasing time can be shortened.

  In the configuration shown in the first embodiment (see FIG. 2), an example in which the same method as the erase shown in the present embodiment is adopted at the time of erase is shown. Therefore, the effect of the data rewriting method shown in the present embodiment is combined with the effect of the concentration difference between the channel forming regions 12 and 13, and the source side end portion of the first channel forming region 12 (the source side of the floating gate electrode 40). The structure is such that the electric field concentrates easily under the edge).

  Further, in the present embodiment, by controlling the charge accumulation state of the floating gate electrode 40 in the state before writing, the inversion layer 17 (channel) is selectively provided directly below the floating gate electrode 40 in the channel formation region 11. The example which forms is shown. However, the present invention is not limited to the example in which the inversion layer 17 (channel) is formed. When the source side end of the first channel formation region 12 shown in the first embodiment is aligned with the source side end of the floating gate electrode 40, the formation range of the first channel formation region 12 and the inversion layer 17 shown in the present embodiment Matches. When the concept of the first transistor 2 and the second transistor 3 shown in the first embodiment is applied to this embodiment in this coincidence state, the inversion layer 17 (corresponding to the first channel formation region 12) shown in this embodiment is formed. This state is equivalent to a state in which the threshold voltage Vt2 of the second transistor 3 is larger than the threshold voltage Vt1 of the first transistor 2. Therefore, not only the presence or absence of the inversion layer 17 (channel), but also the charge accumulation state of the floating gate electrode 40 is controlled so that the threshold voltage Vt2 of the second transistor 3 is larger than the threshold voltage Vt1 of the first transistor 2. good.

  In the present embodiment, the example in which the above-described data rewriting method is applied to the N-channel nonvolatile semiconductor memory device 1 has been described. However, the data rewriting method can also be applied to the P-channel nonvolatile semiconductor memory device 1.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 13 is a cross-sectional view showing a schematic configuration of the nonvolatile semiconductor memory device according to the fifth embodiment.

  Since the nonvolatile semiconductor memory device according to the fifth embodiment is common in common with the nonvolatile semiconductor memory devices shown in the first to third embodiments, a detailed description of the common parts will be omitted below, and different parts will be omitted. Explain mainly. In addition, the same code | symbol shall be provided to the element same as the element shown to each above-mentioned embodiment.

  In the first to third embodiments, the example of the split gate structure is shown as the nonvolatile semiconductor memory device 1. However, the characteristic structure shown in the first to third embodiments has a structure in which the control gate electrode 50 has only a stacked portion that is capacitively coupled to the floating gate electrode 40 on the channel formation region 11 ( That is, the present invention can also be applied to the nonvolatile semiconductor memory device 1 having a structure in which the juxtaposed portion 52 is not provided on the channel formation region 11.

  For example, the nonvolatile semiconductor memory device 1 shown in FIG. 13 is a so-called stacked gate nonvolatile semiconductor memory device 1 in which the entire control gate electrode 50 is disposed on the semiconductor substrate 10 via the floating gate electrode 40. Yes. The structure is the same as the structure shown in the first embodiment (see FIG. 2) except for the structure of the gate electrodes 40 and 50. Specifically, a source 20 and a drain 30 which are N conductivity type (N +) impurity diffusion regions are formed in the surface layer portion of the main surface of the P conductivity type (P) semiconductor substrate 10 so as to be separated from each other. . A region sandwiched between the source 20 and the drain 30 in the surface layer portion of the semiconductor substrate 10 is a channel formation region 11 of the nonvolatile semiconductor memory device 1. On the main surface of the semiconductor substrate 10 (from the end of the source 20 including the channel formation region 11 to the end of the drain 30), the floating gate electrode 40 is stacked via the first gate insulating film 60. In addition, the control gate electrode 50 is stacked on the floating gate electrode 40 with the intermediate insulating film 70 interposed therebetween, whereby the nonvolatile semiconductor memory device 1 having a stacked gate structure is configured. Further, the first channel forming region 12 up to the drain 30 and the second channel forming region 13 adjacent to the first channel forming region 12 (in the example shown in FIG. 13, up to the source 20 corresponding to the first embodiment). In the channel formation region 11, the boundary is different from the end portion near the drain, and is in an intermediate portion between the end portion near the drain and the end portion near the source. Further, the impurity concentration of the second channel formation region 13 is made higher than the impurity concentration of the first channel formation region 12, so that the absolute value of the threshold voltage Vt 2 of the second transistor 3 is the absolute value of the threshold voltage Vt 1 of the first transistor 2. It is higher than the value.

  Even with such a configuration, the electric field can be concentrated in the vicinity of the source-side end portion of the first channel formation region 12 at the time of writing. That is, the electron injection position at the time of writing and the hot carrier injection position at the time of erasing can be set to different positions. Therefore, the amount of electrons trapped in the trap of the first gate insulating film 60 at the time of writing can be reduced, and a decrease in the threshold voltage Vt after writing accompanying an increase in the number of rewrites can be suppressed. In other words, the threshold voltage Vt after writing can be set to a predetermined value in a short time.

  In the present embodiment, an example is shown in which the configuration other than the gate electrodes 40 and 50 is the same as the configuration shown in the first embodiment (see FIG. 2). However, the above-described gate structure may be combined with the modification shown in the first embodiment, the configuration shown in the second embodiment, or the configuration shown in the third embodiment.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a cross-sectional view showing a schematic configuration of the nonvolatile semiconductor memory device according to the sixth embodiment.

  Since the nonvolatile semiconductor memory device according to the sixth embodiment is in common with the nonvolatile semiconductor memory devices shown in the first to third and fifth embodiments, the detailed description of the common parts is omitted below, and the different parts. Will be explained with emphasis. In addition, the same code | symbol shall be provided to the element same as the element shown to each above-mentioned embodiment.

  In the fifth embodiment, the impurity concentration of the second channel formation region 13 is made higher than the impurity concentration of the first channel formation region 12, whereby the absolute value of the threshold voltage Vt 2 of the second transistor 3 is the same as that of the first transistor 2. The example which made it higher than the absolute value of threshold voltage Vt1 was shown. On the other hand, in this embodiment, the threshold voltage of the second transistor 3 is provided by providing a partial difference in the thickness of the insulating film interposed between the main surface of the semiconductor substrate 10 and the floating gate electrode 40. It is characterized in that the absolute value of Vt2 is made higher than the absolute value of the threshold voltage Vt1 of the first transistor 2.

  As an example, the nonvolatile semiconductor memory device 1 shown in FIG. 14 has the same basic structure as the nonvolatile semiconductor memory device 1 shown in the fifth embodiment. In other words, the nonvolatile semiconductor memory device has a so-called stacked gate structure. Then, instead of the first channel formation region 12 and the second channel formation region 13 having substantially the same impurity concentration (there is no difference in impurity concentration), between the main surface of the semiconductor substrate 10 and the floating gate electrode 40 The thickness of the first gate insulating film 60 that is an interposed insulating film is partially different. Specifically, as shown in FIG. 14, in the first gate insulating film 60, the thickness of the second channel facing portion 62 disposed on the second channel formation region 13 (of the floating gate electrode 40 and the control gate electrode 50). The thickness in the stacking direction) is thicker than the thickness of the first channel facing portion 61 disposed on the first channel formation region 12.

  Here, as the thickness of the insulating film interposed between the main surface of the semiconductor substrate 10 and the floating gate electrode 40 increases, the electric field decreases with respect to a certain control gate voltage, and the channel formation region is less likely to be inverted. Become. Therefore, with the above configuration, the second channel formation region 13 is less likely to be inverted to the P conductivity type than the first channel formation region 12. Thus, when the floating gate electrode 40 is in a neutral state, the absolute value of the threshold voltage Vt2 of the second transistor 3 is larger than the absolute value of the threshold voltage Vt1 of the first transistor 2. That is, the electric field can be concentrated near the source side end of the first channel formation region 12 at the time of writing, whereby the electron injection position at the time of writing and the hot carrier injection position at the time of erasing can be set to different positions. it can. Therefore, the amount of electrons trapped in the trap of the first gate insulating film 60 at the time of writing can be reduced, and a decrease in the threshold voltage Vt after writing accompanying an increase in the number of rewrites can be suppressed. In other words, the threshold voltage Vt after writing can be set to a predetermined value in a short time.

  In the present embodiment, an example in which a partial difference is provided in the thickness of the first gate insulating film 60 in the so-called stacked gate structure nonvolatile semiconductor memory device 1 has been described. However, in the so-called split-gate nonvolatile semiconductor memory device 1 (see FIG. 8) as shown in the first embodiment, the thickness of the first gate insulating film 60 is partially different, so that the second The absolute value of the threshold voltage Vt2 of the transistor 3 may be larger than the absolute value of the threshold voltage Vt1 of the first transistor 2.

  Further, the configuration of the first gate insulating film 60 shown in the present embodiment may be combined with the configuration shown in the first to third embodiments or the configuration shown in the fifth embodiment. For example, the absolute value of the threshold voltage Vt2 of the second transistor 3 may be higher than the absolute value of the threshold voltage Vt1 of the first transistor 2 by adjusting both the impurity concentration and the film thickness of the insulating film. For example, as shown in FIG. 15, the channel forming region 11 is constituted by three channel forming regions 12, 13, 15, and the first channel forming region 12 having one end up to the drain 30 and the third channel forming one end up to the source 20. The second channel forming region 13 is sandwiched between the regions 15. In the first gate insulating film 60, the thickness of the third channel facing portion 63 disposed on the third channel forming region 15 is equal to the first channel facing portion 61 disposed on the first channel forming region 12. The thickness of the second channel facing portion 62 disposed on the second channel forming region 13 is thicker than the thickness of the third channel facing portion 63. With such a configuration, the threshold voltage Vt2 of the second transistor 3 including the second channel formation region 13 is set to be equal to that of the transistors 2 and 4 including the other channel formation regions 12 and 15 as in the configuration shown in the second embodiment. It can be made higher than the threshold voltages Vt1 and Vt3. That is, the second channel formation region 13 can be made less likely to be inverted than the other channel formation regions 12 and 15. In the example shown in FIG. 15, the thickness of the third channel facing portion 63 disposed on the third channel forming region 15 is equal to the thickness of the first channel facing portion 61 disposed on the first channel forming region 12. The example which is made thicker than this is shown. However, the thickness may be the same. FIG. 15 is a cross-sectional view showing a modification.

  In the case of the P channel type as well, the thickness of the second channel facing portion 62 arranged on the second channel forming region 13 is arranged on the first channel forming region 12 as in the N channel type described above. The absolute value of the threshold voltage Vt2 of the second transistor 3 may be higher than the absolute value of the threshold voltage Vt1 of the first transistor 2 by making it thicker than the thickness of the first channel facing portion 61.

(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described with reference to FIGS. FIG. 16 is a cross-sectional view showing a schematic configuration of the nonvolatile semiconductor memory device according to the seventh embodiment. 17A to 17F are cross-sectional views showing the manufacturing process of the floating gate electrode in the nonvolatile semiconductor memory device shown in FIG.

  Since the nonvolatile semiconductor memory device according to the seventh embodiment is in common with the nonvolatile semiconductor memory devices shown in the first to third, fifth, and sixth embodiments, a detailed description of common parts is omitted below. Focus on the differences. In addition, the same code | symbol shall be provided to the element same as the element shown to each above-mentioned embodiment.

  In the above embodiment, in order to make the absolute value of the threshold voltage Vt2 of the second transistor 3 higher than the absolute value of the threshold voltage Vt1 of the first transistor 2, the impurity concentration of the second channel formation region 13 is the first channel formation. An example in which the impurity concentration in the region 12 is set higher than that in the region 12 is shown. Further, in the first gate insulating film 60, the thickness of the second channel facing portion 62 disposed on the second channel forming region 13 is equal to the first channel facing portion 61 disposed on the first channel forming region 12. An example in which the thickness is made thicker than the above is shown. In contrast, the present embodiment is characterized in that the floating gate electrode 40 is formed on the first channel formation region 12 and the second channel formation region 13 using materials having different work functions. To do.

  As an example, the nonvolatile semiconductor memory device 1 shown in FIG. 16 is a nonvolatile semiconductor memory device having a so-called stacked gate structure, similar to the nonvolatile semiconductor memory device 1 shown in the fifth embodiment. In the nonvolatile semiconductor memory device 1, the first channel formation region 12 and the second channel formation region 13 have substantially the same impurity concentration, and the thickness of the first gate insulating film 60 is the same as that on the first channel formation region 12. It is almost the same on the two-channel formation region 13. A floating gate electrode 40 is provided on the first channel formation region 12, provided on the first floating gate electrode portion 41 in contact with the first gate insulating film 60, and on the second channel formation region 13. A second floating gate electrode portion 42 is in contact with the insulating film 60 and in contact with the first floating gate electrode portion 41. The first floating gate electrode portion 41 and the second floating gate electrode portion 42 are formed using materials having different work functions.

  Specifically, as shown in FIG. 16, the first floating gate electrode portion 41 and the second floating gate electrode portion 42 are arranged side by side adjacent to each other so as to face the main surface of the semiconductor substrate 10. The second floating gate electrode portion 42 is formed using a material having a work function φ2 larger than the work function φ1 of the material constituting the first floating gate electrode portion 41. The combination of the constituent materials of the first floating gate electrode portion 41 and the second floating gate electrode portion 42 only needs to satisfy the above relationship (φ2> φ1). In the present embodiment, as an example, the first floating gate electrode portion 41 is made of aluminum, and the second floating gate electrode portion 42 is made of p + polycrystalline silicon.

  The floating gate electrode 40 having the above configuration can be formed, for example, by the manufacturing method described below. First, as shown in FIG. 17A, the semiconductor substrate 10 on which the drain 30 is formed is prepared, and the main surface of the semiconductor substrate 10 is formed on the main surface of the semiconductor substrate 10 via the first gate insulating film 60 by, for example, well-known photolithography. A mask 110 made of a silicon oxide film is formed. The mask 110 is opened at a predetermined portion including a portion corresponding to the second channel formation region 13 (not shown), and the p + polycrystalline silicon film 42a is formed on the main surface of the semiconductor substrate 10 through the mask 110. Form a film. Then, the p + polycrystalline silicon film 42a on the mask 110 is removed by, for example, polishing so as to be flush with the mask 110. Thereby, as shown in FIG. 17B, the second floating gate electrode portion 42 is formed. Next, as shown in FIG. 17C, a resist 111 is formed at a predetermined position on the mask 110 and the second floating gate electrode portion 42 by known photolithography. A predetermined portion including a portion corresponding to the first channel formation region 12 (not shown) is opened in the resist 111, and the mask 110 is selectively passed through the resist 111 as shown in FIG. Etch into. Then, after removing the resist 111, an Al film 41a is formed on the main surface of the semiconductor substrate 10 through a mask 110, as shown in FIG. Next, the Al film 41a on the mask 110 and the second floating gate electrode part 42 is removed by, for example, polishing so as to be flush with the mask 110 and the second floating gate electrode part 42. Thereby, as shown in FIG. 17E, the first floating gate electrode portion 41 is formed. Then, as shown in FIG. 17F, after the mask 110 is removed and the source 20 is formed, the intermediate insulating film 70 and the control gate electrode 50 are formed by a known process, so that the nonvolatile semiconductor memory device is formed. 1 can be obtained.

  Here, as is well known, the threshold voltage of the MOS structure, when the thickness of the first gate insulating film 60 is constant as in the example shown in this embodiment, the work function difference between the semiconductor substrate 10 and the floating gate electrode 40, It is determined by the charge in the first gate insulating film 60 and the threshold voltage at the interface between the first gate insulating film 60 and the semiconductor substrate 10. In this embodiment, the charge in the first gate insulating film 60 and the threshold voltage at the interface between the first gate insulating film 60 and the semiconductor substrate 10 are not changed. Therefore, the threshold voltage is determined by the work function difference between the semiconductor substrate 10 and the floating gate electrode 40. The work function is an energy difference between the Fermi level and the vacuum level, which is energy necessary for taking out electrons from the surface. When the work function of the semiconductor substrate 10 is constant, N In the channel type, as the work function of the floating gate electrode 40 is larger, electrons (hot electrons) in a high energy state are less likely to be injected into the floating gate electrode 40. That is, the absolute value of the threshold voltage increases.

  In the present embodiment, as described above, the second floating gate electrode portion 42 that faces the second channel formation region 13 in the portion on the channel formation region 11 in the floating gate electrode 40 faces the first channel formation region 12. The first floating gate electrode portion 41 is made of a material having a work function φ2 larger than that of the material constituting the first floating gate electrode portion 41. Thus, when the floating gate electrode 40 is in a neutral state, the absolute value of the threshold voltage Vt2 of the second transistor 3 is larger than the absolute value of the threshold voltage Vt1 of the first transistor 2. That is, the electric field can be concentrated near the source side end of the first channel formation region 12 at the time of writing, whereby the electron injection position at the time of writing and the hot carrier injection position at the time of erasing can be set to different positions. it can. Therefore, the amount of electrons trapped in the trap of the first gate insulating film 60 at the time of writing can be reduced, and a decrease in the threshold voltage Vt after writing accompanying an increase in the number of rewrites can be suppressed. In other words, the threshold voltage Vt after writing can be set to a predetermined value in a short time.

  In the present embodiment, an example in which the floating gate electrode 40 is formed using a plurality of materials having different work functions in the so-called stacked gate structure nonvolatile semiconductor memory device 1 has been described. However, in the so-called split gate structure nonvolatile semiconductor memory device 1 (see FIG. 8) as shown in the first embodiment, the floating gate electrode 40 is formed by using a plurality of materials having different work functions. The absolute value of the threshold voltage Vt2 of the two transistors 3 may be made larger than the absolute value of the threshold voltage Vt1 of the first transistor 2.

  In the present embodiment, the first floating gate electrode portion 41 and the second floating gate electrode portion 42 constituting the floating gate electrode 40 are arranged adjacent to each other so as to face the main surface of the semiconductor substrate 10. An example of arrangement is shown. However, for example, as shown in FIG. 18, a part of the first floating gate electrode portion 41 may be laminated and disposed in direct contact with the second floating gate electrode portion 42. Such a structure can also be formed by a known process such as photolithography. FIG. 18 is a cross-sectional view showing a modification. In the example shown in FIG. 18, an example in which a part of the first floating gate electrode portion 41 is stacked in direct contact with the second floating gate electrode portion 42 is shown. It is also possible to adopt a configuration in which a part of 42 is laminated in direct contact with the first floating gate electrode portion 41.

  The configuration of the floating gate electrode 40 shown in the present embodiment may be combined with the configuration shown in the first to third embodiments, the configuration shown in the fifth embodiment, and the configuration shown in the sixth embodiment. For example, as shown in FIG. 19, the channel forming region 11 is constituted by three channel forming regions 12, 13, and 15, and the first channel forming region 12 having one end up to the drain 30 and the third channel forming one end up to the source 20. The second channel forming region 13 is sandwiched between the regions 15. Of the portion of the floating gate electrode 40 on the channel formation region 11, the third floating gate electrode portion 43 that faces the third channel formation region 15 is the first floating gate electrode portion that faces the first channel formation region 12. 41 is formed using a material having a work function φ3 larger than the work function φ1 of the material constituting 41. Further, the work function φ2 of the second floating gate electrode portion 42 facing the second channel formation region 13 is higher than the work function φ3 of the material constituting the third floating gate electrode portion 43 facing the third channel formation region 15. It is formed using a large material. With such a configuration, the threshold voltage Vt2 of the second transistor 3 including the second channel formation region 13 is set to the transistor 2 including the other channel formation regions 12 and 15 as in the configuration shown in the second embodiment and FIG. , 4 can be made higher than the threshold voltages Vt1 and Vt3. That is, the second channel formation region 13 can be made less likely to be inverted than the other channel formation regions 12 and 15. In the example shown in FIG. 19, the work function φ3 of the third floating gate electrode portion 43 disposed on the third channel formation region 15 is equal to the first floating gate electrode portion disposed on the first channel formation region 12. An example larger than the work function φ1 of 41 is shown. However, the first floating gate electrode portion 41 and the third floating gate electrode portion 43 may be configured using the same material (material having the same work function). FIG. 19 is a cross-sectional view showing a modification.

  In the case of the P-channel type, the relationship may be opposite to that of the N-channel type described above. That is, the second floating gate electrode portion 42 may be formed using a material having a work function φ2 smaller than the work function φ1 of the material constituting the first floating gate electrode portion 41. Thus, if φ1> φ2 is satisfied, the absolute value of the threshold voltage Vt2 of the second transistor 3 can be made higher than the absolute value of the threshold voltage Vt1 of the first transistor 2.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

It is a figure which shows the relationship between the frequency | count of rewriting and the charge accumulation amount of an insulating film. 1 is a cross-sectional view illustrating a schematic configuration of a main part of a nonvolatile semiconductor memory device according to a first embodiment. It is a figure for demonstrating write-in / erase operation | movement, (a) is writing, (b) has shown erasure | elimination. It is a figure which shows density distribution. 5A and 5B are diagrams illustrating an electric field intensity distribution at the time of data writing, in which FIG. 4A is an electric field intensity distribution in a region 100 surrounded by a broken line in FIG. 4, and FIG. Is shown. 5A and 5B are diagrams illustrating an electric field intensity distribution at the time of erasing data, in which FIG. 4A is an electric field intensity distribution in a region 100 surrounded by a broken line in FIG. 4, and FIG. Is shown. It is a figure which shows the relationship between the frequency | count of rewriting, and a threshold voltage. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification. It is sectional drawing which shows schematic structure of the non-volatile semiconductor memory device which concerns on 2nd Embodiment. It is sectional drawing which shows schematic structure of the non-volatile semiconductor memory device which concerns on 3rd Embodiment. It is a schematic sectional drawing for demonstrating the data rewriting method of the non-volatile semiconductor memory device which concerns on 4th Embodiment, (a) has shown the initial stage at the time of the end of erasing, (a). It is sectional drawing which shows schematic structure of the non-volatile semiconductor memory device which concerns on 5th Embodiment. It is sectional drawing which shows schematic structure of the non-volatile semiconductor memory device which concerns on 6th Embodiment. It is sectional drawing which shows a modification. It is sectional drawing which shows schematic structure of the non-volatile semiconductor memory device which concerns on 7th Embodiment. (A)-(f) is sectional drawing which shows the manufacturing process of a floating gate electrode among the non-volatile semiconductor memory devices shown in FIG. It is sectional drawing which shows a modification. It is sectional drawing which shows a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Nonvolatile semiconductor memory device 2 ... 1st transistor 3 ... 2nd transistor 11 ... Channel formation area 12 ... 1st channel formation area 13 ... 2nd channel formation area 20- ..Source 30 ... Drain 40 ... Floating gate electrode 50 ... Control gate electrode 51 ... Laminated portion 52 ... Parallel portion

Claims (14)

A first conductivity type semiconductor substrate;
A source and a drain which are formed in a surface layer portion of the main surface of the semiconductor substrate so as to be spaced apart from each other and in which a second conductivity type impurity opposite to the first conductivity type is diffused;
A floating gate electrode as a gate electrode disposed via an insulating film on a channel formation region between the source and drain of the semiconductor substrate, and a control gate at least partially capacitively coupled to the floating gate electrode With electrodes,
An electrically rewritable nonvolatile semiconductor memory device that performs erasure by hot carriers generated at an end near the drain of the channel formation region by avalanche breakdown,
The position of the electric field concentration portion where the electric field strength is maximum in the channel formation region at the time of writing is different from the end portion near the drain, and the end portion near the source and the end portion near the drain opposite to the end portion near the drain A non-volatile semiconductor memory device characterized by being in an intermediate portion between the two.   The nonvolatile semiconductor memory device according to claim 1, wherein an interval between the electric field concentration portion and the end portion near the drain is 0.06 μm or more. Of the channel formation region, a first transistor including a first channel formation region from the source side end of the electric field concentration portion to the drain, and a second channel formation adjacent to the first channel formation region A second transistor including a region;
The absolute value of the threshold voltage in the second transistor is larger than the absolute value of the threshold voltage in the first transistor when the floating gate electrode is in a neutral state. The nonvolatile semiconductor memory device described. The control gate electrode is arranged side by side with a predetermined gap between the layered portion laminated and capacitively coupled with the floating gate electrode and the floating gate electrode on the channel formation region. Having a region,
The said electric field concentration part is made into the site | part vicinity of the source side with respect to the said opposing part with respect to the said floating gate electrode among the intermediate parts of the said channel formation area, The Claim 3 characterized by the above-mentioned. Nonvolatile semiconductor memory device.   The nonvolatile semiconductor memory device according to claim 4, wherein the stacked portion is included in the first transistor. The second channel formation region is a region to the source;
6. The nonvolatile semiconductor memory device according to claim 5, wherein the juxtaposed portion is included in the second transistor.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the control gate electrode has only a stacked portion stacked and capacitively coupled to the floating gate electrode on the channel formation region.   The nonvolatile semiconductor memory device according to claim 3, wherein an impurity concentration of the second channel formation region is higher than an impurity concentration of the first channel formation region.   The thickness of the insulating film interposed between the main surface of the semiconductor substrate and the floating gate electrode on the second channel formation region is such that the thickness of the semiconductor substrate on the first channel formation region is The nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory device is thicker than a thickness of the insulating film interposed between a main surface and the floating gate electrode. The floating gate electrode is provided on the first channel formation region, and has a first floating gate electrode portion in contact with the insulating film interposed between the main surface of the semiconductor substrate and the second channel A second floating gate electrode portion provided on a formation region, in contact with the insulating film interposed between the main surface of the semiconductor substrate and in contact with the first floating gate electrode portion;
The non-volatile device according to any one of claims 3 to 9, wherein the first floating gate electrode portion and the second floating gate electrode portion are formed using materials having different work functions. Semiconductor memory device. The second conductivity type is an N conductivity type,
The nonvolatile semiconductor memory according to claim 10, wherein the second floating gate electrode portion is formed using a material having a work function larger than that of the constituent material of the first floating gate electrode portion. apparatus. The semiconductor substrate has a step on its main surface, the height of the second transistor being higher than that of the first transistor from the back surface of the main surface;
12. The step according to claim 3, wherein the step is larger than a thickness of the inversion layer formed in the second channel formation region by applying a predetermined voltage to the control gate electrode. The nonvolatile semiconductor memory device described. A source and a drain which are second conductivity type impurity diffusion regions opposite to the first conductivity type are formed on the main surface of the first conductivity type semiconductor substrate so as to be separated from each other, and the source and drain of the semiconductor substrate are formed. In a nonvolatile semiconductor memory device in which a floating gate electrode and a control gate electrode having a split gate structure are arranged on a channel formation region between the source and the drain, the electrons from the source to the drain during writing Then, electrons in a high energy state are injected into the floating gate electrode to obtain a data write state, and at the time of erasure, an avalanche breakdown is generated between the drain and the semiconductor substrate, and hot carriers associated therewith are transferred to the floating gate electrode. A method of rewriting data in a nonvolatile semiconductor memory device that erases data by injecting into a floating gate electrode,
At the time of erasing, an absolute value of a threshold voltage of a transistor including a stacked portion of the control gate electrode that is stacked and capacitively coupled with the floating gate electrode is between the floating gate electrode and the channel forming region. The data is erased to be smaller than the absolute value of the threshold voltage of the transistor including the juxtaposed portion arranged side by side with a predetermined gap, and writing is performed from a state where the threshold voltage relationship is satisfied. A method of rewriting data in a nonvolatile semiconductor memory device.   14. The data of the nonvolatile semiconductor memory device according to claim 13, wherein at the time of erasing, the potential of the control gate electrode is fixed to the same potential as the semiconductor substrate or a negative potential with respect to the semiconductor substrate. Rewrite method.

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