JP2008276085A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2008276085A5 JP2008276085A5 JP2007122123A JP2007122123A JP2008276085A5 JP 2008276085 A5 JP2008276085 A5 JP 2008276085A5 JP 2007122123 A JP2007122123 A JP 2007122123A JP 2007122123 A JP2007122123 A JP 2007122123A JP 2008276085 A5 JP2008276085 A5 JP 2008276085A5
- Authority
- JP
- Japan
- Prior art keywords
- gate wiring
- gate
- thin film
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (10)
前記ゲート配線を構成する前記ゲート配線部と前記ゲート電極部と前記ゲート端子部のOf the gate wiring portion, the gate electrode portion, and the gate terminal portion constituting the gate wiring. 何れかが耐プラズマ性とバリア特性を有することを特徴とする薄膜トランジスタ。Any one of the thin film transistors having plasma resistance and barrier properties.
前記ゲート配線は、金属主層の表面にキャップ層を披覆した積層構造で形成され、The gate wiring is formed in a stacked structure in which a cap layer is shown on the surface of the metal main layer,
前記ゲート配線部のキャップ層は、耐プラズマ性と下層金属を固溶拡散させないバリアThe cap layer of the gate wiring part has a plasma resistance and a barrier that does not diffuse and dissolve the lower layer metal. 特性を有する導電性の材料を含んでいるインクの焼成で形成され、Formed by firing an ink containing a conductive material having properties,
前記ゲート電極部のキャップ層は、耐プラズマ性と、下層金属を固溶拡散させないバリThe cap layer of the gate electrode portion has a plasma resistance and a barrier that does not allow the lower layer metal to dissolve and diffuse. ア特性と、平坦性および耐電圧性を有する導電性の材料を含んでいるインクの焼成で形成Formed by firing of ink containing conductive material with flat characteristics and voltage resistance され、And
前記ゲート端子部のキャップ層は、耐プラズマ性と、下層金属を固溶拡散させないバリThe cap layer of the gate terminal portion has a plasma resistance and a barrier that does not allow the lower layer metal to be dissolved and dissolved. ア特性と、ドライエッチング耐性を有する導電性の材料を含んでいるインクの焼成で形成Formed by firing of ink containing conductive material with characteristics and dry etching resistance されていることを特徴とする薄膜トランジスタ。A thin film transistor, wherein
前記金属主層が銀・インクの焼成で形成されていることを特徴とする薄膜トランジスタA thin film transistor characterized in that the metal main layer is formed by firing silver and ink. 。.
前記ゲート配線と前記第１基板の間に密着層を有することを特徴とする薄膜トランジス タ。 In any one of Claims 1 thru | or 3,
Thin film transistor capacitor characterized by having an adhesion layer between the first substrate and the previous SL gate wiring.
前記密着層がマンガン・インクの焼成で形成されていることを特徴とする薄膜トランジ スタ。 In claim 4.
Thin film transistors, wherein the adhesion layer is formed by firing manganese-ink.
前記第１基板に、ゲート配線部と、該ゲート配線部から延びて前記薄膜トランジスタの ゲート電極を構成するゲート電極部と、ゲート配線に選択信号を印加するゲート端子部と を備えたゲート配線を有し、
前記ゲート配線を構成する前記ゲート配線部と前記ゲート電極部と前記ゲート端子部の 何れかが耐プラズマ性とバリア特性を有することを特徴とする液晶表示パネル。 A liquid crystal display panel having a first substrate on which a plurality of pixel circuits having thin film transistors are formed, and a second substrate disposed opposite to the first substrate through a liquid crystal layer ,
The first substrate includes a gate wiring having a gate wiring portion, a gate electrode portion extending from the gate wiring portion and constituting a gate electrode of the thin film transistor, and a gate terminal portion for applying a selection signal to the gate wiring . And
Any one of the gate wiring part, the gate electrode part, and the gate terminal part constituting the gate wiring has plasma resistance and barrier characteristics .
前記第１基板に、ゲート配線部と、該ゲート配線部から延びて前記薄膜トランジスタの ゲート電極を構成するゲート電極部と、ゲート配線に選択信号を印加するゲート端子部と を備えたゲート配線を有し、
前記ゲート配線は、金属主層の表面にキャップ層を披覆した積層構造で形成され、
前記ゲート配線部のキャップ層は、耐プラズマ性と下層金属を固溶拡散させないバリア 特性を有する導電性の材料を含んでいるインクの焼成で形成され、
前記ゲート電極部のキャップ層は、耐プラズマ性と、下層金属を固溶拡散させないバリ ア特性と、平坦性および耐電圧性を有する導電性の材料を含んでいるインクの焼成で形成 され、
前記ゲート端子部のキャップ層は、耐プラズマ性と、下層金属を固溶拡散させないバリ ア特性と、ドライエッチング耐性を有する導電性の材料を含んでいるインクの焼成で形成 されていることを特徴とする液晶表示パネル。 A liquid crystal display panel having a first substrate on which a plurality of pixel circuits having thin film transistors are formed, and a second substrate disposed opposite to the first substrate through a liquid crystal layer ,
The first substrate includes a gate wiring having a gate wiring portion, a gate electrode portion extending from the gate wiring portion and constituting a gate electrode of the thin film transistor, and a gate terminal portion for applying a selection signal to the gate wiring . And
The gate wiring is formed in a stacked structure in which a cap layer is shown on the surface of the metal main layer,
The cap layer of the gate wiring portion is formed by baking ink containing a conductive material having a plasma resistance and a barrier property that does not allow the lower layer metal to be dissolved and diffused .
The cap layer of the gate electrode portion, and the plasma resistance, the burr A characteristic of not solid-dissolved and diffused in the underlying metal, is formed by firing an ink containing a conductive material having a flatness and voltage resistance,
Cap layer of the gate terminal portion, wherein the plasma resistance, the burr A characteristic of not solid-dissolved and diffused in the underlying metal, that is formed by firing an ink containing a conductive material having resistance to dry etching the liquid crystal display panel to.
前記金属主層が銀・インクの焼成で形成されていることを特徴とする液晶表示パネル。A liquid crystal display panel, wherein the metal main layer is formed by baking silver and ink.
前記ゲート配線と前記第１基板の間に密着層を有することを特徴とする液晶表示パネルA liquid crystal display panel having an adhesion layer between the gate wiring and the first substrate 。.
前記密着層がマンガン・インクの焼成で形成されていることを特徴とする液晶表示パネA liquid crystal display panel, wherein the adhesion layer is formed by firing of manganese ink. ル。Le.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007122123A JP4510846B2 (en) | 2007-05-07 | 2007-05-07 | Thin film transistor and liquid crystal display panel using the thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007122123A JP4510846B2 (en) | 2007-05-07 | 2007-05-07 | Thin film transistor and liquid crystal display panel using the thin film transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008276085A JP2008276085A (en) | 2008-11-13 |
| JP2008276085A5 true JP2008276085A5 (en) | 2009-07-23 |
| JP4510846B2 JP4510846B2 (en) | 2010-07-28 |
Family
ID=40054088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007122123A Expired - Fee Related JP4510846B2 (en) | 2007-05-07 | 2007-05-07 | Thin film transistor and liquid crystal display panel using the thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4510846B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5092022B2 (en) | 2009-08-26 | 2012-12-05 | 日本特殊陶業株式会社 | Spark plug for internal combustion engine and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4572868B2 (en) * | 2003-05-12 | 2010-11-04 | セイコーエプソン株式会社 | Wiring pattern forming method, non-contact card medium manufacturing method, electro-optical device manufacturing method, and active matrix substrate manufacturing method |
| JP4617983B2 (en) * | 2005-04-22 | 2011-01-26 | セイコーエプソン株式会社 | Film pattern forming method and device manufacturing method |
-
2007
- 2007-05-07 JP JP2007122123A patent/JP4510846B2/en not_active Expired - Fee Related
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2008116502A5 (en) | ||
| JP2022082792A5 (en) | ||
| JP2016189190A5 (en) | ||
| JP2006309161A5 (en) | ||
| JP2008032899A5 (en) | ||
| JP2016184173A5 (en) | Semiconductor device, mobile phone, display device | |
| JP2013243372A5 (en) | Semiconductor device, electronic device, and portable information terminal | |
| JP2003149675A5 (en) | ||
| JP2017146450A5 (en) | ||
| TW200834197A (en) | Liquid crystal display device and electronic device | |
| JP2018116224A5 (en) | ||
| JP2011077517A5 (en) | Active matrix display | |
| JP2010107976A5 (en) | ||
| JP2010097204A5 (en) | ||
| JP2007121587A5 (en) | ||
| WO2009019920A1 (en) | Circuit board and display device | |
| JP2010107977A5 (en) | ||
| JP2010091826A5 (en) | ||
| JP2009099887A5 (en) | ||
| JP2014095895A5 (en) | Liquid crystal display | |
| EP2421030A3 (en) | Display device | |
| JP2006189853A5 (en) | ||
| JP2007213065A5 (en) | ||
| JP2015215606A5 (en) | ||
| JP2010107595A5 (en) |