JP2008271320A - High power-durability receiving amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high power-durability receiving amplifier which can be increased in recovery speed while being improved in power durability and reliability. <P>SOLUTION: The high power-durability receiving amplifier includes: an input terminal 4 and an output terminal 5; a field effect transistor 1, with its gate terminal connected to one end of the input terminal 4 and drain bias terminal connected to one end of the output terminal 5; a detector 6 which is connected to the other end of the input terminal 4 and detects input power; a threshold decision means 8 which compares the input power detected by the detector 6 with a predetermined threshold and outputs the comparison results; and a source voltage driving circuit 9 which switches the output voltage to either the GND or the drain bias voltage on a basis of the comparison results from the threshold decision circuit 8 and applies the output voltage to the source terminal of the field effect transistor 1 via a recovery speed-up resistor 10. When the input voltage is lower than the threshold, the source voltage is made the same as the GND voltage, and when the input voltage is higher than the threshold, the source voltage is made the same as the drain bias voltage. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a high power-resistant receiving amplifier, and more particularly to a high power-resistant receiving amplifier used in high-frequency wireless communication and the like.

  As a conventional limiter amplifier, a configuration has been proposed in which a detector is loaded on the input side of a receiving amplifier to detect input power, and the power supply of the amplifier is cut off when high power is input to improve power durability (for example, a patent) Reference 1). In the related art, a branching unit for branching a received signal input to an amplifier circuit, a detector for detecting a branched signal to generate a DC detection voltage, a generated detection voltage, and an amplifier circuit are configured. Comparing with a predetermined threshold voltage set below the maximum allowable power of the amplifying element, and comparing means for outputting a comparison result signal based on whether or not the detection voltage exceeds the threshold voltage, according to the comparison result signal And bias ON / OFF means for turning on the power supply to the bias circuit when it is lower than the threshold voltage and turning it off when the threshold voltage is exceeded.

  As another conventional technique, similarly, a configuration is proposed in which a detector is loaded on the input side of a reception amplifier, and the gate bias of the amplifier is deepened when high power is input to improve power durability (for example, Patent Documents). 2). In the related art, a detection diode whose detection current changes according to the amplitude of an input signal is incorporated in a gate bias circuit of a transistor as a current source for generating a feedback voltage. A voltage calculated as the product of the detection current biases the gate in the negative voltage direction. By biasing the gate in the negative voltage direction, it acts in the direction of decreasing the gate current of the transistor, reducing the undesirable effect called migration on reliability.

JP 2002-237728 A Japanese Patent Laid-Open No. 10-247828

  However, in the configuration described in Patent Document 1, since the gate voltage Vg is constant at Vg = 0 when a large signal is input, a current in the gate forward direction increases when a large power is input, thereby causing gate breakdown or electrode migration. There was a problem that led to deterioration of reliability.

  Further, in the configuration described in Patent Document 2, when the drain voltage is Vd and the drain-source voltage is Vds, Vd = Vds is constant. Therefore, when high power is input, the drain-source current Ids flows and a high voltage is applied. (The gate-drain voltage Vgd increases as the gate is deepened). Under a high current, trapping of carriers to the trap level at the interface proceeds, and there is a problem that the recovery characteristics deteriorate when returning to the steady state. .

  Here, the trap will be described. When a large signal is input, carriers are trapped at trap levels existing at the interface under high voltage and high current, and a pseudo gate is generated. As a result, the channel in which carriers flow is narrowed, current is reduced, and RF (Radio Frequency) characteristics such as gain and NF (Noise Factor (Noise Figure), noise figure) are deteriorated. As a result, there is a problem that the normal gain and NF do not return to the time constant of carrier emission from the trap when the steady input is restored.

  The present invention has been made to solve such a problem, and an object of the present invention is to obtain a high-power-resistant receiving amplifier capable of improving power resistance and reliability, and capable of speeding up recovery. Yes.

  The present invention is a high power receiving amplifier to be mounted in the first stage of a wireless communication receiver, wherein an input terminal and an output terminal, a gate terminal is connected to one end of the input terminal, and one end of the output terminal is connected. A field effect transistor connected to the drain bias terminal; a detecting means connected to the other end of the input terminal for detecting input power; and comparing the input power detected by the detecting means with a predetermined threshold value. The threshold value judging means for outputting the comparison result, and the output voltage is switched based on the comparison result from the threshold judgment means and applied to the source terminal of the field effect transistor as either the GND voltage or the drain bias voltage. And a recovery speed increasing resistor connected between the source voltage driving circuit and the source terminal of the field effect transistor. When the input power is lower than the threshold, the source voltage driving circuit output is made the same as the GND voltage, and when the input power is higher than the threshold, the source voltage driving circuit output is made the drain bias voltage. This is a high power receiving amplifier characterized by being identical.

  The present invention is a high power receiving amplifier to be mounted in the first stage of a wireless communication receiver, wherein an input terminal and an output terminal, a gate terminal is connected to one end of the input terminal, and one end of the output terminal is connected. A field effect transistor connected to the drain bias terminal; a detecting means connected to the other end of the input terminal for detecting input power; and comparing the input power detected by the detecting means with a predetermined threshold value. The threshold value judging means for outputting the comparison result, and the output voltage is switched based on the comparison result from the threshold judgment means and applied to the source terminal of the field effect transistor as either the GND voltage or the drain bias voltage. And a recovery speed increasing resistor connected between the source voltage driving circuit and the source terminal of the field effect transistor. When the input power is lower than the threshold, the source voltage driving circuit output is made the same as the GND voltage, and when the input power is higher than the threshold, the source voltage driving circuit output is made the drain bias voltage. Since the high power receiving amplifiers are characterized by being the same, it is possible to improve power durability and reliability and to speed up recovery.

Embodiment 1 FIG.
Hereinafter, a high power withstanding receiving amplifier according to Embodiment 1 of the present invention will be described. FIG. 1 is a configuration diagram showing the configuration of the high power withstanding receiving amplifier according to the first embodiment. The high-power-resistant receiving amplifier according to the first embodiment is connected to a connection terminal of a radio communication antenna or a transmission / reception switching circuit, and will be described as being mounted on the first stage of a receiver. In the figure, 1 is a field effect transistor, 2 is a gate terminal of the field effect transistor 1, 3 is a drain terminal of the field effect transistor 1, 4 is an input terminal of a high power withstanding reception amplifier, 5 is an output terminal thereof, and 6 is an input terminal. 4 is connected to the other end of the detector 6, and is connected to the other end of the detector 6. The rectifier circuit rectifies the output of the detector 6, and 8 is connected to the other end of the rectifier circuit 7. , A threshold determination circuit for comparing the voltage rectified by the rectifier circuit 7 with a predetermined threshold (hereinafter referred to as a threshold voltage (Vth)), 9 is connected to the threshold determination circuit 8, and based on the determination result The source voltage driving circuit 10 for switching the output voltage to GND (when ON) / Vd (when OFF), 10 is a recovery acceleration resistor (hereinafter simply referred to as the resistor 10), 11 connected to the source voltage driving circuit 9. Is Scan is a power supply terminal of the voltage driving circuit 9. Reference numeral 12 denotes a choke coil connected to a resistor 10 connected to the source terminal (S), the gate terminal 2 and the drain terminal 3 of the field effect transistor 1. Reference numeral 13 denotes a bypass capacitor connected in parallel between the gate terminal 2 and drain terminal 3 of the field effect transistor 1 and the choke coil 12. The bypass capacitor 13 is also connected in parallel with the choke coil 12 between the source terminal (S) of the field effect transistor 1 and GND (ground). Reference numeral 14 denotes an antenna connection terminal (or transmission / reception switching circuit connection terminal) connected to the detector 6.

  2 and 3 are diagrams summarizing the operation of the high power withstanding receiving amplifier according to the first embodiment. In these drawings, A indicates a normal operation, B indicates a power-proof operation, and C indicates a return operation. In these figures, Pin is the input power detected by the detector 6, and Pth is a predetermined threshold (hereinafter referred to as threshold power) preset for the input power Pin. Vth is a predetermined threshold (hereinafter referred to as a threshold voltage) preset for the input voltage Vin in the threshold determination circuit. Vs is a source bias voltage, Vd is a drain bias voltage, Vg is a gate bias voltage, Vds is a drain-source voltage, Vgs is a gate-source voltage, Vs ′ is a source voltage driving circuit output voltage, Rs is a source resistance value, Ids is a drain-source current.

  4 is a graph showing the relationship between the drain-source voltage Vds and the drain-source current Ids, FIG. 5 is a graph showing the relationship between the gate voltage Vg and the gate current Ig, and FIG. 5 is a graph showing the relationship between the drain-source current Ids and the gate-source voltage Vgs.

  Next, the operation will be described. First, the input power Pin input to the input terminal 4 is detected by the detector 6. The detected input power Pin is compared with the threshold power Pth. Actually, the half-wave waveform output from the detector 6 is rectified by the rectifier circuit 7, and the rectified voltage Vin is compared with a preset threshold voltage (Vth) by the threshold determination circuit 8. The During normal operation (A), since Pin <Pth, that is, Vin <Vth, the threshold determination circuit 8 outputs an ON signal. In response to this, the source voltage driving circuit 9 outputs the GND voltage as the output voltage Vs ′ and applies it to the source terminal of the field effect transistor 1 via the resistor 10 (normal mode). As a result, Vds, dc = Vd−Vs becomes Vds0 = Vd−Ids0 × Rs (set drain bias) with respect to the drain current Ids0 during normal operation, and Vgs0, dc = Vg−Vs is Vgs0 = Vg−. Ids0 × Rs (set gate bias). As shown in FIG. 6, when a large drain current Id flows, Vgs and dc are shifted in the negative direction by the resistor 10 and the current is suppressed. As a result, the reliability is improved.

  On the other hand, when a large amount of power is input, the operation is performed at the time of withstand power. Similarly, during the power withstand operation (B), the input power Pin detected by the detector 6 is compared with the threshold power Pth. In this case, since Pin ≧ Pth and Vin ≧ Vth, an OFF signal is output from the threshold determination circuit 8. In response to this, the source voltage drive circuit 9 outputs a voltage having the same value as the drain bias voltage Vd as the output voltage Vs ′ and applies it to the source terminal of the field effect transistor 1 via the resistor 10 (withstand power). mode). At this time, since Vds and Vs ′ are the same potential and Ids does not flow, Vs also becomes Vd, Vds, dc = Vd−Vs becomes Vd−Vd = 0, and Vgs, dc = Vg−Vs becomes Vg−Vd. Become. In this way, at the time of withstanding power, as shown in FIG. 3, by setting the output voltage from the source voltage drive circuit 9 to the drain bias voltage Vd, Vds and dc are set to 0 V, and when high power is input, Vds = Breakdown due to Vds, dc + Vds, rf exceeding the withstand voltage (Vbr) is prevented. Further, as shown in FIG. 5, the gate-source voltage (Vgs) is set deeply in the negative direction to Vg−Vd, and Vgs = Vgs, dc + Vgs, rf is overvoltaged in the positive direction when high power is input. The destruction due to the flow of the key current (Vgs> Vb) and the reliability degradation due to the gate migration are suppressed.

  If the value of the input power Pin becomes lower than the threshold value Pth after the power withstand operation (power withstand mode), the return operation is performed. Similarly, during the return operation (C), the input power Pin detected by the detector 6 is compared with the threshold power Pth. In this case, since Pin <Pth and Vin <Vth, the threshold determination circuit 8 outputs an ON signal. In response to this, the source voltage drive circuit 9 outputs the GND voltage as the output voltage Vs ′ and applies it to the source terminal of the field effect transistor 1 via the resistor 10 (return mode). Thus, Vds, dc = Vd−Vs becomes Vd−Ids × Rs (depends on the return current), and Vgs, dc = Vg−Vs becomes Vg−Ids × Rs (depends on the return current). In the return operation (C), Ids is lowered due to the trap level generated at the drain interface of the gate when returning from the power-resistant mode. Therefore, in the present embodiment, Vgs and dc are shifted in the positive direction by the resistor 10, the gate becomes shallower, and the Ids flows in a larger direction. As a result, the time for the Ids to return to Ids0 is accelerated (recovery time). (Fig. 3, Fig. 6).

  As described above, in the present embodiment, the input power is observed by the detector 6 for observing the output power, and when the input power is lower than the threshold as determined by the threshold determination circuit 8, the source voltage drive circuit 9 Output voltage (Vs ′) is equal to the GND voltage, the gate source voltage (Vgs) is set according to the drain-source current (Ids) by the resistor 10, and the input power is equal to or higher than the threshold value, Since the output voltage (Vs ′) of the source voltage drive circuit 9 is set to be the same as the drain bias voltage (Vd), Vd = Vs ′ when a large signal is input, and the voltage between the terminals of the transistor is Vds = 0, Vgs. Since Vg−Vd, the drain-source overvoltage and the gate forward voltage can be suppressed, and the drain-source and gate bidirectional power durability is improved. Further, since the drain-source current Ids does not flow, the trapping of carriers to the trap level at the interface is reduced, and the recovery characteristic at the time of returning to the steady input is improved. In addition, when the drain-source current Ids decreases due to trapping of carriers at the trap level at the interface when returning to the steady input, the gate-source voltage Vgs = Vg−Rg × Ids becomes shallow (in the direction of 0 V). Since it works in the direction of flow, the effect of improving recovery characteristics can be obtained.

  Note that loading a capacitor and inductor on the source terminal may cause resonance at a low frequency and reduce stability. Therefore, in this embodiment, a stabilization resistor is added to the source voltage drive circuit system. Since the recovery acceleration resistor 10 that has been used for a long time is loaded, stabilization can be achieved by reducing the resonance Q and increasing the loss near the resonance frequency.

  In the above description, Vg is applied to the gate terminal 2 and Vd is applied to the drain terminal 3 and the power supply terminal 11. However, by adjusting the recovery acceleration resistor 10, Vg = 0 is set. The applied voltage may be only Vd, and in that case, a single power source can be realized.

  Further, when the input power at the time of withstand power (B) is relatively low, it is possible to eliminate the detector 6 as shown in FIG. The configuration of FIG. 7 is different from the configuration of FIG. 1 in that the detector 6, the rectifier circuit 7, the threshold value determination circuit 8, the source voltage drive circuit 9, the resistor 10, and the source terminal (S) of the field effect transistor 1. The choke coil 12 connected between them is excluded. Therefore, other configurations are the same as those in FIG. However, in the configuration of FIG. 7, the recovery acceleration resistor 10 and the bypass capacitor 13 are connected between the source terminal (S) of the field effect transistor 1 and GND (ground) so as to be parallel to each other. Yes. In this case, it is possible to suppress the deterioration of NF and the decrease in stability due to the detection circuit-feedforward system, and the configuration can be simplified. In addition, the recovery time can be shortened.

It is the block diagram which showed the structure of the high electric power receiving amplifier which concerns on Embodiment 1 of this invention. It is explanatory drawing which put together the operation | movement of the high electric power tolerance receiving amplifier which concerns on Embodiment 1 of this invention on the table | surface. FIG. 4 is a waveform diagram summarizing operations of the high power withstand voltage receiving amplifier according to the first embodiment of the present invention. It is explanatory drawing which put together the operation | movement of the high electric power tolerance receiving amplifier which concerns on Embodiment 1 of this invention on the graph. It is explanatory drawing which put together the operation | movement of the high electric power tolerance receiving amplifier which concerns on Embodiment 1 of this invention on the graph. It is explanatory drawing which put together the operation | movement of the high electric power tolerance receiving amplifier which concerns on Embodiment 1 of this invention on the graph. It is explanatory drawing which put together the operation | movement of the high electric power tolerance receiving amplifier which concerns on Embodiment 1 of this invention on the graph.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Field effect transistor, 2 Gate terminal, 3 Drain terminal, 4 Input terminal, 5 Output terminal, 6 Detector, 7 Rectifier circuit, 8 Threshold judgment circuit, 9 Source voltage drive circuit, 10 Recovery acceleration resistance, 11 Power supply terminal, 12 choke coil, 13 bypass capacitor, 14 antenna connection terminal (or transmission / reception switching circuit connection terminal).

Claims (2)

A high power withstand receiving amplifier for mounting in the first stage of a wireless communication receiver,
Input and output terminals;
A field effect transistor having a gate terminal connected to one end of the input terminal and a drain bias terminal connected to one end of the output terminal;
A detecting means connected to the other end of the input terminal for detecting input power;
Threshold determination means for comparing the input power detected by the detection means with a predetermined threshold and outputting a comparison result;
A source voltage driving circuit for switching the output voltage and applying the output voltage to the source terminal of the field effect transistor as one of a GND voltage and a drain bias voltage based on the comparison result from the threshold determination means;
A recovery speed-up resistor connected between the source voltage driving circuit and the source terminal of the field-effect transistor,
When the input power is lower than the threshold value, the source voltage drive circuit output is made the same as the GND voltage, and when the input power is more than the threshold value, the source voltage drive circuit output is made the same as the drain bias voltage. A high power withstanding receiving amplifier. A high power withstand receiving amplifier for mounting in the first stage of a wireless communication receiver,
Input and output terminals;
A field effect transistor having a gate terminal connected to one end of the input terminal and a drain bias terminal connected to one end of the output terminal;
A high-power-resistant receiving amplifier comprising: a recovery speed-up resistor and a bypass capacitor connected in parallel to each other with respect to a source terminal of the field effect transistor.

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