JP2008267998A - Failure diagnosis system for semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To carry out a failure diagnosis of a semiconductor integrated circuit during operation without affecting the operation of the semiconductor integrated circuit by shortening the time required from the occurrence of a failure until the detection thereof during the operation of the circuit. <P>SOLUTION: The failure diagnosis system for the semiconductor integrated circuit includes a logic circuit 11 to be diagnosed having a test pattern injecting circuit and a test result extracting circuit; an output holding circuit 12 holding output from the logic circuit to be diagnosed; a failure diagnosis control circuit 3 controlling a failure diagnosis; a microprocessor 9 carrying out arithmetic processing in addition to the failure diagnosis; and a memory 10 storing a program and data. The output holding circuit 12 holds and outputs output immediately before the start of the diagnosis in the logic circuit 11 to be diagnosed during failure diagnosis operation by the control of the microprocessor and failure diagnosis control circuit. Consequently, even if the output of the logic circuit to be diagnosed changes during a BIST diagnosis period, a logic circuit 101 in a subsequent stage is not affected. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a failure detection method for a semiconductor integrated circuit, and more particularly to a failure diagnosis method in an on-line diagnosis in which a high reliability is required and a diagnosis is performed during circuit operation.

  The technological advancement in the electronics and information fields, the complexity and complexization of functions required for a single device are the driving force, the scope of application of programmable electronic devices has expanded, and the reliability required for programmable electronic control devices has also increased. .

  In recent years, the plant has become larger and more integrated, and with highly automated plant operations, there have been issues such as the spread of international safety standards and the lack of skilled personnel. In addition to safety measures, it is becoming necessary to further improve safety, and it has become important to prevent and mitigate the occurrence of accidents and the expansion of damage at each level.

  In order to satisfy the above-mentioned functions and safety standards in plant control devices, it is required to operate reliably when an abnormality is detected, and even if a failure occurs, it is required to stop the process to the safe side. The functional safety system is required to have a special design that emphasizes “safety”, which is different from the control system.

In a programmable electronic control device, it is required to improve a hardware failure detection rate, and in order to satisfy this, it is usual to implement various self-diagnosis functions at the component level of the device and the device. In a semiconductor, particularly an integrated circuit, which is one of the important components of a programmable electronic device, for example, as disclosed in Patent Document 1, a BIST (Built-In Self having a self-diagnosis function built in the semiconductor integrated circuit is disclosed. The self-diagnosis technique called “Test” is used to check the soundness of the functional blocks inside the semiconductor when the power is turned on or at an arbitrary time.
JP 2003-68865 A

  As described above, in a semiconductor integrated circuit, particularly in a highly integrated LSI, as disclosed in Patent Document 1, a technology called BIST (Built-In Self Test) that incorporates self-diagnosis inside the semiconductor integrated circuit. Is used to improve the detection rate of fault locations. However, the BIST is generally used for detecting a failure of a single component before a semiconductor integrated circuit is incorporated in a device. The BIST is used after the device is incorporated, for example, when the device is turned on. The operation of the semiconductor integrated circuit during the self-diagnosis period is limited to a specific case in which the operation of the semiconductor integrated circuit is not affected. In order to diagnose the semiconductor integrated circuit using the BIST during the operation of the apparatus, the diagnosis period It was a problem not to affect the operation of the device during.

  An object of the present invention is to provide a failure diagnosis method capable of performing failure diagnosis during operation of a semiconductor integrated circuit and further reducing the time from failure occurrence to failure detection.

In order to solve the above problems, the present invention mainly adopts the following configuration.
A diagnosis target logic circuit having a test pattern injection circuit on the input side, a test result extraction circuit on the output side, and a logic operation circuit interposed between the injection circuit and the extraction circuit; and an output from the diagnosis target logic circuit An output holding circuit for holding, a fault diagnosis control circuit for controlling fault diagnosis, a microprocessor for performing arithmetic processing in addition to fault diagnosis, a memory for storing a program and data for operating the microprocessor, A failure diagnosis method for a semiconductor integrated circuit comprising:
The output holding circuit is configured to hold and output an output immediately before the start of diagnosis in the diagnosis target logic circuit during a fault diagnosis operation under the control of the microprocessor and the fault diagnosis control circuit.

  In the failure diagnosis method of the semiconductor integrated circuit, the diagnosis target logic circuit is configured to be able to select an operation mode of a normal operation for performing the arithmetic processing and a failure diagnosis operation, and the output holding circuit outputs its own output. A holding function to hold and an opening function to release the holding function and output an input to itself, injecting a test pattern for diagnosis into the diagnosis target logic circuit during a fault diagnosis operation, The operation output result is extracted and the failure diagnosis is performed by comparing the expected value from the injected test pattern data with the extracted output result data by the microprocessor.

  In the failure diagnosis method for the semiconductor integrated circuit, the diagnosis logic circuit switches the input from the previous circuit block and the test pattern input for failure diagnosis, and the flip-flop with selector as the injection circuit, and the logic operation The output circuit includes an output holding circuit and a failure diagnosis control circuit, and a flip-flop with selector as the extraction circuit and the logical operation circuit.

  Further, in the failure diagnosis method for the semiconductor integrated circuit, the flip-flop with selector to be switched, the flip-flop with selector to be sent in, a connection circuit that cascade connects these flip-flops with selector, and the failure that controls these selectors Based on the configuration of the diagnosis control circuit, before executing the fault diagnosis, the selector-equipped flip-flop and the selector-flip-flop to be fed that represent the input and output of the logic operation circuit in the diagnosis target logic circuit This state is temporarily saved in the memory through the connection circuit, and after the failure diagnosis is completed, the temporarily saved data is restored to the switching flip-flop with selector and the selector flip-flop to be sent.

  According to the present invention, it is possible to perform failure diagnosis while operating an LSI, and it is possible to dramatically shorten the time from occurrence of a failure to detection.

  Further, in a safety system or a system that performs control with a high degree of risk, it is possible to reduce the probability of a disaster that may occur in the time from the occurrence of a hardware failure until detection.

  A semiconductor integrated circuit failure diagnosis method according to an embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a block diagram showing the overall configuration of a failure diagnosis method for a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a scan flip-flop used in the failure diagnosis method according to this embodiment. FIG. 3 is a circuit diagram showing an output holding flip-flop used in the failure diagnosis method according to this embodiment. FIG. 4 is a follow chart showing an operation procedure in the fault diagnosis half-cut method of the conductor integrated circuit according to the present embodiment. FIG. 5 is a follow chart showing the detailed procedure of the failure diagnosis process in the flow of FIG.

  In the drawing, 1 is a logic circuit, 2 is a BIST control target circuit, 3 is a BIST control circuit, 4 is an input signal, 5 is an output signal, 6 is a test pattern input, 71 is an input control signal, 72 is an output control signal, 73 Is a holding control signal, 8 is a test result extraction, 9 is a microprocessor, 10 is a memory, 11 is a BIST target logic circuit, 12 is an output holding circuit, 13 is a combinational circuit, 14, 15, 16, and 17 are scan flip-flops, Reference numerals 18 and 19 denote output holding flip-flops, and 101 and 102 denote logic circuits, respectively.

  In FIG. 1, the semiconductor integrated circuit fault diagnosis half-cut method according to the embodiment of the present invention is a BIST control target circuit 2, a BIST control circuit 3, a microprocessor 9, and a memory 10, which are control targets for fault diagnosis using BIST. It has. Further, the logic circuit 1 is connected to the preceding stage of the BIST control target circuit 2 and the logic circuits 101 and 102 are connected to the succeeding stage. All the circuits and wirings shown in FIG. 1 may be mounted in the same integrated circuit.

  The memory 10 stores input data and output data of the BIST target logic circuit 11 before executing the BIST diagnosis, in addition to a program for operating the microprocessor 9, a test pattern of the BIST diagnostic test, and a BIST diagnostic test result. The Further, the microprocessor 9 performs arithmetic processing in addition to BIST diagnostic control, and performs BIST diagnosis by using the idle time of the arithmetic cycle.

  The BIST control target circuit 2 includes a BIST target logic circuit 11 diagnosed by BIST and an output holding circuit 12. During the BIST diagnosis period, the output signal 5 of the BIST control target circuit 2 holds the output immediately before the diagnosis start by the output holding circuit 12. After the BIST diagnosis is completed, the output holding circuit 12 releases the output holding.

  The BIST target logic circuit 11 has scan flip-flops 14, 15, 16 and 17 mounted before and after the combinational circuit 13 (substantial circuit to be self-diagnosed by the BIST). As shown in FIG. 2, the scan flip-flop is composed of a selector and a latch. In the example of the scan flip-flop 15 shown in FIG. 2, an input signal is selected according to the level of a signal (input control signal) 71, When the signal 71 is “1”, the signal 6 is selected, and when the signal 71 is “0”, the signal “4” is selected (as shown in FIG. 2 and FIG. 1). ("0" and "1" of the signal 71 are shown corresponding to the input terminal).

  The output holding circuit 12 includes output holding flip-flops 18 and 19. FIG. 3 shows a configuration example of an output holding flip-flop, which includes a selector and a latch. The output signal 5 is held when the level of the signal 73 (holding control signal) is “1”, and the output from the BIST target logic circuit 11 is output as the signal 5 when the level of the signal 73 is “0”. It is configured.

  Next, the operation of the failure diagnosis method according to this embodiment shown in FIG. 1 will be described. The failure diagnosis method shown in FIG. 1 is configured to operate in two operation modes, a normal operation and a diagnosis operation. The operation mode is switched by sending an instruction from the microprocessor 9 to the BIST control circuit 3. From the input control signal 71, the output control signal 72, and the holding control signal 73.

  The input control signal 71 is a signal for selecting an input signal to the combinational circuit 13. When “1”, the BIST diagnosis test pattern input 6 is selected, and when “0”, the output of the logic circuit 1 is output. Input to the combinational circuit 13.

  The output control signal 72 is an output signal selection signal of the BIST target logic circuit 11 and selects the output of the combinational circuit 13 when the level is “0”. When the level is “1”, the signal latched in the scan flip-flop (scan FF) 16 is the scan FF. F. The signal latched by the selector 17 is applied to the BIS control circuit 3 and the memory 10 through the test result extraction line 8. At this time, the scan F.P. F. 16 input to the selector 1 is the scan F.D. F. 15 becomes a test pattern input signal. That is, when the input control signal 71 is “1” and the output control signal 72 is also “1”, the test pattern input 6 is scanned F.D. F. 14, 15, 16, 17 connected in cascade to each selector 1, F. The signals latched in the memory 10 are sequentially stored in the memory 10.

  In this way, the output data of the combinational circuit 13 is saved in the memory 10 via the BIST control circuit 3 until the test pattern input is completed, and the test result 8 is transferred via the BIST control circuit 3 after the BIST diagnosis is completed. Write to the memory 10.

  The relationship between the output signals 71, 72 and 73 from the BIST control circuit 3 and the diagnostic operation is as follows.

(1) The input control signal 71 is “0”, the output control signal 72 is “0”, the holding control signal 73 is “1”, and the combinational circuit functions normally.
(2) When the input control signal 71 is “1”, the output control signal 72 is “1”, and the holding control 73 is “0”, the test pattern input to the BIST target logic circuit 11 and the output through the test result extraction line 8 are performed. Data evacuation,
(3) When the input control signal 71 is “1”, the output control signal 72 is “0”, and the holding control signal 73 is “0”, a diagnostic operation is performed (the output holding FFs 18, 19 are those selectors). The input “0” has the output holding function immediately before itself, that is, the diagnosis result is not output as the output signal 5 from the BIST control target circuit 2),
(4) When the input control 71 is “1”, the output control 72 is “1”, and the holding control 73 is “0”, the test result is extracted.

  FIG. 4 shows a flowchart of the operation of the failure diagnosis method (system) according to the present embodiment shown in FIG. When the power is turned on or the microprocessor 9 is reset, the system is started and the system is initialized 400. When the start time 401 of the control cycle comes after completion of the initialization, first, a diagnosis process (BIST diagnosis process) 402 is performed (the details of the diagnosis process 402 will be described later with reference to FIG. 5). When an abnormality is detected in the BIST diagnosis, a system stop process 407 is performed in order to keep the system in a safe state. When the BIST diagnosis ends normally, the microprocessor 9 executes normal processing, ie, input processing (404), calculation processing (405), and output processing (406), and waits for the start of the next control cycle. The same process is repeated when the control cycle comes.

  As shown in FIG. 4, the diagnosis process is performed during the idle time (idle time) within the normal control calculation cycle including the input process, the calculation process, and the output process. In the illustrated example, it is shown that the failure diagnosis process is performed before the input process. However, not limited to this time, a free space set after the end of the operation process 405 in view of the variable time length of the operation process. Time may be used. In addition, when the circuit scale of the combinational circuit 13 that is actually a failure diagnosis target shown in FIG. 1 is large, the circuit may be divided into a plurality of times and the failure diagnosis process may be performed by one cycle. The diagnosis time can be shortened.

  Next, details of the diagnostic processing 402 will be described with reference to FIG. In the diagnosis process, first, the state of the BIST target logic circuit 11 (input value and output value of the combinational circuit 13) is saved in the memory 10 (500) (as described above, the scan FFs 14, 15, 16, 17). The test pattern is generated in the microprocessor 9 (501), and the test pattern 6 is input to the BIST target logic circuit 11 (502).

  The output obtained by calculating the test pattern 6 by the combinational circuit 13 is stored in the scan flip-flops 16 and 17 (503), the test result stored in the scan flip-flops 16 and 17 is extracted and sent to the BIST control circuit (504), and The result is transferred to the memory 10 (505). Finally, the result stored in the memory 10 and the result expected value from the test pattern are compared and collated by the microprocessor 9 to complete the diagnosis process (506).

  Further, in the configuration of the failure diagnosis system according to the present embodiment shown in FIG. 1, the microprocessor 9 and the memory 10 are accommodated in the same LSI as the other circuit blocks shown in FIG. 3 can be speeded up, and diagnosis time by BIST can be shortened. Further, when the built-in microprocessor 9 is used not only for diagnosis by BIST but also for control calculation, if the diagnosis time by BIST is short, the time that the microprocessor 9 can be used for control calculation can be increased. Overhead can be reduced.

  Further, when the microprocessor 9 has a large amount of processing and the memory 10 needs to have a large capacity, the microprocessor 9 and the memory 10 can be packaged separately from other circuit blocks.

  Next, a failure diagnosis method for a semiconductor integrated circuit according to another embodiment of the present invention will be described with reference to FIG. FIG. 6 is a block diagram showing the overall configuration of a fault diagnosis method for a semiconductor integrated circuit according to another embodiment of the present invention.

  The other embodiment of the present invention shown in FIG. 6 differs from the embodiment shown in FIG. 1 in that the microprocessor 9 in the processor built-in LSI 602 passes the processorless LSIs 604A, 604B, and 604C via the communication circuit 601. By controlling each BIST control circuit 3, failure diagnosis by BIST is performed, and control of diagnostic operations can be consolidated by integrating processors. That is, the single microprocessor 9 in the processor built-in LSI 602 can perform fault diagnosis processing by circulating through the processor built-in LSI 602 and the BIST target logic circuits in the plurality of processorless LSIs 604A, 604B, and 604C.

  The memory 10 of the processor built-in LSI 602 needs a relatively large capacity to store the program of the microprocessor 9, but the memory 10 of the processorless LSIs 604A, 604B, and 604C includes BIST test data and BIST control targets. Since the input / output of the circuit 2 is temporarily saved and the result of the BIST diagnosis is only stored, the capacity of the memory 10 can be reduced, and the cost can be lower than that of the processor built-in LSI 602.

  As described above, the embodiment of the present invention is characterized by having the following configuration and having a function. In other words, a circuit for injecting a test pattern before the diagnosis target logic circuit, a test result extraction circuit after the diagnosis target logic circuit, an output hold circuit after the test result extraction circuit, and an output hold The circuit holds the output value immediately before the start of the BIST diagnosis of the LSI so that even if the output of the diagnosis target logic circuit changes during the BIST diagnosis period, the subsequent logic circuit is not affected. .

  Thus, the present invention reduces the time from the occurrence of a failure to the detection of a disaster that may occur due to a failure of the semiconductor integrated circuit in a system that requires safety and a system that performs control with high risk. It can be applied as a means and method for preventing the above.

It is a block diagram which shows the whole structure in the failure diagnosis system of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the scan flip-flop used by the failure diagnosis system regarding this embodiment. It is a circuit diagram which shows the flip-flop for output holding | maintenance used with the failure diagnosis system regarding this embodiment. It is a follow chart which shows the operation | movement procedure in the failure diagnosis system of the semiconductor integrated circuit which concerns on this embodiment. It is a follow chart which shows the detailed procedure of the failure diagnosis process in the flow of FIG. It is a block diagram which shows the whole structure in the failure diagnosis system of the semiconductor integrated circuit which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Logic circuit 2 BIST control object circuit 3 BIST control circuit 4 Input signal 5 Output signal 6 Test pattern input 71 Input control signal 72 Output control signal 73 Holding control signal 8 Test result extraction 9 Microprocessor 10 Memory 11 BIST object logic circuit 12 Output Holding circuit 13 Combinational circuit (logical operation circuit)
14, 15 Scan flip-flop 16, 17 Scan flip-flop 18, 19 Output holding flip-flop 101, 102 Logic circuit 601 Communication circuit 602 Microprocessor built-in LSI
604A, 604B, 604C Processorless LSI

Claims (7)

A diagnosis target logic circuit having a test pattern injection circuit on the input side, a test result extraction circuit on the output side, and a logic operation circuit interposed between the injection circuit and the extraction circuit; and an output from the diagnosis target logic circuit An output holding circuit for holding, a fault diagnosis control circuit for controlling fault diagnosis, a microprocessor for performing arithmetic processing in addition to fault diagnosis, a memory for storing a program and data for operating the microprocessor, A failure diagnosis method for a semiconductor integrated circuit comprising:
The output holding circuit holds and outputs an output immediately before the start of diagnosis in the diagnosis target logic circuit during a fault diagnosis operation under the control of the microprocessor and the fault diagnosis control circuit. Fault diagnosis method. In claim 1,
The diagnosis target logic circuit is configured to be able to select an operation mode of a normal operation for performing the arithmetic processing and a failure diagnosis operation,
The output holding circuit has a holding function for holding its own output and an opening function for releasing the holding function and outputting an input to itself,
At the time of a fault diagnosis operation, a test pattern for diagnosis is injected into the diagnosis target logic circuit, an operation output result from the diagnosis target logic circuit is extracted, and an expected value from the injected test pattern data is calculated by the microprocessor. A failure diagnosis method for a semiconductor integrated circuit, wherein the failure diagnosis is performed by comparing and collating the data of the extracted output results. In claim 1 or 2,
The diagnostic logic circuit switches between an input from a previous circuit block and a test pattern input for fault diagnosis, a flip-flop with selector as the injection circuit, an output holding circuit and an output of the logic operation circuit as the fault diagnosis A failure diagnosis method for a semiconductor integrated circuit, comprising: a flip-flop with a selector, which is the extraction circuit, and the logic operation circuit, which are sent to a control circuit. In claim 3,
Based on the configuration of the flip-flop with selector to be switched, the flip-flop with selector to be fed in, a connection circuit for cascading these flip-flops with selector, and the failure diagnosis control circuit for controlling these selectors, Immediately before executing fault diagnosis, the state of the switching flip-flop with selector and the selector flip-flop to be sent representing the input and output of the logic operation circuit in the logic circuit to be diagnosed is temporarily saved in the memory through the connection circuit. Let
A failure diagnosis method for a semiconductor integrated circuit, wherein after the failure diagnosis is completed, the temporarily saved data is restored to the switching flip-flop with selector and the selector flip-flop to be sent. In claim 1 or 2,
The microprocessor executes, in a time-sharing manner, a control operation including input processing, arithmetic processing, and output processing in the logic operation circuit, and the failure diagnosis processing, and the failure diagnosis processing is performed at an idle time within the cycle of the control operation. A failure diagnosis method for a semiconductor integrated circuit, characterized in that In claim 1 or 2,
The logic operation circuit is divided into a plurality of circuits, and the fault diagnosis processing is cyclically executed for each of the divided circuits to reduce the time of fault diagnosis processing per time. Fault diagnosis method. A diagnosis target logic circuit having a test pattern injection circuit on the input side, a test result extraction circuit on the output side, and a logic operation circuit interposed between the injection circuit and the extraction circuit; and an output from the diagnosis target logic circuit An output holding circuit for holding, a fault diagnosis control circuit for controlling fault diagnosis, a microprocessor for performing arithmetic processing in addition to fault diagnosis, a memory for storing a program and data for operating the microprocessor, A semiconductor integrated circuit comprising:
A diagnosis target logic circuit having a test pattern injection circuit on the input side, a test result extraction circuit on the output side, and a logic operation circuit interposed between the injection circuit and the extraction circuit; A plurality of microprocessor-less semiconductor integrated circuits comprising: an output holding circuit that holds the output of: a fault diagnosis control circuit that controls fault diagnosis; and a memory that stores programs and data;
The one semiconductor integrated circuit and the plurality of microprocessor-less semiconductor integrated circuits are connected by a communication circuit,
A failure diagnosis method for a semiconductor integrated circuit, wherein a failure diagnosis process is executed for each of the plurality of microprocessor-less semiconductor integrated circuits through the communication circuit by the microprocessor in the one semiconductor integrated circuit.

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