JP2008267882A - Analysis of digital data signal by evaluating sampled value in relation to signal bit value - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide sampling with digital data signal improved. <P>SOLUTION: A signal analyzer determining property of data signal (D1) which has a bit sequence of a plurality of bits comprises a first sampling circuit (30), in response to first trigger signals (TR1, TR2), adjusted so as to acquire a first sampled value (A1); a trigger circuit (60), in response to a clock signal (CLK) related to a data signal (D1) and adjusted so as to supply the first trigger signals (TR1, TR2); and an analysis circuit (50) adjusted so as to provide signal analysis, based on the sampled value (A1) received from the first sampling circuit (30), in relation to the bit values (B1, B2, B3) of the data signal within a specified time range, in relation to the first trigger signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to sampling digital data signals.

  The characterization of the transient behavior of high-speed digital circuits (ie, transition from logic 0 to logic 1 (and vice versa)) is becoming increasingly important for the design and manufacture of this type of circuit. ing. Timing problems have the potential to cause single transmission errors and temporary (or even permanent) outages of the entire communication system and must be avoided.

  One of the standard feature determination methods for digital circuits is the so-called bit error ratio (BER), that is, the ratio of error bits to the total number of bits of interest. To this end, at a defined sample point, the received digital data signal is sampled iteratively, and a threshold for comparing the expected signal with the response signal (eg, a clock signal (which typically generates a stimulus signal). Each sampling point is determined by the relative time (in relation to the corresponding transition of the system clock or the clock signal derived from or from the response signal).

  A further technique for determining the characteristics of a digital data signal is real-time sampling of this type of signal with a so-called sampling oscilloscope or equivalent sampling. In this case, the sample is targeted for a specific time delay in the context of the trigger signal. In order to determine the position of the edge in the signal, the signal value at the time thus targeted is determined, and this signal value is defined against a predefined (or acquired) edge model. Thus, the position of this edge is determined by fitting. This type of measurement can be determined by a suitable digital oscilloscope, such as the Agilent 86100 Series digital sampling oscilloscope provided by the applicant, Agilent Technologies, which has a rise of less than 20 picoseconds and A high speed digital data signal having an edge having a fall time can be sampled.

  It is an object of the present invention to provide improved sampling of digital data signals. This object is solved by the independent claims. Preferred embodiments are given in the dependent claims.

  In accordance with an embodiment of the present invention, a signal analyzer is provided for determining a digital edge or transition timing of a digital data signal having a sequence of multiple bits. This data signal could be supplied from a device under test (DUT) to be tested according to the specification. The present invention is based on the insight that “signal edges in high-speed digital signals exhibit significant transition durations”. In order to detect edges accurately and in a timely manner, knowledge of the edge shape can be used to sample a signal within such a transition region and fit the sampled value to a known edge shape. By incorporating such an analyzer in an undersampling oscilloscope (that is, an oscilloscope having a sampling rate lower than the data rate of the signal to be sampled), it is possible to accurately determine the timing of the signal edge.

  Thus, the analyzer can use one or more edge models (eg, rising edges and inverted) to determine the characteristics of signal transitions between digital magnitude levels (Low level and High level) of the data signal. If the falling edges are similar, then one unique edge model, otherwise one rising edge model and one falling edge model, or multiple edge models for different bit histories ) Is stored, generated, or accessed. The edge model defines the expected signal level over time of the data signal. By fitting this edge model to the detected signal value, the detected signal value and a timing reference value or a predefined edge value (this predefined edge value is, for example, Low At a magnitude level of 50% between the level and the High level (or the middle size of the edge could be expressed at an intermediate time between the start of the edge and the end of the edge) Convert the difference to a time difference value. By associating this time difference value with the trigger signal, the exact position of the signal edge can be determined.

  The edge model timing reference value may be any value between the Low and High levels, such as the 50% level in the middle between those levels, or at the geometric center of the edge model, and And / or at the transition point with the highest probability.

  An edge model could be defined as a polynomial best fit curve of measured signal edges. An edge model could be represented as a section-by-section curve composed of one or more linear or multinomial sections. Thus, these edge models can be stored as mathematical formulas or algorithms for generating time values from signal values, tables with multiple pairs of curve values and time values for the edge models, or any mixture between algorithms and data Will.

  In one embodiment, the analyzer is responsive to a first trigger signal indicating a plurality of trigger pulses, preferably located within an edge region of the data signal (also referred to as a transition region), An analog sampling circuit that obtains one sample value, a trigger circuit that is responsive to a clock signal associated with the data signal and provides a first trigger signal, and a data signal within a particular time range associated with the first trigger signal. And an analysis circuit for providing signal analysis based on the sample value received from the first sampling circuit in association with the bit value.

  Preferably, the sampling time is determined according to a clock signal associated with the data signal. Accordingly, these time points are selected to be close to the defined edge points (but at least in a region that exhibits significant signal value changes over time).

  If the bit value is known in advance, the bit value could be received directly from the memory storing the bit value. Alternatively, the signal analyzer further comprises a digital sampling circuit that detects the bit sequence. The digital sampling circuit is preferably configured to receive the data signal at a plurality of successive second trigger points in the central region of the bits (ie, in the center of the data eye of the data signal, ie, in the region between signal transitions). Are sampled, the bit sequence of the data signal is regenerated, and these second values are supplied to the analysis circuit. The analysis circuit will provide signal analysis based on both the first and second values.

  By means of the digital sampling circuit, several second values representing several bits (bit history) preceding the transition and (at least one) subsequent bits represent a transition value sampled by the analog sampling circuit. Stored with 1 value.

  In a further embodiment, the data signal is compared with a threshold value, and at a subsequent trigger point, one of the two bit values is determined depending on the result of this comparison (eg if the comparison result is negative). The bit sequence of the data signal is determined by assigning a “0” value and a “1” value if the comparison result is affirmative.

  Accordingly, a second sampling circuit is provided for receiving a second trigger signal in response to the clock signal and comparing the data signal to a threshold at a trigger point of the second trigger signal. The trigger pulse of the second trigger signal is preferably arranged in a region between signal transitions (substantially the center of the so-called data eye).

  In a further embodiment, the analog sampling circuit includes a sample and hold circuit (or track and hold circuit) and an analog / digital converter. The sample and hold circuit receives the first trigger signal, provides an analog value (eg, an analog voltage) of the data signal at each corresponding first trigger time, and stores this value for a specified amount of time, respectively. ing. The analog / digital converter converts the received analog value into a multi-bit digital value (eg, expressed as 12-bit data or 16-bit data).

  In a further embodiment, the time difference measurement is repeated for a plurality of edges. If the data signal has multiple repetitions of the test sequence (eg, 1000 repetitions of a defined bit pattern), the bit pattern is a pseudo-random bit sequence generated by a linear feedback shift register circuit Or any other pattern that includes multiple frequency components and is suitable for timing testing.

  From these measured values, it is possible to derive the jitter characteristics of the data signal. When only measuring bit time intervals with the same bit history (eg, bit intervals at the same position in a repetitive bit pattern), such average differences exclude data-dependent jitter. Represents the jitter component.

  In a further embodiment, the data signal is analyzed in relation to the depth of influence of previous bits on the actual transition (ie in relation to the influence of bit history). This effect can be expressed as the number of preceding bits. In the context of the transition to be analyzed, a sequence of a predefined number of digital values supplied from a digital sampling circuit is collected (ie, each first (multi-bit) sample value is referred to as a bit history). Assigned to a specific sequence (single bit value) of 2 samples).

  To determine some preceding consecutive bits that are affecting the actual transition (ie to determine the depth of the influence of the previous bits on the actual transition) Are sorted and binned according to their bit history (eg, binned into 8 different groups, each associated with one history of a 3-bit sequence). Such binning is further extended to a longer history as long as it exhibits a different average value in relation to the clock signal.

  In a further embodiment, a signal to determine non-data dependent jitter characteristics by generating a trigger signal based on a condition that a predefined history (ie, a predefined bit sequence of a data signal) is detected. Running the analysis.

  If the effect was found to be limited to a few n bits, the data dependent jitter was eliminated by detecting a specific n bit sequence and triggering on each occurrence of this pattern It would be possible to perform a jitter decision. This is particularly advantageous when a long bit sequence is used and analysis of all edge positions will take a long time.

  Alternatively, it is also possible to perform sampling at random timing points, so that the first sample value (representing the actual edge value) and the first sample (representing the bit of the data signal). Two sample values are stored along with their relationship. In post processing, the first sample values are sorted into different bins in relation to a specific number of preceding bits.

  In a further embodiment, the analysis circuit stores one or more edge models, eg, in terms of digital values or in terms of algorithms that provide data values, configured as a table of time / signal value pairs. It has a processing unit. Further, the above-described time difference is determined by digital calculation of a computer. Such models and algorithms could be stored in software programs.

  In a further embodiment, two rising edges are detected between the edges (i.e., between the rising edge of the digital data signal and the adjacent falling edge, between the rising edge and the non-adjacent falling edge). Time interval analysis between two falling edges or between two edges of different data signals), thereby obtaining a sample value for each signal edge. As a result, a first time difference between the first signal sample and the defined signal value and a second time difference between the second signal sample and the defined signal value are determined. Based on the known time difference of the corresponding trigger pulse and the first and second time differences, the time interval between the edges can be determined.

  In further embodiments, a plurality of similar time intervals (e.g., when determining variations in a return-to-zero time interval, part of one bit cycle, when determining cycle-to-cycle time variations, 1 In order to determine a change in a bit cycle or a plurality of bit cycles, measurement of a time difference is repeated for a plurality of bit cycles). If the data signal has multiple repetitions of the test sequence (eg, 1000 repetitions of a defined bit pattern), the bit pattern is a pseudo-random bit sequence generated by a linear feedback shift register Or any other pattern that includes multiple frequency components and is suitable for timing testing.

  From these measured values, it is possible to derive the jitter characteristics of the data signal. It is possible to derive the first jitter characteristic by determining the distribution functions of the first and second time differences with time, determining the average values, and determining the difference between both average values. is there.

  If only the measurement of bit time intervals with the same bit history (eg, bit intervals at the same position in the repeated bit pattern) is performed, the difference between these average values is data dependent jitter. Represents a jitter component excluding. By determining the distribution function of the difference between the second time difference and the first time difference with time, it is possible to derive further jitter components. When this distribution is determined for every bit cycle (or n bit cycles) of the data signal, the width of this distribution (ie, the minimum and maximum values) is the overall value including data dependent and random jitter. Represents cycle-to-cycle jitter. If this distribution is performed for bit time intervals with the same bit history, this width represents random and periodic cycle-to-cycle jitter.

  In a further embodiment, the analysis circuit stores one or more edge models in terms of digital values or in terms of algorithms that provide digital values, eg configured as a table of time / signal value pairs. It has a processing unit. Further, the above-described time difference is determined by digital calculation of a computer. Such models and algorithms could be stored in software programs.

  One limitation in the above method is that the trigger time must be selected to trigger the signal to have a transition region (this is otherwise because of the value of the stored mode). Because the fitting is not feasible). It would be possible to increase the time width of the transition region (i.e., transition time) to improve the trigger time range in which the trigger signal can be placed. For this purpose, it would be possible to connect a filter with a linear phase response between the data input and the sampling circuit. This filter reduces the (absolute) slope of the signal edge without affecting the jitter characteristics of the data signal.

  In a further embodiment, the trigger time interval measurement range is extended by placing a plurality of trigger signals at a defined distance relative to each other. This distance is preferably chosen to be equal to a single transition measurement or trigger time range. Thereby, the resulting measurement range can be multiplied by the number of trigger signals.

  In a further embodiment, an extended sampling circuit having a plurality of sample paths is provided, each of the plurality of sample paths having a sample and hold circuit and an analog / digital converter. Data signals to be sampled are respectively supplied to one sample and holding circuit. Furthermore, a trigger control circuit is also provided for generating a plurality of continuous trigger signals in response to the clock signal. A trigger signal is supplied to each trigger input of the sample and hold circuit. The output of the sample and hold circuit is connected to the respective analog / digital converter. The corresponding digital value generated by the analog / digital converter is fed to an analysis circuit, which is the most significant value (ie “Low” or “High” signal level for further edge fitting). It would be possible to select a value that is not close to or not equal to.

  Alternatively, the extended digital trigger circuit could have only one sample path with a sample and hold circuit and an analog / digital converter. A data signal to be sampled is supplied to the sample and holding circuit. Furthermore, a trigger control circuit is provided to generate a plurality of subsequent trigger signals in response to the clock signal. A trigger signal is supplied to the sample and hold circuit. The sample and hold circuit generates a plurality of analog sample values in response to the respective trigger signals. These trigger signals can be supplied to one analog / digital converter or to multiple analog / digital converters (for example, switched to the output of the sample and hold circuit by a fast-switchable transfer gate in the previous stage) It will be possible. Similar to the previous embodiment, the analysis circuit is receiving an analog value for further processing.

  In a further embodiment, a time interval analyzer that samples two signal edges of interest to derive a time interval between the aforementioned edges, for each edge sample, the extended measurement is performed as described above. It would be possible to apply. As a result, for example, four corresponding trigger signals are supplied to one or more sample and holding circuits to replicate the measurement range. An analysis circuit receiving four analog values would be able to select one value for further processing for each edge. From this selected value, it will be possible to determine the first time difference and the second time difference as described above.

  Alternatively, the sample and holding circuit of the previous embodiment could be replaced by a so-called tracking and holding circuit.

  Embodiments of the invention can be implemented or supported in part or in whole by one or more suitable software programs, which can be stored on or provided by any type of data carrier. And could be performed in and by any suitable data processing unit.

  Many of the other objects and attendant advantages of embodiments of the present invention can be readily understood by reference to the following more detailed description of the embodiments in connection with the accompanying drawings, in which: I can deepen my understanding. Features that are substantially or functionally equivalent or similar have been given the same reference signs.

  FIG. 1 shows a block diagram of a signal analyzer having an input buffer 31 and supplying an input data signal D 1 to an analog sampling path 30 and a digital sampling path 40. The analog sampling path 30 includes a first sample and hold circuit 32 (also referred to as an analog value sample and hold circuit 32) and an analog / digital converter 36. The output of the sample and hold circuit 32 is connected to the input of an analog / digital converter 36. The output of the analog / digital converter 36 is connected to the first input of the signal analysis circuit 50. Also, a clock signal CLK from a source not shown here (eg, supplied from a data source supplying a digital data signal D1 recovered from the data signal D1 or generated by an independent clock). And a trigger circuit 60 that receives the trigger control signal TC from the analysis circuit 50 is also provided. The trigger circuit 60 supplies the first trigger pulse TR1 to the trigger input of the sample and hold circuit 32, and further supplies a converter trigger pulse or a control signal CC to the analog / digital converter 36. In some cases, the time difference between these trigger signals is selected depending on the sample and the holding circuit 32's ability to hold the captured value over time.

  The data signal D1 to be analyzed is supplied to the input buffer 31, which supplies the corresponding buffered signal to the data input of the sample and hold circuit 32, and the sample and hold circuit 32. Is sampling the actual data signal value A1 when the first trigger pulse TR1 is received. This analog value (which could be expressed as an analog voltage within a specific voltage range) is stored for a specific time. The analog / digital converter 36 converts the received analog value into a multi-bit digital value (for example, expressed as 12-bit data or 16-bit data V1). This digital data value is supplied to the analysis circuit 50 for further edge fitting as described above.

  Analysis circuit 50 stores one or more edge models for determining the characteristics of signal edges (eg, rising and falling edges between digital magnitude levels of the data signal). This edge model defines the expected signal value with time of the digital signal D1. Such an edge model could be stored in the form of multiple (multi-bit) digital data (eg, 12-bit data or 16-bit data) having a specific time resolution. Alternatively, the edge model is stored, for example, as the most probable edge polynomial best fit curve or a section-by-section (time or magnitude) curve composed of one or more linear or polynomial sections. It is also possible. This data could be stored in a memory or database that is part of (or can be accessed from) the time interval analyzer.

  By fitting the edge model and the detection signal to each other, it is possible to convert a magnitude difference between the detection signal value and a predefined signal value into a time difference value. The predefined signal value is, for example, the center value at a level of 50% between the “Low” bit signal level and the “High” bit signal level. By associating this time difference value with the clock signal, it is possible to determine the exact position of the signal edge.

  In addition, a digital sampling path 40 (also referred to as a bit history determination path) is provided to acquire a plurality of second sample values from the digital signal D1 at a plurality of consecutive digital path trigger times TD1-TD3. In this case, these trigger points are preferably located at equidistant points in the middle of each bit of the data signal (ie these trigger points are located in the middle of the data eye). ).

  Accordingly, the analysis circuit further includes a comparator 41, a tunable threshold voltage source 42, a sampling flip-flop (or digital sample and hold circuit) 43, and a tuning time delay circuit 44. The first input of the comparator 41 is connected to the buffer 32 to receive the (buffered) data signal D1, and the second input of the comparator 41 has a tunable threshold voltage TH at this input. Connected to a tunable threshold voltage supply 42 for supply. The output of the comparator 41 is connected to the data input of the sampling flip-flop 43. The output of the sampling flip-flop 43 is supplied to the data analysis circuit 50. The trigger input of the sampling flip-flop 43 is connected to a tunable time delay circuit 44 which receives the clock signal CLK and samples the corresponding delayed clock signal. This is supplied to the trigger input of the flip-flop 43. The clock signal CLK is preferably delayed so that the digital path trigger point is centered in the data eye of the digital data signal D1.

  The comparator 41 compares the digital data signal D1 with an average between a low signal level representing a bit value of “0” and a high signal level representing a bit value of “1” (this is also called a 50% level). A constant threshold value TH or a dynamic threshold value applied as, for example, so-called DFE (Decision Feedback Evaluation). The comparator 41 outputs a first value (for example, a low voltage level) when the corresponding comparison value is below the threshold value, and a second value (when the comparison value is above the threshold value TH). For example, a high voltage value “1”) is generated.

  The sampling flip-flops 43 each sample the comparison result at the digital path trigger point and assign the digital time individual comparison results B1 to B3 (supplied as a bit stream to the analysis circuit 50).

  In one embodiment, the analysis circuit 50 may be able to continuously analyze the received bitstreams B1, B2, B3 to detect a predefined bit sequence in this bitstream. As soon as such a predefined bitstream is detected, the analysis circuit 50 supplies the feedback information FI to the trigger circuit 60. As a result, the trigger circuit 60 supplies the trigger pulse TR1 at the next possible signal transition. The correspondingly derived digital values V1 all have the same defined bit history. When such values are collected, multiple times and corresponding time delays are superimposed (eg, as described above in connection with FIG. 3a) such that the length of the bit history covers the history effect. If it is sufficiently long, it may be possible to determine non-data dependent jitter. The number of bits that become part of the bit history may be a fixed number or a selectable number selected by the user.

  Alternatively, it is also possible to perform sampling at random timing points, in which case the first sample value (representing the actual edge value) and the bit of the data signal are represented. ) The second sample value will be stored along with the correlation. In post processing, the first sample values are sorted into different bins in relation to a specific number of preceding bits.

  In a further embodiment, the signal analyzer automatically determines the number of bits according to the history characteristics of the data signal D1.

  In order to determine a number of preceding consecutive bits that are affecting the actual transition (ie to determine the depth of the influence of the previous bit on the actual transition), the analyzer is (1) of the data signal D1. It is adapted to continuously determine the transition value V1 of all bit transitions (or a subset of bit transitions) (such as all rising edges in one test sequence). At the same time, the digital bit sequences B1, B2, B3 received from the sample flip-flop 43 are received and associated with the transition value V1. The analysis circuit 50 then assigns (in a post-processing phase) a defined number of preceding bits B1, B2, B3 sampled in the digital path to respective sample values V1 sampled in the analog path. Yes.

  Alternatively, if the bit sequence of the data signal D1 is known (in other words, if the data signal D1 is basically known), the sampling can be performed without digital sampling. It would be possible to directly assign that sequence to the value V1.

  Further alternatively, the sampled digital sequence is to be synchronized (ie, detection of matching of the sequence portion of the known data signal D1 with the sampled digital sequence) and time correlation with the analog sampling circuit. It would also be possible to use As a result, the analysis circuit 50 will be able to supply the trigger control signal TC to the trigger circuit 60.

  In order to measure the jitter characteristics without data dependent jitter (ie without the influence of bit history), a data signal having a repetitive bit sequence is provided and in the context of each bit sequence. It is possible to trigger this signal repeatedly at the same location. In this method, only one measurement is allowed per iteration, so the overall measurement time increases with the length of the bit sequence. Since it is often necessary (or at least desirable) to have a short test time, it is possible in this method to have a bit sequence as short as 15 bits (eg PRBS) corresponding to the previous example. (Pseudo Random Bit Sequence) only.

  The effect of the previous bit on the actual bit may result from the low pass characteristics of the DUT circuit (ie, internal transmission line, amplifier output stage, etc.). Depending on the length of the transmission line, the specific characteristics, and the data rate, such an effect is limited in time, in other words it has an effect on the actual data signal value. Only a limited number of previous bits.

  Thus, in a further embodiment, the data signal is analyzed in relation to the depth of influence of previous bits on the actual bits (in other words, in relation to the influence of bit history). This depth of influence can be expressed as the number of preceding bits. To determine non-data dependent jitter, the data signal will be triggered at multiple transitions with the same limited bit history (ie, with the same sequence of preceding m bits) ( Where m represents the depth of influence). As a result, long repetitive test patterns can be used without increasing test time. Furthermore, as a result, it is also possible to use non-repetitive data signals.

  Alternatively, analog sampling can be performed at a timing point (preferably equidistant) that is not associated with the data content (ie, bit sequence) of the data signal, in which case 1 It would be possible to select the distance to be greater than or equal to the conversion time of one or more analog / digital converters (eg, a 200 bit cycle distance of the data signal). Within the analysis circuit 50 (or thereby) the corresponding first sample values V1 and V2 and second sample values B1, B2, B3,. . . Are stored together with each other. In post processing, the first sample values are sorted into different bins in relation to their bit history.

  FIG. 4 illustrates the principle for determining the number of bits that are appropriate as a bit history. In the first row H0 on the left side, a bit sequence of “01” which is two bits indicating a transition having a rising edge (that is, a transition from “0” to “1”) is shown. In the second row on the left (which is also called the first history level H1), two 3-bit bit sequences “001” and “101” are shown. The first sequence “001” at this level is equal to the preceding bit “0” plus the sequence “01” in the upper row. The second sequence “101” at this level is equal to the preceding bit “1” plus the sequence “01” in the upper row. On the right side of this level, for each of these sequences, the edge time distributions D001 and D101, which are the results of a plurality of measurements, in relation to the clock signal are shown. The difference between the average values of both distributions D001 and D101 is shown as the first time distance TD1. This time distance indicates the dependence of the first leading bit on the edge timing of the data signal D1.

  In the third row on the left (which is also referred to as the second history level H2), four bit sequences “0001”, “1001”, “0101”, and “1101” are shown. The first sequence “0001” at this level is equal to the preceding bit “0” plus the first sequence “001” in the upper row. The second sequence “1001” at this level is equal to the preceding bit “1” plus the sequence “001” in the upper row. The third sequence “0101” at this level is equal to the preceding bit “0” plus the second sequence “101” in the upper row. The fourth sequence “1101” at this level is equal to the preceding bit “1” plus the second sequence “101” in the upper row. On the right side of this level, there are shown edge time distributions D001, D1001, D0101, and D1101 in four different histories as a result of a plurality of measurements in relation to the reference signal. The difference between the average values of the distributions D0001 and D1001 is shown as the second time distance TD2. This time difference indicates the dependence of the second leading bit on the edge timing of the data signal D1. Although depicted qualitatively, this time distance TD2 is smaller than the first time distance TD1. Note that for the sake of completeness, this same time difference measurement can also be performed for the third and fourth sequences.

  In the fourth row on the left (which is also referred to as the third history level H3), two exemplary bit sequences “00001” and “10001” in eight sequences with 5 bits are shown. . The first sequence “00001” at this level is equal to the preceding bit “0” plus the first sequence “0001” at the upper level. The second sequence “10001” at this level is equal to the preceding bit “1” plus the first sequence “0001” in the upper row. To the right of this level is the first four distributions of edge times in the corresponding history that are the result of multiple measurements in relation to the time reference to illustrate the first two sequences shown in this row. D00001, D10001, D01001, and D11001 are shown. The difference between the average values of both distributions is shown as the third time distance TD3. This time difference indicates the dependency of the third leading bit on the edge timing of the data signal D1. Although depicted qualitatively, this time distance TD3 is smaller than the second time distance TD2. Also in this case, for the sake of completeness, this same time difference measurement is performed for the third and fourth, fifth and sixth, and seventh and eighth sequences not shown here. Note that it is feasible.

  As a result of the history separation at the fourth history level, the average edge times M1, M2, M3, M4,. . . Is obtained as an average value of the corresponding edge time distribution.

  Thus, a simple algorithm for determining the bit history depth could proceed as follows.

  In the first measurement run, a specific number of transition measurements (eg, 1024 samples) are performed. Store the corresponding timing results in separate bins based on their bit history. At the first history level, the timing result is binned based on the value of the first preceding bit. As a result, the measurement samples are sorted into the two bins 001 and 101. For each bin, the average value of the distribution is determined and the corresponding first time distance TD1 is compared with a predetermined (sufficiently small) maximum time. If the first time distance TD1 does not exceed the predetermined maximum time, the depth of influence is expected to be 1 bit. Otherwise, if the first time distance TD1 exceeds the predetermined maximum time, the timing results are sorted into the four bins 0001, 1001, 0101, and 1101 of the second history level H2. Again, from one bin above this level (eg, bin 001) (and / or the average of bins 0101 and 1101) (eg, the average of bins 0001, 1001, etc.) The second time distance TD2 between the two average values is compared with a predefined maximum time. At this stage, if the second time distance TD2 does not exceed the predetermined maximum time, the depth of influence is expected to be 2 bits. Otherwise, this algorithm will continue in the same manner for further history levels.

  Since a sufficient number of results are required to obtain an appropriate distribution of corresponding edge timings, the number of bins for sorting measurements is a limited number of measurements obtained in the first run. (E.g., for 1024 measurements, the algorithm can be stopped at the third history level, each bin averaging 128 measurements on average) Will be included). If the corresponding time difference is found to exceed the predefined maximum time at a particular history level (eg, the third history level H2 at 1024 values), it is sufficient for further sorting. It would be possible to obtain another set of measurements (e.g., again 1024 measurements) in the second measurement run to provide a numerical value. This second measurement run can be executed in parallel with the history level evaluation algorithm (which is a post-processing).

  As described above, the trigger time must be selected so that the signal is sampled within its transition area. In order to improve the corresponding trigger time range, it would be possible to connect a filter exhibiting a linear phase response between the data input and the corresponding sampling circuit. This filter reduces the (absolute) slope of the signal edge without affecting the timing characteristics (eg, jitter characteristics) of the data signal. An alternative extension of the measurement or trigger time range applicable instead of (or in combination with) such a filter is shown in FIG. 5a.

  FIG. 5a shows a block diagram of a signal analyzer with an improved measurement range according to a further embodiment of the invention. As an example, the signal analyzer shows first and second sample and hold circuits 32 and 32 ', the outputs of which are connected to the inputs of analog / digital converters 33 and 33', respectively. Outputs of the analog / digital converters 33 and 33 ′ are connected to a signal analysis circuit 55.

  Also provided is a trigger circuit 60 that receives a clock signal CLK from a source (eg, DUT 10 or any clock having the same frequency as DUT or any frequency associated with data signal D1). The trigger circuit 60 supplies the first trigger pulse TR1 and the shifted trigger pulse TR1 'to the trigger input of the first sample and holding circuit 32 and the trigger input of the second sample and holding circuit 32', respectively. Although not shown here, the trigger circuit further supplies a corresponding converter trigger signal to the analog / digital converter 33 as described with reference to the above-described figure.

  The data signal D1 includes first and second sample and hold circuits 32 and 32 ′ (which sample actual data signal values A1 and A1 ′ when the first trigger pulse TR1 and the second trigger pulse TR1 ′ are received, respectively). Are supplied in parallel (e.g. via an input buffer not shown here) so that the time distance between both trigger signals is less than or equal to the transition duration. Has been determined. The analog / digital converter converts the received analog values A1 and A1 'into digital values V1 and V1'. This digital data value is supplied to the analysis circuit 50 for further edge fitting. For this purpose, the analysis circuit 50 stores one or more edge models (for example, a rising edge model that determines the characteristics of the rising edge and a falling edge model that determines the characteristics of the falling edge). These edge models define expected signal values with time of individual data signals D1.

  The analysis circuit 50 selects one of the received digital values V1 and V1 ′ and pre-defines the aforementioned detection signal value by fitting the selected digital value V1 or V1 ′ to an edge model. The magnitude difference between the signal values being converted is converted into a time difference value as described above, and edge time determination is executed.

  The trigger circuit 60 generates trigger pulses TR1 and TR1 'having a mutually defined distance in relation to the clock signal CLK. This distance is preferably chosen to be equal to a single transition measurement or trigger time range. FIG. 5b shows an example, in which two signal edges are depicted at the trigger time distance TR1'-TR1. This time distance is selected to be equal to the transition measurement range TM1 or TM2. In the example shown here, the measurement ranges are each between 10% point P1 of the signal amplitude (ie, the difference between the high and low levels) and 90% point P2 of the signal amplitude (or , Correspondingly between the corresponding points P3 and P4 of the delayed transition). Thereby, the resulting measurement range TMR can be multiplied by two. By providing further additional sample and hold circuits connected in parallel to the first and second sample and hold circuits 32 and 32 ', the resulting measurement range corresponds to the number of samples and hold circuits And can be expanded.

  As a result, only one of V1 and V1 ′ can be used for edge fitting, and the other value has a High level value, a Low level value, or a value close to these values. . In the example shown here, the first sample and hold circuit 32 derives a sample value V1, which is approximately 40% of the signal amplitude, and is derived from the delay measurement by the second sample and hold circuit 32 ′. The measured value V1 ′ is almost the maximum level. The first value V1 is sufficiently usable for edge fitting, but the value V1 'cannot be used for such edge fitting. Thus, prior to edge fitting, the analysis circuit will determine the most significant value (ie, a value that is not close to or not equal to the Low or High signal value, or a value that indicates a relatively large signal edge absolute slope). It is possible to select.

  Alternatively, the signal analyzer could have first and second sampling paths with one sample and hold circuit and one switchable transfer gate, respectively. In order to alternately supply the first sampling value and the second sampling value to one analog / digital converter, the transfer gate is alternately triggered. As with the previous embodiment, the analysis circuit receives analog values V1 and V1 'for further processing.

  To determine the time interval between two signal edges, for each edge, the fitted detection signal value and a predefined transition value (e.g., “Low” bit signal level and “High” bit signal level). Determine the time distance between corresponding time points (median at 50% level between). From the time difference values determined for the two edges of the signal interval and the known time difference between the corresponding first trigger and second trigger pulses, the analysis circuit 50 can generate a plurality of timing characteristics (eg, FIGS. It would be possible to determine the signal jitter characteristics shown in 3b.

  FIG. 6a shows an exemplary block diagram of a time interval analyzer. The analog sampling circuit has first and second sample and hold circuits 32 and 33, and this output is input to an analog / digital converter 36 via first and second transfer gates 34 and 35, respectively. It is connected. The data signal D1 is supplied to the input of a buffer 31, which is connected to the inputs of both the first and second sample and holding circuits 32 and 33.

  Similar to the analyzer of FIG. 1, the time interval analyzer has a digital sampling circuit for determining the bit history, which comprises a comparator 41, a tunable threshold voltage source 42, a sampling. A flip-flop 43, a tunable time delay circuit 44, and an analysis circuit 50 are further included.

  The data signal D1 is supplied to the first input of the comparator 41. The second input of the comparator 41 is connected to a tunable threshold voltage supply 42 which supplies a tunable threshold voltage TH to this input. The output of the comparator 41 is connected to the data input of the sampling flip-flop 43. The output of the sampling flip-flop 43 is supplied to the analysis circuit 50. The trigger input of the sampling flip-flop 43 is connected to a tunable time delay circuit 44, which receives the clock signal CLK and samples the corresponding tuned trigger signal. This is supplied to the flip-flop 43.

  The digital sampling circuit measures the position determined by the relative time set by the delay circuit 44 in relation to the transition of the corresponding clock signal CLK and the threshold value TH.

  The trigger circuit 60 receiving the clock signal CLK receives the first trigger pulse TR1 supplied to the first sample and holding circuit 32 and the second trigger pulse TR2 supplied to the second sample and holding circuit 33. A two-gate trigger or control signal SG1 and SG2 is supplied to the control inputs of the first and second transfer gates 34 and 35, respectively, and a converter control signal CC is supplied to the analog / digital converter 36.

  As previously mentioned, it would be possible to perform analog sampling at timing points that are not associated with the data content of the data signal. Within the analysis circuit 50 (or thereby), the corresponding first sample values V1 and V2 and the second sample values B1, B2, B3,. . . Are stored with each other. In post processing, the first sample values are sorted into different bins in relation to a particular bit history.

  To derive non-data dependent jitter characteristics, it would be possible to use only the time difference value of one pair of bins for time interval analysis.

  In a further embodiment, an appropriate number of history bits could be derived by the algorithm described in connection with FIG.

  The number of bits that become part of the transition history may be a fixed number or a selectable number selected by the user or automatically determined by the analyzer.

  In order to determine a number of preceding consecutive bits that affect the actual transition, a trigger circuit similar to that of FIG. 1 is responsible for all of the data signal D1 (eg, all rising edges in one test sequence). It would be adaptable to continuously determine the transition value V1 of a bit transition or a subset of bit transitions. At the same time, the digital bit sequences B1, B2, and B3 received from the sample flip-flop 43 are received and associated with the transition value V1. As a result, the analysis circuit 50 assigns a predefined number of preceding bits B1, B2, and B3 sampled in the digital sampling circuit to each first sample value V1 sampled by the analog sampling circuit path. It will be possible.

  In a further embodiment, the signal analyzer automatically determines the number of bits depending on the history characteristics of the data signal D1, as described in connection with FIG.

  When the bit sequence of the data signal D1 is known (in other words, when the data signal D1 is basically known), the sampled value V1 is changed to the sampled value V1 without digital sampling. It would be possible to assign a sequence. In this case, digital sampling at a specific time is sufficient to synchronize with the data signal D1.

  FIG. 6b shows a variation of FIG. 6a in which two analog / digital converters 36a and 36b are connected to one of the sample and hold circuits 32 and 33, respectively. Therefore, it is not necessary to provide the transfer gate 34 or 35 to alternately supply the first signal sample A1 and the second signal sample A2 to the converter circuit. As a result, high speed data can be processed by the two converters operating in parallel. Furthermore, accuracy is also improved because no transfer gates with the possibility of introducing errors are included.

  FIG. 6c shows a variation of FIG. 6b in which a sampling circuit is configured to receive a first trigger pulse TR1 and a second trigger pulse TR2 at its trigger input and a data signal D1 at its signal input. The sample and holding circuit 301 and, typically, the second and third sample and holding circuits 302 and 303 are output from the first sample and holding circuit 301 in their signal inputs. A signal is being received. The trigger circuit 60 alternately supplies the third and fourth trigger pulses TR21 and TR22 to the respective trigger inputs of the third and fourth sample and holding circuits 302 and 303 described above.

  The high bandwidth first sample and hold circuit provides accurate sampling with little signal degradation. However, the holding time that such a high bandwidth sample and holding circuit can have is short. In this embodiment, only one sample and hold circuit 301 needs to have the maximum bandwidth, and the sample and hold circuits 302 and 303 can have a relatively low bandwidth. And can be optimized for relatively long holding times. As a further advantage, the input signal has a relatively small load impact compared to the previous embodiment.

  Also, due to the presence of two analog / digital converters 36a and 36b, they can have a lower frequency (ie, a lower conversion rate) compared to the single analog / digital converter 36 of FIG. 6a. (Ie, this circuit will be able to handle twice as many samples).

  In a further embodiment, by providing additional sample and hold circuits connected in parallel to the sample and hold circuits 302 and 303, the conversion rate of the corresponding analog / digital converter is reduced or the corresponding processing rate is increased. Is further realized.

  FIG. 2a shows a first diagram of a non-NRZ (Return-To-Zero) data signal having a signal magnitude A with time t. This data signal typically has the bit sequence “01001” within bit cycles 1-5. As an example, the Low signal level AL representing the “0” bit is equal to zero. Therefore, the 50% level between the low signal level AL and the high signal level AH representing “1” is equal to AH / 2.

  Exemplarily, the first time interval TM1 between the rising signal edge E1 and the falling signal edge E2 of the second bit is determined. The corresponding first signal sample A1 is obtained by sampling the data signal at the first sample time T1, and the corresponding second signal value A2 is obtained by sampling at the second sample time T2. These values are fitted to the rising edge model EM1 and the falling edge model EM2, respectively. The edge models EM1 and EM2 define the edge characteristics of the data signal D1. From the difference in magnitude between the median value at the first sampling value A1 and the signal level of 50% and the median value at the signal level of the second sampling value A2 and 50%, the time difference at the rising and falling edges, respectively Alternatively, the displacements Δt1 and ΔT2 are respectively determined. Since the difference between the first sample time T1 and the second sample time T2 corresponds to the bit cycle time T, the time interval TM1 is subtracted from the cycle time T by the displacement Δt1 of the rising edge time. It is obtained by adding the displacement ΔT2 of the falling edge time.

  FIG. 2b shows a variant of the measurement of FIG. 1 in the multicycle time interval TM2. The data signal typically has a third rising edge between the first and second bit cycles and a fourth rising edge between the nth bit cycle and the (n + 1) th bit cycle. . Corresponding to FIG. 2a, by determining the third and fourth time differences ΔT3 and ΔT4 at both rising edges, subtracting the third time displacement ΔT3 from the n cycle time nT and adding the fourth time difference ΔT4 thereto. Determine the difference between both edges.

FIG. 3a, for example, is repeated for each 1 bit, each having the same bit history at the same location in the repeated test bit pattern (or having the same history of the defined length described above). As a result of the measurement, a schematic diagram of the first distribution DE1 of all rising edge times and the second distribution DE2 of all falling edge times with time t is shown. This test bit pattern may be a pseudorandom bit sequence of length 2 ¹⁵ -1 repeated 1000 times. Average values M1 and M2 are determined for both distributions DE1 and DE2. The difference between the average values M1 and M2 represents the so-called DCD (Duty Cycle Distortion) of the data signal.

  FIG. 3b again shows a schematic diagram of the third distribution DER of the bit interval TM1 as a result of repeated measurements on each 1 bit having the same bit history. Since the cycle time T is constant, the variation of the bit interval is equal to the variation of the difference between the time differences Δt1 and ΔT2. The difference between the maximum bit interval MAX and the minimum bit interval MIN represents the peak-to-peak value of cycle-to-cycle jitter. When only bits having the same bit history are measured, this value does not include data dependent jitter DDJ (Data Dependent Jitter), but includes random jitter and periodic jitter.

  As an alternative, it may be possible to measure all bit intervals of a repeated test sequence independently of the bit history. In this case, the difference between the maximum bit interval MAX and the minimum bit interval MIN represents the peak-to-peak value of the entire cycle-to-cycle jitter including the data dependent jitter DDJ. By obtaining the difference between this measurement and the previous measurement (which measures only bits with the same history), it is possible to determine the data dependent jitter DDJ.

  FIG. 7 shows a schematic diagram illustrating jitter separation by bit history considerations that can be performed in the signal analyzer 50 of FIG. 1 or FIGS. 6a-6c.

  In C1, which is the first diagram, time difference values Δt1, Δt2, and Δt3 are obtained from sample values at successive time points T1, T2, and T3 in the transition region of the data signal D1. These values are obtained for transitions with different bit histories. Therefore, jitter analysis of these values will include data dependent jitter.

  The second diagram, C2, includes average time differences M1, M2, M3,... Associated with bit histories with different sampling values (eg, obtained by measurement according to FIG. 4). . . Average time difference values Δt1 ′, Δt2 ′, Δt3 ′ associated with are shown.

  C3 in FIG. 3 includes adjusted difference values Δt1c obtained as a result of obtaining the differences Δt1-Δt1 ′, Δt2-Δt2 ′, Δt3-Δt3 ′ between the time difference value and the average time difference value, respectively. , Δt2c, Δt3c are shown. The jitter analysis of these values does not include data-dependent jitter, and again includes random jitter and periodic jitter.

  For further decomposition, it is possible to perform a discrete Fourier transform (preferably a fast Fourier transform) of the adjusted time difference values Δt1c, Δt2c, Δt3c, resulting in a power density spectrum P at frequency f. It is done. In the presence of periodic jitter, this spectrum will show one or more individual frequency lines.

  By providing spectral jitter analysis, it is possible to detect a jitter component, for example, by deriving a periodic jitter component by converting one or more identified individual spectral components into the time domain. It is possible.

  C4 shows an example of the power density spectrum derived from the discrete Fourier transform of the adjusted time difference values Δt1c, Δt2c, Δt3c. As a result, as an example, the peak frequencies S1 to S6 indicating periodic jitter are shown. And a power density spectrum P having a substantially constant function of the frequency C6 indicating random jitter. As an example, the frequency peaks S1 to S5 are equally spaced at the exemplary frequencies f1 to f5.

  Instead of analyzing the single-ended ground reference signal D1, it would be possible to receive this signal as a differential signal transmitted over a differential line. The differential signal can be terminated by an input buffer that generates a ground reference signal from the differential signal. Alternatively, the input buffer, one or more sample and hold circuits, and / or one or more analog / digital converters of the previous embodiments could be implemented as a differential signal circuit. .

Finally, representative embodiments of the present invention are listed.
(Embodiment 1)
In a signal analyzer for determining the characteristics of a data signal (D1) having a bit sequence of multiple bits,
A first sampling circuit (30) adapted to obtain a first sample value (A1) from the data signal (D1) in response to a first trigger signal (TR1, TR2);
A trigger circuit (60) adapted to supply the first trigger signal (TR1, TR2) in response to a clock signal (CLK) associated with the data signal (D1);
The sample value (A1) received from the first sampling circuit (30) in relation to the bit value (B1, B2, B3) of the data signal within a specific time range in relation to the first trigger signal. An analysis circuit (50) adapted to provide signal analysis based thereon;
A signal analyzer comprising:

(Embodiment 2)
Receiving a second trigger signal (TS1, TS2) in response to the clock signal (CLK), comparing the data signal (D1) to a threshold value (VTH) in response to the second trigger signal; 2. The embodiment 1 further comprising a second sampling circuit (40) adapted to assign the bit values (B1, B2, B3) as a result of a corresponding comparison in response to two trigger signals (TS1, TS2). Signal analyzer.

(Embodiment 3)
The trigger circuit (60) provides the first trigger with a trigger pulse (TR1, TR2) in the time domain of the transition of the data signal (D1) and triggers in the domain between signal transitions Embodiment 3. The signal analyzer according to embodiment 2, adapted to supply said second trigger signal comprising pulses (TS1, TS2).

(Embodiment 4)
The analysis circuit (50) stores the edge models (EM1, EM2) of the signal edges (E1, E2, E3, E4) of the data signal (D1) that define the magnitude of the signal with time in the transition region. And any of embodiments 1-3 adapted to determine a first time difference (Δt1) between a first sample value (A1) and a predefined transition value from the edge model. Signal analyzer.

(Embodiment 5)
The predefined signal values are the geometric center in relation to the time of the edge model (EM1, EM2), the geometric center in relation to the size of the edge model (EM1, EM2), and the most probable Embodiment 5. The signal analyzer of embodiment 4 representing one of the high transition points.

(Embodiment 6)
The edge model (EM1, EM2) is a polynomial best-fit curve of measurement signal edges (E1, E2, E3, E4), a curve per section composed of one or more linear or polynomial sections, and a plurality of measurements. Embodiment 6. The time interval analyzer according to embodiment 4 or 5, representing one of the curves based on edge curves (E1, E2, E3, E4).

(Embodiment 7)
The first sampling circuit (30) includes any one of the first to sixth embodiments including an analog / digital converter (23, 36) that converts the first sampling value (A1) into a multi-bit digital value (V1). Signal analyzer as described.

(Embodiment 8)
The analysis circuit (50) stores the multi-bit digital value (V1) and the bit values (B1, B2, B3), so that a predefined number for each multi-bit digital value (V1). Of consecutive bit values (B1, B2, B3), the set of consecutive bits in the data signal (D1) occurring before the corresponding assigned multi-bit digital value (V1) 8. The signal analyzer of embodiment 7, wherein the signal analyzer represents at least in part a historical sequence of:

(Embodiment 9)
The analysis circuit (50) is adapted to sort the multi-bit digital values (V1) into a plurality of different groups according to their respective bit histories, each group being a digital sequence of a predefined number of bits. Embodiment 9. The signal analyzer of embodiment 8 associated with a unique bit history represented as:

(Embodiment 10)
The first time difference (Δt1) at a plurality of different signal transitions in the data signal (D1) is repeatedly determined, and the average value (M1, M2, M3, M4) of the fluctuation of the first time difference (Δt1) is determined. 10. The signal analyzer according to embodiment 9, adapted to determine for each bit history.

(Embodiment 11)
Further adapted to determine non-data dependent jitter characteristics of the data signal (D1) by analyzing a variation distribution of the first time difference (Δt1) associated with the group of measurement values having the same bit history. Embodiment 11. The signal analyzer according to embodiment 9 or 10.

(Embodiment 12)
Analyzing the variation distribution of the first time difference (Δt1) associated with a plurality of groups having different bit histories by considering the determined average values (M1, M2, M3, M4); Embodiment 11. The signal analyzer of embodiment 10 further adapted to determine non-data dependent jitter characteristics of the data signal (D1).

(Embodiment 13)
A sequence of first time difference values (Δt1, Δt2, Δt3) is determined based on the first sample value obtained by the first sampling circuit (30), and is related to the bit history of the corresponding first time difference value Determining a corrected sequence (Δt1 ′, Δt2 ′, Δt3 ′) by subtracting the average values (M1, M2, M3, M4) from the respective first time difference values (Δt1, Δt2, Δt3); Embodiment 10 that provides a time-to-frequency conversion of the corrected sequence and is further adapted to detect individual lines (S1, S2, S3, S4, S5, S6) in the corresponding spectrum Signal analyzer as described in

(Embodiment 14)
Further to analyze the first time difference value (Δt1) to determine a number of preceding consecutive bits that affect the actual bits and to determine the predefined number of consecutive bit values therefrom. Embodiment 14. A signal analyzer according to any of embodiments 8 to 13, which is adapted.

(Embodiment 15)
Setting the predefined number of bits to a first value, deriving average values (M1, M2, M3, M4) associated with different bit histories, and the time distance (TD1, Embodiment 15. The signal analyzer of embodiment 14, wherein the signal analyzer is further adapted to analyze TD2, TD3) and to increment the number of bits when the time distance exceeds a predefined maximum.

(Embodiment 16)
The control circuit (60) includes the first trigger pulse (TR1) in the first region of the first signal transition (E1, E3) and one or more bit cycles of the first data signal (D1). Is further adapted to generate a first trigger signal having a second trigger pulse (TR2) delayed with respect to the first trigger pulse (TR1), the analysis circuit (50) comprising: A time interval value (TM1, TM2) between signal transitions of the first data signal (D1) is determined based on the sample value pair (A1, A2) associated with the second trigger pulse pair (TR1, TR2). Embodiment 16. A signal analyzer according to any of embodiments 1 to 15, which is further adapted to do so.

(Embodiment 17)
The control circuit (60) includes the first trigger pulse (TR1) and a predetermined time distance selected to be equal to or less than a duration of a signal transition of the first data signal (D1). Generating a first trigger signal having a second trigger pulse (TR1 ′) delayed with respect to (TR1), obtaining a corresponding first sample value pair (A1, A1 ′), and Embodiment 17. The signal analyzer according to any of embodiments 1-16, further adapted to select the most significant sample values from each pair for further analysis.

(Embodiment 18)
In a method for determining the characteristics of a data signal (D1) having a sequence of multiple bits,
Providing a first trigger signal (TR1, TR2) in response to a clock signal (CLK) associated with the data signal (D1);
Supplying a first sample value (A1) from the data signal (D1) in response to the first trigger signal (TR1, TR2);
Providing a signal analysis based on the first sample value (A1) in relation to the bit value (B1, B2, B3) of the data signal within a specific time range in relation to the first trigger signal;
A method characterized by comprising:

(Embodiment 19)
A software program that is stored on a data carrier and that controls execution of the method of embodiment 18 when run on a data processing system such as a computer.

1 is a schematic block diagram of a sampling device having a digital sampling path and an analog sampling path according to an embodiment of the present invention. FIG. 6 illustrates a portion of a first exemplary data signal over time having an exemplary time measurement associated with a time interval between two adjacent signal edges. FIG. 6 illustrates a portion of a second exemplary data signal with time having an exemplary time measurement between signal edges having a plurality of clock cycle distances. FIG. 5 is a schematic diagram of the distribution of repeated measurement rising and falling edge times for each one bit having the same bit history. It is the schematic of distribution of cycle time obtained as a result of the measurement of FIG. FIG. 6 shows an exemplary time distribution of different bins and a tree diagram with different hierarchies of bit history for rising edges collected in different bins. Fig. 4 is a schematic block diagram of a sampling device with an improved measurement range according to a further embodiment of the invention. Fig. 5b is an exemplary sampling diagram associated with Fig. 5a. 4 is a more detailed block diagram in which the time interval analyzer according to FIG. 1a or FIG. 1b has a digital sampling path according to FIG. FIG. 6b shows a variation of FIG. 6a with two analog / digital converters. FIG. 6b shows a variation of FIG. 6b in which the sampling circuit has three samples and a holding circuit. It is the schematic which shows isolation | separation of the jitter which considered the bit history.

Explanation of symbols

A1 First sample value B1, B2, B3 Bit value CLK Clock signal D1 Data signal E1, E2, E3, E4 Signal edge EM1, EM2 Edge model M1, M2, M3, M4 Average value of variation S1, S2, S3, S4 , S5, S6 Individual lines TD1, TD2, TD3 Time distance between average values TM1, TM2 Time interval value TR1, TR2 Trigger signal TS1, TS2 Trigger pulse VTH threshold V1 Multi-bit digital value Δt1, Δt2, Δt3 First time difference value Δt1 ′, Δt2 ′, Δt3 ′ Corrected sequence 2, 2 ′, 6 Time interval analyzer 23, 36 Analog / digital converter 30 First sampling circuit 40 Second sampling circuit 50 Analysis circuit 60 Trigger circuit

Claims (19)

In a signal analyzer for determining the characteristics of a data signal (D1) having a bit sequence of multiple bits,
A first sampling circuit (30) adapted to obtain a first sample value (A1) from the data signal (D1) in response to a first trigger signal (TR1, TR2);
A trigger circuit (60) adapted to supply the first trigger signal (TR1, TR2) in response to a clock signal (CLK) associated with the data signal (D1);
The sample value (A1) received from the first sampling circuit (30) in relation to the bit value (B1, B2, B3) of the data signal within a specific time range in relation to the first trigger signal. An analysis circuit (50) adapted to provide signal analysis based thereon;
A signal analyzer comprising:   Receiving a second trigger signal (TS1, TS2) in response to the clock signal (CLK), comparing the data signal (D1) to a threshold value (VTH) in response to the second trigger signal; 2. The second sampling circuit (40) further adapted to assign the bit values (B 1, B 2, B 3) as a result of a corresponding comparison in response to two trigger signals (TS 1, TS 2). Signal analyzer.   The trigger circuit (60) provides the first trigger with a trigger pulse (TR1, TR2) in the time domain of the transition of the data signal (D1) and triggers in the domain between signal transitions Signal analyzer according to claim 2, adapted to supply the second trigger signal comprising pulses (TS1, TS2).   The analysis circuit (50) stores the edge models (EM1, EM2) of the signal edges (E1, E2, E3, E4) of the data signal (D1) that define the magnitude of the signal with time in the transition region. And adapted to determine a first time difference (Δt1) between a first sample value (A1) and a predefined transition value from the edge model. Signal analyzer.   The predefined signal values are the geometric center in relation to the time of the edge model (EM1, EM2), the geometric center in relation to the size of the edge model (EM1, EM2), and the most probable 5. A signal analyzer according to claim 4 representing one of the high transition points.   The edge model (EM1, EM2) is a polynomial best fit curve of measurement signal edges (E1, E2, E3, E4), a curve per section made up of one or more linear or polynomial sections, and a plurality of measurements. The time interval analyzer (2, 2 ', 6) according to claim 4 or 5, representing one of the curves based on edge curves (E1, E2, E3, E4).   The first sampling circuit (30) includes an analog / digital converter (23, 36) for converting the first sampling value (A1) into a multi-bit digital value (V1). Signal analyzer as described.   The analysis circuit (50) stores the multi-bit digital value (V1) and the bit values (B1, B2, B3), so that a predefined number for each multi-bit digital value (V1). Of consecutive bit values (B1, B2, B3), the set of consecutive bits in the data signal (D1) occurring before the corresponding assigned multi-bit digital value (V1) The signal analyzer of claim 7, wherein the signal analyzer is at least partially representative of one history sequence.   The analysis circuit (50) is adapted to sort the multi-bit digital values (V1) into a plurality of different groups according to their respective bit histories, each group being a digital sequence of a predefined number of bits. 9. The signal analyzer of claim 8 associated with a unique bit history represented as:   The first time difference (Δt1) at a plurality of different signal transitions in the data signal (D1) is repeatedly determined, and the average value (M1, M2, M3, M4) of the fluctuation of the first time difference (Δt1) is determined. 10. The signal analyzer of claim 9 adapted to determine for each bit history.   Further adapted to determine non-data dependent jitter characteristics of the data signal (D1) by analyzing a variation distribution of the first time difference (Δt1) associated with the group of measurement values having the same bit history. The signal analyzer according to claim 9 or 10.   Analyzing the variation distribution of the first time difference (Δt1) associated with a plurality of groups having different bit histories by considering the determined average values (M1, M2, M3, M4); 11. A signal analyzer according to claim 10, further adapted to determine non-data dependent jitter characteristics of the data signal (D1).   A sequence of first time difference values (Δt1, Δt2, Δt3) is determined based on the first sample value obtained by the first sampling circuit (30), and is related to the bit history of the corresponding first time difference value Determining a corrected sequence (Δt1 ′, Δt2 ′, Δt3 ′) by subtracting the average values (M1, M2, M3, M4) from the respective first time difference values (Δt1, Δt2, Δt3); 11. A time-frequency conversion of the corrected sequence is provided and is further adapted to detect individual lines (S1, S2, S3, S4, S5, S6) in the corresponding spectrum. Signal analyzer as described in   Further to analyze the first time difference value (Δt1) to determine a number of preceding consecutive bits that affect the actual bits and to determine the predefined number of consecutive bit values therefrom. 14. A signal analyzer according to any of claims 8 to 13, which is adapted.   Setting the predefined number of bits to a first value, deriving average values (M1, M2, M3, M4) associated with different bit histories, and the time distance (TD1, 15. A signal analyzer according to claim 14, wherein the signal analyzer is further adapted to analyze TD2, TD3) and to increment the number of bits if the time distance exceeds a predefined maximum.   The control circuit (60) includes the first trigger pulse (TR1) in the first region of the first signal transition (E1, E3) and one or more bit cycles of the first data signal (D1). Is further adapted to generate a first trigger signal having a second trigger pulse (TR2) delayed with respect to the first trigger pulse (TR1), the analysis circuit (50) comprising: A time interval value (TM1, TM2) between signal transitions of the first data signal (D1) is determined based on the sample value pair (A1, A2) associated with the second trigger pulse pair (TR1, TR2). Signal analyzer according to any of the preceding claims, further adapted to do so.   The control circuit (60) includes the first trigger pulse (TR1) and a predetermined time distance selected to be equal to or less than a duration of a signal transition of the first data signal (D1). Generating a first trigger signal having a second trigger pulse (TR1 ′) delayed with respect to (TR1), obtaining a corresponding first sample value pair (A1, A1 ′), and 17. A signal analyzer according to any one of the preceding claims, further adapted to select each of the most significant sample values from each pair for further analysis. In a method for determining the characteristics of a data signal (D1) having a sequence of multiple bits,
Providing a first trigger signal (TR1, TR2) in response to a clock signal (CLK) associated with the data signal (D1);
Supplying a first sample value (A1) from the data signal (D1) in response to the first trigger signal (TR1, TR2);
Providing a signal analysis based on the first sample value (A1) in relation to the bit value (B1, B2, B3) of the data signal within a specific time range in relation to the first trigger signal;
A method characterized by comprising:   19. A software program stored on a data carrier for controlling execution of the method of claim 18 when running on a data processing system such as a computer.

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