JP2008263439A - Class f amplifying circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a class F amplifying circuit which has high efficiency even at high frequency where output capacity of an amplifying element (FET) can not be neglected. <P>SOLUTION: The class F amplifying circuit includes an FET 10 which outputs a signal having a basic angular frequency<SB>ωo</SB>and a harmonic component of an input signal, a first reactance two-terminal circuit 12 to which an output terminal N<SB>OF</SB>of the FET and a ground terminal are connected, a basic wave matching circuit 16 disposed on the side of the output terminal N<SB>OF</SB>of the FET, a second reactance two-terminal circuit 14 connected between an input terminal of the basic wave matching circuit and the output terminal of the FET, and a load 22 to which the output terminal of the basic wave matching circuit and the ground terminal are connected, the output impedance of the FET being equal to the impedance of a parallel circuit comprising an output resistance Ro and an output capacitor Co. The first reactance two-terminal circuit 12 is open to DC and short-circuited to even-order harmonic components, and resonates with the output capacitor Co in parallel to odd-order harmonic components, and the second reactance two-terminal circuit, on the other hand, is short-circuited to DC and open to odd-order harmonic components. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a class F amplifier circuit, in a class F operation high frequency semiconductor device in which the impedance viewed from the amplifier element is short-circuited for even harmonics and open for odd harmonics. The present invention relates to a class F amplifier circuit including a harmonic processing circuit that brings the output impedance of the fundamental wave close to the load impedance.

  In recent years, transistors capable of high-frequency operation such as high electron mobility transistors (HEMT) and hetero-junction bipolar transistors (HBT) have been put into practical use. According to these elements, an operating frequency in the 50 to 60 GHz band can be realized.

  In these elements, harmonics may be actively used to improve gain. In this case, it is desirable to suppress power consumption due to harmonics in order to improve power efficiency.

  For this purpose, a so-called class F amplifier circuit is used. The principle of the class F amplifier circuit is to prevent the instantaneous voltage waveform and the instantaneous current waveform from overlapping at any time.

  For this purpose, it is necessary to short-circuit the impedance viewed from the output terminal of the transistor to the even-order harmonics and open to the odd-order harmonics. As a result, the current at the transistor output terminal can be a frequency component of only the fundamental wave and the even-order harmonic component, and the voltage can be a frequency component of only the fundamental wave and the odd-order harmonic component, eliminating power loss due to the harmonic. . At this time, if the phase of the current and voltage of the fundamental wave is completely opposite, direct current power can be converted to microwave power with 100% efficiency.

  In order to make the high-frequency power amplifier highly efficient, not only the impedance expected from the amplifying element is matched to the fundamental wave, but also harmonics that are short-circuited for even harmonics and open for odd harmonics A class F amplifier circuit including a processing circuit is disclosed in Patent Document 1 and Patent Document 2 (see, for example, Patent Document 1 and Patent Document 1).

  For example, in the case of an internal matching FET in which an amplifying element is a field effect transistor (FET) and a DC bias Vdd is supplied from the RF output terminal of the envelope to the drain, as disclosed in Patent Document 1 In addition, if a harmonic processing circuit composed of a distributed constant circuit is built in, the area of the distributed constant circuit increases, and thus the area of the envelope also increases.

  Further, as disclosed in Patent Document 2, a small harmonic processing circuit constituted by a lumped constant circuit is open in terms of DC, and is connected to the drain of the FET via a choke coil on a different path from the harmonic processing circuit. Since the DC bias is directly supplied, it cannot be used for a high-power internal matching FET that supplies a DC bias from the RF output terminal.

  In addition, since the output impedance of the high-power FET with respect to the fundamental frequency is lower than that of the load, when the harmonic processing circuit disclosed in Patent Document 2 is applied, the output impedance is further lowered and matching with the load is performed. It becomes difficult to plan.

In both cases, since the impedance expecting the load from the drain of the FET is opened with odd harmonics, class F operation is performed at a frequency where the output capacity of the FET can be ignored, but at a high frequency where the output capacity of the FET cannot be ignored. Deviate from class F operation.
JP 2001-111362 A JP 2005-117200 A

  The object of the present invention is that a DC bias can be supplied from the RF output terminal, the size can be reduced, and a high-efficiency class F operation can be achieved even at high frequencies where the output capacity of the FET cannot be ignored, and the output impedance for the fundamental frequency of the FET is close to the load impedance. The object is to provide a class F amplifier circuit.

  In order to achieve the above object, a class F amplifier circuit according to claim 1 of the present invention comprises an amplifying element that outputs an output signal including a component of an angular frequency ωo of an input signal and a harmonic component thereof, A first reactance circuit connecting an output terminal and a ground terminal; a fundamental wave matching circuit disposed on the output terminal side of the amplifying element; and an input terminal of the fundamental wave matching circuit and the output terminal of the amplifying element. And a load for connecting the output terminal of the fundamental matching circuit and the ground terminal, and the output impedance of the amplifying element is an impedance of a parallel circuit composed of an output resistor and an output capacitor. The first reactance circuit is open to the direct current component, and has an angular frequency of bωo, 2ωo, 4ωo,..., 2nωo (where 0 <b <1 and n is a natural number of 1 or more). Short-circuit, angular frequency ωo, 3ωo, 5ωo,..., (2n + 1) ωo components resonate in parallel with the output capacitance of the amplifying element, and the second reactance circuit is short-circuited and angular frequency with respect to DC components. 3ωo, 5ωo,..., (2n + 1) ωo components, and the first reactance circuit and the second reactance circuit are configured by a lumped constant circuit including an inductor and a capacitor.

  According to the class F amplifier circuit of the present invention, the DC bias can be supplied from the RF output terminal, the size can be reduced, and the class F operation can be performed even at a high frequency where the output capacity of the FET cannot be ignored. High efficiency can be achieved by approaching to.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

[First embodiment]
FIG. 1 is a schematic circuit diagram of a class F amplifier according to the first embodiment of the present invention, and FIG. 2 is a schematic equivalent circuit of the class F amplifier according to the first embodiment of the present invention. A connection block diagram is shown.

As shown in FIGS. 1 and 2, the class F amplifier according to the first embodiment of the present invention includes an amplifying element (FET) that outputs an output signal including the component of the angular frequency ωo of the input signal and its harmonic component. ) 10, a first reactance two-terminal circuit 12 for connecting the output terminal N _{OF of the} FET 10 and the ground terminal, a fundamental wave matching circuit 16 connected to the high frequency output terminal N _ORF , and the output terminal N _{OF of the} FET 10 and the high frequency A second reactance two-terminal circuit 14 connected in series between the output terminals N _ORF and connecting the output terminal N _{OF of the} FET 10 and the input terminal of the fundamental matching circuit 16, the output terminal of the fundamental matching circuit 16, and the ground terminal And a load 22 for connecting the two.

The output impedance of the FET 10 is the impedance of the parallel circuit composed of the output resistor R _O and the output capacitor C _O , and the first reactance two-terminal circuit 12 is open to the DC component, the angular frequencies bωo, 2ωo, 4ωo,. Short circuit for 2nωo (where 0 <b <1 and n is a natural number of 1 or more), angular frequency ωo, 3ωo, 5ωo,..., (2n + 1) output capacitance C _O of FET10 for ωo components The second reactance two-terminal circuit 14 is short-circuited with respect to the direct current component and opened with respect to the angular frequencies 3ωo, 5ωo,..., (2n + 1) ωo components.

The drain of the FET 10 is used as the output terminal of the FET 10, the drain and the ground terminal are connected by the first reactance two-terminal circuit 12, and the drain and the input terminal of the fundamental wave matching circuit 16 are connected by the second reactance two-terminal circuit 14. Then, the output terminal of the fundamental matching circuit 16 and RF output terminal N _ORF, inserting a choke coil 18 and the DC cut capacitor 20 of the bias circuit between the RF output terminal N _ORF and the load 22. Note that at least a part of the fundamental matching circuit 16 may be transferred to a load.

となる。ただし、０＜ｂ＜１で、ｎは１以上の自然数である。なお、ｂが１に近づくと必要なキャパシタンスは小さくなるが、必要なインダクタンスは大きくなり、特に基本波の角周波数ωoに対する整合化の帯域幅が狭くなる。 In FIG. 2, where the output impedance of the FET 10 is the impedance of the parallel circuit composed of the output resistor R _O and the output capacitor C _O , the admittance of the circuit in which the first reactance two-terminal circuit 12 and the output capacitor C _O are connected in parallel is represented by Yp (s ), Yp (s) is open at DC, angular frequency bωo, 2ωo, 4ωo,..., 2nωo, shorted, angular frequency ωo, 3ωo, 5ωo,..., (2n + 1) ωo. ,

It becomes. However, 0 <b <1 and n is a natural number of 1 or more. When b approaches 1, the required capacitance decreases, but the required inductance increases, and in particular, the matching bandwidth with respect to the angular frequency ωo of the fundamental wave becomes narrower.

において、

とする。なお、右辺第二項のYp１(s)は第１のリアクタンス二端子回路１２のアドミッタンスである。この第１のリアクタンス二端子回路１２は奇数高調波でＦＥＴ１０の出力容量Ｃ_Oと並列共振するので、ＦＥＴ１０の出力抵抗Ｒ_Oから負荷２２側を見込んだインピーダンスを奇数高調波で開放にできる。従って、ＦＥＴ１０の出力容量Ｃ_Oが無視できない高周波でもＦ級動作にできる。さらに、この第１のリアクタンス二端子回路１２は基本波の角周波数ωoにおいても出力容量Ｃ_Oと並列共振するので、基本波の角周波数ωoに対する整合回路も兼ねている。 Since the output resistance R _O of the high-power FET 10 has a lower impedance than the load, the matching bandwidth with respect to the angular frequency ω o of the fundamental wave becomes narrow when the output capacitance C _O is large. Therefore, Yp (s) was partially expanded so as not to narrow the bandwidth further.

In

And Yp1 (s) in the second term on the right side is the admittance of the first reactance two-terminal circuit 12. Since the first reactance two-terminal circuit 12 resonates in parallel with the output capacitance C _{O of} the FET 10 with odd harmonics, the impedance expected from the output resistance R _{O of the} FET 10 on the load 22 side can be opened with odd harmonics. Accordingly, the F class operation can be performed even at a high frequency where the output capacitance C _{O of the} FET 10 cannot be ignored. Further, since the first reactance two-terminal circuit 12 resonates in parallel with the output capacitance C _O even at the fundamental frequency ωo, it also serves as a matching circuit for the fundamental frequency ωo.

となる。 On the other hand, when the impedance of the second reactance two-terminal circuit 14 is Zs (s), it is short-circuited at DC and open at angular frequencies 3ωo, 5ωo,..., (2n + 1) ωo. From Foster's reactance theorem, Zs (s) is short-circuited between 3ωo and 5ωo, between 5ωo and 7ωo, ..., (2n-1) ωo and (2n + 1) ωo. The frequency of the short circuit can be set arbitrarily, but the high frequency and low frequency symmetry of the open angular frequencies 3ωo, 5ωo,..., (2n + 1) ωo are good. When DC is short-circuited only when n is 2, DC is short-circuited at an angular frequency of 4ωo, and when n is DC, the angular frequency is 4ωo, 6ωo,.

It becomes.

The Hs can be set independently of the C _O, 3ωo Larger Hs, 5ωo, ···, is bandwidth of open at (2n + 1) ωo becomes wider.

Since the output resistance R _O of the high output FET 10 has a lower impedance than the load, it is necessary to boost the impedance by the fundamental matching circuit 16. A DC bias can be supplied from the RF output terminal N _ORF by using a system in which L is connected in series to the drain of the FET 10 as the fundamental wave matching circuit 16.

  Since the impedance Zs (ωo) of the second reactance two-terminal circuit 14 becomes inductive at the angular frequency ωo of the fundamental wave, the second reactance two-terminal circuit 14 works as a part of the fundamental wave matching circuit 16. Note that this circuit can be made smaller than a circuit that is short-circuited at DC or ωo.

  FIG. 3 is a circuit configuration diagram of a first reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. The admittance Yp1 (s) of the first reactance two-terminal circuit 12 is shown in FIG. FIG.

表１ 第１のリアクタンス二端子回路のYp1(s)の部分分数展開 Table 1 shows the inductance and capacitance when n = 1, 2 which is practical at high frequencies. The case of n = 2 in which 2ωo and 4ωo are short-circuited and 3ωo and 5ωo are open can be made more efficient than the case of n = 1 in which 2ωo is short-circuited and 3ωo is open, but for example at b = 0.3 When n = 2, the total inductance Σ (Lpip) is about 0.9 times that of n = 1, and the total capacitance Σ (Cpip) is about 1.6 times, so the size of the capacitor is dominant, for example. In some cases, the harmonic processing circuit becomes large.

Table 1 Partial fraction expansion of Yp1 (s) of the first reactance two-terminal circuit

  FIG. 4 is another circuit configuration diagram of the first reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. The impedance Zp1 ( s) = 1 / Yp1 (s) is a connection diagram when partial fraction expansion is performed.

  Table 2 shows inductances and capacitances when n = 1 and 2, which are practical at high frequencies.

here

K ₁ = 1 / {(6-b ² ) ωo ² Co}
K ₂ = (9-4b ² ) / (6-b ² )
K ₃ = (4-b ² ) (16-b ² ) / {(960-364b ² + 35b ⁴ -b ⁶ ) ωo ² Co}
K ₄ = {K ₆ + (K ₆ ² -4K ₇ ) ^0.5 } / 2
K ₅ = {K _6- (K ₆ ² -4K ₇ ) ^0.5 } / 2
K ₆ = 5 × (2496-1036b ² + 119b ⁴ -4b ⁶ ) / (960-364b ² + 35b ⁴ -b ⁶ )
K ₇ = (14400-8596b ² + 1505b ⁴ -64b ⁶ ) / (960-364b ² + 35b ⁴ -b ⁶ )

It is.

表２ 第１のリアクタンス二端子回路のZp1(s)の部分分数展開 For example, when b = 2 and n = 2, the total inductance Σ (Lpis) is about 0.6 times that of n = 1, and the total capacitance Σ (Cpis) is about 1.8 times. When the size of the inductor is dominant, the higher harmonic efficiency n = 2 can make the harmonic processing circuit smaller.

Table 2 Partial fraction expansion of Zp1 (s) of the first reactance two-terminal circuit

  FIG. 5 is still another circuit configuration diagram of the first reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. The impedance Zp1 ( s) = 1 / Yp1 (s) is a connection diagram when a continuous fraction is expanded.

  Table 3 shows inductances and capacitances in the case of n = 1, 2 which is practical at high frequencies.

Where K _{1 to} K ₇ are the same as in Table 2,

K ₈ = b ² + 20-K ₄ -K ₅
K ₉ = 64 + 20b ² -K ₄ K ₅
K ₁₀ = K ₄ + K ₅ -K ₉ / K ₈
K ₁₁ = K ₄ K ₅ -64b ² / K ₈

It is.

表３ 第１のリアクタンス二端子回路のZp1(s)の連分数展開 For example, when b = 2 and n = 2, the total inductance Σ (Lpil) is about 0.6 times that of n = 1 and the total capacitance Σ (Cpil) is about 1.6 times. When the size of the inductor is dominant, the higher harmonic efficiency n = 2 can make the harmonic processing circuit smaller.

Table 3 Zp1 (s) continued fraction expansion of the first reactance two-terminal circuit

表４ 第１のリアクタンス二端子回路の比較＜b=0.3の時＞ Σ (Lpij) and Σ (Cpij) of n = 1 and n = 2 of the first reactance two-terminal circuit are summarized in Table 4 (i = 1, 2, j = p, s, l). Inductance Σ (Lpij) has a small partial fraction expansion of Zp1 (s) in Table 2. On the other hand, the capacitance Σ (Cpij) has a small partial fraction expansion of Yp1 (s) in Table 1 and a continuous fraction expansion of Zp1 (s) in Table 3.

Table 4 Comparison of the first reactance two-terminal circuit <when b = 0.3>

  FIG. 6 is a circuit configuration diagram of a second reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention, where the admittance Ys (s) = FIG. 6 is a connection diagram when 1 / Zs (s) is partially fractionally expanded.

表５ 第２のリアクタンス二端子回路のYs(s)の部分分数展開 Table 5 shows inductances and capacitances in the case of n = 1, 2 which is practical at high frequencies. The case of n = 2 in which 2ωo and 4ωo are short-circuited and 3ωo and 5ωo are open can be made more efficient than the case of n = 1 in which 2ωo is short-circuited and 3ωo is open. On the other hand, when n = 2, the total Σ (Lsip) of inductance is about three times that of n = 1 and the total Σ (Csip) of capacitance is about 1.3 times, so that the harmonic processing circuit becomes large.

Table 5 Partial fraction expansion of Ys (s) of the second reactance two-terminal circuit

  FIG. 7 is another circuit configuration diagram of the second reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention, and shows the impedance Zs (s) of the second reactance two-terminal circuit. ) Is a connection diagram in the case of partial fraction expansion.

表６ 第２のリアクタンス二端子回路のZs(s)の部分分数展開 Table 6 shows inductances and capacitances when n = 1, 2 which is practical at high frequencies. The case of n = 1 is the same as Table 5. In the case of n = 2, the total inductance Σ (Lsis) is about 0.6 times and the total capacitance Σ (Csis) is about 4 times that in the case of n = 1. In the dominant case, the harmonic processing circuit can be made smaller in the case of high efficiency n = 2.

Table 6 Partial fraction expansion of Zs (s) of the second reactance two-terminal circuit

  FIG. 8 is still another circuit configuration diagram of the second reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention, in which the admittance Ys of the second reactance two-terminal circuit 14 is shown. FIG. 6 is a connection diagram when (s) = 1 / Zs (s) is developed as a continued fraction.

表７ 第２のリアクタンス二端子回路のYs(s)の連分数展開 Table 7 shows inductances and capacitances when n = 1, 2 which is practical at high frequencies. When n = 1, it is the same as Tables 5 and 6. In the case of n = 2, the total inductance Σ (Lsil) is about 0.6 times and the total capacitance Σ (Csil) is about 6 times that in the case of n = 1. In such a case, the harmonic processing circuit can be made smaller in the case of high efficiency n = 2.

Table 7 Ys (s) continued fraction expansion of the second reactance two-terminal circuit

表８ 第２のリアクタンス二端子回路の比較（n=2） Σ (Lsij) and Σ (Csij) of n = 2 of the second reactance two-terminal circuit are summarized in Table 8 (i = 1, 2, j = p, s, l). The inductance Σ (Lsij) has a small partial fraction expansion of Zs (s) in Table 6 and a continuous fraction expansion of Ys (s) in Table 7. On the other hand, the capacitance Σ (Csij) has a small partial fraction expansion of Ys (s) in Table 5.

Table 8 Comparison of the second reactance two-terminal circuit (n = 2)

  FIG. 9 shows a schematic circuit pattern configuration example of a high-power internal matching FET on which the class F amplifier according to the first embodiment of the present invention is mounted.

As shown in FIG. 9, the input unit includes a microstrip line 38 connected to an RF input terminal _NIRF and supplied with a gate voltage Vgg, and an input-side external circuit 40 arranged in the periphery, and includes a microstrip line. 38 is connected to the FET portion via an envelope lead 48.

As shown in FIG. 9, the FET section is surrounded by an envelope 26, an input gate side fundamental wave matching circuit 42 connected to the microstrip line 38, an input gate side fundamental wave matching circuit 42, and a bonding wire. The FET 10 to which the gate electrode is connected via the (BW) 28, the harmonic processing circuit 32 connected to the drain electrode of the FET 10, and the output drain side fundamental wave matching circuit 44 connected to the harmonic processing circuit 32. The output drain side fundamental wave matching circuit 44 is connected to the RF output terminal N _ORF .

As shown in FIG. 9, the output unit is supplied with a DC bias Vdd with respect to the microstrip line connected to the RF output terminal _{NORF. From the} microstrip line supplied with the DC bias Vdd, a DC cut capacitor is provided. The RF output voltage V _ORF is output via 20. A pass capacitor 34 is connected to the microstrip line supplied with the DC bias Vdd.

  In the example of the high output internal matching FET of FIG. 9, the harmonic processing circuit 32 is integrated on the chip of the FET 10, but if the parasitic reactance does not become a problem, the harmonic processing circuit 32 is configured on a separate substrate. May be. Moreover, you may comprise combining the separate components of an inductor and a capacitor.

  However, when the output is high at high frequency, the harmonic processing circuit 32 cannot be made sufficiently smaller than the wavelength in terms of the withstand voltage of the capacitor and the current capacity of the inductor, and the parasitic capacitance of the inductor and the parasitic inductance of the capacitor cannot be ignored. At least a portion of the harmonic processing circuit 32 is integrated with the chip of the FET 10 to form a monolithic microwave integrated circuit (MMIC), or MEMS (Micro Electro Mechanical Systems) having a high Q value of the circuit is used. It is effective to use.

  For example, regarding the first reactance two-terminal circuit 12 in the case of n = 2, if the ground inductance of the via hole of the MMIC cannot be ignored, the ground inductance of the via hole is included in Lp1s and Lp1l in the circuit configurations shown in FIGS. In the circuit configuration shown in FIG. 3, three via holes are necessary because the ground inductance of the via hole must be included in separate Lp1p, Lp2p, and Lp3p.

On the other hand, when the microchip capacitor is mounted on the ground plane, there is no problem of ground inductance. 4 and 5, the wiring pattern connected to the drain can be one of Lp1s and Lp1l. However, in the circuit configuration of FIG. 3, there is no need to use Cpip (i = 1, 2, 3). However, since two Lp1p, Lp2p, and Lp3p are required, the layout becomes more difficult.
Thus, in the case of n = 2, the first reactance two-terminal circuit 12 has three types (FIGS. 3 to 5) and the second reactance two-terminal circuit 14 has three types (FIGS. 6 to 8) in total 9 Since combinations of types are possible, an optimal circuit may be selected in consideration of the type, size, parasitic reactance, layout, etc. of the inductor and capacitor.

  The FET applied to the class F amplifier circuit according to the first embodiment of the present invention may be a junction FET, a Schottky gate FET, or a MIS (Metal Insulator Semiconductor) type.

  Needless to say, the amplifying element is not limited to the FET, but can be applied to other amplifying elements such as HEMT, LDMOS (Lateral Doped Metal-Oxide-Semiconductor Field Effect Transistor), and HBT.

  Furthermore, the material constituting the FET is not limited to silicon, but may be GaN, InP, SiGe, SiC, GaAs, or diamond. Moreover, as HBT, GaAlN / GaN system etc. are applicable, for example.

  According to the class F amplifier circuit according to the first embodiment of the present invention, a DC bias can be supplied from the RF output terminal, the size can be reduced, and the class F operation is possible even at a high frequency where the output capacity of the FET cannot be ignored. The output impedance with respect to the fundamental frequency of the FET can be made close to the load impedance, and high efficiency can be achieved.

[Second Embodiment]
FIG. 10 is a schematic circuit diagram of a class F amplifier according to the second embodiment of the present invention.

  As shown in FIG. 10, in the case of a push-pull amplifier in which two FETs 10a and 10b are operated in opposite phases and power is synthesized by the balun 50, at least a part of the fundamental matching circuit is like the fundamental matching circuits 17a and 17b. In addition, the ground terminal may be floated from the ground and connected between the two FETs 10a and 10b.

As shown in FIG. 10, the class F amplifier according to the second embodiment of the present invention includes an in-phase side FET 10a that outputs an output signal including the component of the angular frequency ωo of the input signal and its harmonic component, and the FET 10a. The first reactance two-terminal circuit 12a on the in-phase side connecting the output terminal N _{OF +} and the ground terminal, the fundamental matching circuit 17a on the in-phase side connected to the RF output terminal N _{ORF +} , and the output terminal N _{OF + of the} FET 10a A second reactance two-terminal circuit 14a and a fundamental wave matching circuit 16a on the in-phase side that are connected in series between the RF output terminal N _{ORF +} and connect the FET 10a output terminal NOF ₊ and the input terminal of the fundamental wave matching circuit 17a are provided.

Furthermore, as shown in FIG. 10, the class F amplifier according to the second embodiment of the present invention has an anti-phase side FET 10b that outputs an output signal including the component of the angular frequency ωo of the input signal and its harmonic component. A negative-phase-side first reactance two-terminal circuit 12b connecting the output terminal N _{OF− of the FET 10b} and the ground terminal, a negative-phase-side fundamental wave matching circuit 17b connected to the RF output terminal N _ORF− , A second reactance two-terminal circuit on the opposite phase side that is connected in series between the output terminal N _OF− and the RF output terminal N _{ORF− of the} FET _10a and connects the output terminal N _{OF− of the FET 10b} and the input terminal of the fundamental matching circuit 17b. 14b and a fundamental wave matching circuit 16b.

The output terminals of the fundamental wave matching circuits 17a and 17b are respectively connected to the RF output terminal N _{ORF +} and the RF output terminal N _ORF− . The RF output terminal N _{ORF +} and the RF output terminal N _ORF− are connected to the balun 50 through DC cut capacitors 20a and 20b, respectively, and push-pull from the load 22 between the output terminal of the balun 50 and the ground terminal. The output signal of the amplifier is obtained.

The output impedance of the FET 10a is taken as the impedance of a parallel circuit composed of the output resistor R _O and the output capacitor C _O , and the first reactance two-terminal circuit 12a is open to the DC component, angular frequency bωo, 2ωo, 4ωo,. 2nωo (where 0 <b <1, n is a natural number greater than or equal to 1), short circuit, angular frequency ωo, 3ωo, 5ωo,..., (2n + 1) output capacitance C of the FET 10a with respect to the ωo component Resonating in parallel with _O , the second reactance two-terminal circuit 14a is short-circuited with respect to the DC component, and open with respect to the angular frequencies of 3ωo, 5ωo,..., (2n + 1) ωo components.

Similarly, the output impedance of the FET 10b is set as the impedance of the parallel circuit composed of the output resistor R _O and the output capacitor C _O , and the first reactance two-terminal circuit 12b is open to the DC component, and the angular frequencies bωo, 2ωo, 4ωo, ... 2nωo (where 0 <b <1, n is a natural number greater than or equal to 1), short circuit, angular frequency ωo, 3ωo, 5ωo, ..., (2n + 1) Resonating in parallel with the output capacitance C _O , the second reactance two-terminal circuit 14b is short-circuited with respect to the DC component, and is open with respect to the angular frequencies 3ωo, 5ωo,..., (2n + 1) ωo components. To do.

The drain of the FET 10a is the output terminal N _{OF +} of the FET 10a, the drain and the ground terminal are connected by the first reactance two-terminal circuit 12a, and the drain and the input terminal of the fundamental matching circuit 16a are connected by the second reactance two-terminal circuit 14a. To do. Then, the output terminal of the fundamental matching circuit 17a is the RF output terminal N _{ORF +,} and the choke coil 18a for the bias circuit and the DC cut capacitor 20a are inserted between the RF output terminal N _{ORF +} and the load 22 via the balun 50. To do. Note that at least a part of the fundamental wave matching circuit 17a may be transferred to a load.

Similarly, the drain of the FET 10b is the output terminal N _OF− of the FET _10b , the drain and the ground terminal are connected by the first reactance two-terminal circuit 12b, and the input terminal of the fundamental wave matching circuit 16b is connected to the drain and the second reactance two-terminal. Connection is made by the circuit 14b. The output terminal of the fundamental wave matching circuit 17b is the RF output terminal N _ORF−, and the choke coil 18b for the bias circuit and the DC cut capacitor 20b are connected between the RF output terminal N _ORF− and the load 22 via the balun 50. Insert. Note that at least a part of the fundamental wave matching circuit 17b may be transferred to a load.

  Also in the class F amplifier according to the second embodiment of the present invention, the first reactance two-terminal circuits 12a and 12b are similar to those of the class F amplifier according to the first embodiment of the present invention in FIGS. The circuit configuration shown in FIG. 5 can be applied. In that case, it is also clear that the circuit components shown in Tables 1 to 3 are included as in the class F amplifier according to the first embodiment of the present invention.

  In the class F amplifier according to the second embodiment of the present invention, the second reactance two-terminal circuits 14a and 14b are similar to those of the class F amplifier according to the first embodiment of the present invention. The circuit configuration shown in FIG. 8 can be applied. In that case, it is also clear that the circuit components shown in Tables 5 to 7 are included as in the class F amplifier according to the first embodiment of the present invention.

  The FET applied to the class F amplifier circuit according to the second embodiment of the present invention may be a junction type FET, a Schottky gate type FET, or a MIS type.

  Needless to say, the amplifying element is not limited to the FET, but can be applied to other amplifying elements such as HEMT, LDMOS, and HBT.

  Furthermore, the material constituting the FET is not limited to silicon, but may be GaN, InP, SiGe, SiC, GaAs, or diamond. Moreover, as HBT, GaAlN / GaN system etc. are applicable, for example.

  According to the class F amplifier circuit according to the second embodiment of the present invention, in a push-pull amplifier that operates two FETs 10a and 10b in opposite phases and combines power with a balun 50, a DC bias is applied from an RF output terminal. It can be supplied, miniaturized, and can operate in class F even at a high frequency where the output capacity of the FET cannot be ignored, thereby achieving high efficiency.

[Other embodiments]
As described above, the present invention has been described according to the first to second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.

As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  The class F amplifier circuit according to the first to second embodiments of the present invention can supply a DC bias from the RF output terminal, can be miniaturized, and can perform class F operation even at a high frequency where the output capacity of the FET cannot be ignored. Therefore, there is a wide range of application fields such as an internal matching power amplifying element, a power MMIC (Monolithic Microwave Integrated Circuit), a microwave power amplifier, and a millimeter wave power amplifier.

1 is a schematic circuit configuration diagram of a class F amplifier according to a first embodiment of the present invention. FIG. The typical equivalent circuit connection block diagram of the class F amplifier which concerns on the 1st Embodiment of this invention. The circuit block diagram of the 1st reactance two terminal circuit applied to the class F amplifier which concerns on the 1st Embodiment of this invention. FIG. 5 is another circuit configuration diagram of the first reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. FIG. 5 is still another circuit configuration diagram of the first reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. The circuit block diagram of the 2nd reactance two terminal circuit applied to the class F amplifier concerning the 1st Embodiment of this invention. FIG. 5 is another circuit configuration diagram of a second reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. FIG. 6 is still another circuit configuration diagram of a second reactance two-terminal circuit applied to the class F amplifier according to the first embodiment of the present invention. 1 is a schematic circuit pattern configuration example of a high-power internal matching FET on which a class F amplifier according to a first embodiment of the present invention is mounted. The typical circuit block diagram of the class F amplifier which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

10, 10a, 10b ... Field Effect Transistor (FET)
12, 12a, 12b ... first reactance two-terminal circuit 14, 14a, 14b ... second reactance two-terminal circuit 16 ... fundamental wave matching circuits 16a, 16b ... fundamental wave matching circuit 1
17a, 17b ... fundamental wave matching circuit 2
18, 18a, 18b ... choke coils 20, 20a, 20b ... DC cut capacitor 22 ... load 26 ... envelope 28 ... bonding wire (BW)
32 ... Harmonic processing circuit 34 ... Pass capacitor 38 ... Microstrip line 40 ... Input side external circuit 42 ... Input gate side fundamental wave matching circuit 44 ... Output drain side fundamental wave matching circuit 46 ... Output side external circuit 48 ... Envelope lead 50 ... Balun

Claims (16)

An amplifying element that outputs an output signal including the component of the angular frequency ωo of the input signal and its harmonic component;
A first reactance circuit connecting an output terminal of the amplifying element and a ground terminal;
A fundamental wave matching circuit disposed on the output terminal side of the amplification element;
A second reactance circuit connected between the input terminal of the fundamental matching circuit and the output terminal of the amplifying element;
A load connecting the output terminal of the fundamental matching circuit and the ground terminal;
The output impedance of the amplifying element is the impedance of a parallel circuit composed of an output resistor and an output capacitor
The first reactance circuit is open to the direct current component, short-circuited to the angular frequency bωo, 2ωo, 4ωo,..., 2nωo (where 0 <b <1, n is a natural number of 1 or more), Resonant in parallel with the output capacitance of the amplifying element with respect to the angular frequency ωo, 3ωo, 5ωo,.
The second reactance circuit is a short circuit with respect to a direct current component and is open with respect to an angular frequency of 3ωo, 5ωo,..., (2n + 1) ωo components. The class F amplifier circuit according to claim 1,
The class F amplifier circuit, wherein the first reactance circuit is a circuit in which (n + 1) series resonant circuits are connected in parallel. The class F amplifier circuit according to claim 1,
The class F amplifier circuit, wherein the first reactance circuit is a circuit in which n parallel resonant circuits, one inductor, and one capacitor are connected in series. The class F amplifier circuit according to claim 1,
The class F amplifier circuit, wherein the first reactance circuit is an (n + 1) -stage ladder-type circuit having a series inductor and a parallel capacitor as one stage. The class F amplifier circuit according to claim 1,
The class F amplifying circuit, wherein the second reactance circuit is a circuit in which (n-1) series resonant circuits, one inductor, and one capacitor are connected in parallel. The class F amplifier circuit according to claim 1,
The class F amplifier circuit, wherein the second reactance circuit is a circuit in which n parallel resonant circuits are connected in series. The class F amplifier circuit according to claim 1,
The class F amplifying circuit, wherein the second reactance circuit is an n-stage ladder circuit having a parallel capacitor and a series inductor as one stage. The class F amplifier circuit according to claim 1,
The second reactance circuit is short-circuited to a DC component when n is 1, short-circuited to a DC component and an angular frequency 4ωo component when n is 2, and a DC component, an angular frequency 4ωo when n is n, A class F amplifier circuit that is short-circuited with respect to 6ωo,..., 2nωo components. The class F amplifier circuit according to claim 1,
A class F amplifier circuit, wherein at least a part of the fundamental wave matching circuit is moved to the load. The class F amplifier circuit according to any one of claims 1 to 9,
The class F amplifier circuit, wherein the amplifying element is a junction gate type field effect transistor. The class F amplifier circuit according to any one of claims 1 to 9,
The class F amplifier circuit, wherein the amplifying element is a Schottky gate type field effect transistor. The class F amplifier circuit according to any one of claims 1 to 9,
The class F amplifier circuit, wherein the amplifying element is an insulated gate field effect transistor. The class F amplifier circuit according to any one of claims 1 to 9,
The class F amplifier circuit, wherein the amplifying element is a high electron mobility field effect transistor. The class F amplifier circuit according to any one of claims 1 to 9,
The class F amplifier circuit, wherein the amplifying element is a heterojunction bipolar transistor.   15. A class F amplifier circuit comprising two class F amplifier circuits according to claim 1 that perform push-pull operations in mutually opposite phases and combine power by a balun. The class F amplifier circuit according to claim 15,
A class F amplifier circuit characterized in that at least some of the ground terminals of the fundamental wave matching circuit are floated from ground and connected to each other.

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