JP2008257596A - Data pre-fetch device, data pre-fetch method, and data pre-fetch program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve the high speed operation of data transfer between an I/O and a memory without adding a change to the software or host bridge of a computer system without causing a system bus error. <P>SOLUTION: A page size investigation part 183 autonomously reads a page size registered in a configuration register 171-3 held by an I/O 17-3 by simulating a host. When receiving a read request to a memory 12 of the I/O 17-3, a data pre-fetch part 185 performs pre-fetch to the page boundary of a page where requested data exists to the maximum, and performs pre-fetch to the data pertinent to the next page after receiving a read request to the next page from the I/O. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data prefetch device, a data prefetch method, and a data prefetch program, and more particularly to a data prefetch device, a data prefetch method, and a data prefetch program that autonomously determine page boundaries and control prefetch.

  Conventionally, this type of data prefetch device is used in a computer system to realize high-speed data transfer between an I / O and a memory. An example of a computer system using a conventional data prefetch device is described in Patent Document 1.

  Referring to FIG. 7, the form of the computer system described in Patent Document 1 includes a CPU 11, a memory 12, a host bridge 15 that connects each bus, and a CPU bus that connects the CPU 11 and the host bridge 15. 13, a memory bus 14 that connects the memory 12 and the host bridge 15, I / O devices (hereinafter referred to as I / O) 17-1 to 17-3, I / O 17-1 to 17-3 and the host I / O buses 16-1 to 16-3 connecting the bridge 15 are included.

  In the computer system shown in FIG. 7, the host bridge 15 executes the function of the data prefetch device and prefetches the read request for the memory 12 issued by the I / Os 17-1 to 17-3, so that the I / O17- Realizes high-speed data transfer between 1-17-3 and memory 12.

  Assume that the host has set the direct memory access (DMA) operation of I / O 17-1. The I / O 17-1 transmits a request for reading an address designated by the host to the memory 12. The host bridge 15 transfers the read request received from the I / O 17-1 to the memory 12, and at the same time, performs prefetch for an address that is +1 to the read request address value. Subsequently, when the I / O 17-1 issues the next read request with consecutive addresses, the host bridge 15 sends the prefetched data to the I / O 17-1, and further sets the next +1 address. On the other hand, prefetch is performed. In this way, high-speed data transfer between the I / Os 17-1 to 17-3 and the memory 12 is realized.

  Here, in a form in which individual components such as blade servers are mounted on separate boards and cards, the physical distance between the host bridge 15 and the I / O 17-3 may be separated as shown in FIG. In this case, data prefetch that further prefetches a read request to the memory 12 of the I / O 17-3 between the I / O bus 16-3 and the I / O bus 16-4 and in the vicinity of the I / O 17-3. Use of the device 81 is effective. In addition, for I / O 17-3 that reads a large amount of data from consecutive addresses in the memory 12 in a single DMA operation, the data prefetch device 81 applies to the address added to the value of the read request address. In addition to the above, it is desirable to prefetch the addresses after that.

  However, since the data prefetch device 81 is transparent from the host, the software used as standard in the computer system cannot know the page size used in the memory 12. Therefore, when prefetching of data exceeding the page boundary is performed on the memory 12, a system bus error may occur.

In the computer system, data is incorporated in the memory 12 in units of pages, and the incorporation is dynamic, and pages corresponding to all addresses are not incorporated in the memory 12 at a certain point in time. Because.
JP 2001-84216 A (Fig. 1)

  The first problem is that a system bus error occurs when prefetching a read to the I / O memory in the middle of the I / O bus.

  The reason is that the conventional data prefetch device cannot know the page size used in the memory, and performs prefetch exceeding the page boundary.

  The second problem is that when the page size is notified to the data prefetch device, the software or the host bridge needs to be changed.

  The reason is that a conventional computer system does not assume a data prefetch device, and therefore it is necessary to design special software or a host bridge when notifying the data prefetch device of the page size.

  A first object of the present invention is to provide a data prefetch device that determines a page boundary of a memory and controls data prefetch so as not to cause a system bus error.

  It is a second object of the present invention to provide a data prefetch device that determines a page boundary of a memory without changing the software of a computer system or a host bridge.

The data prefetch device of the present invention is a data prefetch device that prefetches data from memory before the data is needed.
Data prefetching is performed so as not to cross the page boundary of the memory, and prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page.

The data prefetch device of the present invention is a data prefetch device that prefetches data from memory before the data is needed.
Simulate the host to obtain the page size used in the memory from the configuration register of the I / O device, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, The prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page.

The data prefetch method of the present invention is a data prefetch method for prefetching data from a memory before the data is needed.
Data prefetching is performed so as not to cross the page boundary of the memory, and prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page.

The data prefetch method of the present invention is a data prefetch method for prefetching data from memory before the data is needed.
Simulate the host to obtain the page size used in the memory from the configuration register of the I / O device, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, The prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page.

The data prefetch program of the present invention is a data prefetch program for causing a computer to execute data prefetch for prefetching data from memory before the data is required.
Data prefetch is performed so as not to cross the page boundary of the memory, and the prefetch of data corresponding to the next page causes the computer to execute processing that starts after receiving a read request for data corresponding to the next page Data prefetch program.

The data prefetch program of the present invention is a data prefetch program for causing a computer to execute data prefetch for prefetching data from memory before the data is required.
Simulate the host to obtain the page size used in the memory from the configuration register of the I / O device, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, The prefetching of data corresponding to the next page is a data prefetching program that causes the computer to execute a process that starts after receiving a read request for data corresponding to the next page.

  The first effect of the present invention is that data prefetch can be performed without causing a system bus error.

  The reason for this is that the page size used in the memory is retained and the read request prefetch for the memory is not crossed over the page size boundary, and the prefetch of data corresponding to the next page is a read request for that page. This is because it starts after receiving.

  The second effect of the present invention is that the computer system according to the present invention can acquire the page size used in the memory without changing the software of the computer system or the host bridge.

  The reason is that the data prefetch device autonomously reads and obtains the page size used in the memory registered in the configuration register of the I / O device by simulating the host.

Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a computer system according to the first embodiment for carrying out the present invention.

  The computer system shown in FIG. 1 includes a CPU 11, a memory 12, a host bridge 15 that connects the respective buses, a CPU bus 13 that connects the CPU 11 and the host bridge 15, and a memory 12 and a host bridge 15. Memory bus 14 to be connected, I / O devices (hereinafter referred to as I / O) 17-1 to 17-3, I / O bus 16 for connecting I / O 17-1, 17-2 and the host bridge 15 -1, 16-2, data prefetch device 18, I / O bus 16-3 connecting host bridge 15 and data prefetch device 18, and I connecting data prefetch device 18 and I / O 17-3. Includes / O bus 16-4.

    Referring to FIG. 1, a data prefetch device 18 is incorporated in a computer system, connected to an I / O bus 16-3 and an I / O bus 16-4, and data read from the memory 12 by the I / O 17-3. Prefetch. At this time, the data prefetch device 18 is transparent to the host.

    The data prefetch device 18 includes a host information investigation unit 181 that examines a host ID from data issued by a host that passes through the I / O bus 16-3, a host information storage unit 182 that holds the host ID, and a memory 12 Page size survey unit 183 that acquires the page size used in I / O 17-3, page size storage unit 184 that stores the page size, and data prefetch unit that prefetches data within a range that does not exceed the page boundary 185 and a data storage unit 186 for storing prefetched data. Each component of the data prefetch device can be configured using a dedicated IC. A plurality of components can be configured by one IC.

    The I / Os 17-1 to 17-3 include configuration registers 171-1 to 171-3 that provide device information to the host and receive device control.

    One of the fields of the configuration registers 171-1 to 171-3 is an area for registering the page size used by the host in the memory 12. This is because when mapping the resources of I / O 17-3, the area to be mapped is aligned with the page size.

    The page size checking unit 183 simulates access from the host by using the host ID described in the host information storage unit 182 after the device has been set by writing to the configuration register 171-3. The field in which the page size of the registration register 171-3 is registered is read and stored in the page size storage unit 182. At this time, if necessary, access from the host to the I / O 17-3 is blocked and stored, and after obtaining the page size, the access is resumed collectively.

    When the data prefetch unit 185 receives a read request to the memory 12 of the I / O 17-3, the data prefetch unit 185 checks whether the address of the read request is a prefetched data area. The data is read from the data storage unit 186 and returned to the I / O 17-3. On the other hand, when the address of the read request is not the corresponding area of the prefetched data, the read request for prefetching the subsequent address is transmitted to the memory 12 at the same time as the read request of the I / O 17-3 is transferred. At this time, the page size described in the page size storage unit 184 is referred to and control is performed so that prefetch does not cross the page boundary. Therefore, the data prefetch unit 185 stops fetching data from the memory 12 at the page boundary, and when the read request for the next page is received from the I / O 17-3, the data prefetch unit 185 again prefetches the data for the address of the next page. To start. When the read request received from the I / O 17-3 requests all data up to the page boundary, the data prefetch unit 185 does not prefetch data. Further, the data prefetch unit 185 simply transfers data not related to the read request to the memory 12 of the I / O 17-3 between the I / O 17-3 and the memory 12.

    Next, the operation of the first embodiment for carrying out the present invention will be described in detail with reference to FIGS.

    First, the operation of the data prefetch device 18 for acquiring the host ID and page size when the host configures the I / O 17-3 will be described with reference to FIGS.

    When configuration of the I / O 17-3 by the host is started (step 201), data relating to the configuration flows through the I / O bus 16-3 and the I / O bus 16-316-4.

  The host information examining unit 181 detects host ID information from the data passing through the data prefetch device 18 (step 202) and registers it in the host information storage unit 182 (step 203). When the configuration of the I / O 17-3 by the host is completed (step 204), the page size examining unit 183 temporarily blocks access from the host to the I / O 17-3 and stores the access (step 205). Subsequently, the page size checking unit 183 simulates the host using the host ID registered in the host information storage unit 182 and reads the page size registered in the configuration register 171-3 (step 206). Registration in the page size storage unit 184 (step 207). Finally, the access blocked at step 205 is resumed (step 208). With the above operation, the data prefetch device 18 acquires the host ID and the page size.

    Next, with reference to FIGS. 1 and 3, the operation when the data prefetch device 18 performs prefetching of data read from the memory 12 by the I / O 17-3 will be described.

    When the data prefetch unit 185 receives a read request for the memory 12 from the I / O 17-3 (step 301), the data prefetch unit 185 checks whether the data at the address for which the read request has been already prefetched (step 302). When prefetching has already been performed, the data requested by the data prefetching unit 185 to the memory 12 may already be stored in the data storage unit 186 or may be waiting for reception (step 303). If the corresponding data is already stored in the data storage unit 186, the data prefetch unit 185 reads the corresponding data and returns it to the I / O 17-3 (step 304). On the other hand, when waiting for reception, the data prefetch unit 185 waits until the memory 12 returns the corresponding data (step 312), and when prefetch data is received (step 313), the address requested from the I / O 17-3. Data corresponding to the range is returned (step 314).

In step 302, if the data at the address requested by the I / O 17-3 has not been prefetched, it is checked whether the read request requires all data up to the page boundary (step 305). If all the data up to the page boundary is requested, the data prefetch unit 185 transfers the I / O 17-3 request to the memory 12 and does not perform data prefetch (step 306). When the data prefetch unit 305 receives a response to the read request of the transferred I / O 17-3 from the memory 12, the data prefetch unit 305 transfers the received data to the I / O 17-3 (step 307).
On the other hand, if the I / O 17-3 does not request data up to the page boundary in step 305, the data prefetch unit 185 transfers the read request of the I / O 17-3 to the memory 12, and then after the address of the read request. A request for prefetching data corresponding to the address up to the boundary of the same page at maximum is transmitted to the memory 12. The data prefetch unit 185 first receives a response to the read request of the transferred I / O 17-3 from the memory 12, and transfers it to the I / O 17-3 (step 310). Subsequently, the prefetched data is received and stored in the data storage unit 186 (step 311).

  Next, effects of the first exemplary embodiment for carrying out the present invention will be described.

  In the first embodiment of the present invention, when the I / O configuration by the host is completed, the data prefetch device simulates the host, acquires the page size from the I / O configuration register, and the I / O The prefetch of data read from memory is limited to the page boundary of the page where the requested data from I / O exists, and the prefetch of the data corresponding to the next page is read from I / O to the next page. After the request is actually received.

  For this reason, the data prefetch device autonomously determines the page boundary without changing the computer system software or host bridge, and efficient data transfer between memory and I / O without causing system bus errors. it can.

In this embodiment, the page size checking unit 183 reads the page size registered in the configuration register 171-3. However, the page size checking unit 183 is configured to configure the I / O 17-3 by the host. It is also possible to acquire the page size included in the data when the data written to the configuration register 171-3 passes through the data prefetch device 18 during the configuration (also in the second embodiment below) The same). At this time, it is possible to confirm from the host ID information stored in the host information storage unit 182 whether the acquired data is issued by the host.
[Second Embodiment]
Next, a second embodiment for carrying out the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 4, a data prefetch device 41 according to the second embodiment of the present invention is incorporated in a computer system, connected to an I / O bus 16-3 and an I / O bus 16-4, and an I / O 17 -3 performs prefetch of data read from the memory 12.

  The data prefetch device 41 includes a CPU 411 that performs data processing, a data storage unit 412 that stores data, and a data prefetch device program 413 that causes the CPU 411 to perform processing of the data prefetch device 41.

  The data prefetch device program 413 is read by the CPU 411, and the data corresponding to the host information storage unit 182, page size storage unit 184, and data storage unit 186 in the first embodiment shown in FIG. The data is stored in the storage unit 4121, the page size storage unit 4122, and the prefetch data storage unit 4123. Under the control of the data prefetch device program 413, the CPU 411 is the same as the host information examining unit 181, the page size examining unit 183, and the data prefetch unit 185 in the first embodiment described with reference to FIGS. Process. The data prefetch device program 413 may be stored in a storage unit such as a ROM provided separately from the CPU 411.

  Next, a first embodiment of the present invention will be described with reference to the drawings. Such an example corresponds to the first embodiment for carrying out the present invention. FIG. 5 is a diagram for explaining a computer system including a data prefetch device according to the first embodiment of the present invention.

  The configuration of FIG. 5 will be described in comparison with FIG. 1. In the data prefetch device 58 of this embodiment, the host information survey unit 581 is used as the host information survey unit 181, the host information storage unit 582 is used as the host information storage unit 182, and the page The size checking unit 183 includes a page size checking unit 583, the page size storing unit 184 includes a page size storing unit 584, the data prefetching unit 185 includes a data prefetching unit 585, and the data storing unit 186 includes a data storing unit 586. The I / O bus 16-1 to I / O bus 16-4 are PCIe buses 56-1 to 56-4 that conform to the PCIe (PCI Express) standard standardized by the PCI-SIG (PCI Special Interest Group). The I / Os 57-1 to 57-3 include PCIe configuration registers 571-1 to 571-3 as the configuration registers 171-1 to 171-3.

  Now, assuming that the computer system is powered on, system configuration is started by the host. The host cannot recognize the data prefetch device 58 and recognizes that the host bridge 55 and the I / O 57-3 are directly connected. In the configuration of the I / O 57-3, the host reads device information registered in the PCIe configuration register 571-3 using a configuration read TLP (Transaction Layer Packet). At this time, these TLPs pass through the data prefetch device 58. Therefore, the host information examining unit 581 acquires a combination of a bus number, a device number, and a function number, which is a host ID, from the passing TLP and writes it to the host information storage unit 582. On the other hand, after acquiring the device information of I / O 571-3 by the configuration read TLP, the host writes the I / O 571-3 to the PCIe configuration register 571-3 using the configuration write TLP based on the information. Complete configuration of O57-3.

  When the configuration by the series of hosts is completed, the page size examining unit 583 temporarily blocks TLP from the host side to the I / O 17-3. Subsequently, a configuration read TLP is created using a combination of the bus number, device number, and function number that is the host ID registered in the host information storage unit 182, and the page size of the configuration register 171-3 is registered. And the acquired information is registered in the page size storage unit 584. Finally, the page size examining unit 583 resumes access from the blocked host and transfers it to the I / O 57-3. With the above operation, the data prefetch device 58 autonomously acquires the page size.

    Next, it is assumed that the data prefetch device 58 receives a memory read TLP requesting to read data from the memory 52 by DMA from the I / O 57-3 during normal operation. The data prefetch unit 585 checks whether the address area of the memory read TLP matches the area where the data prefetch unit 585 has already made a prefetch request. If the area matches the area where the prefetch request has been made and the corresponding data is already stored in the data storage unit 586, the data prefetch unit 585 reads the corresponding data and returns it to the I / O 57-3. On the other hand, when a prefetch request is made but waiting for a reply from the memory 52, the data prefetch unit 585 waits until the corresponding data is received, and after receiving the data, the address corresponding to the memory read TLP of the I / O 57-3 The range data is returned to I / O57-3 as a response TLP.

    In addition, if the address area of the memory read TLP of the I / O 57-3 does not match the area where the data prefetch unit 585 has already made a prefetch request, the data prefetch unit 585 reads all the data up to the page boundary. Find out if you are requesting it. At this time, since the page size is registered in the page size storage unit 584, the determination is made based on the information. For example, in a system with a page size of 4 KB, when the memory read TLP requests all data up to an address that becomes a 4 KB break, the data up to the page boundary is requested. At this time, the data prefetch unit 585 does not perform prefetching, and only the memory read TLP of the I / O 57-3 is transferred to the memory 52, and when the response TLP is received, it is transferred to the I / O 57-3.

  On the other hand, if the memory read TLP of the I / O 57-3 does not request all the data up to the page boundary, the data prefetch unit 585 first transfers the memory read TLP of the I / O 57-3 to the memory 52, and then the memory read. The data corresponding to the address after the TLP request address is prefetched to the page boundary of the page where the data requested by the maximum I / O 57-3 exists. Thereafter, the data prefetch unit 585 first receives a response TLP to the memory read request of the I / O 57-3 from the memory 52, and transfers this to the I / O 57-3. Subsequently, the data corresponding to the response to the data prefetch request is stored in the data storage unit 586, and prepared for the case where the I / O 57-3 requests data by the memory read TLP later.

    Next, a second embodiment of the present invention will be described with reference to the drawings. This example corresponds to the second embodiment for carrying out the present invention.

    Referring to FIG. 6, the data prefetch device 61 of the present embodiment is a CPU 611 as a CPU 411, a data storage unit 612 as a data storage unit 412, a data prefetch device program 613 as a data prefetch device program 413, and a host information storage unit 4121. The host information storage unit 6121 includes a page size storage unit 6122 as the page size storage unit 4122, and a prefetch data storage unit 6123 as the prefetch data storage unit 4123.

    The data prefetch device program 613 is read by the CPU 611, and the host information storage unit 582, the page size storage unit 584, and the data corresponding to the data storage unit 586 in the first embodiment shown in FIG. 6121, a page size storage unit 6122, and a prefetch data storage unit 6123. Under the control of the data prefetch device program 613, the CPU 611 performs the same processing as the host information examining unit 581, page size examining unit 583, and data prefetch unit 585 in the first embodiment.

  In the embodiment described above, the configuration is described in which the page information is read from the I / O registers. However, when the host writes information into these registers, the page size is determined from the related information passing through the data prefetch devices 58 and 61. It is also possible to obtain.

  Further, although the host system is provided in the computer systems of the respective examples and embodiments described above, the CPU, the memory, and the data prefetch device may be directly connected by a bus without providing the host bridge.

  INDUSTRIAL APPLICABILITY According to the present invention, it can be applied to uses such as high-speed data transfer of a bus that interconnects internal components of a computer system or a network system. In addition, the present invention can be applied to applications such as bus and interconnect data transfer speedups that interconnect physically separated components in computer systems and network systems.

It is a block diagram which shows the structure of the 1st Embodiment of this invention. It is a flowchart which shows the operation | movement of the 1st Embodiment of this invention. It is a flowchart which shows the operation | movement of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the 2nd Embodiment of this invention. It is a figure for demonstrating the 1st Example of this invention. It is a figure for demonstrating the 2nd Example of this invention. It is a figure for demonstrating a prior art. It is a figure for demonstrating a prior art.

Explanation of symbols

11 CPU
12 memory
13 CPU bus
14 Memory bus
15 Host bridge
16-1 to 16-4 I / O bus
17-1 to 17-3 I / O
18 Data prefetch devices
41 Data prefetch device
51 CPU
52 memory
53 CPU bus
54 Memory bus
55 Host bridge
56-1 to 56-4 I / O bus
57-1 to 57-3 I / O
58 Data prefetch device
61 Data prefetch device
81 Data prefetch device
171-1 to 171-3 Configuration register
181 Host Information Research Department
182 Host information storage unit
183 Page Size Research Department
184 Page size memory
185 Data prefetch section
186 Data storage
411 CPU
412 Data storage unit
413 Data prefetch device program
4121 Host information storage unit
4122 Page size memory
4123 Prefetch data storage

Claims (30)

In a data prefetch device that prefetches data from memory before it is needed,
Data prefetch is performed so as not to cross a page boundary of the memory, and prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page. device. Page size storage means for holding the page size used in the memory;
By referring to the page size held in the page size storage means, data prefetching is performed so as not to cross the page boundary of the memory, and prefetching of data corresponding to the next page is performed using the data corresponding to the next page. A data prefetch means that starts after receiving a read request;
The data prefetch device according to claim 1, further comprising: In a data prefetch device that prefetches data from memory before it is needed,
Simulate the host to obtain the page size used in the memory from the configuration register of the I / O device, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, A data prefetch device, wherein prefetching of data corresponding to a next page is started after receiving a read request for data corresponding to the next page. In a data prefetch device that prefetches data from memory before it is needed,
From the data that the host writes to the configuration register of the I / O device, obtain the page size used in the memory, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, A data prefetch device, wherein prefetching of data corresponding to a next page is started after receiving a read request for data corresponding to the next page. Host information storage means for holding a host ID;
Page size checking means for acquiring the page size used in the memory from the configuration register of the I / O device using the ID held in the host information storage means;
Data prefetching is performed so as not to exceed the page boundary of the memory defined by the page size, and prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page. Data prefetching means;
The data prefetch device according to claim 3, further comprising: Host information storage means for holding a host ID;
Page size checking means for acquiring the page size used in the memory from the configuration register of the I / O device using the ID held in the host information storage means;
With
The data prefetch device according to claim 2, wherein the acquired page size is held in the page size storage means. A page size investigation means for obtaining a page size used in the memory from data written by the host to the configuration register of the I / O device;
Data prefetching is performed so as not to exceed the page boundary of the memory defined by the page size, and prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page. Data prefetching means;
The data prefetch device according to claim 4, further comprising: A page size checking means for acquiring a page size used in the memory from data written by the host to the configuration register of the I / O device;
The data prefetch device according to claim 2, wherein the acquired page size is held in the page size storage means. 8. The host ID stored in advance is referred to in order to confirm that the data written to the configuration register of the I / O device by the host is data issued by the host. 9. The data prefetch device according to any one of items 8 to 8. 10. The page size used in the memory is obtained from data issued by a host that passes through the data prefetch device. Data prefetch device.   The data prefetch device according to claim 5 or 6, wherein the host ID registered in the host information storage means is obtained from data issued by the host that passes through the data prefetch device.   The data prefetch device according to any one of claims 1 to 11, wherein a standard of a bus connected to the data prefetch device conforms to PCI Express.   A computer system comprising the data prefetch device according to any one of claims 1 to 12, a memory for storing data read by the data prefetch device, and a CPU. In a data prefetch method for prefetching data from memory before the data is needed,
Data prefetch is performed so as not to cross a page boundary of the memory, and prefetching of data corresponding to the next page is started after receiving a read request for data corresponding to the next page. Method. In a data prefetch method for prefetching data from memory before the data is needed,
Simulate the host to obtain the page size used in the memory from the configuration register of the I / O device, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, A data prefetch method, wherein prefetching of data corresponding to a next page is started after receiving a read request for data corresponding to the next page. In a data prefetch method for prefetching data from memory before the data is needed,
From the data that the host writes to the configuration register of the I / O device, obtain the page size used in the memory, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, A data prefetch method, wherein prefetching of data corresponding to a next page is started after receiving a read request for data corresponding to the next page.   16. The data prefetch method according to claim 15, wherein in the host simulation, a read for the configuration register is issued using a host ID.   18. The data prefetch method according to claim 17, wherein the host ID is acquired from data issued by a host that passes through the data prefetch device. The host ID stored in advance is referred to in order to confirm that the data written to the configuration register of the I / O device by the host is data issued by the host. Data prefetch method. The data prefetch method according to claim 16, wherein the page size used in the memory is obtained from data issued by a host that passes through the data prefetch device.   The data prefetch method according to any one of claims 14 to 20, wherein the data prefetch is performed based on a PCI Express standard. A data prefetch program for causing a computer to perform data prefetching to prefetch data from memory before the data is needed,
Data prefetch is performed so as not to cross the page boundary of the memory, and the prefetch of data corresponding to the next page causes the computer to execute processing that starts after receiving a read request for data corresponding to the next page Data prefetch program.     23. The computer according to claim 22, further comprising: causing the computer to execute a first process for holding a page size used in the memory and a second process for referring to the held page size before the process. The data prefetch program described. A data prefetch program for causing a computer to perform data prefetching to prefetch data from memory before the data is needed,
Simulate the host to obtain the page size used in the memory from the configuration register of the I / O device, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, A prefetching of data corresponding to the next page causes the computer to execute a process that starts after receiving a read request for data corresponding to the next page. A data prefetch program for causing a computer to perform data prefetching to prefetch data from memory before the data is needed,
From the data that the host writes to the configuration register of the I / O device, obtain the page size used in the memory, perform data prefetching so as not to cross the page boundary of the memory defined by this page size, A prefetching of data corresponding to the next page causes the computer to execute a process that starts after receiving a read request for data corresponding to the next page. Causing the computer to execute another process that holds the ID of the host before the process;
The data prefetch program according to claim 24, wherein the acquisition of the page size in the processing is performed using the ID.   27. The data prefetch program according to claim 26, wherein the ID is obtained from data issued by a host passing through a computer.   26. The host ID stored in advance is referred to in order to confirm that the data written to the configuration register of the I / O device by the host is data issued by the host. Data prefetch program.   26. The data prefetch program according to claim 25, wherein the page size used in the memory is obtained from data issued by a host that passes through the data prefetch device.     The data prefetch program according to any one of claims 22 to 29, wherein the data prefetch program operates in accordance with a PCI Express standard.

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