JP2008256774A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably generate a write discharge in a plasma display panel which has a larger screen and higher definition. <P>SOLUTION: A plasma display device has the plasma display panel having a display electrode pair including a scan electrode and a sustain electrode, and a driving circuit which drives the plasma display panel by applying a first ramped waveform voltage which gently rises in the initialization period of at least one sub-field of a one-field period to the scan electrode and alternately applying a sustain pulse voltage which performs displacement from a base potential to a potential for generating a sustain discharge in a sustain period to the display electrode pair. The driving circuit has a first Miller integrating circuit 55 which generates the first ramped waveform voltage and a second Miller integrating circuit 56 which generates a second ramped waveform voltage having its gradient steeper than the first ramped waveform voltage and falling immediately when the rising waveform voltage reaches a predetermined specific potential in the ending of the sustain period. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a plasma display device used for a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of red (R), green (G) and blue (B) colors are excited and emitted by the ultraviolet rays, thereby performing color display. It is carried out.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for stably generating the address discharge (priming agent for discharge = excited particles) ). In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse voltage is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has caused the address discharge, and the phosphor layer of the corresponding discharge cell emits light. To display an image.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, in the initialization period of one subfield, an all-cell initializing operation for generating an initializing discharge in all discharge cells is performed, and in an initializing period of the other subfield. Performs a selective initializing operation in which initializing discharge is generated only in the discharge cells that have undergone sustain discharge in the immediately preceding sustain period. By driving in this way, the luminance of the black display area that changes depending on the light emission not related to the image display (hereinafter abbreviated as “black luminance”) is only weak light emission in the all-cell initialization operation, High-contrast image display is possible (see, for example, Patent Document 1).

In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By this narrow erase discharge, the address operation in the address period of the subsequent subfield can be stabilized and a plasma display device with a high contrast ratio can be realized.
JP 2000-242224 A

  In recent years, further miniaturization of discharge cells has been progressed with higher definition of panels. In this miniaturized discharge cell, it has been confirmed that a phenomenon called charge loss, in which wall charges are lost, is likely to occur, and when this charge loss occurs, discharge failure occurs and image display quality deteriorates, Or the problem that the applied voltage required for generation | occurrence | production of discharge raises arises.

  One of the main causes of charge loss is discharge variation during the address operation. For example, if the discharge variation during the address operation is large and the address discharge is generated strongly, the discharge cell that emits light and the non-light-emitting discharge cell are adjacent to each other when the discharge cell that emits light and the non-light-emitting discharge cell are adjacent to each other. May be taken away, resulting in loss of charge.

  Therefore, it is important to generate address discharge as stably as possible in order to prevent charge loss.

  On the other hand, in recent years, the panel has been further increased in screen size and resolution, and accordingly, the driving impedance of the panel tends to increase. When the drive impedance increases, waveform distortion such as ringing is likely to occur in the drive waveform generated from the panel drive circuit. The narrow erase discharge described above is intended to stabilize the address operation of the subsequent subfield. For example, if waveform distortion occurs in the drive waveform for generating the narrow erase discharge, the narrow erase discharge is performed. There is a possibility that the erasing discharge itself may be strongly generated. In such a case, there is a problem that it is difficult to stably generate the subsequent address discharge.

  The present invention has been made in view of the above problems, and provides a plasma display device capable of stably generating an address discharge and having a good image display quality even in a panel with a large screen and high definition. For the purpose.

The plasma display device of the present invention includes an initialization period in which a first ramp waveform voltage that gradually rises is applied to the display electrode of a plasma display panel including display electrodes that form a plurality of discharge cells; An address period in which an address pulse voltage is selectively applied to the display electrode, and a sustain period in which a sustain pulse voltage for generating a sustain discharge is applied to the display electrode of the discharge cell selected in the address period,
At the end of the sustain period, a second ramp waveform voltage that rises with a steeper slope than the first ramp waveform voltage is generated, and when the second ramp waveform voltage reaches a predetermined potential, it is lowered immediately. An operating ramp waveform generating circuit is provided.

  Thereby, even in a panel with a large screen and high definition, address discharge can be stably generated, and the image display quality of the panel can be improved.

  In the plasma display device, the ramp waveform generation circuit includes a switching circuit that stops the operation of the ramp waveform generation circuit as soon as the second ramp waveform voltage reaches a predetermined voltage. As a result, the second ramp waveform voltage can be generated with high accuracy.

  According to the present invention, it is possible to stably generate an address discharge even in a panel having a large screen and a high definition, and it is possible to provide a plasma display device with good image display quality.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to an embodiment of the present invention. On the front plate 21 made of glass, a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustain electrode 23 are formed. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  The protective layer 26 has been used as a panel material in order to lower the discharge start voltage in the discharge cell, and has a large secondary electron emission coefficient and durability when neon (Ne) and xenon (Xe) gas is sealed. It is formed from a material mainly composed of MgO having excellent properties.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. A mixed gas of neon and xenon is sealed as a discharge gas in the internal discharge space. In the present embodiment, a discharge gas having a xenon partial pressure of about 10% is used in order to improve luminous efficiency. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall. Further, the mixing ratio of the discharge gas is not limited to the above-described numerical values, and may be other mixing ratios.

  FIG. 2 is an electrode array diagram of panel 10 according to the embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. As shown in FIGS. 1 and 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is a large interelectrode capacitance Cp.

  Next, a driving voltage waveform for driving the panel 10 and an outline of the operation will be described. The plasma display device according to the present embodiment performs gradation display by subfield method, that is, by dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In each subfield, initializing discharge is generated in the initializing period, and wall charges necessary for subsequent address discharge are formed on each electrode. In addition, it has a function of generating priming particles (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. The initializing operation at this time is an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and an initializing discharge is selectively generated only in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is a selective initialization operation.

  In the address period, an address discharge is selectively generated in the discharge cells to emit light in the subsequent sustain period to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 24 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportionality constant at this time is called “luminance magnification”.

  In this embodiment, one field is composed of 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, 18). , 30, 44, 60, 80). Then, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF. As a result, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation in the first SF, and the black luminance, which is the luminance of the black display area that does not generate the sustain discharge, is weak in the all-cell initialization operation. Only the emission of light makes it possible to display an image with high contrast. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification is applied to each display electrode pair 24.

  However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  In the present embodiment, the ramp waveform voltage is generated at the end of the sustain period, thereby stabilizing the write operation in the subsequent subfield write period. Hereinafter, the outline of the drive voltage waveform will be described first, and then the configuration of the drive circuit will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of panel 10 in one embodiment of the present invention. FIG. 3 shows driving voltage waveforms of two subfields, that is, a subfield that performs an all-cell initializing operation (hereinafter referred to as “all-cell initializing subfield”) and a subfield that performs a selective initializing operation ( Hereinafter, it is referred to as “selective initialization subfield”), but the driving voltage waveforms in the other subfields are substantially the same. Further, scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected from the respective electrodes based on image data.

  First, the first SF, which is an all-cell initialization subfield, will be described.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the discharge start voltage with respect to the sustain electrodes SU1 to SUn is applied to the scan electrodes SC1 to SCn. A first ramp waveform voltage (hereinafter referred to as “up-ramp waveform voltage”) that gradually rises from voltage Vi1 below toward voltage Vi2 that exceeds the discharge start voltage is applied.

  In the present embodiment, this up-ramp waveform voltage is generated with a slope of about 1.3 V / μsec.

  While the rising ramp waveform voltage rises, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and sustain electrodes SU1 to SUn are applied to scan electrodes SC1 to SCn. In contrast, a ramp waveform voltage (hereinafter referred to as a “down-ramp waveform voltage”) that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4 that exceeds the discharge start voltage is applied. During this time, weak initializing discharges are continuously generated between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  Note that, as shown in the initialization period of the second SF in FIG. 3, a drive voltage waveform in which the first half of the initialization period is omitted may be applied to each electrode. That is, a voltage Ve1 is applied to sustain electrodes SU1 to SUn, 0 (V) is applied to data electrodes D1 to Dm, and a ramp voltage waveform that gradually decreases from voltage Vi3 ′ to voltage Vi4 to scan electrodes SC1 to SCn. Is applied. As a result, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the previous subfield, and the wall voltage above scan electrode SCi and sustain electrode SUi is weakened. Further, in a discharge cell in which a sufficient positive wall voltage is accumulated on the data electrode Dk (k = 1 to m) by the last sustain discharge, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the address operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. Thus, the initializing operation in which the first half is omitted is a selective initializing operation in which initializing discharge is performed on the discharge cells in which the sustaining operation has been performed in the sustain period of the immediately preceding subfield.

  In the subsequent address period, voltage Ve2 is first applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Then, a negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell to be emitted in the first row among the data electrodes D1 to Dm is positive. The write pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. As a result, a discharge is generated between data electrode Dk and scan electrode SC1. In addition, since voltage Ve2 is applied to sustain electrodes SU1 to SUn, the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (Ve2-Va) and on sustain electrode SU1. The difference between the wall voltage and the wall voltage on the scan electrode SC1 is added. At this time, by setting the voltage Ve2 to a voltage value that is slightly lower than the discharge start voltage, the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do. Thereby, the discharge generated between data electrode Dk and scan electrode SC1 can be triggered to generate a discharge between sustain electrode SU1 and scan electrode SC1 in the region intersecting with data electrode Dk. Thus, an address discharge occurs in the discharge cell to emit light, a positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. Accumulated.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and a ground potential that is a base potential, that is, 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeding the discharge start voltage.

  Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) as a base potential is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, the sustain electrodes of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to the scan electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, and a potential difference is given between the electrodes of the display electrode pair 24, thereby writing. The sustain discharge is continuously performed in the discharge cell that has caused the address discharge in the period.

  At the end of the sustain period, a second ramp waveform voltage (hereinafter referred to as “erase ramp waveform voltage”) gently rising from 0 (V) as the base potential toward the voltage Vers is applied to scan electrodes SC1 to SCn. Applied). As a result, a weak discharge is continuously generated, and some or all of the wall voltages on scan electrode SCi and sustain electrode SUi are erased while the positive wall voltage on data electrode Dk remains.

  Specifically, after the sustain electrodes SU1 to SUn are returned to 0 (V), the erase is a second ramp waveform voltage that rises from 0 (V) as the base potential toward the voltage Vers that exceeds the discharge start voltage. The ramp waveform voltage is generated with a steeper slope than the up-ramp waveform voltage, which is the first ramp waveform voltage, for example, about 10 V / μsec, and is applied to scan electrodes SC1 to SCn. Then, a weak discharge is generated between sustain electrode SUi and scan electrode SCi of the discharge cell in which the sustain discharge has occurred. This weak discharge is continuously generated during a period in which the voltage applied to sustain electrodes SU1 to SUn increases. Then, as soon as the rising voltage reaches the voltage Vers, which is a predetermined potential, the voltage applied to the scan electrodes SC1 to SCn is dropped to 0 (V) as the base potential.

  At this time, the charged particles generated by the weak discharge are always accumulated as wall charges on the sustain electrode SUi and the scan electrode SCi so as to alleviate the voltage difference between the sustain electrode SUi and the scan electrode SCi. It will be done. As a result, the wall voltage between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn remains between the voltage applied to scan electrode SCi and the discharge start voltage while leaving positive wall charges on data electrode Dk. The difference is reduced to the extent of (voltage Vers−discharge start voltage). Hereinafter, the last discharge in the sustain period generated by the erase ramp waveform voltage is referred to as “erase discharge”.

In the present embodiment, when the voltage applied to scan electrodes SC1 to SCn reaches a predetermined voltage Vers, the voltage is immediately lowered to 0 (V) as the base potential. After the rising voltage reaches the predetermined voltage Vers, if this voltage is maintained, the following condition is satisfied:
The cell itself is a non-light emitting discharge cell (a discharge cell not addressed in the subfield).
This is a discharge cell that emits light from an adjacent cell (a discharge cell addressed in the subfield).
A self-sustained discharge occurred in the immediately preceding subfield.
This is because it has been experimentally confirmed that abnormal discharge is likely to occur in discharge cells that meet the above conditions.

  Since this abnormal discharge induces erroneous discharge in the subsequent address period, it is desirable to prevent it from being generated as much as possible. In this embodiment, when the erase ramp waveform voltage is generated, it is applied to scan electrodes SC1 to SCn. After the voltage to reach the voltage Vers, it is immediately lowered to 0 (V), which is the base potential, so that the addressing operation that continues the wall voltage in the discharge cell is stable while preventing the occurrence of this abnormal discharge. It can be optimally adjusted to do so.

  Subsequent subfield operations are substantially the same as those described above except for the number of sustain pulses in the sustain period, and thus description thereof is omitted. The above is the outline of the drive voltage waveform applied to each electrode of panel 10 in the present embodiment.

  In this embodiment, the voltage value of the voltage Vers is set to the sustain pulse voltage Vs + 3 (V), for example, about 213 (V), but here the voltage value of the voltage Vers is set to the sustain pulse voltage Vs−. It is desirable to set a voltage range of 10 (V) or more and sustain pulse voltage Vs + 10 (V) or less. If the voltage value of the voltage Vers is larger than the upper limit value, the wall voltage will be excessively adjusted. If the voltage value is smaller than the lower limit value, the wall voltage will be insufficiently adjusted and the subsequent writing operation may not be performed stably. Because.

  In the present embodiment, the configuration in which the gradient of the erase ramp waveform voltage is set to about 10 V / μsec has been described, but this gradient is preferably set to 2 V / μsec or more and 20 V / μsec or less. If the slope is steeper than this upper limit value, the discharge for adjusting the wall voltage will not be weak, and if the slope is made gentler than this lower limit value, the discharge itself will be too weak, This is because the voltage may not be adjusted properly.

  Next, the configuration of the plasma display device in the present embodiment will be described. FIG. 4 is a circuit block diagram of the plasma display device in one embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on outputs from the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. As described above, in this embodiment, the erase ramp waveform voltage is generated at the end of the sustain period, and a timing signal corresponding to the erase ramp waveform voltage is output to scan electrode drive circuit 43 and sustain electrode drive circuit 44. . As a result, stable initialization discharge is realized, and initialization bright spots in the panel are reduced.

  Scan electrode drive circuit 43 generates an initialization waveform voltage (not shown) for generating an initialization waveform voltage to be applied to scan electrodes SC1 to SCn in the initialization period, and applies to scan electrodes SC1 to SCn in the sustain period. A sustain pulse generating circuit (not shown) for generating a sustain pulse, a scan pulse generating circuit (not shown) for generating a scan pulse voltage to be applied to scan electrodes SC1 to SCn in an address period, and a timing Each of the scan electrodes SC1 to SCn is driven based on the signal. Sustain electrode drive circuit 44 includes a sustain pulse generation circuit (not shown) and a circuit for generating voltages Ve1 and Ve2, and drives sustain electrodes SU1 to SUn based on a timing signal.

  Next, the scan electrode drive circuit 43 will be described. FIG. 5 is a circuit diagram of scan electrode driving circuit 43 according to the embodiment of the present invention. Scan electrode driving circuit 43 includes sustain pulse generating circuit 50 for generating a sustain pulse, initialization waveform generating circuit 53 for generating an initialization waveform, and scan pulse generating circuit 54 for generating a scan pulse. FIG. 5 shows a separation circuit using the switching element Q12 and a separation circuit using the switching element Q13. In the following description, the operation for turning on the switching element is expressed as “on”, the operation for cutting off the switching element is expressed as “off”, the signal for turning on the switching element is expressed as “Hi”, and the signal for turning off is expressed as “Lo”.

  Sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 includes a power recovery capacitor C1, a switching element Q1, a switching element Q2, a backflow prevention diode D1, a backflow prevention diode D2, and a resonance inductor L1. The power recovery capacitor C1 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half the voltage value Vs, so as to serve as a power source for the power recovery circuit 51. Clamp circuit 52 includes switching element Q3 for clamping scan electrodes SC1 to SCn to voltage Vs, and switching element Q4 for clamping scan electrodes SC1 to SCn to 0 (V). Then, based on the timing signal output from the timing generation circuit 45, the switching elements are switched to generate the sustain pulse voltage Vs.

  In sustain pulse generating circuit 50, for example, when a sustain pulse waveform is raised, switching element Q1 is turned on to resonate interelectrode capacitance Cp and inductor L1, and switching element Q1 and diode from power recovery capacitor C1 Power is supplied to scan electrodes SC1 to SCn through D1 and inductor L1. Then, when the voltage of scan electrodes SC1 to SCn approaches Vs, switching element Q3 is turned on, and scan electrodes SC1 to SCn are clamped to voltage Vs. Even when the switching element Q12 is off, a parasitic diode called a body diode is anti-parallel to the portion that performs the switching operation (in parallel to the portion that performs the switching operation, and the current due to the switching operation). Therefore, when switching element Q3 is turned on, scan electrodes SC1 to SCn can be clamped to voltage Vs via this body diode.

  On the contrary, when the sustain pulse waveform is lowered, the switching element Q2 is turned on to resonate the interelectrode capacitance Cp and the inductor L1, and the interelectrode capacitance Cp is used for power recovery through the inductor L1, the diode D2, and the switching element Q2. The power is recovered in the capacitor C1. Then, when the voltage of scan electrodes SC1 to SCn approaches 0 (V), switching element Q4 is turned on, and scan electrodes SC1 to SCn are clamped to 0 (V).

  In the present embodiment, a ramp waveform generating circuit for generating an erase ramp waveform voltage is provided separately from the ramp waveform generating circuit for generating an up ramp waveform voltage during the initialization operation. . Specifically, the initialization waveform generating circuit 53 is a first ramp waveform generating circuit that has a capacitor C10 and a resistor R10 and generates an up-ramp waveform voltage that gradually rises in a ramp shape up to the voltage Vi2. Miller integrating circuit 55, a second Miller integrating circuit 56, which is a second ramp waveform generating circuit that has a capacitor C 11 and a resistor R 12 and generates an erasing ramp waveform voltage that gradually rises in a ramp shape up to voltage Vers, switching A third Miller integrating circuit 57, which is a third ramp waveform generating circuit that has an element Q14, a capacitor C12, and a resistor R11, and generates a ramp waveform voltage that gently ramps down to a voltage Vi4. In FIG. 5, the input terminals of the Miller integrating circuit are shown as an input terminal INa, an input terminal INb, and an input terminal INc.

  Further, in the present embodiment, in order to accurately stop the rise in voltage when the erase ramp waveform voltage is generated at the voltage Vers, the erase ramp waveform voltage is compared with a predetermined voltage, and the erase ramp waveform voltage is determined. A switching circuit for stopping the operation of the second Miller integrating circuit that generates the erase ramp waveform voltage immediately after reaching the predetermined voltage is provided. Specifically, the backflow prevention diode D13, the resistor R13 for adjusting the voltage value of the voltage Vers, and the voltage output from the initialization waveform generation circuit 53 reaches the voltage Vers. A switching element Q16 for setting the input terminal INc to “Lo”, a protective diode D12, and a resistor R14 are provided.

  The switching element Q16 is formed of a commonly used NPN transistor, and has a base connected to the output of the initialization waveform generating circuit 53, a collector connected to the input terminal INc of the second Miller integrating circuit 56, and an emitter connected in series. The resistor R13 and the diode D13 are connected to the voltage Vs. The resistor R13 has a resistance value set so that the switching element Q16 is turned on when the voltage output from the initialization waveform generation circuit 53 reaches the voltage Vers. Therefore, the resistance R13 is output from the initialization waveform generation circuit 53. When the voltage reaches voltage Vers, switching element Q16 is turned on. Then, the current input to the input terminal INc for operating the second Miller integrating circuit 56 is drawn to the switching element Q16, so that the second Miller integrating circuit 56 stops operating.

  In general, Miller integration circuits are easily affected by variations in the ramp waveform to be generated due to variations in the elements constituting the circuit. Therefore, if waveform generation is performed only during the operation period of the Miller integration circuit, the ramp waveform The maximum voltage value tends to vary. On the other hand, in this embodiment, it has been confirmed that it is desirable to keep the maximum voltage value of the erase ramp waveform voltage within ± 3 (V) with respect to the target voltage value. By using the configuration in this embodiment, Thus, it can be within a range of about ± 1 (V) with respect to the target voltage value, and the erase ramp waveform voltage can be generated with high accuracy.

  The voltage Vers 'is preferably set to a voltage value higher than the voltage Vers, and in this embodiment, the voltage Vers' is set to the voltage Vs + 30 (V). In this embodiment, the resistance value of the resistor R13 is set so that the voltage Vers becomes the voltage Vs + 3 (V). Specifically, the resistor R13 is set to 100Ω, the voltage Vs is set to 210 (V), and the resistor R14 is set. Is set to 1 kΩ. However, these values are only values set based on a 42-inch panel having 1080 display electrode pairs, and may be optimally set according to the characteristics of the panel and the specifications of the plasma display device.

  The initialization waveform generation circuit 53 generates the above-described initialization waveform voltage or erase ramp waveform voltage based on the timing signal output from the timing generation circuit 45.

  For example, when generating an up-ramp waveform voltage in the initialization waveform, a constant current of a predetermined voltage (for example, 15 (V)) is input to the input terminal INa to set the input terminal INa to “Hi”. As a result, a constant current flows from the resistor R10 toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 43 also starts to increase in a ramp shape.

  In addition, when generating the down-ramp waveform voltage in the initialization waveform of the all-cell initialization operation and the selection initialization operation, a constant current of a predetermined voltage (for example, 15 (V)) is input to the input terminal INb. The input terminal INb is set to “Hi”. Then, a constant current flows from the resistor R11 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 43 starts to decrease in a ramp shape.

  Further, when the erase ramp waveform voltage is generated at the end of the sustain period, a constant current of a predetermined voltage is input to the input terminal INc, and the input terminal INc is set to “Hi”. As a result, a constant current flows from the resistor R12 toward the capacitor C11, the source voltage of the switching element Q15 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 43 also starts to increase in a ramp shape. In the present embodiment, the resistance value of the resistor R12 is made smaller than the resistance value of the resistor R10, whereby the erase ramp waveform voltage, which is the second ramp waveform voltage, is changed to the first ramp waveform voltage. It is generated with a steeper slope than some up-ramp waveform voltage.

  When the drive voltage waveform output from the initialization waveform generating circuit 53 gradually increases and becomes higher than the voltage Vers, the switching element Q16 is turned on and the constant current input to the input terminal INc is pulled to the switching element Q16. As a result, the second Miller integrating circuit 56 stops operating. As a result, the drive voltage waveform output from the initialization waveform generation circuit 53 immediately drops to 0 (V), which is the base potential. Thus, in this embodiment, the rise in voltage when the erase ramp waveform voltage is generated is accurately stopped at the voltage Vers that is the predetermined potential, and then immediately lowered to 0 (V) that becomes the base potential.

  Scan pulse generation circuit 54 includes switch circuits OUT1 to OUTn that output scan pulse voltages to scan electrodes SC1 to SCn, switching element Q21 for clamping the low voltage side of switch circuits OUT1 to OUTn to voltage Va, Control circuits IC1 to ICn for controlling the switch circuits OUT1 to OUTn, and a diode D21 and a capacitor C21 for applying a voltage Vc obtained by superimposing the voltage Vscn on the voltage Va to the high voltage side of the switch circuits OUT1 to OUTn. ing. Each of the switch circuits OUT1 to OUTn includes switching elements QH1 to QHn for outputting the voltage Vc and switching elements QL1 to QLn for outputting the voltage Va. Based on the timing signal output from the timing generation circuit 45, the scan pulse voltage Va to be applied to the scan electrodes SC1 to SCn in the address period is sequentially generated. Scan pulse generation circuit 54 outputs the voltage waveform of initialization waveform generation circuit 53 during the initialization period and the voltage waveform of sustain pulse generation circuit 50 during the sustain period.

  Since a very large current flows through switching element Q3, switching element Q4, switching element Q12, and switching element Q13, a plurality of FETs, IGBTs, etc. are connected in parallel to these switching elements to reduce impedance. Yes.

  The scan pulse generation circuit 54 includes an AND gate AG that performs a logical product operation, and a comparator CP that compares the magnitudes of input signals input to the two input terminals. The comparator CP compares a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the voltage Va and the drive voltage waveform. If the drive voltage waveform is higher than the voltage (Va + Vset2), “0” is set. Then, “1” is output. Two input signals, that is, an output signal (CEL1) of the comparator CP and a switching signal CEL2 are input to the AND gate AG. As the switching signal CEL2, for example, a timing signal output from the timing generation circuit 45 can be used. The AND gate AG outputs “1” when any of the input signals is “1”, and outputs “0” otherwise. The output of the AND gate AG is input to the control circuits IC1 to ICn. If the output of the AND gate AG is “0”, the drive voltage waveform is output via the switching elements QL1 to QLn, and the output of the AND gate AG is “1”. If there is, the voltage Vc in which the voltage Vscn is superimposed on the voltage Va is output via the switching elements QH1 to QHn.

  In the present embodiment, a Miller integration circuit using FETs that are practical and have a relatively simple configuration for the first ramp waveform generation circuit, the second ramp waveform generation circuit, and the third ramp waveform generation circuit. However, the ramp waveform generating circuit is not limited to this configuration, and any circuit can be used as long as it can generate an up-ramp waveform voltage and a down-ramp waveform voltage. Good.

  Next, the sustain electrode drive circuit 44 will be described. FIG. 6 is a circuit diagram of the sustain electrode driving circuit 44 according to the embodiment of the present invention. In FIG. 6, the interelectrode capacitance of the panel 10 is shown as Cp.

  Sustain pulse generation circuit 60 of sustain electrode drive circuit 44 has substantially the same configuration as sustain pulse generation circuit 50 of scan electrode drive circuit 43, and collects and reuses power when driving sustain electrodes SU1 to SUn. Power recovery circuit 61 and a clamp circuit 62 for clamping sustain electrodes SU1 to SUn to voltages Vs and 0 (V), and sustain electrodes SU1 to SU1 that are one end of interelectrode capacitance Cp of panel 10 are provided. Connected to SUn.

  The power recovery circuit 61 includes a power recovery capacitor C30, a switching element Q31, a switching element Q32, a backflow prevention diode D31, a diode D32, and a resonance inductor L30. Then, the interelectrode capacitance Cp and the inductor L30 are LC-resonated, and the sustain pulse rises and falls. The clamp circuit 62 includes a switching element Q33 for clamping the sustain electrodes SU1 to SUn to the voltage Vs, and a switching element Q34 for clamping the sustain electrodes SU1 to SUn to 0 (V). Then, sustain electrodes SU1 to SUn are connected to power source VS via switching element Q33 and clamped to voltage Vs, and sustain electrodes SU1 to SUn are grounded via switching element Q34 and clamped to 0 (V).

  The sustain electrode drive circuit 44 also includes a power source VE1 that generates the voltage Ve1, a switching element Q36 for applying the voltage Ve1 to the sustain electrodes SU1 to SUn, a switching element Q37, a power source ΔVE that generates the voltage ΔVe, and a backflow prevention A diode D33, a pump-up capacitor C31 for accumulating the voltage ΔVe on the voltage Ve1, a switching element Q38 for accumulating the voltage ΔVe on the voltage Ve1 to obtain the voltage Ve2, and a switching element Q39 are provided.

  For example, at the timing of applying the voltage Ve1 shown in FIG. 3, the switching element Q36 and the switching element Q37 are turned on, and the positive voltage Ve1 is connected to the sustain electrodes SU1 to SUn via the diode D33, the switching element Q36, and the switching element Q37. Apply. At this time, the switching element Q38 is turned on and charged so that the voltage of the capacitor C31 becomes the voltage Ve1. In addition, at the timing of applying the voltage Ve2 shown in FIG. 3, the switching element Q36 and the switching element Q37 are kept conductive, the switching element Q38 is cut off, and the switching element Q39 is turned on to apply the voltage ΔVe to the voltage of the capacitor C31. The voltage (Ve1 + ΔVe), that is, the voltage Ve2 is applied to the sustain electrodes SU1 to SUn. At this time, the current from the capacitor C31 to the power source VE1 is cut off by the action of the backflow preventing diode D33.

  Next, details of the drive voltage waveform in the sustain period will be described. FIG. 7 is a timing chart for explaining an example of operations of scan electrode drive circuit 43 and sustain electrode drive circuit 44 in the embodiment of the present invention, and is a detailed timing chart of a portion surrounded by a broken line in FIG. It is. First, one period of the sustain pulse repetition period is divided into six periods indicated by T1 to T6, and each period will be described. The repetition period is an interval between sustain pulses repeatedly applied to the display electrode pair in the sustain period, and represents a period repeated by the periods T1 to T6, for example. In FIG. 7, the waveform of the positive electrode is described, but the present invention is not limited to this. For example, although the embodiment in the negative waveform is omitted, what is expressed as “rising” in the positive waveform in the following description is “falling” in the negative waveform, and “ By replacing the expression “falling” with “rising” in the negative waveform, the same effect can be obtained even in the negative waveform. In the drawing, a signal for turning on the switching element is represented as “ON”, and a signal for turning off is represented as “OFF”.

(Period T1)
At time t1, switching element Q2 is turned on. Then, the charges on the scan electrodes SC1 to SCn side start to flow to the capacitor C1 through the inductor L1, the diode D2, and the switching element Q2, and the voltage of the scan electrodes SC1 to SCn starts to decrease. Since the inductor L1 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the scan electrodes SC1 to SCn drops to near 0 (V) at time t2 after the time ½ of the resonance period has elapsed. However, the voltage of scan electrodes SC1 to SCn does not drop to 0 (V) due to power loss due to the resistance component of the resonance circuit. During this period, the switching element Q34 is kept on.

(Period T2)
At time t2, switching element Q4 is turned on. Then, scan electrodes SC1 to SCn are directly grounded through switching element Q4, so that the voltages of scan electrodes SC1 to SCn are forcibly lowered to 0 (V).

  Further, switching element Q31 is turned on at time t2. Then, current begins to flow from the power recovery capacitor C30 through the switching element Q31, the diode D31, and the inductor L30, and the voltages of the sustain electrodes SU1 to SUn begin to rise. Since the inductor L30 and the interelectrode capacitance Cp form a resonance circuit, the voltage of the sustain electrodes SU1 to SUn rises to near Vs at time t3 after a time ½ of the resonance period has elapsed. Due to power loss due to the resistance component or the like, the voltage of the sustain electrodes SU1 to SUn does not rise to Vs.

(Period T3)
At time t3, switching element Q33 is turned on. Then, since sustain electrodes SU1 to SUn are directly connected to power supply VS through switching element Q33, the voltages of sustain electrodes SU1 to SUn are forcibly increased to Vs. Then, in the discharge cell in which the address discharge has occurred, the voltage between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs.

(Period T4-T6)
The sustain pulse applied to scan electrodes SC1 to SCn and the sustain pulse applied to sustain electrodes SU1 to SUn have the same waveform, and the operation from period T4 to period T6 scans the operation from period T1 to period T3. Since this is equivalent to the operation of driving the electrodes SC1 to SCn and the sustain electrodes SU1 to SUn, the description thereof will be omitted.

  Switching element Q2 may be turned off after time t2 and before time t5, and switching element Q31 may be turned off after time t3 and before time t4. Further, the switching element Q32 may be turned off by the next time t2 after the time t5, and the switching element Q1 may be turned off by the next time t1 after the time t6. In order to lower the output impedance of sustain pulse generating circuits 50 and 60, switching element Q34 is preferably turned off immediately before time t2, switching element Q3 is preferably turned off immediately before time t1, and switching element Q4 is turned off immediately before time t5. Switching element Q33 is preferably turned off immediately before time t4.

  In the sustain period, the operations in the above periods T1 to T6 are repeated according to the required number of pulses. In this way, a sustain pulse voltage that shifts from 0 (V) as the base potential to the voltage Vs that is a potential for generating a sustain discharge is alternately applied to each of the display electrode pairs 24 to cause the discharge cells to sustain discharge. .

  Next, an operation when the erase ramp waveform voltage is generated at the end of the sustain period will be described.

(Period T7)
This period is the fall of the sustain pulse applied to sustain electrodes SU1 to SUn, and is the same as period T4. That is, by turning off switching element Q33 immediately before time t7 and turning on switching element Q32 at time t7, the charges on the sustain electrodes SU1 to SUn side begin to flow to capacitor C30 through inductor L30, diode D32, and switching element Q32. The voltage of sustain electrodes SU1 to SUn begins to drop. Further, the switching element Q4 is kept on, and the scan electrodes SC1 to SCn are maintained at 0 (V) which is the base potential.

(Period T8)
At time t8, switching element Q34 is turned on to forcibly reduce the voltage of sustain electrodes SU1 to SUn to 0 (V).

  At time t8, the input terminal INc is set to “Hi”. As a result, a constant current flows from the resistor R12 toward the capacitor C11, the source voltage of the switching element Q15 rises in a ramp shape, and the output voltage of the scan electrode drive circuit 43 has a steeper slope than the up-ramp waveform voltage. It begins to rise like a ramp. In this way, the erase ramp waveform voltage which is the second ramp waveform voltage rising from 0 (V) as the base potential toward the voltage Vers is generated. The voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage while the erase ramp waveform voltage rises. At this time, in the present embodiment, each numerical value is set so that discharge is generated only between scan electrode SCi and sustain electrode SUi. For example, sustain pulse voltage Vs is about 210 (V), and voltage Vers is about 213 (V), and the gradient of the erase ramp waveform voltage is about 10 V / μsec. Thus, a weak discharge can be generated between scan electrode SCi and sustain electrode SUi, and this weak discharge can be continued during the period when the erase ramp waveform voltage rises.

  At this time, if a momentary strong discharge due to a sudden voltage change is generated, a large amount of charged particles generated by the strong discharge form a large wall charge so as to relieve the sudden voltage change, The wall voltage formed by the sustain discharge is excessively erased. In addition, in a panel with a large screen, high definition, and increased driving impedance, waveform distortion such as ringing is likely to occur in the driving waveform generated from the driving circuit. Then, there is a risk of generating strong discharge due to waveform distortion.

  However, in the present embodiment, a weak erase discharge is continuously generated between the scan electrode SCi and the sustain electrode SUi by the erase ramp waveform voltage that gradually increases the applied voltage. Even in a panel with high definition and increased driving impedance, the erase discharge can be generated stably, and the wall voltage on the scan electrode SCi and the sustain electrode SUi can be generated stably. It can be adjusted to the optimum state.

  Although not shown in the drawing, since the data electrodes D1 to Dm are held at 0 (V) at this time, a positive wall voltage is formed on the data electrodes D1 to Dm.

(Period T9)
When the drive voltage waveform output from initialization waveform generation circuit 53 reaches voltage Vers at time t9, switching element Q16 is turned on and input to input terminal INc to operate second Miller integration circuit 56. The current is drawn to the switching element Q16, and the second Miller integrating circuit 56 stops operating.

  As described above, after the voltage applied to scan electrodes SC1 to SCn reaches voltage Vers, if the voltage is maintained, abnormal discharge that induces erroneous discharge in the subsequent address period may occur. However, in this embodiment, since the voltage applied to scan electrodes SC1 to SCn reaches voltage Vers, the voltage is immediately dropped to 0 (V), which is the base potential, so that this abnormal discharge is prevented from occurring. can do.

  Then, after time t10, which is the initializing period of the next subfield, the initializing operation of the subsequent subfield, for example, if the subsequent subfield is a selective initializing subfield, the scan electrodes SC1 to SCn have a down-ramp waveform. A voltage is applied, and a voltage Ve1 is applied to the sustain electrodes to start a selective initialization operation.

  Next, details of the drive voltage waveform in the initialization period will be described. FIG. 8 is a timing chart for explaining an example of the operation of scan electrode driving circuit 43 in the all-cell initializing period in one embodiment of the present invention. In the drawing, the drive waveform during the all-cell initialization operation is described as an example, but the down-ramp waveform voltage can be generated by the same control in the selective initialization operation.

  In FIG. 8, the drive voltage waveform for performing the all-cell initialization operation is divided into five periods indicated by periods T10 to T14, and each period will be described. Further, the voltage Vi1, the voltage Vi3, and the voltage Vi3 ′ are equal to the voltage Vs, the voltage Vi2 is equal to the voltage Vr, and the voltage Vi4 is equal to a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the negative voltage Va. Will be described. In the drawing, the input signals CEL1 and CEL2 to the AND gate AG are similarly expressed as “Hi” and “0” as “Lo”.

  FIG. 8 also shows the operations of the period T8 to period T9 in which the erase ramp waveform voltage is generated in order to show the difference between the generation of the erase ramp waveform voltage and the generation of the up ramp waveform voltage.

  Here, in order to change the voltage Vi4 to a voltage (Va + Vset2) obtained by superimposing the voltage Vset2 on the negative voltage Va, the switching signal CEL2 is maintained at “1” in the periods T10 to T14. Although not shown, the switching element Q21 is kept off during the periods T10 to T14. Although not shown, a signal having a reverse polarity to the signal input to the input terminal INa is input to the switching element Q12 constituting the separation circuit, and the input terminal is connected to the switching element Q13 constituting the separation circuit. A signal having a polarity opposite to that of the signal input to INb is input.

(Period T8)
In the period T8, the input terminal INc is set to “Hi”. As a result, a constant current flows from the resistor R12 toward the capacitor C11, the source voltage of the switching element Q15 rises in a ramp shape, and the output voltage of the scan electrode drive circuit 43 has a steeper slope than the up-ramp waveform voltage. It begins to rise like a ramp.

(Period T9)
When the drive voltage waveform output from the initialization waveform generating circuit 53 reaches the voltage Vers, the switching element Q16 is turned on, and the current input to the input terminal INc for operating the second Miller integrating circuit 56 is the switching element. Pulled out by Q16, the second Miller integrating circuit 56 stops its operation.

  Thus, the erase ramp waveform voltage, which is the second ramp waveform voltage rising from 0 (V) as the base potential toward the voltage Vers, is generated.

(Period T10)
Then, switching element Q1 of sustain pulse generating circuit 50 is turned on. Then, the interelectrode capacitance Cp and the inductor L1 resonate, and the voltage of the scan electrodes SC1 to SCn starts to rise from the power recovery capacitor C1 through the switching element Q1, the diode D1, and the inductor L1.

(Period T11)
Next, switching element Q3 of sustain pulse generating circuit 50 is turned on. Then, voltage Vs is applied to scan electrodes SC1 to SCn via switching element Q3 and switching element Q12, and the potential of scan electrodes SC1 to SCn becomes voltage Vs (equal to voltage Vi1 in the present embodiment).

(Period T12)
Next, the input terminal INa of the Miller integrating circuit that generates the up-ramp waveform voltage is set to “Hi”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal INa. Then, a constant current flows from the resistor R10 toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 43 starts to increase in a ramp shape. This voltage increase continues while the input terminal INa is “Hi”.

  When this output voltage rises to the voltage Vr (equal to the voltage Vi2 in this embodiment), the input terminal INa is then set to “Lo”. Specifically, for example, a voltage of 0 (V) is applied to the input terminal INa.

  In this way, the voltage Vs (equal to the voltage Vi1 in the present embodiment) that is equal to or lower than the discharge start voltage gradually decreases toward the voltage Vr (equal to the voltage Vi2 in the present embodiment) that exceeds the discharge start voltage. Is applied to scan electrodes SC1 to SCn.

(Period T13)
When the input terminal INa is set to “Lo”, the voltage of scan electrodes SC1 to SCn decreases to voltage Vs (equal to voltage Vi3 in the present embodiment). Thereafter, the switching element Q3 is turned off.

(Period T14)
Next, the input terminal INb of the Miller integrating circuit that generates the down-ramp waveform voltage is set to “Hi”. Specifically, for example, a voltage of 15 (V) is applied to the input terminal INb. Then, a constant current flows from the resistor R11 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 43 starts to decrease in a ramp shape. Then, immediately before the initialization period ends, the input terminal INb is set to “Lo”. Specifically, for example, a voltage of 0 (V) is applied to the input terminal INb.

  In the period T14, the switching element Q13 is turned off, but the Miller integrating circuit that generates the down-ramp waveform voltage can decrease the output voltage of the scan electrode driving circuit 43 via the body diode of the switching element Q13.

  In the comparator CP, the down-ramp waveform voltage is compared with the voltage (Va + Vset2) obtained by adding the voltage Vset2 to the voltage Va, and the output signal from the comparator CP is the voltage of the down-ramp waveform voltage ( Va + Vset2) At time t14 when the time becomes equal to or less than “0”, “0” is switched to “1”. Since the switching signal CEL2 is “1”, the inputs of the AND gate AG are both “1”, and “1” is output from the AND gate AG. The scan pulse generation circuit 54 outputs the negative voltage Va. A voltage Vc in which the voltage Vscn is superimposed on is output. Accordingly, the scan pulse generation circuit 54 outputs a down-ramp waveform voltage with the voltage Vi4 set to (Va + Vset2).

  As described above, scan electrode drive circuit 43 generates an up-ramp waveform voltage that is a first ramp waveform voltage that gradually increases from voltage Vi1 that is equal to or lower than the discharge start voltage to voltage Vi2 that exceeds the discharge start voltage. And applied to scan electrodes SC1 to SCn, and thereafter, a ramp voltage waveform that gently falls from voltage Vi3 to voltage Vi4 is applied.

  Although not shown, the switching element Q21 is kept on in the subsequent writing period after the end of the initialization period. As a result, the voltage input to one terminal of the comparator CP becomes the negative voltage Va, and the output signal CEL1 from the comparator CP is maintained at “1”. As a result, the output from the AND gate AG is maintained at “1”, and the scan pulse generation circuit 54 outputs the voltage Vc in which the voltage Vscn is superimposed on the negative voltage Va. Then, by setting the switching signal CEL2 to “0” at the timing of generating the negative scanning pulse voltage, the output signal of the AND gate AG becomes “0”, and the negative voltage Va is output from the scanning pulse generation circuit 54. The In this way, a negative scanning pulse voltage in the address period can be generated.

  As described above, in the present embodiment, at the end of the sustain period, that is, after the sustain pulse is applied to the display electrode pair, the erase ramp waveform voltage having a steeper slope than the up ramp waveform voltage. Is applied to the scan electrodes SC1 to SCn to continuously generate a weak erasure discharge, and after the rising voltage reaches the voltage Vers, the voltage is immediately lowered to 0 (V) as the base potential. Therefore, even in panels with larger screens and higher definition, address discharge can be generated stably without increasing the voltage required to generate address discharge, and image display quality can be improved. It becomes.

  In the present embodiment, in the erase ramp waveform voltage, when the rising voltage reaches the voltage Vers, the configuration is immediately lowered to 0 (V) as the base potential. However, in order to prevent the abnormal discharge described above. For this, it is desirable to set the fall potential to 70% or less of the voltage Vers. FIG. 9 is a diagram showing another example of the drive voltage waveform in the embodiment of the present invention. For example, as shown in this drawing, if the erase ramp waveform voltage reaches the voltage Vers and immediately drops to the voltage Vb (the voltage Vb is equal to or lower than the voltage Vers × 0.7), Even if the voltage Vb is maintained for a certain period, the above-described effects can be obtained while preventing the above-described abnormal discharge. In this embodiment, the lower limit voltage value of the drop arrival potential is set to 0 (V) as the base potential. This lower limit voltage value facilitates the selective initialization operation by the subsequent down-ramp waveform voltage. It's just a value set to make it possible. In the present embodiment, the lower limit voltage value is not limited to the above-described value, and may be optimally set within a range in which the operation following the erasing operation can be smoothly performed.

  In the present embodiment, scan electrode drive circuit 43 and sustain electrode drive circuit 44 shown in FIG. 5 and FIG. 6 are merely examples of a configuration, and can perform the same operation. Any circuit configuration may be used. For example, the circuit that applies the voltage Ve1 and the voltage Ve2 is not limited to the circuit shown in FIG. 6, and for example, a power source that generates the voltage Ve1 and a power source that generates the voltage Ve2, and the respective voltages are maintained electrodes. A plurality of switching elements for applying to SU1 to SUn can be used to apply the sustain electrodes SU1 to SUn at necessary timings. Further, the circuit for generating the erase ramp waveform voltage shown in FIG. 5 is merely a configuration example, and can be replaced with another circuit that can realize the same operation.

  In the present embodiment, scan electrodes SC1 to SCn are divided into a first scan electrode group and a second scan electrode group, and an address period is scanned to each of the scan electrodes belonging to the first scan electrode group. A first address period in which a pulse is sequentially applied, and a second address period in which a scan pulse is sequentially applied to each of the scan electrodes belonging to the second scan electrode group, and the first address period and the second address period In at least one of the address periods, a scan pulse belonging to the scan electrode group to which the scan pulse is applied is supplied with a scan pulse that transits from the second voltage higher than the scan pulse voltage to the scan pulse voltage and then transits to the second voltage again. A scan electrode belonging to a scan electrode group to which the scan pulse is not applied is sequentially applied to any one of the third voltage higher than the scan pulse voltage and the fourth voltage higher than the second voltage and the third voltage. Voltage It can be applied to a panel driving method by so-called two-layer driving, in which a third voltage is applied while a scanning pulse voltage is applied to at least adjacent scanning electrodes. Obtainable.

  In the present embodiment, the configuration in which the erase ramp waveform voltage is applied to scan electrodes SC1 to SCn has been described. However, when the last sustain pulse is applied to scan electrodes SC1 to SCn, erase ramp waveform voltage is applied. Can be applied to sustain electrodes SU1 to SUn. However, in the present embodiment, it is desirable to use a configuration in which the electrode to which the last sustain pulse is applied is the sustain electrodes SU1 to SUn, and the erase ramp waveform voltage is applied to the scan electrodes SC1 to SCn.

  In the present embodiment, the power recovery circuits 51 and 61 have been described with a configuration in which one inductor is commonly used for the rise and fall of the sustain pulse. However, the rise and rise of the sustain pulse are performed using a plurality of inductors. A different inductor may be used for the lower end.

  Note that the specific numerical values shown in the present embodiment, for example, the voltage value of the voltage Vers and the gradient of the erase pulse waveform voltage are set based on the characteristics of the 42-inch panel having 1080 display electrode pairs used in the experiment. However, it is merely an example of the embodiment. This embodiment is not limited to these numerical values, and is desirably set to an optimal value according to the characteristics of the panel, the specifications of the plasma display device, and the like. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained.

  INDUSTRIAL APPLICABILITY The present invention can stably generate address discharge even in a panel with a large screen and high definition, and is useful as a plasma display device with good image display quality.

The disassembled perspective view which shows the structure of the panel in one embodiment of this invention. Electrode arrangement of the panel Drive voltage waveform diagram applied to each electrode of the panel The circuit block diagram of the plasma display apparatus in one embodiment of the present invention 1 is a circuit diagram of a scan electrode driving circuit according to an embodiment of the present invention. 1 is a circuit diagram of a sustain electrode driving circuit according to an embodiment of the present invention. Timing chart for explaining an example of operation of scan electrode drive circuit and sustain electrode drive circuit in one embodiment of the present invention 4 is a timing chart for explaining an example of the operation of the scan electrode driving circuit during the all-cell initialization period in one embodiment of the present invention. The figure which showed the other example of the drive voltage waveform in one embodiment of this invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50, 60 Sustain pulse generation circuit 51, 61 Power recovery circuit 52, 62 Clamp circuit 53 Initialization waveform generation circuit 54 Scan pulse generation circuit 55 1 Miller integration circuit 56 Second Miller integration circuit 57 Third Miller integration circuit

Claims (2)

An initializing period in which a slowly increasing first ramp waveform voltage is applied to the display electrodes of a plasma display panel having display electrodes constituting a plurality of discharge cells, and an address pulse selectively applied to the display electrodes of the discharge cells An address period for applying a voltage, and a sustain period for applying a sustain pulse voltage for generating a sustain discharge in the display electrode of the discharge cell selected in the address period,
At the end of the sustain period, a second ramp waveform voltage that rises with a steeper slope than the first ramp waveform voltage is generated, and when the second ramp waveform voltage reaches a predetermined potential, it is lowered immediately. A plasma display device comprising an operating ramp waveform generating circuit. 2. The plasma display device according to claim 1, wherein the ramp waveform generating circuit includes a switching circuit that stops the operation of the ramp waveform generating circuit as soon as the second ramp waveform voltage reaches a predetermined voltage.

Images