JP2008244388A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008244388A
JP2008244388A JP2007086503A JP2007086503A JP2008244388A JP 2008244388 A JP2008244388 A JP 2008244388A JP 2007086503 A JP2007086503 A JP 2007086503A JP 2007086503 A JP2007086503 A JP 2007086503A JP 2008244388 A JP2008244388 A JP 2008244388A
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semiconductor element
semiconductor
electrode
semiconductor device
gate
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Naoki Ozawa
直樹 小澤
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NEC Electronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small semiconductor device with low power consumption. <P>SOLUTION: The semiconductor device has a plurality of semiconductor elements stacked and connected in series, the semiconductor element having a vertical structure including a source electrode and a gate electrode as surface electrodes and a drain electrode as a backside electrode, wherein the drain electrode (not shown in Fig.1) of a second semiconductor element 15 is stacked on a source electrode 12 of a first semiconductor element 14 and connected in series with the source electrode 12, and a gate electrode 10 of the first semiconductor element is disposed so as not to overlap with the second semiconductor element 15. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、縦型構造の半導体素子を備える半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device provided with a semiconductor element having a vertical structure.

近年、高電圧が入力されるスイッチング電源の一次側のスイッチング用途をはじめ、高電圧スイッチング用途に縦型構造の半導体素子である縦型構造のパワーＭＯＳＦＥＴが、多く使用されている。この縦型構造のパワーＭＯＳＦＥＴが使用される各種装置は、小型・低消費電力、高効率などの特徴、機能が求められており、これら装置のキーデバイスであるパワーＭＯＳＦＥＴに対しても同様の特徴、機能が求められている。具体的には、小型のパッケージで、導通時の損失を下げるために低オン抵抗性能が求められている。   2. Description of the Related Art In recent years, vertical structure power MOSFETs, which are semiconductor elements having a vertical structure, are widely used for high voltage switching applications, including switching applications on the primary side of a switching power supply to which a high voltage is input. Various devices using this vertical structure power MOSFET are required to have features and functions such as small size, low power consumption, high efficiency, etc. The same features are also applied to the power MOSFET which is the key device of these devices. , Function is sought. Specifically, low on-resistance performance is required in a small package in order to reduce loss during conduction.

一方、パワーＭＯＳＦＥＴのオン抵抗と耐圧とはトレードオフの関係であるため、耐圧を上げるとオン抵抗が増加する。オン抵抗を下げるためにはチップサイズを大きくする必要があり、パッケージサイズが大きくなる、という関係であり、小型化・低消費電力、高効率という要求を同時に満足するのには困難があった。   On the other hand, since the on-resistance and the withstand voltage of the power MOSFET are in a trade-off relationship, increasing the withstand voltage increases the on-resistance. In order to reduce the on-resistance, it is necessary to increase the chip size and increase the package size, and it has been difficult to satisfy the requirements of downsizing, low power consumption, and high efficiency at the same time.

特許文献１には、小型で低損失なスイッチング素子を直列に接続し、ダイオードを組み合わせることにより、小型、高スイッチング速度、低損失の半導体装置を提供することが開示されている。特許文献１を図６乃至図８を用いて以下に簡単に説明する。図６に示すように、スイッチング素子１０１を複数個直列に接続し、これら複数個のスイッチング素子に対してダイオード１０２を並列に接続している半導体装置の回路図が開示されている。   Patent Document 1 discloses providing a semiconductor device with a small size, a high switching speed, and a low loss by connecting small and low-loss switching elements in series and combining diodes. Patent Document 1 will be briefly described below with reference to FIGS. As shown in FIG. 6, a circuit diagram of a semiconductor device in which a plurality of switching elements 101 are connected in series and a diode 102 is connected in parallel to the plurality of switching elements is disclosed.

また、図６の回路図の具体的な実現手段として図７に示される構成例が開示されている。即ち、絶縁板１０６を介して配置されたスイッチング素子チップ１０４が、配線１０８で直列に接続されることなどが開示されている。   Further, a configuration example shown in FIG. 7 is disclosed as a specific means for realizing the circuit diagram of FIG. That is, it is disclosed that the switching element chip 104 arranged via the insulating plate 106 is connected in series by the wiring 108.

さらに、特許文献１には、他の実施形態として図８に示すように、複数のスイッチング素子チップ１０４をそれぞれ直列にし、これら複数のスイッチング素子チップ４に対して、ＳiＣダイオードチップが並列に、それぞれのチップ間に導電板１０７を挟んで接続されており、これらチップ１０４、１０５と導電板１０７を絶縁構造物１０９が被覆する構成が開示されている。
特開平１１−２７４４８２号公報 Further, in Patent Document 1, as shown in FIG. 8 as another embodiment, a plurality of switching element chips 104 are connected in series, and SiC diode chips are connected in parallel to the plurality of switching element chips 4, respectively. A structure is disclosed in which a conductive plate 107 is sandwiched between the chips, and the chips 104 and 105 and the conductive plate 107 are covered with an insulating structure 109.
JP-A-11-274482

上述の通り、特許文献１にはスイッチング素子チップを重ね合わせて直列接続することは開示されているが、その詳細、すなわち、直列接続した際のスイッチング素子の各電極と対応する外部端子との接続方法などについては、開示されておらず、不明確であり、これを用いて具体的に直列接続した半導体装置を実現することができなかった。   As described above, Patent Document 1 discloses that the switching element chips are stacked and connected in series, but the details thereof, that is, the connection between each electrode of the switching element and the corresponding external terminal when connected in series are disclosed. The method and the like are not disclosed and are unclear, and it has not been possible to realize a semiconductor device specifically connected in series using this method.

したがって、 本発明は、スイッチング素子チップを複数個重ね合わせた半導体装置を具体的に実現することを目的とする。   Therefore, an object of the present invention is to specifically realize a semiconductor device in which a plurality of switching element chips are stacked.

本発明の半導体装置は、表面電極としてソース電極とゲート電極とを備え、裏面電極としてドレイン電極を備える縦型構造の半導体素子を複数個用いる半導体装置であって、第１の半導体素子のソース電極と第２の半導体素子のドレイン電極とを重ね合わせて接続し、前記第１の半導体素子のゲート電極が、前記第２の半導体素子に重なり合わないことを特徴とする。   A semiconductor device according to the present invention is a semiconductor device using a plurality of semiconductor elements having a vertical structure including a source electrode and a gate electrode as a front electrode and a drain electrode as a back electrode, the source electrode of the first semiconductor element And the drain electrode of the second semiconductor element are connected in an overlapping manner, and the gate electrode of the first semiconductor element does not overlap the second semiconductor element.

本発明は、縦型構造の半導体素子を複数個重ね合わせて接続する際に、第１の半導体素子のソース電極に第２の半導体素子のドレイン電極を重ね合わせて接続すると共に、第１の半導体素子のゲート電極が、前記第２の半導体素子に重なり合わないことにより、外部端子との接続を効率的に行うことができ、小型で低オン抵抗、つまり、小型で低消費電力の半導体装置を得ることができる。   According to the present invention, when a plurality of semiconductor elements having a vertical structure are connected in an overlapping manner, a drain electrode of a second semiconductor element is connected in an overlapping manner to a source electrode of the first semiconductor element, and the first semiconductor is connected. Since the gate electrode of the element does not overlap with the second semiconductor element, the connection with the external terminal can be performed efficiently, and a small and low on-resistance, that is, a small and low power consumption semiconductor device can be obtained. Obtainable.

（第１の実施形態）
以下、本発明の第１の実施形態を図１〜図３を用いて説明する。なお、本発明の第１の実施形態を要説すると、縦型の半導体素子１４と縦型の半導体素子１５とが、ドレイン電極とソース電極を介して直列に接続され、全体を外装樹脂で覆っている構造である。更に、半導体素子１４のゲートボンディングパッド１０（後述するようにゲート電極とも言える）が、上方の半導体素子１５に重なり合わない構造である。このため第１の実施形態では、上方の半導体素子１５の方が半導体素子１４よりも表面積が小さい構造となっている。 (First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In brief description of the first embodiment of the present invention, the vertical semiconductor element 14 and the vertical semiconductor element 15 are connected in series via the drain electrode and the source electrode, and the whole is covered with the exterior resin. It is a structure. Furthermore, the gate bonding pad 10 (also referred to as a gate electrode as will be described later) of the semiconductor element 14 has a structure that does not overlap the upper semiconductor element 15. For this reason, in the first embodiment, the upper semiconductor element 15 has a smaller surface area than the semiconductor element 14.

図１は、本発明の半導体装置３０の上面図である。なお、図１は、厳密にいうと実線で 示した外装樹脂１６を外して上から見た透過平面図ともいうべきものである。図中、１は第１の半導体素子１４のソース端子であり、そのソースワイヤ７を介して、第１の半導体 素子１４のソース電極の一部であるソースボンディングパット１２に接続されている。２は、第１の半導体素子１４のゲート端子であり、そのゲートワイヤ６を介して第１の半導 体素子１４のゲート電極の一部であるゲートボンディングパット１０に接続されている。 ３は第２の半導体素子１５のゲート端子であり、そのゲートワイヤ８を介して、第２の半導体素子のゲート電極の一部であるゲートボンディングパット１１に接続されている。４は、第２の半導体素子１５のソース端子であり、そのソースワイヤ９を介して第２の半導体素子のソース電極の一部であるソースボンディングパット１３に接続されている。従って、ソースボンディングパット１３は、第２の半導体素子のソース電極とも換言でき、また、ソースボンディングパット１２は、第１の半導体素子のソース電極とも換言できる。   FIG. 1 is a top view of a semiconductor device 30 of the present invention. In addition, strictly speaking, FIG. 1 should also be referred to as a transmission plan view seen from above with the exterior resin 16 shown by a solid line removed. In the figure, reference numeral 1 denotes a source terminal of the first semiconductor element 14, which is connected to the source bonding pad 12, which is a part of the source electrode of the first semiconductor element 14, through the source wire 7. A gate terminal 2 of the first semiconductor element 14 is connected to a gate bonding pad 10 which is a part of the gate electrode of the first semiconductor element 14 through the gate wire 6. A gate terminal 3 of the second semiconductor element 15 is connected to a gate bonding pad 11 which is a part of the gate electrode of the second semiconductor element via the gate wire 8. Reference numeral 4 denotes a source terminal of the second semiconductor element 15, which is connected to the source bonding pad 13 that is a part of the source electrode of the second semiconductor element via the source wire 9. Accordingly, the source bonding pad 13 can also be referred to as the source electrode of the second semiconductor element, and the source bonding pad 12 can also be referred to as the source electrode of the first semiconductor element.

以上述べたように、ゲートボンディングパッド１０の上には第２の半導体素子１５は組み立てされない。これは、ゲートワイヤ６を接続するなどのためである。なお、ゲートボンディングパッドの表面積は、ソースボンディングパッドに比べて相当小さくても性能上は問題がないため、このような構成としても、製品表面積の増加など実用上の問題は生じない。なお、ゲートボンディングパッド１０は換言すると、第１の半導体素子のゲート電極とも言えるので、第１の半導体素子のゲート電極の上には、第２の半導体素子１５は組み立てされないとも言える。これを更に換言すると、第１の半導体素子のゲート電極が第２の半導体素子に重なり合わない構成となっていると言える。   As described above, the second semiconductor element 15 is not assembled on the gate bonding pad 10. This is because the gate wire 6 is connected. Even if the surface area of the gate bonding pad is considerably smaller than that of the source bonding pad, there is no problem in terms of performance. Therefore, even with such a configuration, there is no practical problem such as an increase in the surface area of the product. In other words, since the gate bonding pad 10 can be said to be the gate electrode of the first semiconductor element, it can be said that the second semiconductor element 15 is not assembled on the gate electrode of the first semiconductor element. In other words, it can be said that the gate electrode of the first semiconductor element does not overlap with the second semiconductor element.

さらに、５は第１の半導体素子のドレイン端子であり、リードフレームも兼ねている。また、これは、図示しない第１の半導体素子のドレイン電極と接続している。この詳細は図２に示す。なお、第１の半導体素子１４はチップ状であり、第１の半導体素子チップ１４、又は第１の半導体素子のチップ１４、もしくは第１の半導体チップ１４とも換言できる。第２半導体素子１５についても同様である。   Further, 5 is a drain terminal of the first semiconductor element, which also serves as a lead frame. This is also connected to the drain electrode of the first semiconductor element (not shown). The details are shown in FIG. Note that the first semiconductor element 14 has a chip shape, and can also be referred to as the first semiconductor element chip 14, the first semiconductor element chip 14, or the first semiconductor chip 14. The same applies to the second semiconductor element 15.

また、第１の半導体素子１４、第２の半導体素子１５は共に縦型構造の半導体素子であり、表面にソース電極とゲート電極を備え、裏面にドレイン電極を備える。従って、前述のように図１には、裏面のドレイン電極は見えないが、これらは図２で説明する。   Each of the first semiconductor element 14 and the second semiconductor element 15 is a semiconductor element having a vertical structure, and includes a source electrode and a gate electrode on the surface and a drain electrode on the back surface. Therefore, as described above, the drain electrode on the back surface cannot be seen in FIG. 1, but these will be described with reference to FIG.

図２は、図１の半導体装置３０のＡ−Ａ´部の断面図である。図中、１６は外装樹脂である。図２を参照して実施形態の構造を説明すると、第１の半導体素子のドレイン端子も兼ねるリードフレーム５に第１の半導体素子１４の裏面のドレイン電極１７が接続されている。更に、第１の半導体素子１４の表面のソース電極１２に第２の半導体素子１５の裏面のドレイン電極１８が接続している。また、第２の半導体素子１５の表面にはソース電極１３がある。なお、図２は、図１のＡ−Ａ´部の断面図であるため、それぞれのゲート電極やそれぞれのゲート電極と外部端子とを接続するゲートワイヤはこの図では見えないので示されていない。また、それぞれのソース電極とそれぞれの外部端子とを接続するソースワイヤについても図の説明の簡便さから記載を省略している。   FIG. 2 is a cross-sectional view of the AA ′ portion of the semiconductor device 30 of FIG. In the figure, 16 is an exterior resin. The structure of the embodiment will be described with reference to FIG. 2. The drain electrode 17 on the back surface of the first semiconductor element 14 is connected to the lead frame 5 that also serves as the drain terminal of the first semiconductor element. Furthermore, the drain electrode 18 on the back surface of the second semiconductor element 15 is connected to the source electrode 12 on the front surface of the first semiconductor element 14. A source electrode 13 is provided on the surface of the second semiconductor element 15. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and therefore, the respective gate electrodes and the gate wires connecting the respective gate electrodes and the external terminals are not shown in FIG. . Further, the source wires connecting the respective source electrodes and the respective external terminals are also omitted from the explanation of the drawings.

図３は、本実施形態の半導体装置３０の等価回路図である。図中、１は第１の半導体素子のソース端子、２は第１の半導体素子のゲート端子、３は第２の半導体素子のゲート端子、４は第２の半導体素子のソース端子、５は第１の半導体素子のドレイン端子である。なお、等価回路図の説明としては、厳密には、ソース端子１は、第２の半導体素子のドレイン端子も兼ねる、つまり第１の半導体素子のソース端子兼第２の半導体素子のドレイン端子１と呼称すべきかもしれないが、説明が煩雑になるので、単にソース端子１と呼称する。また、こう呼称するもう一つの理由は、図２に示すように、第２の半導体素子のドレイン電極１８が第１の半導体素子のソース電極１２と直列に接続されており、図１に示すようにソース電極１２から端子を取り出しているという構造であり、説明を簡便にするためである。   FIG. 3 is an equivalent circuit diagram of the semiconductor device 30 of the present embodiment. In the figure, 1 is the source terminal of the first semiconductor element, 2 is the gate terminal of the first semiconductor element, 3 is the gate terminal of the second semiconductor element, 4 is the source terminal of the second semiconductor element, and 5 is the first terminal. 1 is a drain terminal of one semiconductor element. For the explanation of the equivalent circuit diagram, strictly speaking, the source terminal 1 also serves as the drain terminal of the second semiconductor element, that is, the source terminal of the first semiconductor element and the drain terminal 1 of the second semiconductor element. Although it may be called, since description becomes complicated, it is only called the source terminal 1. Another reason for this is that, as shown in FIG. 2, the drain electrode 18 of the second semiconductor element is connected in series with the source electrode 12 of the first semiconductor element, as shown in FIG. This is because the terminal is taken out from the source electrode 12 to simplify the description.

以下に本発明の半導体装置３０の詳しい構成と動作を説明する。本発明の半導体装置においては、第１、第２の半導体素子を同時にオン、オフさせる必要がある。このため、これら２つの半導体素子は、同一特性を有する素子であることが望ましい。接続上は、図２等から容易に理解されるように、裏面のドレイン電極１７から直接端子を取り出している側の素子、つまり、第１の半導体素子１４の方の外形、より正確には素子の表面積を大きくする必要がある。   The detailed configuration and operation of the semiconductor device 30 of the present invention will be described below. In the semiconductor device of the present invention, the first and second semiconductor elements must be turned on and off simultaneously. For this reason, it is desirable that these two semiconductor elements are elements having the same characteristics. As can be easily understood from FIG. 2 and the like, the element on the side where the terminal is directly taken out from the drain electrode 17 on the back surface, that is, the outer shape of the first semiconductor element 14, more precisely, the element It is necessary to increase the surface area.

このため、第１の半導体素子はアクティブトランジスタの領域以外の箇所を大きくし、アクティブトランジスタ領域の形状を同一にする。即ち、それぞれの半導体素子の活性層の形状、表面積をほぼ同一にする。電気的特性、特に耐圧、オン抵抗などを合わせるための具体的な手段としては、例えば、ＤＭＯＳ（Double-Diffused MOSFET）構造のＮチャンネルＭＯＳＦＥＴで半導体素子を構成する場合には、それぞれの半導体素子のチャネル長を同一にすることが好ましい。更にＮ層の不純物濃度と厚みを同じにすることなどが好ましい。つまり、高濃度拡散層の不純物濃度と厚さとをほぼ同一にすることが好ましい。   For this reason, the first semiconductor element has a portion other than the active transistor region enlarged to have the same shape of the active transistor region. That is, the shape and surface area of the active layer of each semiconductor element are made substantially the same. As specific means for adjusting the electrical characteristics, particularly withstand voltage, on-resistance, etc., for example, when a semiconductor element is constituted by an N-channel MOSFET having a DMOS (Double-Diffused MOSFET) structure, The channel length is preferably the same. Furthermore, it is preferable that the N layer has the same impurity concentration and thickness. That is, it is preferable that the impurity concentration and thickness of the high-concentration diffusion layer are substantially the same.

また、重畳した両半導体素子（下側の半導体素子表面のソース電極と上側半導体素子裏面のドレイン電極が接続）の表面電極（ソース電極、ゲート電極）をボンディングワイヤを介して外部端子（リードフレーム含む）と接続し、また第一の半導体素子の裏面電極（ドレイン電極）を外部端子（リードフレーム）に実装することで、両半導体装置の各３電極を外部に導出する。外部端子は、両半導体素子の各ゲート、ソース端子と、第一の半導体素子裏面電極のドレインと接続されたドレイン端子の５端子から構成される。   In addition, the surface electrodes (source electrode, gate electrode) of both superimposed semiconductor elements (the source electrode on the lower semiconductor element surface and the drain electrode on the back surface of the upper semiconductor element are connected) are connected to external terminals (including lead frames) via bonding wires. And the back electrode (drain electrode) of the first semiconductor element is mounted on the external terminal (lead frame), thereby leading out the three electrodes of both semiconductor devices to the outside. The external terminal is composed of five terminals, that is, the gate and source terminals of both semiconductor elements and the drain terminal connected to the drain of the first semiconductor element back electrode.

縦型構造のパワーＭＯＳＦＥＴの耐圧は、オン抵抗の約２．５乗に比例するため、例えば、耐圧２００Ｖの１cm２あたりのオン抵抗は、約０．００７Ω・cm２、耐圧４００Ｖでは、オン抵抗は、約０．０３５Ω・cm２と約５倍になる。耐圧４００Ｖの製品を一つ作るよりも耐圧２００Ｖの素子を２つ直列接続した製品にすることで、低オン抵抗化が図れ、かつチップを重畳することで形状的に小型化が図れる。   Since the withstand voltage of the power MOSFET having a vertical structure is proportional to about 2.5 of the on-resistance, for example, the on-resistance per 1 cm 2 of the withstand voltage of 200 V is about 0.007 Ω · cm 2, and the on-resistance at the withstand voltage of 400 V is About 0.035Ω · cm2 and about 5 times. Rather than making a single product with a withstand voltage of 400V, by making a product in which two elements with a withstand voltage of 200V are connected in series, the on-resistance can be reduced, and the size can be reduced by overlapping the chips.

以上、半導体素子を複数個、具体的には２個重ねる実施例を図面を用いて説明したが、本発明はこれにとらわれず、３個以上重ね合わせることもできる。即ち、第２の半導体素子の上に第３の半導体素子を上記の実施例同様に重ね合わせれば良い。念のため、概要を述べると、第２の半導体素子のソース電極と第３の半導体素子のドレイン電極とを接続し、第３の半導体素子のソース電極、ゲート電極から端子を取り出すことである。勿論、第２の半導体素子のソース、ゲートの各電極、第１の半導体素子のソース、ゲート、ドレインの各電極から端子を取り出すのはいうまでもないことである。   As described above, the embodiment in which a plurality of semiconductor elements, specifically two, are stacked has been described with reference to the drawings. However, the present invention is not limited to this, and three or more semiconductor elements can be stacked. That is, the third semiconductor element may be overlaid on the second semiconductor element as in the above embodiment. As a precaution, the outline is to connect the source electrode of the second semiconductor element and the drain electrode of the third semiconductor element, and to take out the terminal from the source electrode and gate electrode of the third semiconductor element. Of course, it goes without saying that the terminals are taken out from the source and gate electrodes of the second semiconductor element and the source, gate and drain electrodes of the first semiconductor element.

３個の半導体素子を重ね合わせる場合も、２個の場合と同様である。即ち、第３の半導体素子の表面積を最も小さくし、第２の半導体素子、第１の半導体素子と順次、表面積を大きくすることが好ましい。また、それぞれの素子のアクティブトランジスタ領域の形状を同一にする。即ち、活性層の形状、表面積をほぼ同一にする。更には、２個の場合と同様に、チャネル長、高濃度拡散層の厚さ及び不純物濃度をほぼ同一にすることが好ましい。これらにより耐圧、オン抵抗などの電気的特性を合わせることが好ましい。   The case where three semiconductor elements are stacked is the same as the case where two semiconductor elements are stacked. That is, it is preferable to minimize the surface area of the third semiconductor element and sequentially increase the surface area of the second semiconductor element and the first semiconductor element. In addition, the shape of the active transistor region of each element is made the same. That is, the shape and surface area of the active layer are made substantially the same. Furthermore, it is preferable that the channel length, the thickness of the high-concentration diffusion layer, and the impurity concentration are substantially the same as in the case of two. Thus, it is preferable to combine electrical characteristics such as withstand voltage and on-resistance.

なお、本発明の半導体装置を動作させるに際しては、それぞれの素子のＯＮ、ＯＦＦの時間を一致させる駆動回路が必要であるが、これは公知のタイミング制御回路などを用いて構成できるので、本明細書には図示及びこの回路の詳細な説明は割愛している。   Note that when operating the semiconductor device of the present invention, a drive circuit that matches the ON and OFF times of the respective elements is necessary. This can be configured using a known timing control circuit or the like. In the book, illustration and detailed description of this circuit are omitted.

（第２の実施形態）
次に本発明の第２の実施形態を図４、図５を用いて説明する。なお、第２の実施形態では、各半導体素子に全て同一の形状のものを用いて構成したことに特徴がある。他の構成などは第１の実施形態と同様ある。従って、第１の実施形態と異なる点を中心に説明する。 (Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. The second embodiment is characterized in that each semiconductor element is configured using the same shape. Other configurations are the same as those of the first embodiment. Therefore, the description will focus on the differences from the first embodiment.

図４は、本発明の第２の実施形態の半導体装置４０の上面図である。なお、図４は、厳密にいうと実線で示した外装樹脂１６を外して上から見た透過平面図ともいうべきものである。図中、１は第１の半導体素子２４のソース端子であり、そのソースワイヤ７を介して、第１の半導体素子２４のソース電極の一部であるソースボンディングパット２２に接続されている。２は、第１の半導体素子２４のゲート端子であり、そのゲートワイヤ６を介して第１の半導体素子２４のゲート電極の一部であるゲートボンディングパット２０に接続されている。３は第２の半導体素子２５のゲート端子であり、そのゲートワイヤ８を介して、第２の半導体素子のゲート電極の一部であるゲートボンディングパット２１に接続されている。４は、第２の半導体素子２５のソース端子であり、そのソースワイヤ９を介して第２の半導体素子のソース電極の一部であるソースボンディングパット２３に接続されている。   FIG. 4 is a top view of the semiconductor device 40 according to the second embodiment of the present invention. Strictly speaking, FIG. 4 should also be referred to as a transmission plan view seen from above with the exterior resin 16 shown by a solid line removed. In the figure, reference numeral 1 denotes a source terminal of the first semiconductor element 24, which is connected to a source bonding pad 22 that is a part of the source electrode of the first semiconductor element 24 through the source wire 7. Reference numeral 2 denotes a gate terminal of the first semiconductor element 24, and is connected to the gate bonding pad 20 which is a part of the gate electrode of the first semiconductor element 24 through the gate wire 6. Reference numeral 3 denotes a gate terminal of the second semiconductor element 25, and is connected to a gate bonding pad 21, which is a part of the gate electrode of the second semiconductor element, through the gate wire 8. Reference numeral 4 denotes a source terminal of the second semiconductor element 25, which is connected via the source wire 9 to a source bonding pad 23 that is a part of the source electrode of the second semiconductor element.

さらに、５は第１の半導体素子のドレイン端子であり、リードフレームも兼ねている。また、これは、図示しない第１の半導体素子のドレイン電極と接続している。この詳細は図５に示す。なお、第１の半導体素子２４は、チップ状であり、それぞれ、第１の半導体素子チップ２４又は第１の半導体チップ２４とも換言できる。第２半導体素子についても同様である。また、第１の半導体素子２４、第２の半導体素子２５は共に縦型構造の半導体素子であり、表面にソース電極とゲート電極を備え、裏面にドレイン電極を備える。従って、前述のように図４には、裏面のドレイン電極は見えないが、これらは図５で説明する。   Further, 5 is a drain terminal of the first semiconductor element, which also serves as a lead frame. This is also connected to the drain electrode of the first semiconductor element (not shown). The details are shown in FIG. The first semiconductor element 24 has a chip shape, and can also be referred to as the first semiconductor element chip 24 or the first semiconductor chip 24, respectively. The same applies to the second semiconductor element. Each of the first semiconductor element 24 and the second semiconductor element 25 is a semiconductor element having a vertical structure, and includes a source electrode and a gate electrode on the surface and a drain electrode on the back surface. Therefore, as described above, the drain electrode on the back surface cannot be seen in FIG. 4, but these will be described with reference to FIG.

図５は、図４の半導体装置４０のＢ−Ｂ´部の断面図である。第１の実施形態と大きく異なるのは、第１、第２の半導体チップの形状が同じであることと、このため、第２の半導体素子２５の位置をずらして接続していることである。即ち、第２の実施形態では、同一構造の半導体素子を積みかねているので、当然に活性層の形状、表面積や、チャネル長、Ｎ層の不純物濃度などは、ほぼ同一であり、その耐圧、オン抵抗などの電気的特性もほぼ同一となる。第１の実施形態と組み立て上の違いは、図４の方が良くわかるが、ゲートボンディングパット２０をさけて、第２の半導体素子が第１の半導体素子と水平方向にずらして組み立てされていることである。これにより、第１の半導体素子のゲート電極が第２の半導体素子２５に重なり合わない構成としている。これは、ゲートワイヤ６の接続などのためである。   FIG. 5 is a cross-sectional view of the BB ′ portion of the semiconductor device 40 of FIG. The major difference from the first embodiment is that the shapes of the first and second semiconductor chips are the same, and for this reason, the second semiconductor element 25 is shifted in position and connected. That is, in the second embodiment, since semiconductor elements having the same structure are stacked, the shape of the active layer, the surface area, the channel length, the impurity concentration of the N layer, and the like are naturally the same. Electrical characteristics such as resistance are almost the same. The difference in assembly from the first embodiment can be seen more clearly in FIG. 4, but the second semiconductor element is assembled with the first semiconductor element shifted in the horizontal direction with the gate bonding pad 20 being avoided. That is. As a result, the gate electrode of the first semiconductor element does not overlap the second semiconductor element 25. This is due to the connection of the gate wire 6 and the like.

図５中、１６は外装樹脂である。念のため、図５を参照して第２の実施形態の構造を説明すると、第１の半導体素子のドレイン端子も兼ねるリードフレーム５に第１の半導体素子２４の裏面のドレイン電極２７が接続されている。更に、第１の半導体素子２４の表面のソース電極２２に第２の半導体素子２５の裏面のドレイン電極２８が接続している。また、第２の半導体素子２５の表面にはソース電極２３があるという構成になっている。   In FIG. 5, 16 is an exterior resin. As a precaution, the structure of the second embodiment will be described with reference to FIG. 5. The drain electrode 27 on the back surface of the first semiconductor element 24 is connected to the lead frame 5 that also serves as the drain terminal of the first semiconductor element. ing. Further, the drain electrode 28 on the back surface of the second semiconductor element 25 is connected to the source electrode 22 on the front surface of the first semiconductor element 24. Further, the source electrode 23 is provided on the surface of the second semiconductor element 25.

なお、第２の実施形態の等価回路図も第１の実施形態と同じである。即ち図３と同じであるので、この説明は割愛する。また、タイミング制御回路の必要性などは第１の実施形態同様であるので、その記載は割愛する。さらに半導体素子を３つ以上重ねて組み立ててもよいことも第１の実施形態同様である。   The equivalent circuit diagram of the second embodiment is the same as that of the first embodiment. That is, since it is the same as FIG. 3, this description is omitted. Further, since the necessity of the timing control circuit is the same as that of the first embodiment, the description thereof is omitted. Further, as in the first embodiment, three or more semiconductor elements may be stacked and assembled.

以上のように本発明によれば、小型、低消費電力のパワーＭＯＳＦＥＴが構成でき、本発明の実用上の意義は高い。   As described above, according to the present invention, a small, low power consumption power MOSFET can be configured, and the practical significance of the present invention is high.

なお、本発明は以上の開示内容に限定されず、その技術思想の範囲内で自由に変形など行えることは言うまでもない。   Needless to say, the present invention is not limited to the above disclosure, and can be freely modified within the scope of the technical idea.

本発明の第１の実施形態の上面図である。It is a top view of the 1st Embodiment of this invention. 図１のＡ−Ａ´部の断面図である。It is sectional drawing of the AA 'part of FIG. 本発明の第１の実施形態の等価回路図である。FIG. 3 is an equivalent circuit diagram of the first embodiment of the present invention. 本発明の第２の実施形態の上面図である。It is a top view of the 2nd Embodiment of this invention. 図４のＢ−Ｂ´部の断面図である。It is sectional drawing of the BB 'part of FIG. 従来技術（特許文献１）の等価回路図である。It is an equivalent circuit schematic of a prior art (patent document 1). 従来技術（特許文献１）の一実施形態の上面図である。It is a top view of one embodiment of prior art (patent document 1). 従来技術（特許文献１）の他の実施形態の断面構造図である。It is a cross-sectional structure figure of other embodiment of a prior art (patent document 1).

符号の説明Explanation of symbols

１ 第１の半導体素子のソース端子
２ 第１の半導体素子のゲート端子
３ 第２の半導体素子のゲート端子
４ 第２の半導体素子のソース端子
５ 第１の半導体素子のドレイン端子（リードフレーム）
６ 第１の半導体素子のゲートワイヤ
７ 第１の半導体素子のソースワイヤ
８ 第２の半導体素子のゲートワイヤ
９ 第１の半導体素子のソースワイヤ
１０、２０ 第１の半導体素子のゲートボンディングパッド
１１、２１ 第２の半導体素子のゲートボンディングパッド
１２、２２ 第１の半導体素子のソースボンディングパッド
１３、２３ 第２の半導体素子のソースボンディングパッド
１４、２４ 第１の半導体素子
１５、２５ 第２の半導体素子
１６ 樹脂層
１７、２７ 第１の半導体素子のドレイン電極
１８、２８ 第２の半導体素子のドレイン電極
３０、４０ 半導体装置

DESCRIPTION OF SYMBOLS 1 Source terminal of 1st semiconductor element 2 Gate terminal of 1st semiconductor element 3 Gate terminal of 2nd semiconductor element 4 Source terminal of 2nd semiconductor element 5 Drain terminal (lead frame) of 1st semiconductor element
6 Gate wire of first semiconductor element 7 Source wire of first semiconductor element 8 Gate wire of second semiconductor element 9 Source wire 10, 20 of first semiconductor element Gate bonding pad 11 of first semiconductor element, 21 Gate bonding pads 12 and 22 of the second semiconductor element Source bonding pads 13 and 23 of the first semiconductor element Source bonding pads 14 and 24 of the second semiconductor element First semiconductor elements 15 and 25 Second semiconductor element 16 Resin layers 17 and 27 Drain electrodes 18 and 28 of the first semiconductor element Drain electrodes 30 and 40 of the second semiconductor element Semiconductor device

Claims (6)

表面電極としてソース電極とゲート電極とを備え、裏面電極としてドレイン電極を備える縦型構造の半導体素子を複数個用いる半導体装置であって、
第１の半導体素子のソース電極と第２の半導体素子のドレイン電極とを重ね合わせて接続し、前記第１の半導体素子のゲート電極が、前記第２の半導体素子に重なり合わないことを特徴とする半導体装置。
A semiconductor device using a plurality of semiconductor elements having a vertical structure including a source electrode and a gate electrode as a front electrode and a drain electrode as a back electrode,
A source electrode of the first semiconductor element and a drain electrode of the second semiconductor element are overlapped and connected, and the gate electrode of the first semiconductor element does not overlap the second semiconductor element. Semiconductor device.
請求項１に記載の半導体装置であって、更に、前記それぞれの半導体素子の耐圧、オン抵抗は、ほぼ同一であることを特徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein each of the semiconductor elements has substantially the same breakdown voltage and on-resistance.
請求項１又は請求項２に記載の半導体装置であって、更に、前記第１の半導体素子の表面積は前記第２の半導体素子の表面積よりも大きいことを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein a surface area of the first semiconductor element is larger than a surface area of the second semiconductor element. 4.
請求項１又は請求項２に記載の半導体装置であって、更に、それぞれの半導体素子の形状は同一であり、前記第１の半導体素子と前記第２の半導体素子とがずらして配置されていることを特徴とする半導体装置。
3. The semiconductor device according to claim 1, wherein the shape of each semiconductor element is the same, and the first semiconductor element and the second semiconductor element are arranged so as to be shifted. A semiconductor device.
請求項１乃至請求項４のいずれかに記載の半導体装置であって、更に、それぞれの半導体素子のチャネル長がほぼ等しく、それぞれの半導体素子の高濃度拡散層の厚さ及び不純物濃度もほぼ等しいことを特徴とする半導体装置。

5. The semiconductor device according to claim 1, wherein the channel length of each semiconductor element is substantially equal, and the thickness and impurity concentration of the high concentration diffusion layer of each semiconductor element are also substantially equal. A semiconductor device.

請求項１乃至請求項５のいずれかに記載の半導体装置であって、前記第１の半導体素子の裏面電極と接続された第１の外部端子と、前記第１の半導体素子のソース電極と接続された第２の外部端子と、前記第１の半導体素子のゲート電極と接続された第３の外部端子と、前記第２の半導体素子のソース電極とボンディングワイヤを介して接続された第４の外部端子と、前記第２の半導体素子のゲート電極と接続された第５の外部端子と、前記第１及び第２の半導体素子を被覆する樹脂と、を更に備えることを特徴とする半導体装置。
6. The semiconductor device according to claim 1, wherein the first external terminal connected to the back electrode of the first semiconductor element and the source electrode of the first semiconductor element are connected. A second external terminal connected to the gate electrode of the first semiconductor element, a third external terminal connected to the gate electrode of the first semiconductor element, and a fourth electrode connected to the source electrode of the second semiconductor element via a bonding wire. A semiconductor device, further comprising: an external terminal; a fifth external terminal connected to the gate electrode of the second semiconductor element; and a resin covering the first and second semiconductor elements.
JP2007086503A 2007-03-29 2007-03-29 Semiconductor device Pending JP2008244388A (en)

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