JP2008243925A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin semiconductor device improved in accuracy in alignment between a built-in semiconductor structure and a side circuit, and a manufacturing method for the semiconductor device. <P>SOLUTION: The semiconductor device P1 has the semiconductor structure 4 built into at least an insulating layer 2 and rewiring layers 11 provided on the insulating layers 2 on the upside and side of the semiconductor structure 4. A circuit board 3 is built into the insulator layer 2 on the side of the semiconductor structure 4 while the circuit board 3 has a conductor layer 9a on a surface of the side provided with at least the rewiring layer 11 formed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Currently, a semiconductor device called a wafer level CSP (wafer-level chip size package) is used as a semiconductor device mounted on an electronic device, and corresponds to the recent reduction in size and size of devices.

  In the wafer level CSP, a passivation film (intermediate insulating film) is provided on the upper surface of a bare chip on which a plurality of connection pads for external connection are formed, and an opening is formed in a corresponding portion of each connection pad of the passivation film. A rewiring connected to each connection pad is formed through the portion, a columnar external connection electrode is formed on the other end side of each rewiring, and a sealing material is filled between each external connection electrode Is.

  The wafer level CSP can be bonded to a circuit board having connection terminals by forming a solder ball on each columnar external connection electrode in a face-down manner, and has a mounting area substantially the same size as a bare chip. Therefore, it is possible to greatly reduce the size of the electronic device as compared with the conventional face-up method using wire bonding or the like.

  In order to increase the productivity of the wafer level CSP, a passivation film, a rewiring, an electrode for external connection, and a sealing material are formed on a semiconductor substrate in a wafer state, and the exposed external portion is not covered with the sealing material. A method has been reported in which a solder ball is provided on the upper surface of a connection electrode and then cut by a dicing line (see, for example, Patent Document 1).

  However, in the conventional semiconductor device, when integration is progressed and the number of external connection electrodes is increased, the size and pitch of the external connection electrodes are extremely reduced, and the degree of difficulty in alignment with the circuit board is increased. In addition to problems such as a decrease in strength and short circuit between electrodes, external connection electrodes due to stress generated due to the difference in linear expansion coefficient between a semiconductor substrate, usually a silicon substrate, and a circuit substrate, usually an organic substrate In some cases, fatal problems such as destruction of the product may occur.

  Thus, a method of connecting a wafer level CSP to a circuit board without using wire bonding while using a face-up method has also been reported (see, for example, Patent Document 2).

  The semiconductor device manufactured by using the method of connecting the wafer level CSP to the circuit board without using wire bonding while using the face-up method is, for example, a semiconductor device P9 shown in FIG. The semiconductor structure 4 is mounted on the semiconductor structure 4, and a buried layer is formed together with the insulating layer 102 so that the circuit board 103 is provided on the side of the semiconductor structure 4. Then, rewiring is performed on the rewiring pad 113 at a position corresponding to the mother board. This is provided with a rewiring layer 111 that is configured to perform the following.

  Here, the semiconductor structure 4 has a plurality of external connection electrodes 5 provided on the upper surface of the silicon substrate 7 and a sealing material 6 formed on the side surfaces of the external connection electrodes 5. Hereinafter, the semiconductor structure used in this specification basically indicates a semiconductor structure having the structure.

  In addition, a method has been reported in which a circuit board is provided inside an insulating layer on the side of a semiconductor structure to cope with high density, high speed operation, and the like that are required for recent semiconductor devices (for example, see Patent Document 3). ).

  However, a semiconductor device manufactured by using a method of connecting the wafer level CSP to a circuit board without using wire bonding while using the face-up method is a layer serving as a support for placing (arranging) the semiconductor structure. However, in general, a thickness with a certain degree of rigidity is required to obtain transportability during the manufacturing process, and there are cases in which it is not possible to cope with the thinning that has recently been demanded.

  Here, a conventional manufacturing method of the semiconductor device P9 shown in FIG. 6 will be described with reference to FIGS.

  First, as shown in FIG. 7A, the semiconductor structure 4 is mounted on the support 115 via the adhesive 8.

  Next, as shown in FIG. 7B, the pin guide 116 is provided with a support 115 on which the semiconductor structure 4 is mounted, an insulating layer 102a in which a pin guide insertion hole is previously drilled, and a pin guide in advance. The circuit board 103 with the insertion holes formed is laid up and stacked to obtain the structure P10 shown in FIG. 7C.

  Next, as shown in FIG. 8D, the insulating layer 102b and the conductor layer 109a are laminated on both surfaces of the structure P10, and then through a circuit formation process and a plating process, as shown in FIG. 8E. As described above, rewiring is performed on the external connection electrode 5 of the semiconductor structure 4 to obtain the structure P11 including the rewiring layer 111. Next, as shown in FIG. 8F, through the solder resist formation step, the semiconductor device P12 including the rewiring pad 113 and the solder resist 114 (that is, the semiconductor device P9 shown in FIG. 6) is obtained.

However, in the above-described conventional manufacturing method, the pin guide 116 is used as an alignment method when stacking the built-in semiconductor structure 4 and the circuit on the side circuit board 103, so the accuracy is several tens of μm. There was a gap and it was hard to say that it was good.
JP 2001-168128 A JP 2004-221417 A JP 2005-159199 A

  The present invention has been made in view of the above problems and actual circumstances, and in a semiconductor device having a structure in which a semiconductor structure is built in an insulating layer, the semiconductor device is thinned, and the built-in semiconductor structure and a side circuit are provided. It is an object of the present invention to provide a semiconductor device having improved alignment accuracy, that is, high circuit position accuracy and a method for manufacturing the same.

  That is, the present invention according to claim 1 is a semiconductor device having at least a semiconductor structure incorporated in an insulating layer and a redistribution layer provided on an insulating layer above and on the side of the semiconductor structure. The circuit board is built in the insulating layer on the side of the semiconductor structure, and the circuit board includes a conductor layer on at least the surface on which the rewiring layer is provided. The semiconductor device solves the above problems.

  According to this semiconductor device, the circuit position accuracy is high and the thickness can be further reduced.

  Further, in the present invention according to claim 2, at least a part of the external connection electrode of the semiconductor structure and the conductor layer of the circuit board built in the insulating layer is connected via the rewiring layer. It is characterized by being.

  As a result, the built-in semiconductor structure and the side circuit are accurately connected by the shortest route in the inner layer, and a thin semiconductor device in which optimum circuit wiring is formed can be obtained.

  According to a third aspect of the present invention, there is provided a semiconductor device having at least a semiconductor structure incorporated in an insulating layer and a redistribution layer provided on the insulating layer above and on the side of the semiconductor structure. A manufacturing method, comprising a metal plate provided with a convex portion, a first insulating layer previously provided with a hole corresponding to the convex portion, and a hole corresponding to the convex portion previously provided. A step of laminating a circuit board having a conductor layer on the upper surface, a second insulating layer, and a conductor layer; a step of removing the metal plate after the lamination step to form a recess for embedding a semiconductor structure; Mounting the semiconductor structure in the formed recess, embedding the mounted semiconductor structure with a resin, and rewiring the embedded semiconductor structure. Manufacture of semiconductor devices It is obtained by solving the above problems by law.

  As a result, a semiconductor device having a built-in semiconductor structure can be obtained by a relatively simple process without increasing the thickness of the semiconductor device.

  The present invention according to claim 4 is characterized in that, in the mounting step of the semiconductor structure, at least a part of the conductor layer of the circuit board is used as a mounting positioning alignment mark of the semiconductor structure.

  Thereby, a thin semiconductor device with improved alignment accuracy between the built-in semiconductor structure and the side circuit can be obtained.

  The present invention according to claim 5 is characterized in that the metal plate removal is performed by etching.

  Thereby, since the recessed part which has a flat inner bottom face is obtained by a comparatively simple process, without using cutting processes, such as a counterbore process, the mounting of a more stable semiconductor structure is attained.

  According to the present invention, in a semiconductor device having a structure in which a semiconductor structure is built in an insulating layer, the semiconductor device is thinned, and the alignment accuracy between the built-in semiconductor structure and a side circuit is improved, that is, circuit position accuracy. Semiconductor device and a method for manufacturing the same can be provided.

  An embodiment of a semiconductor device of the present invention will be described with reference to FIG.

  In FIG. 1A, P1 is a semiconductor device, which is built in the insulating layer 2 via the adhesive layer 8 and embedded in the insulating layer 2 and in the insulating layer 2 on the side of the semiconductor structure 4. The circuit board 3 and the external connection electrode 5 of the semiconductor structure 4 are connected via the rewiring layer 11 and connected to the outside of the semiconductor structure 4 and above the insulating layer 2 via the buildup material 12. The circuit board 3 includes a conductor layer 9a on the surface on which the rewiring layer 11 is provided. The rewiring pad 13 and the solder resist 14 are included.

  Incidentally, when the semiconductor device P1 observes the cross section of the semiconductor device P1, the upper opening of the recess is slightly larger than the semiconductor structure 4 and a circuit is formed inside the side of the recess as will be described later. The semiconductor structure 4 is placed on the inner bottom portion of the concave structure in which the substrate 3 is embedded and the inner side surface and the inner bottom surface of the concave portion are covered with the resin, and then the concave portion is formed with the resin layer. When laminated like a lid, the resin is buried in a small gap between the semiconductor structure 4 and the opening and is in close contact with the resin layer on the inner side surface of the recess, but originally formed as the side of the recess. The resin layer thus cured is cured before the lamination, and a boundary line L exists between the resin layer and the resin embedded after the placement.

  Here, the semiconductor structure 4 includes a silicon substrate (semiconductor substrate) 7 as in the prior art, and the silicon substrate 7 is bonded to the insulating layer 2 via the adhesive layer 8, and a predetermined surface is formed on the upper surface of the silicon substrate 7. A functional integrated circuit is provided, and a plurality of connection pads made of an aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit, and the upper surface of the silicon substrate 7 excluding the central portion of the connection pad is oxidized. An insulating film made of silicon or the like is provided, and a central portion of the connection pad is exposed through a first opening provided in the insulating film, and an upper surface of the insulating film is made of an epoxy resin, a polyimide resin, or the like. A protective film (insulating film) is provided, and a protective film in a portion corresponding to the first opening of the insulating film is provided with a second opening, and the first opening and the second opening are provided. Exposed connection pads A base metal layer made of copper or the like is provided from a top surface of the switch to a predetermined portion of the top surface of the protective film, and a rewiring made of copper is provided on the entire top surface of the base metal layer, and a connection pad portion of the rewiring A columnar external connection electrode 5 made of copper is provided on the upper surface, and a sealing material (insulating film) 6 made of epoxy resin, polyimide resin or the like is provided on the upper surface of the protective film including the rewiring. Is provided so as to be flush with the upper surface of the external connection electrode 5.

  As described above, the semiconductor structure 4 called the wafer level CSP includes the silicon substrate 7, the external connection electrode 5, and the sealing material 6.

  Since the semiconductor device P1 has a structure in which the semiconductor structure 4 is directly mounted in the insulating layer 2 via the adhesive 8, it is not necessary to provide another layer as a support for the semiconductor structure 4. Thus, a thinned semiconductor device is obtained.

  Further, since the circuit board 3 is built in the insulating layer 2 on the side of the semiconductor structure 4, the semiconductor structure is formed using the conductor layer 9a on the circuit board 3 as a mounting positioning alignment mark. Since it can be used when the body 4 is mounted, a semiconductor device in which the circuit of the semiconductor structure 4 (external connection electrode 5) and the side circuit of the semiconductor structure 4 are accurately aligned is obtained. be able to.

  Further, as in the semiconductor device P13 shown in FIG. 1B, the semiconductor of the circuit wiring that connects the external connection electrode 5 of the semiconductor structure 4 and the circuit on the side circuit board 3 by the rewiring layer 11. In the case of an apparatus, the circuit (external connection electrode 5) of the semiconductor structure 4 and the side circuit are accurately connected by the shortest route in the inner layer, and the high-frequency circuit and high-speed transmission required in the market these days. A thin semiconductor device having a structure more suitable for a circuit is obtained.

  Next, an embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 2A, a metal plate 1 is prepared.

  The metal plate 1 is not particularly limited as long as it is a metal that can be etched, but is preferably copper or an alloy similar to copper, which is frequently used in general circuit formation processes.

  Next, as shown in FIG.2 (b), the said metal plate 1 is made into the shape provided with the convex part 1a by the metal removal means.

  The metal removing means may be any method as long as it can be formed into a desired shape, and examples thereof include machining by cutting or etching with a chemical solution.

  Next, as shown in FIG. 2 (c), the metal plate 1 having the shape including the convex portion 1a and a hole slightly larger than the size of the concave portion in which the semiconductor structure is embedded in advance, that is, the formed The first insulating layer 2a having a hole slightly larger than the size of the convex portion 1a of the metal plate, the circuit board 3 provided with the conductor layer 9a, the second insulating layer 2b, and the conductor layer 9b are overlapped, A lamination press is performed using a vacuum lamination press or the like to obtain a structure P2 in the state shown in FIG. 3D in which the circuit board 3 is built in the insulating layer 2.

  In addition, the insulating layer 2a does not necessarily need to be a single sheet. If one sheet does not have an appropriate thickness in consideration of the height of the convex portion 1a, a plurality of insulating layers 2a are stacked so that the insulating layer has an appropriate thickness. It is desirable.

  Next, as shown in FIG. 3E, the metal plate 1 of the structure P2 is removed to obtain the structure P3 in which the semiconductor structure embedding recess Q is formed in the insulating layer 2.

  Note that the metal plate 1 removing means here forms the concave portion Q to be a place where the semiconductor structure 4 is to be placed later, so that there is a possibility that cutting traces and cutting chips remain on the inner bottom portion of the concave portion Q. It is desirable to use etching rather than some cutting.

  Next, the semiconductor structure 4 is mounted in the recess Q formed by removing the metal plate 1 to obtain a structure P4 shown in FIG.

  In addition, the semiconductor structure 4 includes a plurality of external connection electrodes 5 on the upper surface of the silicon substrate 7 as described above, and a sealing material 6 between the external connection electrodes 5.

  Further, it is desirable to use the adhesive 8 when mounting the components.

  Further, an adhesive sheet such as DAF (Die Attach Film) may be used as the adhesive 8.

  Next, as shown in FIG. 4G, the insulating layer 2c and the copper foil 9c are laid up on the structure P4 on which the semiconductor structure 4 is mounted, and a lamination press is performed using a vacuum lamination press machine or the like. As shown in FIG. 4H, the structure P5 in which the semiconductor structure 4 is built in the insulating layer 2 is obtained.

  Next, each step for forming the interlayer connection via hole 10 is performed in the same manner as in a normal substrate to obtain a structure P6 shown in FIG.

  Next, as shown in FIG. 5 (m), each step of plating and circuit formation is performed in the same manner as a normal substrate to obtain a structure P7 including the rewiring layer 11.

  Next, as shown in FIG. 5 (n), the rewiring pad 13 and the solder resist are processed through the respective steps of build-up material 12 lamination, plating, circuit formation, and solder resist formation as in the case of a normal substrate. A semiconductor device P8 having 14 is obtained.

  In the description of the present invention, the above embodiment has been described by way of example. However, the configuration of the present invention is not limited thereto, and is not limited by these examples, and is within the scope of the present invention. Various changes can be made.

  The following four features can be cited as features of the present invention described in the above embodiment.

  First, the first feature of the present invention is that a recess Q for embedding a semiconductor structure is formed in the insulating layer 2 and the semiconductor structure 4 is mounted and embedded on the inner bottom surface of the recess Q.

  As a result, the semiconductor structure 4 is built in the insulating layer 2, and it is not necessary to provide another layer as a support for the semiconductor structure 4, so that the entire semiconductor device is thinned.

  The second feature of the present invention is that the insulating substrate 2a, the circuit board 3 provided with the conductor layer 9a, and the insulating layer 2b are stacked to support the side of the semiconductor structure 4 (second insulating layer 2b). The other circuit board 3 is integrated.

  As a result, the circuit board 3 is built inside the side of the insulating layer 2 on which the semiconductor structure 4 is mounted, and the conductor layer 9a on the circuit board 3 can be used as a mounting positioning alignment mark. Therefore, the circuit of the semiconductor structure 4 (external connection electrode 5) and the side circuit of the semiconductor structure 4 can be aligned with high accuracy.

  Specifically, with regard to mounting alignment accuracy, since the conventional pin guide alignment has been performed by inserting pins into holes formed in the board, the alignment accuracy is based on the alignment marks on the circuit of the support. “Puncture accuracy” for drilling for pin guide insertion, “Pole accuracy between holes” by inserting pins into the holes and aligning with the side circuit board, “Mounting accuracy for mounting components with the support circuit as an alignment mark” The margin which added the three precisions of "was required.

  On the other hand, in the method of the present invention, only “mounting accuracy” for mounting the side circuit board 3 as the alignment mark is required, so that the accuracy is very high compared to the alignment by the conventional pin guide. Is preserved.

  In addition, by integrating the support portion (second insulating layer 2b) and the side circuit board 3, a circuit is also provided on the side of the built-in semiconductor device 4, so that it supports high-density wiring. In addition, a thinned semiconductor device can be obtained.

  Further, when the circuit of the semiconductor structure 4 (external connection electrode 5) and the side circuit are connected by the rewiring layer 11, the circuit of the semiconductor structure 4 (external connection electrode 5) and the side circuit are connected. It is possible to connect with the above circuit with the shortest route in the inner layer with high accuracy, and a thin semiconductor device having a structure more suitable for the high-frequency circuit and the high-speed transmission circuit required in the market these days can be obtained.

  The third feature of the present invention is that the concave portion Q for embedding the semiconductor structure is laminated on the insulating layer 2 with the metal plate 1 having the convex portion 1a corresponding to the concave portion Q, and then the metal plate 1 is removed. It is to be formed by.

  Thereby, the semiconductor device provided with the recess Q can be obtained by a relatively simple process.

  Further, since the support as a separate layer is not required when forming the recess Q, the thickness of the semiconductor device can be reduced.

  Further, since the concave portion Q is formed at the time of the lamination press, the process can be shortened as compared with the step of forming the concave portion using machining such as cutting after the substrate pressing.

  The fourth feature of the present invention resides in that etching is used as a means for removing the metal plate 1.

  As a result, the inner bottom surface of the recess Q, which is the mounting location of the semiconductor structure 4, has a flat shape, so that more stable mounting can be performed and a semiconductor device with higher circuit accuracy can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 3 is a schematic cross-sectional process explanatory diagram following FIG. 2. FIG. 4 is a schematic cross-sectional process explanatory diagram following FIG. 3. FIG. 5 is a schematic cross-sectional process explanatory diagram subsequent to FIG. 4. FIG. 10 is a schematic cross-sectional explanatory view showing an example of a conventional semiconductor device. FIG. 10 is a schematic cross-sectional process explanatory diagram illustrating an example of a conventional method for manufacturing a semiconductor device. FIG. 8 is a schematic cross-sectional process explanatory diagram following FIG. 7.

Explanation of symbols

1: Metal plate 1a: Convex portions 2, 2a, 2b, 2c, 102, 102a, 102b: Insulating layer 3, 103: Circuit board 4: Semiconductor structure 5: Electrode for external connection 6: Sealing material 7: Silicon substrate 8: Adhesive layers 9a, 9b, 9c, 109a: Conductor layer 10: Interlayer connection via hole 11, 111: Rewiring layer 12: Buildup material 13: Rewiring pad 14, 114: Solder resist 115: Support 116 : Pin guides P2, P3, P4, P5, P6, P7, P10, P11: Structures P1, P8, P9, P12, P13: Semiconductor device Q: Recess

Claims (5)

  A semiconductor device having at least a semiconductor structure incorporated in an insulating layer and a redistribution layer provided on an insulating layer above and on the side of the semiconductor structure, A semiconductor device, wherein a circuit board is incorporated in an insulating layer, and the circuit board includes a conductor layer on at least a surface on which a rewiring layer is provided.   The external connection electrode of the semiconductor structure and at least a part of a conductor layer of a circuit board built in the insulating layer are connected via the rewiring layer. Semiconductor device.   A method of manufacturing a semiconductor device comprising at least a semiconductor structure incorporated in an insulating layer, and a rewiring layer provided on an insulating layer above and on the side of the semiconductor structure, the method comprising a convex A metal plate, a first insulating layer previously provided with a hole corresponding to the convex portion, a circuit board provided with a conductor layer on at least an upper surface previously provided with a hole corresponding to the convex portion, A step of laminating the second insulating layer and the conductor layer; a step of removing the metal plate after the laminating step to form a recess for embedding the semiconductor construct; and the semiconductor construct in the formed recess A method for manufacturing a semiconductor device, comprising: a step of mounting; a step of embedding the mounted semiconductor structure with a resin; and a step of performing rewiring on the embedded semiconductor structure.   4. The method of manufacturing a semiconductor device according to claim 3, wherein in the mounting step of the semiconductor structure, at least a part of the conductor layer of the circuit board is used as a mounting positioning alignment mark of the semiconductor structure.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the metal plate is removed by etching.