JP2008236653A - Packet transfer order security method, packet transfer order security apparatus, and packet transfer order security program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein following packet processing is not performed conventionally until first arriving packet processing is completed, transfer efficiency becomes low and when packets having the same input information are inputted while being concentrated, the merit of performing parallel processing is impaired. <P>SOLUTION: At input/output terminals of packet processing elements 102-1 to 102-N performing parallel processing, counters 101, 103 independent for each predetermined packet condition are installed in places where the counters can be referenced and updated. A packet to be processed is fetched by a packet processing element for starting processing.Sequence number imparting sections 102-1 to 102-N-1 impart sequence numbers (input side counter values) to input packets. Sequence number comparing sections 102-1 to 102-N-2 compare sequence numbers imparted to processed packets with an output side counter value and outputs the packet only when its sequence number is matched to the output side counter value. Thus, the transfer order of packets is secured. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a packet transfer order guarantee method, a packet transfer order guarantee apparatus, and a packet transfer order guarantee program, and more particularly to a packet transfer order guarantee method, a packet transfer order guarantee apparatus, and a packet transfer order guarantee program in parallel processing.

  In a packet processing device in which a packet is input to a plurality of parallel processing elements for switching and processed in parallel, the packet transfer order may be changed. In this case, among the packets output from the packet processing device, the packet passes through a relay device. Some packets are discarded without reaching the transfer destination that is the final reception processing device of the packet. In order to prevent this, it is necessary to guarantee the packet transfer order. Therefore, conventionally, as a method for guaranteeing the packet transfer order in parallel processing, packets having the same input information (for example, packet type, processing content, input / output port number, etc.) are assigned to the same processing element based on the input information. Allocation and sequential processing methods are used.

  Further, as a method similar to a method for guaranteeing the order of packet transfer, a method for guaranteeing the order of frames is conventionally known (see, for example, Patent Document 1). This patent document 1 discloses a data communication system in which two information processing apparatuses are connected to each other via one or more communication lines and communication data frames are distributed to one or more communication lines to perform data communication. The transmission control unit of the side system inserts order information into the frame, and the reception control unit of the reception side system determines the order of the frame from the order information inserted into the frame when the frame is received, and then collects and receives the order. A technique for ensuring the order of frames by performing processing is described.

Japanese Patent Laid-Open No. 2002-9866

  However, the above-described conventional method for guaranteeing the packet transfer order in parallel processing ends the processing of the packet arriving first if the processing time of the packet arriving first is long and the processing time of the packet arriving later is short. The subsequent packet processing is awaited until the transfer efficiency is lowered. In addition, when packets having the same input information are input in a concentrated manner, processing is performed by the same processing element, so that the load is concentrated on the processing element, and the merit of performing parallel processing is impaired.

  Further, since the method for guaranteeing the order of frames described in Patent Document 1 assumes one-to-one communication, the order of frames is guaranteed for each communication partner. It cannot be applied to applications that guarantee the order by input / output port numbers. Further, the method for guaranteeing the frame order described in Patent Document 1 does not guarantee the order unless there is an order order guarantee mechanism for output at the transmission source apparatus and input at the transmission destination apparatus. There is a limit.

  The present invention has been made in view of the above points. A packet transfer order guarantee method, a packet transfer order guarantee apparatus, and a packet transfer order guarantee apparatus that eliminate the overhead caused by the processing as much as possible by simplifying the order guarantee control and reduce the packet transfer efficiency. An object is to provide a packet transfer order guarantee program.

  Another object of the present invention is to provide a packet transfer order guarantee method capable of guaranteeing the order of packets by packet type, input / output number, etc. in many-to-many communication without having conditions (limitations) in the opposite device, and packet transfer An object is to provide an order guarantee device and a packet transfer order guarantee program.

In order to achieve the above object, the packet transfer order guarantee method of the present invention distributes packets sequentially taken out from a processing packet input queue to a plurality of packet processing elements and performs parallel processing on each of them, and then a plurality of packet processing elements. A packet transfer order guarantee method for a packet transfer system that outputs packets after processing from each of the packets in a common processing packet output queue,
A first step of sequentially inputting different packets sequentially taken out from the processing packet input queue to the plurality of packet processing elements, and in each of the plurality of packet processing elements, the input packet is determined for each unit for guaranteeing the order of the input packets. A second step of assigning a sequence number of a value indicating an input order between a plurality of packet processing elements to the input packet when a predetermined packet condition is met, and each of the plurality of packet processing elements A third step for processing a packet to which a sequence number is assigned, and a sequence number assigned to a packet to which a processed sequence number is assigned and a predetermined packet condition in each of a plurality of packet processing elements Output counter value indicating the output order of packets A fourth step of comparing, and a fifth step of extracting a processed packet having a sequence number matching the output counter value from the packet processing element and loading the packet into the processing packet output queue. .

In order to achieve the above object, the packet transfer order assurance device of the present invention distributes the packets sequentially taken out from the processing packet input queue to a plurality of packet processing elements and processes them in parallel, and then processes the plurality of packets. A packet transfer order assurance device for a packet transfer system that outputs packets after being processed from each of the processing elements in a common processing packet output queue,
Input side counter group formed from a plurality of counters that can be referred to / updated from a plurality of packet processing elements and individually manage sequence numbers for each unit for guaranteeing the transfer order of input packets, and a plurality of packet processing elements A sequence number that can be referred to / updated from each other and that can be output for each unit (for each combination of various conditions) that guarantees the packet transfer order, and that forms a pair with a plurality of counters in the input side counter group An output side counter group formed from the counters, a packet input means for sequentially taking out packets from the processing packet input queue and sequentially inputting them to a plurality of packet processing elements, and an order of input packets in each of the plurality of packet processing elements The input packet matches the predetermined packet condition for each unit to be guaranteed A sequence number giving means for reading out a value indicating an input order between a plurality of packet processing elements from a counter that matches a predetermined packet condition in the input counter group, and giving the input packet as a sequence number; In each of the packet processing elements, the sequence number given to the packet to which the processed sequence number is given and the output order of the packets read from the counter that matches the predetermined packet condition in the output counter group A sequence number comparing means for comparing the output counter value indicated, and a processed packet to which a sequence number obtained by the sequence number comparing means for which a comparison result is obtained is taken out from the packet processing element and placed in the processing packet output queue. Having an output selection means for loading And butterflies.

  In order to achieve the above object, the packet transfer order guarantee program of the present invention is characterized by causing a computer to execute each step of the packet transfer order guarantee method of the present invention.

  In the present invention, a plurality of independent counters for each predetermined packet condition (packet type, processing content, input / output port number, etc.) requiring order guarantee at the input / output end of the packet processing element Install in a place where packet processing elements can be referenced and updated. A packet to be processed is captured by a packet processing element that can start processing (packet capture control such as round robin is not performed). At the packet processing element input end, a sequence number (input side counter value) is assigned to the input packet. At the packet processing element output end, the sequence number assigned to the processed packet is compared with the output side counter value. Only output, otherwise wait and compare until the counter values match.

  As a result, intermediate parallel packet processing can be performed freely without regard to order guarantees, and parallel processing can be performed for packets that need to be ordered, and packet output order guarantees are performed at the time of output. Load distribution is possible. That is, the present invention realizes a method of outputting packets in the order of packet input (order guarantee) in a packet processing apparatus capable of parallel processing with a simple mechanism, and effective use of parallel processing elements. It is possible to reduce transfer efficiency deterioration.

  According to the present invention, the packet transfer order guarantee method can be processed freely without worrying about overtaking of the packet from the time when the packet is given a sequence number until the part where the order is actually guaranteed (immediately before output). Compared with, it is possible to reduce packet transfer efficiency degradation.

  Further, according to the present invention, since the sequence number assignment and the sequence number comparison are performed only by the coincidence comparison between the counter and its value, the order guarantee logic can be simplified as compared with the conventional packet transfer order guarantee method. .

  Next, the best mode for carrying out the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram of an embodiment of a packet transfer sequential guarantee method and guarantee apparatus according to the present invention. As shown in FIG. 1, in the present embodiment, a processing packet input queue 100 that stores input packets from the previous stage, takes a packet from the processing packet input queue 100, processes the packet, and sends the packet to the processing packet output queue 104. Processing packets for storing N packets (N is a natural number greater than or equal to 2) packet processing elements 102-1 to 102-N and packets processed by the packet processing elements 102-1 to 102-N for passing to the subsequent stage An output queue 104 is arranged.

  Further, at the entrance of the packet processing elements 102-1 to 102-N, an input formed by a plurality of counters individually managing sequence numbers for each unit (for each combination of various conditions) for guaranteeing the order of input packets. Sequence number assigning units 102-1-1 to 102-N-1 for reading out sequence numbers from the side counter group 101 and assigning them to input packets are arranged, and the input side counter group 101 is provided at the exit of the packet processing element. In the same manner as described above, the output side counter group 103 formed by a plurality of counters individually managing sequence numbers that can be output for each unit (for each combination of various conditions) for guaranteeing the order is referred to the processing packet output queue 104. Sequence number comparison units 102-1-2 to 102-N-2 for checking whether loading is possible are arranged.

  The input-side counter group 101 and the output-side counter group 103 are arranged so as to be paired under the same conditions at positions that can be referred to and updated from all the packet processing elements 102-1 to 102-N. The number N or more that can be processed at the same time can be expressed.

  Next, the basic operation of order assurance in the present invention will be described with reference to the explanatory diagram of FIG. 2 and the flowchart of FIG. In FIG. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. As a precondition, among counters 101-1 to 101-N of the input-side counter group 101 and counters 103-1 to 103-N of the output-side counter group 103, a pair of counters (101-1 and 103-) are paired. 1, 101-2 and 103-2,..., 101-N and 103-N) are the same in the initial state, and the counter update is performed according to the same rule (increment by 1).

  First, as shown in FIG. 2A, the sequence number assigning unit 102-X-1 in the Xth (X is a natural number from 1 to N) packet processing element 102-X in FIG. The packet 200 is extracted from 100 (step S1 in FIG. 3). At the time of extraction, the sequence number assigning unit 102-X-1 extracts the conditions (packet type, processing contents, input) of the extracted packet in the input-side counter group 101. A value is read from a counter (assumed to be the counter 101-1) matching the output port (step S2 in FIG. 3). Subsequently, the sequence number assigning unit 102-X-1 updates the value of the counter 101-1 that has read the value so as not to assign the same sequence number to subsequent packets that are input under the same conditions (step of FIG. 3). S3) Further, the value of the read counter 101-1 is given as a sequence number to the packet 200 (step S4 in FIG. 3).

  Subsequently, as shown in FIG. 2B, the packet 200 given the sequence number is freely processed in the packet processing element 102-X without being aware of the input order (step S5 in FIG. 3). ). Before finishing the packet processing of the packet 200 and passing it to the processing packet output queue 104, the sequence number comparison unit 102-X-2 is paired with the counter 101-1 in the output counter group 103 to which a value is added to the packet 200. A value is read from the counter 103-1 (step S6 in FIG. 3), and a comparison is made with the sequence number given to the packet (step S7 in FIG. 3).

  As a result of the coincidence comparison, if there is no coincidence, it waits for a certain time (step S8 in FIG. 3), reads the value of the counter 103-1 again, and performs a coincidence comparison (steps S6 and S7 in FIG. 3). This operation is repeated until they match. As a result of the match comparison, if they match, as shown in FIG. 2C, the value of the counter 103-1 used for the match comparison is updated (step S9 in FIG. 3), and the processing packet 200 is processed. The data is loaded on the output queue 104 (step S10 in FIG. 3). When the packet 200 is loaded on the processing packet output queue 104, the order of the packets is guaranteed by this basic operation.

  Next, a case where packets that must be ordered (packets with the same condition) are processed in parallel by a plurality of packet processing elements will be described with reference to FIG. Assume that packets 400 and 401 are stacked in the processing packet input queue 100. These two packets 400 and 401 are taken out in the order in which they are vacant by the packet processing elements that are not processed (extraction control such as round robin is not performed).

  Here, as shown in FIG. 4, it is assumed that the packets 400 and 401 are sequentially extracted to the packet processing elements 102 -X and 102 -Y, respectively. The sequence number assigning unit 102-X-1 of the packet processing element 102-X has a counter (packet type, processing content, input / output port, etc.) that matches the conditions of the packet 400 (and packet 401) of the input side counter group 101 ( The sequence number n is read from (assumed to be 101-1) and is given to the packet 400, and the value of the counter 101-1 is updated to (n + 1). A little later, the sequence number assigning unit 102-Y-1 of the packet processing element 102-Y similarly reads the updated value (n + 1) from the counter 101-1, and assigns it to the packet 401 as a sequence number. Update the value to (n + 2).

  Packet processing performed by the packet processing elements 102-X and 102-Y is performed in parallel without being aware of the packets being processed by the other packet processing elements. When the processing time of the packet 400 is longer than the processing time of the packet 401, the order is switched before reaching the sequence number comparison units 102-X-2 and 102-Y-2.

  In this case, the packet 401 first arrives at the sequence number comparison unit 102-Y-2, the value assigned to the packet 401 by the sequence number comparison unit 102-Y-2, and the counter 101-1 to which the value is assigned. When the values of the counters 103-1 in the pair of output side counters to be paired are compared, the value given to the packet 401 is (n + 1) and the value of the counter 103-1 is n. Until the value of 1 reaches the sequence number assigned to the packet 401, the standby and comparison for a predetermined time are alternately repeated.

  While the packet 401 is comparing with standby in the packet processing element 102-Y, the packet 400 reaches the sequence number comparison unit 102-X-2, and the value assigned to the packet 400 and the value of the counter 103-1. And compare. In this case, since the value of the sequence number given to the packet 400 is n and the value of the counter 103-1 is n, both values match, and the packet processing element 102-X sends the packet 400 to the processing packet output queue 104. To load.

  Thereafter, since the value of the counter 103-1 is updated to (n + 1), the value of the counter 103-1 matches the sequence number assigned to the packet 401, so that the packet 401 is the processing packet output queue next to the packet 400. 104 is loaded. In this way, the order of packets requiring order guarantee can be maintained.

  Next, a case where packets that do not need to be guaranteed in order (packets with different conditions) are processed in parallel by a plurality of packet processing elements will be described with reference to FIG. Assume that packets 500 and 501 are loaded in the processing packet input queue. These two packets are taken out in the order in which they are vacant by the packet processing elements that have not been processed, as described above. Here, it is assumed that the packets 500 and 501 are sequentially extracted to the packet processing elements 102-X and 102-Y, respectively.

  The sequence number assigning unit 102-X-1 of the packet processing element 102-X reads the sequence number n1 from the counter (assumed to be 101-1) that matches the condition of the packet 500 of the input side counter group 101, and sends it to the packet 500. And update the value of the counter 101-1 to n2. A little later, the sequence number assigning unit 102-Y-1 of the packet processing element 102-Y reads the sequence number n2 from the counter (assumed to be 101-2) that matches the condition of the packet 501 and assigns it to the packet 501, and the counter The value of 101-2 is updated. Packet processing performed in the packet processing elements 102-X and 102-Y is performed in parallel without being aware of the packets being processed by other packet processing elements.

  When the processing of the packet 500 is longer than the processing of the packet 501, the order of the packet 500 and the packet 501 is switched before reaching the sequence number comparison units 102-X-2 and 102-Y-2. First, the packet 501 arrives at the sequence number comparison unit 102-Y-2, and the value n2 assigned to the packet 501 by the sequence number comparison unit 102-Y-2 is paired with the counter 101-2 to which the value is assigned. Is compared with the value n2 of the counter 103-2 in the output side counter group 103, the processing packet output queue 104 waits for the packet 500 that reaches the sequence number comparison unit 103-1 after the two values match. Stacked. Thereafter, the packet 500 is loaded in the processing packet output queue 104 by the same operation. As a result, in the case of the packets 500 and 501 that do not require the order guarantee, the packets are output without maintaining the packet transfer order.

  In this way, according to the present embodiment, even when packets requiring / unnecessary for order are mixed, it is possible to guarantee the order of only the packets requiring order guarantee as described above. As a result, in the present embodiment, a packet processing device capable of parallel processing with a simple mechanism outputs a packet in the order of packet input (order guarantee), and effectively uses packet processing elements arranged in parallel. This makes it possible to reduce transfer efficiency deterioration due to the control. Further, in the present embodiment, sequence number assigning units 102-1-1 to 102-N-1 and sequence number comparing units 102-1-2 to 102-102-1 are provided inside packet processing elements 102-1 to 102-N, respectively. Since the packet transfer order guarantee mechanism 102-N-2 is provided, there is no condition (limitation) in the opposite device, and the packet order is guaranteed by the packet type, input / output number, etc. Applicable to.

  In the above embodiment, the packet type, processing content, and input / output port are used as the packet condition, and when all of these are matched, the counter value is set to satisfy the packet condition (match the packet condition). It is given as a sequence number. However, if the packet condition cannot be classified, any one of the above three may be used. However, if the condition can be classified, it is desirable to classify as much as possible without being limited to the above three conditions. If it does not match the conditions of the same packet, there will be no problem even if packet overtaking occurs or packet order is not guaranteed (since discarding due to packet reordering does not occur), the reverse If the conditions are very rough, even if an overtaking of a packet occurs, the order of the packet is guaranteed in most cases, so that the processing of the packet that does not cause the overtaking of the packet will be awaited. This is because useless processing waiting time is created.

  In addition, this invention is not limited to said embodiment, For example, it can utilize also as competition control. An operation that requires contention control is started from a certain processing element by assigning a sequence number before starting the operation that should perform contention control and comparing the sequence number immediately before the operation that requires contention control. Is allowed. The present invention also includes a packet transfer order guarantee program that causes the procedure of each step of FIG. 3 to be executed by computer software.

It is explanatory drawing of one Embodiment of the packet transfer sequential guarantee method and guarantee apparatus of this invention. It is explanatory drawing of the basic operation | movement of order guarantee in this invention. It is a flowchart for basic operation | movement description of the order guarantee in this invention. It is explanatory drawing in case the packet (packet of the same conditions) which must guarantee an order is processed in parallel by several packet processing elements. It is explanatory drawing when the packet (packet of different conditions) which does not need to perform order guarantee is processed in parallel by a plurality of packet processing elements.

Explanation of symbols

100 processing packet input queue 101 input side counter group 101-1 to 101-N input side counter 102-1 to 102-N packet processing element 102-1-1, 102-2-1, 102-N-1, 102- X-1, 102-Y-1 Sequence number assigning unit 102-1-2, 102-2-2, 102-N-2, 102-X-2, 102-Y-2 Sequence number comparing unit 103 Output side counter Group 103-1 to 103-N Output side counter 104 Processing packet output queue 400, 401, 500, 501 packets

Claims (12)

Packets sequentially taken out from the processing packet input queue are distributed and input to a plurality of packet processing elements and processed in parallel, and then the processed packets from each of the plurality of packet processing elements are loaded into a common processing packet output queue. A packet transfer order guarantee method for a packet transfer system to output,
A first step of sequentially inputting different packets sequentially retrieved from the processing packet input queue to the plurality of packet processing elements;
In each of the plurality of packet processing elements, when the input packet matches a predetermined packet condition for each unit in which the order of the input packets is guaranteed, the input packet is between the plurality of packet processing elements. A second step of assigning a sequence number of values indicating the input order;
A third step of processing a packet assigned the sequence number in each of the plurality of packet processing elements;
In each of the plurality of packet processing elements, the sequence number given to the packet given the sequence number after the processing, and an output counter value indicating the output order of packets matching the predetermined packet condition, A fourth step of comparing
A packet transfer order guarantee comprising: a fifth step of taking out the processed packet assigned with a sequence number matching the output counter value from the packet processing element and loading it into the processed packet output queue. Method.   When a coincidence comparison result is obtained by comparing the sequence number and the output counter value in the fourth step, a sixth step of updating the output counter value to a value indicating the next packet output order; The packet transfer order guarantee method according to claim 1, further comprising:   If the comparison result is not obtained by comparing the sequence number and the output counter value in the fourth step, after waiting for a certain period of time, it is added to the packet to which the processed sequence number is assigned again. 2. The packet transfer order guarantee method according to claim 1, wherein the sequence number is compared with an output counter value indicating an output order of packets matching the predetermined packet condition.   The packet transfer order guarantee method according to any one of claims 1 to 3, wherein the predetermined packet condition includes a packet type, a processing content, and an input / output port. Packets sequentially taken out from the processing packet input queue are distributed and input to a plurality of packet processing elements and processed in parallel, and then the processed packets from each of the plurality of packet processing elements are loaded into a common processing packet output queue. A packet transfer order assurance device for a packet transfer system to output,
An input-side counter group formed of a plurality of counters that can be referred to and updated from the plurality of packet processing elements and that individually manage sequence numbers for each unit that guarantees the transfer order of input packets,
It is possible to refer to and update from the plurality of packet processing elements, individually manage sequence numbers that can be output for each unit (for each combination of various conditions) for ensuring the transfer order, and a plurality of input side counter groups An output-side counter group formed of a plurality of counters constituting a pair with the counter;
Packet input means for sequentially retrieving packets from the processing packet input queue and sequentially inputting the packets to the plurality of packet processing elements;
In each of the plurality of packet processing elements, when the input packet matches a predetermined packet condition for each unit that guarantees the order of the input packets, the counter that matches the predetermined packet condition in the input counter group A sequence number giving means for reading a value indicating an input order among a plurality of packet processing elements and giving the input packet as a sequence number;
In each of the plurality of packet processing elements, read from the counter that matches the sequence number given to the packet to which the sequence number after processing has been given and the predetermined packet condition in the output counter group Sequence number comparison means for comparing the output counter value indicating the output order of the received packets;
Output selection means for taking out the processed packet, to which the sequence number obtained by the sequence number comparison means for matching results has been assigned, from the packet processing element and loading it into the processing packet output queue. A packet transfer order guarantee device.   When the comparison result is obtained by comparing the sequence number with the output counter value by the sequence number comparison means, the update means further updates the output counter value to a value indicating the next packet output order. 6. The packet transfer order assurance device according to claim 5, wherein:   When a comparison result is not obtained by comparing the sequence number with the output counter value by the sequence number comparison means, the sequence number is again given to the packet with the processed sequence number after waiting for a predetermined time. 6. The packet transfer order assurance device according to claim 5, wherein the sequence number is compared with an output counter value indicating an output order of packets matching the predetermined packet condition.   8. The packet transfer order assurance device according to claim 5, wherein the predetermined packet condition includes a packet type, a processing content, and an input / output port. Packets sequentially taken out from the processing packet input queue are distributed and input to a plurality of packet processing elements and processed in parallel, and then the processed packets from each of the plurality of packet processing elements are loaded into a common processing packet output queue. A packet transfer order guarantee program for ensuring a packet transfer order of a packet transfer system to be output by a computer,
In the computer,
A first step of sequentially inputting different packets sequentially retrieved from the processing packet input queue to the plurality of packet processing elements;
In each of the plurality of packet processing elements, when the input packet matches a predetermined packet condition for each unit in which the order of the input packets is guaranteed, the input packet is between the plurality of packet processing elements. A second step of assigning a sequence number of values indicating the input order;
A third step of processing a packet assigned the sequence number in each of the plurality of packet processing elements;
In each of the plurality of packet processing elements, the sequence number given to the packet given the sequence number after the processing, and an output counter value indicating the output order of packets matching the predetermined packet condition, A fourth step of comparing
And a fifth step of executing the fifth step of taking out the processed packet assigned the sequence number that matches the output counter value from the packet processing element and loading it into the processed packet output queue. Security program.   When a coincidence comparison result is obtained by comparing the sequence number and the output counter value in the fourth step, a sixth step of updating the output counter value to a value indicating the next packet output order; 10. The packet transfer order guarantee program according to claim 9, further comprising:   If the comparison result is not obtained by comparing the sequence number and the output counter value in the fourth step, after waiting for a certain period of time, it is added to the packet to which the processed sequence number is assigned again. 10. The packet transfer order guarantee program according to claim 9, wherein the sequence number is compared with an output counter value indicating an output order of packets that match the predetermined packet condition.   12. The packet transfer order guarantee program according to claim 9, wherein the predetermined packet condition includes a packet type, a processing content, and an input / output port.

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