JP2008236194A - Video display device and video display system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a video display device capable of displaying video signals, to be transmitted as serial signals for the portion of a plurality of channels, by mounting only an option board for inputting the serial signal of one channel. <P>SOLUTION: The video display device 1 has slots 2a-2d for mounting N (N is an integer being ≥2) or more option boards 50 for performing the parallel conversion of the video signal of one channel for serial transmission, and then, performing demultiplexing. The device 1 includes: memories 6a, 6b for phase-focusing the parallel signals of the N channels, to be transmitted from the N option boards 50 mounted on the slots 2a-2d; and a demultiplexer 7 for demultiplexing the parallel signals of the N channels, which are phase-focused in the memories 6a, 6b, thereby restoring the video signals to be transmitted as the serial signals for the portion of the N channels. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video display device and a video display system for displaying a video signal transmitted as a serial signal for a plurality of channels such as a Dual Link HD-SDI (Serial Digital Interface) signal.

  In television broadcasting stations and editing studios, it is common practice to display and evaluate broadcast images and production images on a monitor.

The broadcast station or the studio, the 74.25MHz the HDTV standard 4: 2: _2YC B _{C R} signals, be transmitted as a HD-SDI signal according to the serial transmission standard has been widely by SMPTE292M. Therefore, a monitor that can be equipped with an option board for inputting the HD-SDI signal has been widely used. In the following, the 74.25 MHz 4: 2: the HD-SDI signal transmitted through _2YC B _{C R} signal is referred to as a Single Link HD-SDI signal, an option board for inputting the Single Link HD-SDI signal This is called an option board for Single Link.

  FIG. 1A is a diagram showing a state of input of a Single Link HD-SDI signal using this Single Link option board. The Single Link HD-SDI signal is input to the Single Link option board 50 mounted in the slot 41 of the monitor 40 through one BNC cable 60.

  In the single link option board 50, this single link HD-SDI signal is supplied to a deserializer (serial / parallel conversion circuit) 52 via a cable equalizer (equalizer) 51, as shown in FIG. , 74.25 MHz, 20-bit parallel signal (parallel transmission standard signal by SMPTE274M or the like). In FIG. 2, the number assigned to each signal for each sampling period is a number indicating the number of the sample.

Further, in the option substrate 50 for Single Link, this parallel signal is demultiplexed by the demultiplexer 53, whereby 74.25 MHz, 30-bit width 4: 2: 2YC _B as shown in FIG. The _CR signal is restored.

Then, the 4: 2: _2YC B _{C R} signal, transmitted from the Single Link Options substrate 50 to the monitor 40, is displayed on the monitor 40.

However, in recent years, a broadcasting station or the studio, the 74.25 MHz 4: 4: and 4RGB / _YC B _{C R} signal, the 148.5MHz where the clock rate is doubled 4: 2: _2YC B _{C R} signal The SMPTE 372M (see Non-Patent Document 1) is often transmitted as a Dual Link HD-SDI signal. The Dual Link HD-SDI signal of _{74.25MHz 4: 4: 4RGB / YC} B C R signal and the 148.5MHz 4: 2: _2YC B _C a _R signal, the two channels Single Link HD-SDI signal As a transmission.

  In the conventional monitor, in order to input the Dual Link HD-SDI signal, a dedicated option board (hereinafter referred to as a Dual Link option board) different from the Single Link option board was mounted. .

  FIG. 1B is a diagram showing a state of inputting a Dual Link HD-SDI signal in a conventional monitor, and the same reference numerals are given to portions common to FIG. Dual Link HD-SDI signals (2-channel HD-SDI signals of Link A and Link B) are input to the Dual Link option board 70 mounted in the slot 41 of the monitor 40 through the two BNC cables 60 and 61.

In the Dual Link option board 70, the Link A and Link B HD-SDI signals are supplied to the deserializers 73 and 74 via the cable equalizers 71 and 72, respectively. Then, the 74.25MHz 4: 4: 4RGB / when the _YC B _{C R} signal, as shown in FIG. 3 (a), 74.25 MHz, 20 bits wide LinkA, parallel signals (each LinkB, SMPTE274M The signal is converted into a parallel transmission standard signal. Also in FIG. 3, the number given to each signal for each sampling period is a number indicating the number of the sample.

In the case of a 74.25 MHz 4: 4: 4 RGB / YC BC _R signal, the 10th to 19th bits of Link _B are called an alpha channel and are used for information transmission. However, when the quantization level is 12 bits, the alpha channel transmits the lower 2 bits of the RGB signal, and transmits the upper 10 bits in the 0th to 9th bits of Link A and Link B.

On the other hand, the 148.5 MHz 4: 2: in the case of _2YC B _{C R} signal, LinkA supplied to the deserializer 73 and 74, HD-SDI signals of LinkB, such as shown in FIG. 4 (a), 74. It is converted to 25 MHz, 20-bit width Link A and Link B parallel signals (signals of parallel transmission standards by SMPTE 274M, etc., respectively). Also in FIG. 4, the number assigned to each signal for each sampling period is a number indicating the number of the sample.

4 of 148.5MHz: 2: _2YC B _C in the case of _R signals, the N-th line in LinkA 4: 2: _2YC B _C The _R signal is transmitted, the N + 1 th line in LinkB 4: 2: _2YC B C Transmit the _R signal. Originally, it is desired to transmit each line of each frame at 148.5 MHz as shown in FIG. 4 (c). However, due to the restriction of the transmission system, a 74.25MHz clock having a half frequency is used. In this way, transmission is performed using two channels of Link A and Link B.

In FIG. 1B, in the Dual Link option board 70, the parallel signals of Link A and Link B converted by the deserializers 73 and 74 are phase aligned using the delay absorbing memories 75 and 76, and then the demultiplexer. 77. Then, the 74.25 MHz 4: 4: in the case of 4RGB / _YC B _{C R} signal, de by being demultiplexed by the multiplexer 77, 74.25 MHz, as shown in FIG. 3 (b), 30 bits wide of _{4: 4: 4RGB / YC B} C R signal is restored.

On the other hand, the 148.5 MHz 4: 2: in the case of _2YC B _{C R} signal, by being demultiplexed by compressing the time axis by the demultiplexer 77, as shown in FIG. 4 (b) 148.5 MHz, 30-bit wide 4: 2: _2YC B _{C R} signal is restored.

Then, the thus restored _{4: 4: 4RGB / YC B} C R signals or 148.5MHz of 4: 2: _2YC B _{C R} signal, transmitted from the Dual Link Options substrate 70 to the monitor 40, It is displayed on the monitor 40.

SMPTE 372M PROPOSED SMPTE STANDARD for Television − Dual Link 292M Interface for 1920 × 1080 Picture Raster

However, in the conventional monitor as shown in FIG. 1, if the user has only used the single link option board until then, the Dual Link HD-SDI signal is input as it is, and the 4: 4: 4 RGB / YC is input. _B C _R signal and 148.5MHz of 4: 2: _2YC B _{C R} signal can not display the newly becomes necessary to prepare an option board for Dual Link.

  In the present invention, in view of the above points, a video signal transmitted as a serial signal for a plurality of channels, such as a Dual Link HD-SDI signal, is converted into a one-channel serial such as the single link option board shown in FIG. It is an object of the present invention to provide a video display device and a video display system that can be mounted and displayed with only an option board for inputting signals.

In order to solve the above problems, an image display device according to the present invention provides:
In a video display device having slots for mounting N (N is an integer of 2 or more) option boards for demultiplexing after converting a serially transmitted 1-channel video signal into a parallel transmission standard signal,
A memory for performing phase alignment of N-channel parallel signals sent from the N option boards mounted in the slot;
And a demultiplexer that restores a video signal transmitted as a serial signal for N channels by demultiplexing the N-channel parallel signals phase-matched by the memory.

  In this video display device, when displaying a video signal transmitted as a serial signal for N channels, an option board that demultiplexes the serially transmitted one-channel video signal after converting it into a parallel transmission standard signal. N (that is, an optional board for inputting a serial signal of one channel) is installed in the slot. Then, video signals transmitted as serial signals for N channels are input to the N option boards one by one.

  Then, the N channel parallel signals that have been converted into parallel transmission standard signals by the N option boards and then demultiplexed are supplied to a phase matching memory in the video display device.

  The N-channel parallel signal is phase-matched using the memory, and then demultiplexed by a demultiplexer in the video display device, whereby a video signal transmitted as a serial signal for N channels is obtained. Restored.

  Accordingly, it is possible to display a video signal transmitted as a serial signal for N channels (a plurality of channels) by mounting only an option board for inputting a serial signal of one channel.

Next, the video display system according to the present invention includes:
An option board for demultiplexing after converting a serially transmitted 1-channel video signal into a parallel transmission standard signal;
In a video display system configured with a video display device having a slot for mounting N (N is an integer of 2 or more) of the option boards,
The optional board is
A selection circuit for selecting whether to output the signal of the parallel transmission standard by demultiplexing or not demultiplexing,
The video display device
A decoding circuit for decoding the identification information of the signal format superimposed on the video signal from the parallel signal sent from the option board;
When the identification information decoded by the decoding circuit indicates that the video signal is transmitted as a serial signal for N channels, the parallel transmission is performed to the option board mounted in the slot. A control circuit for sending a control signal for controlling the selection circuit so as to output a standard signal without demultiplexing;
A memory for performing phase alignment of N-channel parallel signals sent from the N option boards mounted in the slot;
And a demultiplexer that restores a video signal transmitted as a serial signal for N channels by demultiplexing the N-channel parallel signals phase-matched by the memory.

  In this video display system, when a video signal transmitted as a serial signal for N channels is displayed on a video display device, an option board for demultiplexing after converting the serial signal of one channel into a signal of a parallel transmission standard N (that is, an optional board for inputting a serial signal of one channel) is mounted in the slot of the video display device. Then, video signals transmitted as serial signals for N channels are input to the N option boards one by one.

  Then, the N-channel parallel signals that have been converted into parallel transmission standard signals by the N option boards and then demultiplexed are sent to a decoding circuit in the video display device. The decoding circuit decodes the identification information indicating that the video signal is transmitted as a parallel signal for N channels as the identification information of the signal format superimposed on the video signal.

  Based on this decoding result, the control circuit in the video display device controls the selection circuit to output parallel transmission standard signals without demultiplexing to the N option boards installed in the slots. Send a control signal. As a result, parallel transmission standard signals are supplied from the N option boards to the phase matching memory in the video display device while being multiplexed.

  The N-channel parallel signal is phase-matched using the memory, and then demultiplexed by a demultiplexer in the video display device, whereby a video signal transmitted as a serial signal for N channels is obtained. Restored.

  Accordingly, it is possible to display a video signal transmitted as a serial signal for N channels (a plurality of channels) by mounting only an option board for inputting a serial signal of one channel.

  In addition, the parallel transmission standard signal (that is, a signal having a bit width smaller than that of the demultiplexed signal) is sent from the option board to the video display device for phase matching in the video display device. The capacity of the memory can be reduced. In addition, unlike the case where the demultiplexed signal is sent from the option board to the video display device, this phase can be obtained without adding a multiplexer in the video display device for remultiplexing the demultiplexed signal. The capacity of the matching memory can be reduced.

  According to the video display device of the present invention, it is possible to restore a video signal transmitted as a serial signal for a plurality of channels by mounting only an option board for inputting a one-channel serial signal. Is obtained.

  According to the video display system of the present invention, a video signal transmitted as a serial signal for a plurality of channels is restored by mounting only an option board for inputting a serial signal of one channel on the video display device. The effect of being able to be obtained.

  Further, according to the video display system of the present invention, it is possible to reduce the capacity of the phase matching memory in the video display device without adding a multiplexer in the video display device.

  Hereinafter, an example in which the present invention is applied to input a Dual Link HD-SDI signal to a video evaluation monitor in a television broadcasting station or an editing studio will be specifically described with reference to the drawings.

  FIG. 5 is a block diagram showing a configuration example of a monitor to which the present invention is applied. In FIG. 5, the option board for Single Link 50 has the same configuration as that shown in FIG.

  On the housing surface of the monitor 1, four slots 2a to 2d for inserting / removing one single link option board 50 are provided.

The monitor 1 includes ID decoders 3a to 3d, a register 4, a 4-input 2-output selector 5, memories 6a and 6b for phase matching (delay absorption), a demultiplexer 7, and YC _B C _R A matrix circuit 8 for converting signals into RGB signals, an OSD (on-screen display) circuit 9, a superimposing circuit 10 for superimposing an output signal of the OSD circuit 9 on a video signal, an LCD (liquid crystal display) 11, and a monitor A CPU 12 that controls the entire system 1 is provided.

  Parallel signals sent from the single link option board 50 (hereinafter also simply referred to as option board 50) mounted in the slots 2a to 2d to the monitor 1 are supplied to the ID decoders 3a to 3d, respectively, Input to the input terminal.

  Output signals from the two output terminals of the selector 5 are supplied to the demultiplexer 7 via the memories 6a and 6b, respectively. As will be described later, the memories 6a and 6b are memories for performing phase alignment of the parallel signals of the two channels selected by the selector 5 when a Dual Link HD-SDI signal is input.

As will be described later, when the Dual Link HD-SDI signal is input, the demultiplexer 7 demultiplexes the parallel signals of the two channels phase-matched by the memories 6a and 6b, so that FIG. 74.25MHz like, a 30 bit wide _{4: 4: 4RGB / YC B} C R signal or 148.5MHz as shown in FIG. 4 (b), of 30-bit wide 4: 2: restore _2YC B _{C R} signal It is a circuit for doing.

  An output signal of the demultiplexer 7 is supplied to the liquid crystal display 11 through the matrix circuit 8 and the superimposing circuit 10.

  The ID decoders 3a to 3d decode the FORMAT ID, which is the signal format identification information superimposed on the HD-SDI signal in accordance with the SMPTE352M standard, from the parallel signal sent from the option board 50 mounted in the slots 2a to 2d. Circuit.

  This FORMAT ID includes information on sampling structure, frame / field rate information, quantization level information, and information indicating which channel is Link A or Link B in the case of a Dual Link HD-SDI signal. It is included.

  The FORMAT ID decoded by the ID decoders 3 a to 3 d is stored in the register 4 and then supplied to the demultiplexer 7. Further, the CPU 12 reads out the FORMAT ID stored in the register 4 and executes a process as shown in FIG.

  In this process, first, it is determined whether or not this FORMAT ID is a FORMAT ID for a Dual Link HD-SDI signal (step S1).

If NO (in the case of FORMAT ID for the Single Link HD-SDI signal), the selector 5 is controlled and the parallel sent from the option board 50 that is inputting the Single Link HD-SDI signal. The signal is selected as a signal to be output from the output terminal on the memory 6a side (step S11). Further, the memory 6a is controlled so that the written parallel signal is immediately read out without performing phase alignment with the signal on the memory 6b side (step S12). Further, by controlling the matrix circuit 8, to convert the _YC B _{C R} signal into an RGB signal (step S13).

  When the FORMAT ID for the Single Link HD-SDI signal is supplied from the register 4, the demultiplexer 7 outputs the parallel signal supplied from the memory 6a as it is without performing the demultiplexing process.

Thus, the 74.25MHz restored in the option board _{50 4: 2: 2YC B C} R signal is supplied as it is from the demultiplexer 7 in a matrix circuit 8, converted into RGB signals by the matrix circuit 8, the liquid crystal It is displayed on the display 11.

  On the other hand, if yes in step S1, is the FORMAT ID for both the Link A and Link B channels present in register 4 (ie, the HD-SDI signals for both the Link A and Link B channels are input)? Whether or not) is determined (step S2).

  If NO, that is, if only the HD-SDI signal of only one channel of Link A and Link B is input, the option board 50 to which the HD-SDI signal of the one channel is input It is determined whether another option board 50 is currently installed in any of the slots 2a to 2d (step S3).

  If yes, the OSD circuit 9 is controlled to generate a character image signal instructing to input the HD-SDI signal of the remaining one channel to the other option board 50 (step S4).

  As a result, the character is displayed on the screen on the liquid crystal display 11 via the superimposing circuit 10. FIG. 7A is a diagram illustrating the on-screen display. In this example, only the Link-B HD-SDI signal is input, and the slot number No. This is an example in which another option board 50 is installed in the slot of “1”. Input Link A to option board 1. Is displayed.

  In FIG. 6, if NO in step S3, the OSD circuit 9 is controlled to specify the slot in which the option board 50 is to be installed and the HD-SDI signal of the remaining one channel is installed in that slot. Then, an image signal of a character that gives an instruction to input to the option board 50 is generated (step S5).

  As a result, the character is displayed on the screen on the liquid crystal display 11 via the superimposing circuit 10. FIG. 7B is a diagram illustrating the on-screen display. In this example, only the Link A HD-SDI signal is input. Specify slot 2 and “There is not enough link B option board. Slot No. Attach to 2 and input LinkB. Is displayed.

  In FIG. 6, when step S4 or S5 is finished, until the FORMAT IDs for both the link A and link B channels are stored in the register 4 (that is, the HD-SDI signal of the remaining one channel that has not been input is stored). It waits (until it is input to another option board 50) (step S6). Then, the OSD circuit 9 is controlled to end the generation of the character image signal (step S7), and the process proceeds to step S8.

  If YES in step S2 (that is, if the HD-SDI signals of both the Link A and Link B channels are input from the beginning), the process proceeds from step S2 to step S8 as it is.

  In the state where the HD-SDI signal of one channel of each of Link A and Link B is input to the two option boards 50, the two option boards 50 are as shown in FIG. 3 (a) and FIG. 4 (a). 74.25 MHz, 20-bit width Link A and Link B parallel signals are supplied from the deserializer 52 (FIG. 1A) to the demultiplexer 53 (FIG. 1A), respectively, as shown in FIG. A signal of .25 MHz, 30 bits wide is output from the demultiplexer 53 and sent to the monitor 1.

  Therefore, in step S8, the selector 5 is controlled so that the parallel signals sent from the two option boards 50 to which the HD-SDI signals of one of the links A and B are input are respectively stored in the memory 6a and the memory 6b. The signal to be output from the output terminal on the side is selected.

  Subsequently, the memories 6a and 6b are controlled to read out the written parallel signals in phase with each other (step S9).

  When the FORMAT ID for the Dual Link HD-SDI signal is supplied from the register 4, the demultiplexer 7 uses the signals from the memory 6a and the memory 6b as the signals for Link A and Link B, respectively, and indicates the FORMAT ID. The demultiplex processing is set so as to restore the video signal having a signal format that matches the current signal format.

That is, information of the information and the frame / field rate of sampling structure in the FORMAT ID is, of 74.25 MHz 4: 4: when the identification information indicates that the 4 RGB / _YC B _{C R} signals, the demultiplexer 7 by demultiplexing the signal from the memory 6a and 6b, 74.25 MHz, such as in FIG. 3 (b), the 30 bit wide _{4: 4: 4RGB / YC B} C R signal to restore (time, When the quantization level information in the FORMAT ID indicates 10 bits, a 10-bit signal is restored, and when the quantization level information indicates 12 bits, 10 to 19 bits of LinkB. Use eye to restore 12-bit signal.)

On the other hand, information of the information and the frame / field rate of sampling structure in the FORMAT ID is, of 148.5 MHz 4: 2: when the identification information indicates that the _2YC B _{C R} signals, the demultiplexer 7, the memory by demultiplexing the signal from 6a and 6b by compressing the time axis, 148.5 MHz as in FIG. 4 (b), the 30 bit wide 4: 2: restoring the _2YC B _{C R} signal.

Following step S9, the information of the sampling structure in the FORMAT ID performs conversion processing to the RGB signal when the identification information indicates that the YC _B C _R signal, the information of the sampling structure is RGB signals In the case shown, the matrix circuit 8 is controlled in accordance with the FORMAT ID so as not to perform the conversion process to the RGB signal (step S10).

Thereby, restored by the demultiplexer _{7 4: 4: 4YC B C} R signal and the _{148.5MHz 4: 2: 2YC B C} R signal is converted into RGB signals by the matrix circuit 8, the liquid crystal display 11 Is displayed. Further, the 4: 4: 4 RGB signal restored by the demultiplexer 7 is output as it is from the matrix circuit 8 and displayed on the liquid crystal display 11.

  When step S10 or step S13 is completed, the processing based on this FORMAT ID is terminated.

  Next, how to use the single link option board 50 when inputting the Dual Link HD-SDI signal to the monitor 1 will be described with reference to FIG.

Dual Link HD-SDI signal 4 is transmitted _{as: 4: 4RGB / YC B C} R signal and the 148.5 MHz 4: 2: a _2YC B _{C R} signal when displayed on the monitor 1, the user, FIG. As illustrated in FIG. 8, two single link option boards 50 are mounted in any two of the slots 2a to 2d.

  Then, among the Dual Link HD-SDI signals, the Link A HD-SDI signal is input to one of the two option boards 50 through one BNC cable 60, and the Link B HD-SDI signal is input to this one. The other one of the two option boards 50 is inputted through one BNC cable 61.

Then, in steps S1, S2, and S8 to S10 in FIG. 6, the two option boards 50 respectively convert the signals to the parallel transmission standard signals, and then demultiplex the two parallel signals of Link A and Link B. (See FIG. 2B) is phase-matched using the memories 6a and 6b in the monitor 1, and then demultiplexed by the demultiplexer 7 in the monitor 1, whereby 4: 4: 4 RGB / YC _B C _R signal and 148.5MHz of 4: 2: _2YC B _{C R} signal is restored.

Thus, 4 is transmitted as Dual Link HD-SDI _{signal: 4: 4RGB / YC B C} R signal and the 148.5 MHz 4: 2: a _2YC B _{C R} signal, for inputting a Single Link HD-SDI signal Only the option board 50 for Single Link, which is the option board, can be mounted and displayed.

  Also, the demultiplexer 7 is a signal format that matches the original signal format (sampling structure, frame / field rate, quantization level) based on the FORMAT ID that is the identification information of the signal format superimposed on the HD-SDI signal. The demultiplexing process is automatically set to restore the video signal. Further, whether or not the matrix circuit 8 performs the conversion process to the RGB signal is automatically set based on the FORMAT ID in step S10 of the process of FIG.

  In the conventional monitor, various settings inside the monitor are manually performed by the user, and the user is required to have accurate knowledge for setting operation. In contrast, these settings are automatically performed based on the FORMAT ID, thereby reducing the burden on the user.

  If the user mistakenly inputs only the HD-SDI signal of one of the link A and link B channels, or installs only one option board 50, step S3 in the process of FIG. Through the on-screen display as illustrated in FIG. 7, the user should be able to input the HD-SDI signal of the other channel through S5 and install another option board 50 for that purpose. Be notified.

  As a result, the user can quickly notice an error and input the HD-SDI signal of the remaining one channel, or install another option board 50 for that purpose.

  Next, another configuration example of a monitor to which the present invention is applied will be described with reference to FIG. The monitor 20 shown in FIG. 9 is provided with multiplexers 21a and 21b between the selector 5 in the monitor 1 shown in FIG. 5 and the phase matching memories 6a and 6b, respectively. Since it is common with the monitor 1 of FIG. The processing executed by the CPU 12 based on the FORMAT ID is the same as the processing shown in FIG.

  The multiplexers 21a and 21b respectively multiplex the two-channel parallel signals selected by the selector 5 (74.25 MHz, 30-bit width signals as shown in FIG. 2B) to thereby multiplex the signals shown in FIG. Alternatively, as shown in FIG. 4A, the circuit converts back to a 74.25 MHz, 20-bit Link A and Link B parallel signal.

The memories 6a and 6b perform phase alignment of 20-bit width Link A and Link B parallel signals output from the multiplexers 21a and 21b. Further, the demultiplexer 7 demultiplexes the 20-bit link A and Link B parallel signals phase-matched in the memories 6a and 6b, thereby 74.25 MHz, 30-bit width as shown in FIG. of _{4: 4: 4RGB / YC B} C R signal or 148.5MHz as shown in FIG. 4 (b),, 30-bit wide 4: 2: restoring the _2YC B _{C R} signal.

  By providing such multiplexers 21a and 21b between the selector 5 and the memories 6a and 6b, the memories 6a and 6b have a bit width smaller than that of the 30-bit width signal supplied in the monitor 1 of FIG. % Bit width) is provided.

  As a result, a memory having a smaller capacity (66% capacity) than that in the monitor 1 of FIG. 5 can be used as the phase matching memories 6a and 6b.

  Next, a configuration example of a monitor system to which the present invention is applied will be described with reference to FIG. This monitor system includes a monitor 1 and an option board 30 for Single Link. The monitor 1 has the same components as the monitor 1 shown in FIG. 5 (however, as will be described later, the processing of the CPU 12 based on the FORMAT ID is partially different from the processing shown in FIG. 6). ).

  In this monitor system, when the Dual Link HD-SDI signal is input to the monitor 1, the single link option board 30 is used in the same way as the single link option board 50 in the monitor 1 of FIG. 5 (see FIG. 8). The same.

  The single link option board 30 (hereinafter also simply referred to as option board 30) is partially different from the conventional single link option board 50 shown in FIG. FIG. 11 is a block diagram showing the configuration of the option board 30, and parts common to the option board 50 are denoted by the same reference numerals. The option board 30 is provided with a two-input one-output selector 31 and a register 32 in addition to a cable equalizer 51, a deserializer 52, and a demultiplexer 53 (FIG. 1A).

  The output signal of the demultiplexer 53 (74.25 MHz, 30-bit width signal as shown in FIG. 2B) is input to one input terminal of the selector 31. An output signal of the deserializer 52 (that is, a signal having a multiplexed value of 74.25 MHz and 20 bits) is sent to the demultiplexer 53 and input to the remaining one input terminal of the selector 31.

  The register 32 is for storing a control signal sent from the CPU 12 in the monitor 1. Of the control signals stored in the register 32, a control signal for controlling selection by the selector 31 is supplied to a control input terminal of the selector 32.

  Then, the output signal of the selector 32 is sent to the monitor 1 (FIG. 10) on which the option board 30 is mounted, supplied to the ID decoders 3a to 3d, and inputted to the four input terminals of the selector 5.

  FIG. 12 is a flowchart showing processing executed by the CPU 12 in the monitor 1 based on the FORMAT ID in the register 4 in the monitor system of FIG. This processing is basically the same processing content as steps S1 to S13 in FIG. 6, and FIG. 12 shows the same processing as steps S1 to S13 in FIG. However, in this process, a new step S21 is added between steps S1 and S11, and a new step S22 is added immediately before step S8.

  That is, if the answer is NO in step S1 (if the HD-SDI signal currently input to the currently installed option board 30 is a Single Link HD-SDI signal), before proceeding to step S11, As step S21, a control signal for selecting the output signal of the demultiplexer 53 to the selector 31 (FIG. 11) is sent to the option board 30.

  The control signal is stored in the register 32 (FIG. 11) in the option board 30 and then supplied to the control input terminal of the selector 31. As a result, the output signal of the demultiplexer 53 is sent from the option board 30 to the monitor 1 in the same manner as the conventional option board 50.

  On the other hand, if the answer is yes in step S1 (the HD-SDI signal input to the currently installed option board 30 is a Dual Link HD-SDI signal), and if yes in step S2, then step If the result in S2 is no, but the process is completed up to step S7 (when the HD-SDI signals of both the link A and link B channels are input), before proceeding to step S8, as step S22, link A, link B The control signal for selecting the output signal of the deserializer 52 to the selector 31 is sent to the two option boards 30 to which the HD-SDI signals of one of the channels are input.

  As a result, the output signal of the deserializer 52 (74.25 MHz, 20-bit Link A and Link B parallel signals as shown in FIG. 3A or 4A) is monitored from the two option boards 30. Sent to 1.

In the monitor system of FIG. 10, the memories 6 a and 6 b perform phase alignment of the 20-bit width Link A and Link B parallel signals selected by the selector 5. Further, the demultiplexer 7 demultiplexes the 20-bit link A and Link B parallel signals phase-matched in the memories 6a and 6b, thereby 74.25 MHz, 30-bit width as shown in FIG. of _{4: 4: 4RGB / YC B} C R signal or 148.5MHz as shown in FIG. 4 (b),, 30-bit wide 4: 2: restoring the _2YC B _{C R} signal.

  As described above, in the monitor system of FIG. 10, when the Dual Link HD-SDI signal is input, the output signal (demultiplexed 20-bit width parallel signal) of the deserializer 52 is output from the option board 30. Sent to monitor 1 Therefore, the memory 6a and 6b in the monitor 1 is supplied with a signal having a smaller bit width (66% bit width) than the 30-bit width signal supplied in the monitor 1 of FIG.

  As a result, a memory having a smaller capacity (66% capacity) than that in the monitor 1 of FIG. 5 can be used as the phase matching memories 6a and 6b.

  In addition, unlike the case where the demultiplexed signal is sent from the option board 50 as in the monitor 20 of FIG. 9, a multiplexer (multiplexers 21a and 21b in the monitor 20) for multiplexing the demultiplexed signal again. ) To the monitor 1, the capacity of the memories 6 a and 6 b can be reduced.

In the above each embodiment, the monitor can be mounted option board Single Link, Dual Link HD-SDI signal 4 is transmitted _{as: 4: 4RGB / YC B C} R signal and 148.5 MHz 4: 2: the present invention is applied to display 2YC _B C _R signal. However, the present invention is not limited to this, and when a higher-resolution video signal is transmitted as an HD-SDI signal for three channels or more (for example, in the case of Quad Link transmitted as an HD-SDI signal for four channels), The present invention may be applied to display such a high-resolution video signal on a monitor on which a single link option board can be mounted.

  13 changes the configuration of the selector 5, the memories 6a and 6b, and the demultiplexer 7 of the monitor 1 shown in FIG. 5 and FIG. 10 so that a quad link HD-SDI signal can be input to display a video signal. FIG. In this modified example, the selector 5 in FIG. 5 is omitted, and memories 6a to 6d are provided for performing phase alignment of parallel signals sent from option boards mounted in all slots 2a to 2d. The video signal is restored by the demultiplexer 7 from the parallel signals of the four channels phase-adjusted in 6d.

  In this modification, when inputting Quad Link HD-SDI signals, option boards (option board 50 in FIG. 5 and option board 30 in FIG. 10) are installed in all slots 2a to 2d, and the four options are installed. What is necessary is just to input a Quad Link HD-SDI signal for 1 channel at a time to a board | substrate.

  In each of the above examples, the present invention is applied to a video evaluation monitor in a television broadcasting station or an editing studio. However, the present invention can be applied to any video display device as long as the single link option board can be mounted.

  Also, the present invention mounts only an option board for inputting a single-channel serial signal as a video signal transmitted as a serial signal for a plurality of channels in accordance with a serial transmission standard other than HD-SDI (eg, SD-SDI). It can also be applied to display.

It is a figure which shows the mode of the input of the Dual Link HD-SDI signal with the conventional monitor. It is a figure which shows the Single Link HD-SDI signal before and after demultiplexing. It is a figure which shows the Dual Link HD-SDI signal before and after demultiplexing. It is a figure which shows the Dual Link HD-SDI signal before and after demultiplexing. It is a block diagram which shows the structural example of the monitor to which this invention is applied. 6 is a flowchart showing processing executed by a CPU based on FORMAT ID in the monitor of FIG. It is a figure which shows the example of the on-screen display by the process of FIG. It is a figure which shows how to use the option board | substrate for Single Link at the time of inputting Dual Link HD-SDI signal to the monitor of FIG. It is a block diagram which shows another structural example of the monitor to which this invention is applied. It is a block diagram which shows the structural example of the monitor system to which this invention is applied. It is a block diagram which shows the structure of the option board | substrate for Single Link of FIG. 11 is a flowchart showing processing executed by a CPU in the monitor based on FORMAT ID in the monitor system of FIG. It is a figure which shows the example of a change for Quad Link HD-SDI signal input.

Explanation of symbols

  1 monitor, 2a to 2d slot, 3a to 3d ID decoder, 4 registers, 5 selector, 6a to 6d memory, 7 demultiplexer, 8 matrix circuit, 9 OSD (on-screen display) circuit, 10 superposition circuit, 11 LCD (liquid crystal) Display), 12 CPU, 20 Monitor, 21a, 21b Multiplexer, 30 Single Link Option Board, 31 Selector, 32 Register, 50 Single Link Option Board, 51 Cable Equalizer, 52 Deserializer, 53 Demultiplexer

Claims (10)

In a video display device having slots for mounting N (N is an integer of 2 or more) option boards for demultiplexing after converting a serially transmitted 1-channel video signal into a parallel transmission standard signal,
A memory for performing phase alignment of N-channel parallel signals sent from the N option boards mounted in the slot;
A video display device comprising: a demultiplexer that restores a video signal transmitted as a serial signal for N channels by demultiplexing parallel signals of N channels phase-matched by the memory. The video display device according to claim 1,
A multiplexer further returning each of the N channel parallel signals sent from the N option boards mounted in the slots to a signal of the parallel transmission standard by multiplexing the signals;
The video display device, wherein the N-channel parallel transmission standard signal output from the multiplexer is phase-matched by the memory. The video display device according to claim 1,
A decoding circuit for decoding identification information of a signal format superimposed on a video signal from a parallel signal sent from the option board;
The video display apparatus, wherein the demultiplexer restores a video signal having a signal format that matches a signal format indicated by the identification information decoded by the decoding circuit. The video display device according to claim 1,
A decoding circuit for decoding the identification information of the signal format superimposed on the video signal from the parallel signal sent from the option board;
According to the identification information decoded by the decoding circuit, the number of the option boards to be installed in the slot and / or information on the serial signal to be input to each option board installed in the slot is displayed on the screen. An image display device further comprising a control circuit. The video display device according to claim 1,
A decoding circuit for decoding the identification information of the signal format superimposed on the video signal from the parallel signal sent from the option board;
When the identification information decoded by the decoding circuit indicates that the video signal is transmitted as a serial signal for N channels, the parallel transmission is performed to the option board mounted in the slot. A video display device, further comprising a control circuit for sending a control signal for outputting a standard signal without demultiplexing. The video display device according to claim 1,
The option board converts a 1-channel HD-SDI signal into a parallel transmission standard signal and then demultiplexes the signal.
The memory performs phase alignment of two channels of parallel signals sent from the two option boards mounted in the slot,
The demultiplexer 4, by demultiplexing the parallel signals of two channels that are phasing in the memory, are transmitted as Dual Link HD-SDI signal by the _{SMPTE372M: 4: 4RGB / YC B} C R signals or 148 4 .5MHz: 2: image display apparatus characterized by restoring the _2YC B _{C R} signal. An option board for demultiplexing after converting a serially transmitted 1-channel video signal into a parallel transmission standard signal;
In a video display system configured with a video display device having a slot for mounting N (N is an integer of 2 or more) of the option boards,
The optional board is
A selection circuit for selecting whether to output the signal of the parallel transmission standard by demultiplexing or not demultiplexing,
The video display device
A decoding circuit for decoding the identification information of the signal format superimposed on the video signal from the parallel signal sent from the option board;
When the identification information decoded by the decoding circuit indicates that the video signal is transmitted as a serial signal for N channels, the parallel transmission is performed to the option board mounted in the slot. A control circuit for sending a control signal for controlling the selection circuit to output a standard signal without demultiplexing;
A memory for performing phase alignment of N-channel parallel signals sent from the N option boards mounted in the slot;
A video display system comprising: a demultiplexer that restores a video signal transmitted as a serial signal for N channels by demultiplexing the N channel parallel signals phase-matched by the memory. The video display system according to claim 7,
The video display system, wherein the demultiplexer of the video display device restores a video signal having a signal format that matches the signal format indicated by the identification information decoded by the decoding circuit. The video display system according to claim 7,
The video display device
According to the identification information decoded by the decoding circuit, the number of the option boards to be installed in the slot and / or information on the serial signal to be input to each option board installed in the slot is displayed on the screen. A video display system further comprising a control circuit. The video display system according to claim 7,
The option board converts a 1-channel HD-SDI signal into a parallel transmission standard signal and then demultiplexes the signal.
The memory of the video display device performs phase alignment of parallel signals of two channels sent from the two option boards mounted in the slot,
The demultiplexer of the video display device is transmitted as a Dual Link HD-SDI signal by SMPTE 372M by demultiplexing two-channel parallel signals phase-matched by the memory, and 4: 4: 4 RGB / YC _B C _R signal or 148.5MHz of 4: 2: image display system, characterized in that to restore the _2YC B _{C R} signal.

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