JP2008236039A - Signal change detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the operation abnormality or the like of a system with a simple configuration without using a counter circuit and to contribute to the improvement of system reliability. <P>SOLUTION: The signal change detection circuit for detecting the change of input signals comprises: an MOS inverter 10 connected between a first power supply end (Vdd) and a second power supply end (Vss), wherein signals from an inspection object system are inputted to an input end; and a resistance change element 20 connected between a reference voltage end (Vref) set to a voltage between the respective voltages of the first and second power supply ends and the output end of the inverter 10, wherein a resistance value is controlled by the direction of voltage application. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal change detection circuit that detects an abnormal operation of a system by detecting a change in a signal input from the system.

  In recent years, there is a concern that faults due to noise, process variations, and the like increase due to miniaturization of elements used in LSIs and a decrease in power supply voltage. In particular, in space use, medical equipment, and systems such as financial institutions, high reliability is required. Therefore, when a fault occurs, it is necessary to detect it and take some measures.

  Conventionally, a circuit configuration called a watchdog timer is known as a fault detection circuit that detects when a fault occurs during system operation. This is because a free counter is prepared, a program is set up to reset it every fixed time, and when the counter overflows without being reset even if the scheduled time is exceeded, the system will fail. (For example, refer patent document 1).

However, this type of watchdog timer has the following problems. That is, a counter circuit is used to configure the watchdog timer, and the counter circuit requires at least one flip-flop to express one bit. For this reason, there is a problem that the circuit scale becomes large in order to measure the necessary time.
JP-A-2-236742 S. Kaeriyama et al., IEEE J. Solid-State Circuits., Vol. 40, No. 1, p. 168-176., Jan. 2005.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to detect system malfunctions and the like with a simple configuration without using a counter circuit or the like, and to improve system reliability. Another object is to provide a signal change detection circuit that can contribute to the above.

  In order to solve the above problems, the present invention adopts the following configuration.

  That is, one aspect of the present invention is a signal change detection circuit that receives a signal from a system and detects a system abnormality or the like, and includes a first power supply terminal (Vdd) and a second power supply terminal (Vss). And a reference voltage terminal (Vref) set to a voltage between the voltages of the first and second power supply terminals, and a MOS inverter connected between the first and second power supply terminals. And a variable resistance element connected between the output terminal of the inverter and having a resistance value controlled in the direction of voltage application.

  Another aspect of the present invention is a signal change detection circuit that detects a system abnormality by inputting a signal from the system, and includes a first power supply terminal (Vdd) and a second power supply terminal (Vss). ), A gate connected to the output terminal of the MOS inverter, a source connected to the voltage of the first power supply terminal and the first power source terminal. Connected to a reference voltage terminal (Vref) set to a voltage between the two power supply terminals, a load resistor is connected to the drain, and a voltage application direction between the gate and the reference voltage terminal is determined. And a nonvolatile memory element whose threshold value changes.

  According to the present invention, by using a MOS inverter and a resistance change element or a memory element, it is possible to detect a change in an input signal due to a system abnormality or the like. For this reason, it is possible to detect a system operation abnormality or the like with a simple configuration without using a counter circuit or the like, which can contribute to improvement of system reliability.

  The details of the present invention will be described below with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a circuit diagram showing a signal change detection circuit according to the first embodiment of the present invention.

  A p-channel MOS transistor 11 (hereinafter abbreviated as pMOS) and an n-channel MOS transistor 12 (hereinafter abbreviated as nMOS) are connected in series to form a CMOS inverter 10. The drain of the pMOS 11 is connected to the first power supply terminal (Vdd), and the source of the nMOS 12 is connected to the second power supply terminal (Vss). A signal from an inspection target system to be inspected for a failure or the like is input to an input terminal of the inverter 10 which is a common gate of the pMOS 11 and the nMOS 12. One end of the variable resistance element 20 is connected to the output terminal of the inverter 10, and the other end of the variable resistance element 20 is connected to the reference voltage terminal (Vref).

  Here, the resistance change element 20 is a resistance change type two-terminal memory element whose resistance value changes according to an applied voltage. Further, the relationship between the voltages Vdd, Vss, and Vref of each part is Vdd> Vref> Vss.

  Further, since the circuit of this embodiment can be realized by two transistors (pMOS11, nMOS12) and one memory element (resistance change element 20), the circuit can be made smaller than the conventional method. Furthermore, the circuit area can be further reduced by three-dimensionally arranging the variable resistance element 20 above the transistor. At this time, the resistance change element 20 may be provided above the semiconductor circuit, may be placed in a wiring layer, or may be formed in a via between the wirings.

  FIG. 2 is a block diagram showing an example in which the signal change detection circuit of this embodiment is used as a watchdog timer. A signal for failure detection is output from the inspection target system 100, and this signal is input to the watchdog timer 200. That is, a signal for failure detection is input to the input terminal of the inverter 10 in FIG. If the operation of the system 100 is normal, the signal for detecting the failure is, for example, a periodic pulse signal (for example, duty ratio 1). If the operation of the system 100 becomes abnormal, no pulse is output, and Low It is a signal as it is. When an operation abnormality occurs in the system 100, the abnormality is detected by the watchdog timer 200, and the operation abnormality of the system 100 can be detected from the output of the watchdog timer 200.

  In the configuration of the signal change detection circuit shown in FIG. 1, the direction of the current flowing through both ends of the resistance change element 20 can be changed according to the input value. That is, when a voltage of Vss is applied to the input, the pMOS 11 is turned on and the nMOS 12 is turned off, so that a current flows through the resistance change element 20 from Vdd to Vref as shown in FIG. On the other hand, when a voltage of Vdd is applied to the input, the pMOS 11 is turned off and the nMOS 12 is turned on, so that a current flows through the resistance change element 20 from Vref to Vss as shown in FIG. become.

The resistance change element 20 can change the resistance value depending on the direction of voltage applied to both ends thereof, that is, the direction of current. For example, Cu ₂ described in Non-Patent Document 1 (S. Kaeriyama et al., IEEE J. Solid-State Circuits., Vol. 40, No. 1, p. 168-176., Jan. 2005.). A memory element using S is given. However, the present invention is not limited to this, and any device that can program the resistance in the direction of current is acceptable. Many other memory devices have been reported at present. For example, giant magnetoresistance such as spin injection MTJ using electron spin, Ag ₂ S, ZnxCd _1-x S, Ag—Ge—Se system, Pr _0.7 Ca _0.3 MnO _3, etc., which are known as resistance variable memory elements Substances that exhibit effects, such as NiOx, TiOx, HfO ₂ , ZrO ₂ , SrZrO ₃ , SrTiO _3, etc. are candidates.

  By the way, these resistance change type memory elements can change the time until programming depending on the magnitude of the voltage or current applied to both ends thereof. For example, Non-Patent Document 1 described above describes that the time required for the memory element to change from the low resistance state to the high resistance state varies depending on the magnitude of the voltage. The operation of this embodiment will be described below according to this phenomenon.

  Here, assuming that the initial state is the low resistance state, the resistance change element 20 is in the high resistance state in the direction in which current flows from Vdd to Vref, and the resistance change element 20 is in the low resistance state in the direction in which current flows from Vref to Vss. Of course, this is not limited to this. The initial state can be operated in the high resistance state, or the state change of the resistance change element 20 and the direction of current may be set in reverse.

  In the normal state, Vss is given to the input. Then, since the pMOS 11 is turned on, the current flows from Vdd to Vref. At this time, since the resistance change element 20 is in a high resistance state, if the state is maintained as it is, the resistance change after a predetermined time according to the magnitude of the voltage applied to both ends of the resistance change element 20. The element 20 is rewritten to a high resistance state. However, before the input is inverted from Vss to Vdd, the pMOS 11 is turned off and the nMOS 12 is turned on, so that the current flow is switched in the direction from Vref to Vss so that the resistance change element 20 is in a low resistance state. A voltage is given.

  That is, the state of the resistance change element 20 can be reset by switching from the state in which the resistance value of the resistance change element 20 is rewritten to the state of being held. If a problem occurs on the system side that provides the input, and the signal for switching the input cannot be obtained, the resistance change element 20 is rewritten to a high resistance state, and thus the state of the resistance change element 20 is observed. Can detect a system failure.

  In practice, an operation is usually performed in which an input is given in a direction in which the resistance value of the resistance change element 20 is rewritten, and an operation of giving a reverse input is performed earlier than the rewrite to restore the state of the resistance change element 20 By doing so, it is possible to monitor the state of the system. That is, if the state of the resistance change element 20 changes, it can be determined that there is some abnormality in the system.

  When a voltage of Vdd or Vss is applied to the input, voltages of Vdd−Vref and Vref−Vss are applied to both ends of the pMOS 11 and nMOS 12 at the maximum. Since these are smaller than Vdd-Vss, ideally each transistor operates in a so-called linear region. FIG. 3 shows this state simply as resistance.

  When the resistances of the pMOS 11 and the nMOS 12 at this time are Rp and Rn and the resistance of the memory element (resistance change element 20) is Rm, the current flowing through the resistance change element 20 when the pMOS 11 is on is shown in FIG. As shown in (4), (Vdd−Vref) / (Rp + Rm). On the other hand, the current flowing through the resistance change element 20 when the nMOS 12 is on is (Vref−Vdd) / (Rn + Rm) as shown in FIG. Since the time until the resistance state of the variable resistance element 20 is switched depends on the magnitude of the flowing current, this value is adjusted so as to obtain a desired time limit. Rp and Rn can be changed by adjusting the size of the transistor, such as channel length and channel width, and parameters such as threshold voltage. Rm can also be adjusted by selecting the size and material of the variable resistance element 20. Vdd, Vss, and Vref are set so as to obtain a desired operation.

The time interval for resetting the variable resistance element 20 depends on the fault rate and the operating frequency. If the probability of causing a fault in one clock operation is p and the operating frequency of the system is f, the time that a fault is expected to occur once is 1 / pf. For example, if p = 10 ⁻⁶ and f = 10 ⁹ , the fault is expected to occur once in 1 ms, so that the resistance change element 20 is reset once in a shorter time interval such as 0.1 ms. It is good to set as follows. If p = 10 ⁻⁹ , the fault is expected once every 1 s. Therefore, the resistance value and voltage are set so that the resistance change element 20 is reset once every 0.1 s. These are examples and do not mean that the reset interval must be shorter than the expected value causing the fault.

  When the reset operation of the resistance change element 20 performed periodically is shorter than the time for applying the memory rewrite voltage, a current value that can sufficiently reset the state of the resistance change element 20 in the short time is desired. On the contrary, when the current cannot be taken so much, it can be dealt with by adjusting the time for applying the reset voltage and setting it longer in some cases. That is, as the input voltage of the present embodiment, a signal for resetting the resistance change element 20 (for example, High level) and a normal signal for rewriting the resistance change element 20 (for example, Low level) are alternately input. However, the ratio of the High time to the Low time does not have to be 50%. The entire period is set to be an interval for resetting the variable resistance element 20.

  Reading the state of the resistance change element 20 can be realized by looking at the voltage of the node (output) connecting the resistance change element 20 and the transistor. 4 assumes that the resistance value of the resistance change element 20 is 1 MΩ and 100Ω in the high resistance state and the low resistance state, respectively, and the current flowing through the transistor when the resistance change element 20 is in the low resistance state is about 0.5 mA. This is a simulation of the difference in output voltage with respect to the input voltage when assumed. As shown in FIG. 4, it can be seen that there is a large difference in the output voltage value due to the difference in the resistance value of the variable resistance element 20. By reading this difference, the state of the resistance change element 20 can be known.

  FIG. 5 shows an example of a circuit for reading out the voltage difference and the input voltage-output voltage characteristics. Although the circuit diagram is a CMOS inverter 30, the logic inversion voltage is moved by adjusting the sizes of the pMOS and nMOS. By setting the logic inversion voltage between the output voltage of the resistance change element 20 in both the high resistance state and the low resistance state, the difference in output voltage can be distributed between the Vdd and Vss voltages. Can be processed by a digital circuit.

  5, when the channel length / channel width of the pMOS is (1 μm / 1 μm and the channel length / channel width of the nMOS is (0.2 μm / 1 μm), the logic inversion voltage is 0.6 V. When the channel length / channel width is (0.2 μm / 2.6 μm) and the nMOS channel length / channel width is (0.2 μm / 1 μm), the logic inversion voltage is 0.9 V. pMOS channel length / When the channel width is (0.2 μm / 2.6 μm) and the channel length / channel width of the nMOS is (1 μm / 0.5 μm), the logic inversion voltage is 1.1 V. For example, the logic inversion voltage is 0. By using the 6V inverter 30, it can be determined from the voltage at the output terminal of the inverter 10 when the input voltage is High whether the resistance change element 20 is in the low resistance state or the high resistance state. It can be.

  In addition to changing the logic inversion voltage, the impurity distribution of each transistor is adjusted to change the threshold value and the amount of current, or, as shown in FIG. 6, the input is only the pMOS 31 or the nMOS 32, and the pMOS 31 or the nMOS 32 is changed. This can also be realized by adjusting the load applied to a fixed value. Furthermore, as shown in FIG. 7, it can also be realized by adding a load resistance to the power supply side from the pMOS 31 and the nMOS 32.

  FIG. 6A shows a case where a load voltage (fixed value) is input to the gate of the pMOS 31 and an output of the inverter 10 is input to the gate of the nMOS 32. In FIG. 6B, the load voltage (fixed value) is input to the gate of the nMOS 32, and the output of the inverter 10 is input to the gate of the pMOS 31. FIG. 7A shows a load resistor 33 connected between the pMOS 31 of the inverter 30 and the first power supply terminal (Vdd). FIG. 7B shows a load resistor 34 connected between the nMOS 12 of the inverter 30 and the second power supply terminal (Vss). Any of the above circuits can be used as the output circuit of the signal change detection circuit.

  As described above, according to this embodiment, it is possible to detect an abnormal operation of the system with an extremely simple configuration using only the MOS inverter 10 and the resistance change element 20. That is, a watchdog timer that detects a system failure can be realized in a small size. Further, since the circuit is reduced in size, this circuit can be arranged at a plurality of locations in the system, and the reliability of the system can be further improved.

(Second Embodiment)
FIG. 8 is a circuit configuration diagram showing a signal change detection circuit according to the second embodiment of the present invention. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and the detailed description is abbreviate | omitted.

  This embodiment is different from the first embodiment described above in that a three-terminal memory element 50 having a structure like a flash memory (EEPROM) is used instead of the resistance change element 20. That is, the three-terminal memory device 50 has a two-layer gate configuration having a floating gate and a control gate, the control gate is connected to the output terminal of the inverter 10, the source is connected to the reference voltage terminal (Vref), and the drain. Is connected to a load resistor 61.

  Usually, a three-terminal memory device 50 such as a flash memory requires a high voltage for writing / erasing, and a booster circuit is used for this purpose. In order to use this type of three-terminal memory device 50 in the voltage range from 0 volts to (Vdd-Vss), Vdd is increased, Vss is decreased, or the floating gate is connected between the channel and the floating gate. Therefore, it is necessary to design the tunnel insulating film with a small thickness or a combination thereof.

  Specifically, depending on what structure or material is used for the three-terminal memory element 50, for example, the tunnel insulating film is about 2 nm, Vdd is 5 V, Vss is 0 V, Vref is 2.5 V, etc. Alternatively, in order to shorten the time for writing and erasing, it is conceivable that Vref is shifted from 2V or 3V to an intermediate value. In order to use in the voltage range from Vdd to Vss, it is necessary to reduce the thickness of the tunnel insulating film as described above. Therefore, it is necessary to set the reset time within a short time, for example, 0.1 ms or less. . Alternatively, in the case of a three-terminal memory, the change in threshold value changes gradually rather than abruptly. Therefore, the reset time can also be adjusted by adjusting the threshold value of the circuit that reads the output.

  In the configuration of this embodiment, when a voltage of Vdd is applied to the input, the pMOS 11 is turned off and the nMOS 12 is turned on, so that the voltage Vref−Vss is applied between the source and gate of the three-terminal memory element 50 from the source. It depends on the direction of the gate. When a voltage of Vss is applied to the input, the pMOS 11 is turned on and the nMOS 12 is turned off, so that a voltage of Vdd−Vref is applied between the source and gate of the three-terminal memory element 50 in the direction from the gate to the source.

  Hereinafter, when the voltage Vref−Vss is continuously applied between the source and the gate of the three-terminal memory element 50, the threshold value between the source and the drain of the three-terminal memory element 50 decreases (low threshold state). The operation of this circuit will be described on the assumption that the threshold voltage between the source and the drain increases (high threshold state) when a voltage of Vdd-Vref is continuously applied between the source and the gate. However, the present invention is of course not limited to this, and the circuit can be operated even when the voltage direction and the memory characteristics are reversed.

  A three-terminal memory device 50 having a two-layer gate configuration having a floating gate and a control gate is a memory that changes a threshold voltage between a source and a drain by charges accumulated in the floating gate. In general, the voltage for accumulating charges and the read voltage are usually in the same direction, and the voltage to be erased is in the opposite direction. Since the circuit needs to have the same voltage for changing the state and the read voltage, the operation of the circuit using the three-terminal memory element 50 is changed from the low threshold state to the high threshold state. Limited. Even if the erase voltage and the read voltage are in the same direction and the charge storage voltage is in the opposite direction, this is limited to the operation from the high threshold state to the low threshold state. It is done.

  When the initial state is the low threshold state and Vss is input, a voltage of Vdd−Vref is applied from the gate of the three-terminal memory element 50 to the source. If the state is kept as it is, electric charges are accumulated in the floating gate, the state is shifted to a high threshold state, and no current flows, so the voltage applied to the output resistance is reduced. If the input voltage is inverted to Vdd before shifting to the high threshold state, the floating gate of the three-terminal memory device 50 has no charge and the low threshold state is maintained. In practice, it is possible to determine whether or not there is a failure in the system connected to the input by periodically performing an operation of switching the input voltage and determining whether or not a shift to the high threshold state occurs.

  Further, if the low threshold state is set to a sufficiently low threshold such that a leakage current is generated between the source and the drain, it is possible to avoid a restriction on the operation direction of the threshold state. In other words, the peak current is generated in the low threshold state and the leakage current is decreased in the high threshold state. Therefore, by reading the magnitude of the leakage current, the low threshold state can be obtained without applying the read voltage. It is possible to know whether the threshold value is high. For example, when the initial state is a high threshold state and Vdd is input to the input, a voltage of Vref−Vss is applied from the source of the three-terminal memory element 50 to the gate. If the state is kept as it is, the electric charge of the floating gate is released, the state shifts to a low threshold state, and a leak current flows, so that the voltage applied to the output resistance increases. If the input voltage is inverted to Vss before shifting to the low threshold state, charges are accumulated in the floating gate of the three-terminal memory device 50, and the high threshold state is maintained.

  Actually, it is possible to determine whether or not there is a failure in the system connected to the input by periodically performing the operation of switching the input voltage and determining whether or not the shift to the low threshold state occurs. Of course, in this case as well, it is possible to operate this circuit by changing from the low threshold state to the high threshold state, and even if the direction of the voltage and the direction of the threshold state are reversed, It is possible to operate this circuit.

  The failure determination can be performed by reading the voltage applied to the output resistor 61. Further, the method for reading the output voltage is the same as that in the first embodiment, and is therefore omitted.

  As described above, according to the present embodiment, it is possible to detect an abnormal operation of the system with a very simple configuration using only the MOS inverter 10 and the three-terminal memory element 50. Therefore, the same effect as the first embodiment can be obtained.

(Modification)
In addition, this invention is not limited to each embodiment mentioned above. The directions of voltage and current described in the embodiment are examples used for the description, and do not limit the scope of the present invention. Further, the resistance change element may be any element as long as its resistance value changes depending on the direction of voltage application, and particularly any element that can program the resistance value in the direction of voltage application. Further, the three-terminal memory element is not necessarily limited to a non-volatile memory element having a two-layer gate structure, and may be any element that can control the threshold value according to the direction of the voltage applied to the gate.

  In addition, the present invention is not necessarily limited to detection of system operation abnormality (failure detection), and may be applied to the case where it is detected that there is some change in the signal from the system even if there is no system abnormality. Is possible. In addition, various modifications can be made without departing from the scope of the present invention.

The circuit block diagram which shows the signal change detection circuit concerning 1st Embodiment. The block diagram which shows the example which used the signal change detection circuit of 1st Embodiment as a watchdog timer. The schematic diagram which shows the mode of the electric current which flows into the resistance change element used for 1st Embodiment. The figure which shows the result of having simulated the difference of the output voltage with respect to the input voltage of the resistance change element used for 1st Embodiment. The figure which shows an example of the circuit which reads the difference in the output voltage in 1st Embodiment, and its input voltage-output voltage characteristic. The circuit block diagram which shows an example of the output circuit used for 1st Embodiment. The circuit block diagram which shows the other example of the output circuit used for 1st Embodiment. The circuit block diagram which shows the signal change detection circuit concerning 2nd Embodiment.

Explanation of symbols

10 ... CMOS inverter 11 ... p-channel MOSFET
12 ... n-channel MOSFET
20 ... variable resistance element (two-terminal memory)
30 ... CMOS inverter 31 ... p-channel MOSFET
32 ... n-channel MOSFET
33 ... Load resistance 34 ... Load resistance 50 ... Three-terminal memory element 61 ... Load resistance 100 ... System to be inspected 200 ... Watchdog timer

Claims (7)

A MOS inverter connected between the first power supply terminal (Vdd) and the second power supply terminal (Vss), and a signal from the system under test is input to the input terminal;
Connected between a reference voltage terminal (Vref) set to a voltage between the voltages of the first and second power supply terminals and the output terminal of the inverter, and the resistance value is controlled in the direction of voltage application. A resistance change element;
A signal change detection circuit comprising:   The resistance change element has a resistance value that changes from an initial value to another value by applying a voltage in one direction for a predetermined time or more, and the resistance value is reset to an initial value by applying a voltage in the reverse direction. The signal change detection circuit according to claim 1. A MOS inverter connected between the first power supply terminal (Vdd) and the second power supply terminal (Vss), and a signal from the system under test is input to the input terminal;
The gate is connected to the output terminal of the MOS inverter, and the source is connected to a reference voltage terminal (Vref) set to a voltage between the voltage of the first power supply terminal and the voltage of the second power supply terminal, A non-volatile memory device having a drain connected to a load resistor and a threshold value changing according to a direction of voltage application between the gate and the reference voltage end;
A signal change detection circuit comprising:   The memory element is configured such that a threshold value changes from an initial value by applying a voltage to the gate for a predetermined time or more, and the threshold value is reset to an initial value by applying a voltage in the reverse direction to the gate. The signal change detection circuit according to claim 3, wherein:   4. The signal change detection circuit according to claim 1, wherein the resistance change element or the memory element is laminated on the inverter.   4. The signal change detection circuit according to claim 1, further comprising an output circuit that is connected to an output terminal of the inverter or an output terminal of the memory element and determines a state of the resistance change element or the memory element. 5.   The system to be inspected continuously outputs a signal in a direction in which the resistance value or threshold value fluctuates to a setting value different from the initial value when the system is normal, and the resistance value or threshold value. 5. The signal change detection circuit according to claim 2, wherein a pulse in a direction for returning the resistance value or the threshold value to an initial value is output before the value changes to the set value.

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