JP2008235704A - Semiconductor element and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element capable of programming a logic operation and being operated as a nonvolatile memory element as well. <P>SOLUTION: The semiconductor element comprises: a substrate 2; a first insulation film 4 provided on the substrate; an electric resistance change film 6 provided on the first insulation film; a first electrode 8 provided on the first insulation film on the side of one of both side faces of the electric resistance change film in contact with one side face of the electric resistance change film; a second electrode 10 provided on the first insulation film on the side of the other one of both side faces of the electric resistance change film in contact with the other side face of the electric resistance change film; a second insulation film 12 provided on the electric resistance change film; and a third electrode 14 provided on the second insulation film. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor element and a semiconductor integrated circuit.

  As for the logic integrated circuit incorporated in various products, it is necessary to prepare dedicated integrated circuits for different products. For products that are in great demand, it is low-cost to design a dedicated semiconductor integrated circuit optimized for each such product, check its operation, and mass-produce it on a semiconductor manufacturing line. However, in the case of an integrated circuit for a product for which there is only a small amount of demand, there is a problem that the cost per chip becomes enormous if it is manufactured by the above method.

  On the other hand, in a device that uses a microcomputer and designs all logic operations by software, the device becomes large-scale. In this device, in addition to a CPU (Central Processing Unit) and a bus control circuit, which are logic circuits, a memory circuit having a manufacturing method different from that of the logic circuit must be prepared. Also, since the operation speed is slow, it is difficult to make a logic circuit that requires real-time operation such as connecting to an RF (Radio Frequency) circuit such as a mobile phone.

  Therefore, a semiconductor integrated circuit that allows a user to change an operation program of a logic circuit, such as an FPGA (Field Programmable Gate Array), has been proposed (see, for example, Patent Document 1), and the demand is increasing year by year.

  However, there is a problem in the semiconductor integrated circuit in which the user can change the operation program of the logic circuit.

  For example, a semiconductor integrated circuit that uses an SRAM (Static Random Access Memory) for a circuit portion that records the setting of an operation program for a logic circuit has the following two problems. First, SRAM requires a very large chip area, so the cost is very high. Second, a boot ROM (Read Only Memory) for writing logic operation settings onto the SRAM after power-on. Is necessary and does not stand up immediately.

  In addition, for example, in a semiconductor integrated circuit that uses a flash memory in a circuit portion that records setting of an operation program of a logic circuit, the manufacturing process of the logic circuit is different from the manufacturing process of the memory circuit. As a result, the semiconductor process conditions suitable for the logic circuit manufacturing are different from the semiconductor manufacturing process conditions suitable for the memory circuit manufacturing, so that both process conditions overlap. However, it is difficult to obtain high device performance and yield because it is necessary to select a very narrow range of process conditions, and such process conditions are not necessarily the optimum manufacturing processes for both manufactures. .

  In addition, for example, an antifuse in a circuit portion that records the setting of an operation program of a logic circuit, that is, an electrically insulated state in an initial state, but an irreversible dielectric breakdown is generated by applying a high voltage and electrically conducted. In the case of a semiconductor integrated circuit using an element that enters a state, the setting of the logic circuit operation can be written only once. Therefore, first, it is necessary to frequently check the operation of the circuit when designing the logic circuit, but a new integrated circuit must be used each time, so that the development cost increases. Second, in order to correct the problem of circuit operation found after being sold as a product, there is a problem that the semiconductor integrated circuit must be replaced.

  On the other hand, recently, ReRAM (Resistivity Random Access Memory) has been studied as a non-volatile memory that does not lose its memory even when power is turned off, such as flash memory and FeRAM (Ferroelectric Random Access Memory). .

  However, the memory element used in ReRAM basically has a resistance change material that retains a history of electrical resistance in a non-volatile manner even when the power is turned off, such as NiO, and sandwiches the resistance change between the two electrodes. The operation principle is such as recording and reading, and it is a two-terminal element. Two-terminal elements have industrial applications as memories, but tend to be poorly developed.

  An element in which two or more terminals are added to the resistance change material is disclosed in Patent Document 2, for example.

  However, although the element described in Patent Document 2 is intended to improve the operation as a memory element and has three terminals or four terminals, it is intended to operate as a memory element. Is not intended for use in logic integrated circuits.

Non-Patent Document 1 discloses a principle of resistance change of a resistance change material such as formation of a conductive filament in the resistance change material.
JP-A-6-295233 JP 2006-120702 A Kohei Fujiwara, Taku Nemoto, Yoshinobu Nakamura, Hidenori Takagi, Proceedings of the 67th Japan Society of Applied Physics, 31p-RA-3

  According to the principle of resistance change described in Non-Patent Document 1, the element described in Patent Document 2 detects a resistance change between electrodes different from that between the electrodes on which the filament is formed. It is found that there is a problem that even the operation as a memory element, which is the prospect of the technique described in Patent Document 2, is difficult.

  As described above, it can be repeatedly and reversibly programmed so that it can be used in an integrated circuit for logic, and the operation program of the logic circuit is non-volatile even when the power is turned off, and is also used as a non-volatile memory element. There is no known semiconductor element that can be used.

  The present invention has been made in consideration of the above circumstances, and the logic operation can be repeatedly and reversibly programmed, and the operation program of the logic circuit is non-volatile even when the power is turned off, and as a non-volatile memory element An object of the present invention is to provide a semiconductor device that can operate as well as a semiconductor integrated circuit having the semiconductor device as a logic circuit device.

  The semiconductor device according to the first aspect of the present invention includes an electrical resistance change film having first and second surfaces facing each other, and a third surface different from the first and second surfaces, and the electrical resistance change. A first electrode provided in contact with the first surface of the film; a second electrode provided in contact with the second surface of the electric resistance change film; and the third electrode of the electric resistance change film. And an insulating film provided in contact with the surface, and a third electrode provided with the insulating film sandwiched between the third surface of the electric resistance change film.

  The semiconductor device according to the second aspect of the present invention includes a substrate, a first insulating film provided on the substrate, an electric resistance change film provided on the first insulating film, and the electric resistance change. A first electrode provided on and in contact with the one side surface of the electric resistance change film on the first insulating film on one side surface of the both side surfaces of the film; A second electrode provided in contact with the other side surface of the electric resistance change film on the first insulating film on the other side surface; and a second insulating film provided on the electric resistance change film. And a third electrode provided on the second insulating film.

  A semiconductor device according to a third aspect of the present invention includes a substrate, a first insulating film provided on the substrate, a first electrode provided on the first insulating film, and the first electrode. A laminated film having an electric resistance change film provided on the first electrode, a second electrode provided on the electric resistance change film, a second insulating film covering a side surface of the laminated film, and sandwiching the second insulating film Thus, the third electrode provided on the side surface of the laminated film is provided.

  A semiconductor integrated circuit according to a fourth aspect of the present invention is characterized in that any of the semiconductor elements described above is used as a logic circuit element whose operation program can be reconstructed.

  According to the present invention, it is possible to provide a semiconductor element that can be programmed as a logic operation and that can also operate as a nonvolatile memory element, and a semiconductor integrated circuit that includes this semiconductor element as a logic circuit element.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
A cross section of the semiconductor device according to the first embodiment of the present invention is shown in FIG. In the semiconductor element 1 of this embodiment, an insulating film 4 is formed on a substrate 2, and an electric resistance change film 6 is formed in a part of the insulating film 4. A source electrode 8 and a drain electrode 10 are provided on the insulating film 2 on both sides of the electric resistance change film 6 so as to be in contact with the side surface of the electric resistance change film 6. In the electric resistance change film 6, a single low resistance filament 7 that leads from the source electrode 8 to the drain electrode 10 is formed. The low resistance filament 7 is formed by forming described later. A gate insulating film 12 is provided on the electric resistance change film 6, and a gate electrode is provided on the gate insulating film 12. An interlayer insulating film 16 is provided so as to cover the source electrode 8, the drain electrode 10, and the gate electrode 14, and the interlayer insulating film 16 is connected to the gate electrode 14, the source electrode 8, and the drain electrode 10, respectively. Contacts 18a, 18b and 18c are provided.

Next, a method for manufacturing the semiconductor element 1 of the present embodiment will be described with reference to FIGS. First, as shown in FIG. 2, the natural oxide film was peeled off by dilute hydrofluoric acid treatment on the silicon substrate 2 from which the (001) plane of the silicon single crystal was exposed. Subsequently, an HfSiON film as an insulating film 4 was formed on the silicon substrate 2 with a thickness of about 4 nm. As a film forming method, in this embodiment, a method is used in which co-sputtering is performed in argon, oxygen, and nitrogen using Hf and Si targets. However, a method of forming by using a CVD (Chemical Vapor Deposition) method using Hf [N (CH ₃ ) ₂ ] ₄ , SiH [N (CH ₃ ) ₂ ] ₃ and H ₂ O as raw materials is also well known. Alternatively, other methods may be used. In the present embodiment, HfSiON is used as the material of the insulating film 4. However, for example, SiO ₂ , SiON, Al ₂ O ₃ , HfAlO, LaAlO ₃ , or the like may be used. The insulating film 4 is preferably an insulating film in which a leak current does not flow much even when a high voltage is applied. Various materials can be used as the insulating film 4 as long as the material satisfies such conditions. It is preferable that the insulating film can withstand heat treatment at 800 ° C. or higher as required.

Next, as shown in FIG. 2, an Hf ₂ ON ₂ film is formed on the HfSiON film 4 as an electrical resistance change film 6 that retains a history of electrical resistance values in a nonvolatile manner even when the power is turned off. The film forming method is the same as the film forming method of the HfSiON film 4 except that a raw material containing Si is not used. Examples of the electrical resistance change film 6 that retains a history of electrical resistance values in a nonvolatile manner even when the power is turned off include Ni—O, Fe—O, Co—O, Cu—O, Zr—O, Hf—O, and Ti—O. , Nb-O, Cr-doped STO, Nb-doped STO, PCMO (Ca-doped PrMnO ₃ ), BIT (bismuth titanate), HfON, ZrON, TiON, NiON, FeON, CoON, CuON, NbON, etc. It is possible to use materials used for memory. Although the semiconductor element of the present embodiment uses the same material as that of the resistance change memory, the semiconductor element is not a resistance change element but a programmable element that can also be used for a logic circuit.

Next, a polycrystalline silicon film (not shown) was formed on the Hf ₂ ON ₂ film 6 to a thickness of about 50 nm. As a film forming method, a method in which a Si target is sputtered in argon is adopted, but the CVD method is also possible as described above. The laminated film composed of the Hf ₂ ON ₂ film 6 and the polycrystalline silicon film was subjected to spike annealing at 1100 ° C. to crystallize the Hf ₂ ON ₂ film 6. The crystals of the Hf ₂ ON ₂ film 6 were oriented so that the 111 direction was oriented in the film thickness direction, and the crystal grain size in the in-plane direction was 50 nm or more. The polycrystalline silicon film was removed from the laminated film by CDE (Chemical Dry Etching) using a gas such as CCl ₄ or CF ₄ to expose the crystallized Hf ₂ ON ₂ film 6. In addition, a method of immersing in a potassium hydroxide solution or hydrofluoric acid is possible. The inventors of the present application have found that such a crystal orientation is a characteristic of the Hf ₂ ON ₂ film 6, and since Zf ₂ ON ₂ has extremely similar chemical properties to each other. It is easily predicted that the same orientation can be realized by a similar means in the film, and a method for realizing the same orientation with other variable resistance materials is expected to be studied in the future. However, it is most preferable in the forming operation to be described later that the orientation like the Hf ₂ ON ₂ film 6 is realized as in the present embodiment, but the resistance change material other than the Hf ₂ ON ₂ film or the Zr ₂ ON ₂ film is used. Even if such an orientation cannot be realized, it can be used for a logic circuit. In the case of a resistance change material that cannot realize crystal orientation such as an Hf ₂ ON ₂ film or a Zr ₂ ON ₂ film, the polycrystalline silicon film is removed after performing the spike annealing after the polycrystalline silicon film is formed. Such a step for crystal orientation becomes unnecessary.

  Next, as shown in FIG. 2, an HfSiON film having a thickness of about 4 nm was formed on the electric resistance change film 6 as the gate insulating film 12. The film forming method is the same as that of the HfSiON film 4. Subsequently, a TaC film as a gate electrode film 14 was formed on the gate insulating film 12 to a thickness of about 100 nm. As a film forming method, a method of sputtering a TaC target in an argon atmosphere was used (FIG. 2). FIG. 2 is a schematic cross-sectional view and does not show the actual film thickness.

As the gate electrode film 14, it is possible to use an electrical conductor containing oxygen such as RuO ₂ , SrRuO ₃ , ReO _3, or LaCuO _{3 in} addition to TaC. Further, for example, single metal oxides such as IrO ₂ , NbO, MoO ₂ , OsO ₂ , RhO ₂ , and PtO ₂ , and perovskite-like composite metal oxides LaTiO ₃ , LaVO ₃ , SrFeO ₃ , CaVO ₃ , SrMoO ₃ , _{SrIrO 3, BaMoO 3, BaIrO 3} , BaRuO 3, CaMoO 3, CaNbO 3, SrNbO 3, BaNbO 3, KMoO 3, LaMnO 3, LaNiO 3, SrCrO 3, Pb 2 M 2 O 7, LiTi 2 O 4, YCoO 3 , ErCoO ₃ , LaCoO ₃ , Ln ₂ NiO ₄ (where Ln represents a lanthanoid element), La ₄ BaCu ₅ O ₁₃ , La ₅ SrCu ₆ O ₁₅ , Bi ₄ Se ₄ Cu ₅ O _{19 + y,} etc., pyrochlore composite oxide _a 2 _B 2 _{O 7-} (Wherein, A is Y, Ln (Ln is a lanthanoid element), Tl, In, Pb, Bi, B, indicates any of such Cd, B is Ti, V, Cr, Mn, Nb, Mo, Zr, Tc , Hf, Re, Ru, Rh, Pd, Os, Ir, Pt, Si, Ge, Sn, Ga, Sb or the like) or La _(2-x) Ba of a copper oxide high-temperature superconductor. _x CuO ₄ (x is a value that becomes a superconducting expression composition or an excessively doped composition region), La _(2-x) Sr _x CuO ₄ (x is a value that becomes a superconducting expression composition or an excessively doped composition region), YBa ₂ Cu _{3 O 7, YmBa 2 Cu 3} O 7 (Ym is Yb, Lu, Tm, Ho, _{etc.), Bi 2 Sr 2 Ca (} n-1) Cu n O (2n + 4) (n = 1,2,3), TlM _{2 Ca (n-1) Cu} n O (2n + 2.5) n is an integer from 1 to 5, M is Ba or _{Sr), Tl 2 M 2 Ca} (n-1) Cu n O (2n + 4) ( n is an integer from 1 to 3, M is Ba or Sr), HgBa _{2 Ca (n-1) Cu} n O (2n + 2) ( n is an integer from 1 to _{3), Nd (2-x} ) Ce x CuO 4, Sr (1-x) Nd x CuO 2, Sr (1- _x) Ba _x CuO ₂ (x is a value that becomes a superconducting expression composition or an overdoped composition region), La _1.6 Sr _0.4 CaCu ₂ O ₆ , La _1.7 Ca _1.3 Cu ₂ O _6, etc. Ba _(1-x) K _x BiO ₃ (x is a value that is a superconducting expression composition or an overdoped composition region), Sr ₂ RuO ₄ , BaPb _(1-x) Bi _x O ₃ , _{Bi (2-x) Gd x} Ru 2 O 7, La (1- _{) Sr x MnO 3, Zn (} 1-x) Li x V 2 O 4 and the _{like, SnO 2, TiO 2, Cu} 2 O of composition deviation oxide _{semiconductor, Ag 2 O, In 2 O} 3, Tl 2 O 3 , ZnO, BaTi (Nb) O ₃ , SrTi (Nb) O ₃ , LaCrO ₃ , WO ₃ , TlOF, and the like, and Mott insulator NiO, CoO that has been made to exhibit metallic electrical conduction by being doped. _{, CuO, Cr 2 O 3,} MnO, from _{(V (1-x) Cr} x) 2 O 3, Fe 3 O 4, VO 2, Ti 2 O 3, Ti n O (2n-1) (n is 3 An integer up to 6) or EuO _x (Gd) of an f-electron electric conductor (x is a value of 1.5 or more and 2 or less) is also possible. For example, HfAlN, HfN, ZrN, ZrAlN, TiN, TiAlN, HfB, HfC, TaB, TaC, TaN, WB, WC, WN, ReB, ReC, ReN, OsB, OsC, OsN, IrB, IrC, IrN. , PtB, PtC, PtN, RuB, RuC, RuN, RhB, RhC, RhN, PdB, PdC, PdN, LnB ₆ (Ln is a lanthanoid element), LnC (Ln is a lanthanoid element), LnN (Ln is a lanthanoid element), ZrB, ZrC, NbB, NbC, NbN, MoB, MoC, MoN, TiB, TiC, VB, VC, VN, CrB, CrC, CrN, MnB, MnC, MnN, FeB, FeC, FeN, CoB, CoC, CoN, NiB, NiC, NiN, HfSi, ZrSi, TiSi, aSi, WSi, ReSi, OsSi, IrSi, PtSi, NbSi, MoSi, RuSi, RhSi, PdSi, VSi, CrSi, MnSi, FeSi, CoSi, NiSi, LnSi (Ln is a lanthanoid element), Hf, Zr, Ti, Ta, It is also possible to use W, Re, Os, Ir, Pt, Nb, Mo, Ru, Rh, Pd, V, Cr, Mn, Fe, Co, Ni, or the like. These gate electrodes are required to withstand a heat treatment temperature of approximately 800 ° C. required for semiconductor processes.

Next, after forming a hard mask (not shown) on the gate electrode film 14 made of TaC, the stacked film made of the gate electrode film 14, the gate insulating film 12, and the electric resistance change film 6 is formed into a gate shape by using CDE. Then, a gate structure including the gate electrode film 14, the gate insulating film 12, and the electric resistance change film 6 was formed (see FIG. 3). By this patterning, the electrical resistance change film 6 made of Hf ₂ ON ₂ was removed by etching to half or more of the film thickness.

  Next, a source electrode 8 and a drain electrode 10 were formed on the side portion of the electrical resistance change film 6 by depositing Pt by, for example, a collimated sputtering method (see FIG. 4). Subsequently, an interlayer insulating film 16 was formed on the entire surface of the substrate 2 so as to cover the source electrode 8, the drain electrode 10, and the gate structure. Thereafter, contact holes to the gate electrode 14, the source electrode 8, and the drain electrode 10 are formed in the interlayer insulating film 16, and metal is buried in these contact holes to form contacts 18a, 18b, and 18c (FIG. 5). reference). Subsequent processes are the same as those after the wiring process of a normal semiconductor integrated circuit.

After forming a package on the chip of the semiconductor element manufactured by the above method, forming was performed by applying a forming voltage of about 20 V between the source electrode 8 and the drain electrode 10 in each element on the chip. By ending the forming, the semiconductor element of this embodiment can exhibit its original function. In this forming process, the effect of crystallizing the Hf ₂ ON ₂ film 6 in an oriented state appears. That is, forming is an operation of forming a filament 7 having a low electrical resistivity between the source electrode 8 and the drain electrode 10 in the variable resistance material having a high electrical resistivity in the initial state (see FIG. 1). The filament 7 is formed so as to extend from the source electrode 8 and the drain electrode 10 as shown in FIG. 6A, and the extended filament has a diameter of about 1 nm or less as shown in FIG. 6B. It becomes the structure connected by a thin wire | line part.

  Once the filament 7 is formed by forming, the filament 7 switches between a high resistance state and a low resistance state by a voltage applied to both ends of the filament 7, that is, a voltage applied between the source electrode 8 and the drain electrode 10. It becomes like this. The high resistance state here is characterized in that the resistivity is lower than the electrical resistivity before the filament 7 is formed.

The Hf ₂ ON ₂ film functions as the electric resistance change film 6, but due to the characteristics of the crystal structure of Hf ₂ ON ₂ , the direction in which dielectric breakdown is likely to occur as shown in FIGS. 7 (a) and 7 (b). is there. When the method for producing the crystal structure of Hf ₂ ON ₂ of this embodiment is used, the 111 direction of the Hf ₂ ON ₂ crystal is oriented in the film thickness direction as shown in FIG. As shown, the 111 direction, such as the 11-1 direction, which forms an angle of about 71 degrees with respect to the 111 direction, and an equivalent direction on the crystal structure have an angle of about 19 degrees with respect to the in-plane direction. That is, there is an advantage that the path where the dielectric breakdown is easy becomes the direction connecting the source electrode 8 and the drain electrode 10 and the formation of the filament 7 in the unintended direction can be suppressed. That is, the first electrode (source electrode) 8 provided in contact with the first surface of the electric resistance change film 6 and the second surface opposite to the first surface of the electric resistance change film are provided. The direction connecting the second electrode (drain electrode) 10 is an easy dielectric breakdown direction, and the filament 7 is formed in this direction. At this time, the distance between the source electrode 8 and the drain electrode 10 is about three times that of the film thickness of the source electrode 8 and the drain electrode 10, that is, more than 1 / tan ⁻¹ (19 °) times. In this case, since the easy breakdown direction has an angle of about 19 degrees with respect to the film surface direction, the easy breakdown path is in the direction connecting the source electrode 8 and the drain electrode 10 due to the geometric limitation. Not formed. For this reason, when Hf ₂ ON ₂ is used as the resistance change film, the distance between the source electrode 8 and the drain electrode 10 needs to be three times or less of the electrode film thickness.

  The HfSiON film 4 and the HfSiON film 12 have an action of relaxing an electric field applied from the source electrode 8 to the gate electrode 14 or from the drain electrode 10 to the gate electrode 14 during forming. By the presence of these HfSiON films 4 and 12, unintended filament formation between these electrodes can be reliably suppressed.

FIG. 9 shows the operation of the circuit caused by applying a voltage for forming. In the structure shown in FIG. 5, a forming voltage V _F = 20 V shown in FIG. 9 is applied between the source electrode 8 and the drain electrode 10. However the optimum value of the forming voltage V _F by size and material and the peripheral circuit elements, such as thickness because 20V is changed. Nevertheless, the magnitude relationship of V _F > V _S > V _R > V _U does not depend on the size of the device. Here the voltage setting to the low resistance state to the V _S, the voltage for resetting the V _R to the high resistance state, the V _U is the voltage sense to use for logic operation. Each of these values varies depending on the element size, material, peripheral circuit, and the like.

By applying the forming voltage V _F = 20 V, a filament is generated in the electric resistance change film 6 along the path r1 from the initial state S in FIG. Thereafter, when the application of the forming voltage V _F = 20 V between the source electrode 8 and the drain electrode 10 is stopped, the low resistance filament 7 shown in FIG. 1 is left between the source electrode 8 and the drain electrode 10. The electric resistance change film 6 remains in a low resistance state. That is, the state L shown in FIG.

  The semiconductor element thus manufactured can be provided to the developer of the logic circuit dedicated to each product in the stage where the forming is completed, that is, in the state shown in FIG. 1 or the L state shown in FIG. A basic or general logic circuit can be set in advance and then provided to the developer of the logic circuit dedicated to each product, or the logic circuit can be provided in the S state of FIG. 9, that is, without forming. It is also possible for the developer of the logic circuit to perform the forming operation provided to the developer. At this time, a circuit for forming operation may be incorporated in advance as a peripheral circuit of the element of the present application, or a dedicated instrument having a circuit dedicated to forming operation may be provided separately. In the former case, there is an advantage that a dedicated instrument is unnecessary, but the circuit design that can withstand forming is complicated. In the latter case, there is an advantage that the design of the circuit including the element of the present application is easy and low cost, but the cost is increased for developers with low development frequency because the developer takes time and effort to form, and special equipment is required. It becomes.

Developer of each product only logic circuits, do not want to operate as a switch, i.e. for a transistor to be cut, for example, V _R as for example a reset voltage to the high resistance state between the source electrode 8 and the drain electrode 10 When the voltage is lowered after adding = 0.6 V, the state L in FIG. When an operation for applying such a reset voltage is performed, the resistance between the source electrode 8 and the drain electrode 10 is increased. At this time, the filament 7 between the source electrode 8 and the drain electrode 10 does not disappear, but the resistance is increased by partially disconnecting.

Although not always necessary, when the set voltage V _S = 1.8 V is applied between the source electrode 8 and the drain electrode 10 and then the voltage is lowered, the path r2 is traced from the state L after forming in FIG. After increasing the resistance, the resistance is decreased again by following the path r3, and the state returns to the state L while maintaining the low resistance state at V _S = 1.8V. In this case, the low resistance state remains between the source electrode 8 and the drain electrode 10, and the filament 7 remains unchanged.

As described above, after the semiconductor element of the present embodiment is set for use in the operation of the logic circuit, it is reversible but non-volatile. Therefore, the semiconductor element once set for the logic operation has a resistance value of the filament 7. The operation as a logic circuit changes unless a high voltage such as an alternative is applied between the source electrode 8 and the drain electrode 10 at a reset voltage V _R (= 0.6 V) or more and the logic operation is set again. There is nothing. In other words, the nonvolatile logic circuit can be programmed even when the power is turned off.

When reprogramming or program correction of the logic circuit is desired, a set voltage or a reset voltage is again applied between the source electrode 8 and the drain electrode 10. That is, when a transistor that has been programmed not to operate as a switch is to be programmed to operate as a switch, for example, V _{S is} set as a set voltage to a low resistance state between the source electrode 8 and the drain electrode 10. When = 1.8 V is applied, the resistance decreases from the state H of FIG. 9 by following the path r3, and as the voltage is lowered, the state transitions to the state L in the low resistance state and operates as a switch.

When programming the semiconductor element of the present embodiment that has been programmed to operate as a switch so as not to operate as a switch, for example, as a reset voltage to the high resistance state between the electrode 8 and the electrode 10, for example, When V _R = 0.6 V is applied, the resistance increases from the state L in FIG. 9 along the path r2, and as the voltage is lowered, the state transitions to the state H while remaining in the high resistance state, and does not operate as a switch.

When programming the semiconductor device of this embodiment that has been programmed to operate as a switch to operate as a switch, it is not necessary to add a set voltage or a reset voltage. However, when, for example, V _S = 1.8 V is applied as a set voltage to the low resistance state between the source electrode 8 and the drain electrode 10, after increasing the resistance from the state L in FIG. Following the path r3, the resistance is lowered again, and as the voltage is lowered, the state transitions to the state L in the low resistance state and remains in the state of operating as a switch.

Similarly, when programming the semiconductor device of the present embodiment programmed not to operate as a switch so as not to operate as a switch, it is not necessary to add a set voltage or a reset voltage. However, if, for example, V _R = 0.6 V is applied as a reset voltage to the high resistance state between the source electrode 8 and the drain electrode 10, for example, if the voltage is lowered, the state from the state H in the high resistance state in FIG. It traces back at V _R = 0.6 V, returns to the state H in the high resistance state, and remains in a state where it does not operate as a switch. That is, even if the power is turned off, the non-volatile logic circuit can be reprogrammed.

  For the operation of applying a voltage to the semiconductor element for setting such a logic circuit, a peripheral circuit of the element according to the embodiment of the present invention is created, or a writing device dedicated to the integrated circuit is prepared. It is also possible to create a system that performs only by controlling the software.

In order to operate the semiconductor element of the present embodiment in which the logic operation is set as described above as a logic circuit, for example, switching of the resistance value as described above does not occur between the source electrode 8 and the drain electrode. By changing the voltage applied to the gate electrode 14 while applying a working voltage of V _U = 0.3V or less, the current between the source electrode 8 and the drain electrode 10 is controlled to switch reversibly and volatilely. It becomes possible. When used in such a state, it is not necessary for the user of the product to be aware of the difference from the currently available general logic circuits.

For example, when a working voltage of V _U = 0.3 V or less is applied between the source electrode 8 and the drain electrode 10, the semiconductor element of the present embodiment in a state of operating as a switch has a range of the path r4A in FIG. The resistance between the source and the drain, that is, between the source electrode 8 and the drain electrode 10 is not reprogrammed to be non-volatile. The semiconductor element of the present embodiment that is not in a state of operating as a switch follows the range of the path r4B in FIG. 9, and the resistance between the source and drain, that is, between the source electrode 8 and the drain electrode 10, is reprogrammed to be non-volatile. There is nothing.

Whether or not a voltage is applied to the gate electrode 14 in the semiconductor device of the present embodiment programmed not to operate as a switch, for example, V _U = 0.3 V between the source and drain, that is, between the source electrode 8 and the drain electrode 10. As long as the following voltage is applied, current flows only between 1 × 10 ⁻⁴ A and below between the source electrode 8 and the drain electrode 10, that is, it does not operate as a switch.

When a voltage is applied to the gate electrode 14 in the semiconductor device of the present embodiment programmed to operate as a switch, a constant voltage of, for example, V _U = 0.3 V or less is applied between the source and drain, that is, between the source electrode 8 and the drain electrode 10. As long as a voltage in the range is applied, as shown in FIG. 10, the current flowing between the source electrode 8 and the drain electrode 10 changes, that is, it operates as a switch.

  For example, as shown in FIG. 11, the operating characteristics of the semiconductor element of the present embodiment vary depending on the difference in the thickness of the filament 7 formed by forming between the source electrode 8 and the drain electrode 10. In the case where a thin filament is generated, it may behave as if the current between the source and the drain is oscillated by changing the gate voltage as shown in FIG.

  Therefore, the developer of the logic circuit dedicated to each product can mount the logic circuit in which the switch operation is programmed on the individual semiconductor element of this embodiment in the product by such a method.

  When a developer of a logic circuit dedicated to each product finds a problem later in the operation of the logic circuit installed in the product, the programming voltage is again applied between the source electrode 8 and the drain electrode 10 without changing the semiconductor element. There is a great advantage that it is possible to modify the operation of the logic circuit by simply reapplying. Nowadays, the responsibility for manufacturing the product is greatly questioned, so it can be said that it is a great advantage that the problem of the product can be corrected at a low cost without replacing the hardware.

  In the semiconductor element of this embodiment manufactured as described above, a channel is formed by a filament that is a thin line. Therefore, the channel shows one-dimensional electrical conduction. In general, it can be generally shown as a property of the D'Alembert equation that the interaction between electric charges decreases as the electrical conductor is reduced in dimension, but the coherence of carriers is disturbed due to the decrease in electric charge interactions. Scattering is less likely to occur. That is, an increase in channel mobility is expected, and a logic circuit that operates at higher speed can be manufactured. Therefore, the structure of the semiconductor device according to the present embodiment is advantageous in terms of scaling.

  Further, scaling is performed so that the channel length is shorter than the mean free path of carriers in the channel portion, so that coherent carrier conduction occurs and quantum mechanical electrical characteristics are developed. A device exhibiting such electrical characteristics is generally known as a quantum wire transistor, and its operating principle is known to those skilled in the art.

  However, the conventional quantum wire transistor has not provided reconfigurability (reconfigurability) such that the circuit is reconfigured after the circuit is configured once.

  On the other hand, the semiconductor device (quantum wire transistor) according to the present embodiment is reconfigurable due to its operation principle and has great practical value.

  FIG. 12 shows an example of a reconfigurable logic circuit element, for example, an FPGA (Field Programming Gate Array), as an example of a semiconductor integrated circuit manufactured using the semiconductor element of this embodiment. Inside the FPGA, a plurality of CLBs (Configuration Logic Blocks) are coupled by wiring. For example, the semiconductor element of this embodiment can also be used for determining the coupling of wiring.

  Further, as shown in FIG. 13, the CLB includes a lookup table (LUT), a multiplexer (MUX), and a flip-flop (FF), and a function as a logic circuit is recorded in the lookup table. Conventionally, a lookup table, which is a combination of a huge memory circuit and a logic circuit, requires a large chip area. The semiconductor device of this embodiment, in which the memory circuit and the logic circuit are inseparable, is used for this lookup table. Thus, the chip area can be greatly reduced.

  Further, since the semiconductor element of this embodiment operates as a transistor, it can be used as a transistor in a multiplexer or flip-flop.

  As described above, according to the present embodiment, it is possible to obtain a semiconductor element that can be programmed as a logic operation and that can also operate as a nonvolatile memory element, and a manufacturing method thereof. In addition, it is possible to manufacture a semiconductor element only by a process for manufacturing a logic circuit, and there is an advantage that miniaturization can be easily promoted due to the operation principle of the element. Further, the semiconductor element of this embodiment can also be used as a nonvolatile memory element even when the power is turned off.

(Second Embodiment)
Next, a semiconductor device according to a second embodiment of the present invention will be described. In the first embodiment, the semiconductor element of the present embodiment has a configuration in which a Zr ₂ ON ₂ film is used as the electric resistance change film 6 instead of the Hf ₂ ON ₂ film. Hf ₂ ON ₂ and Zr ₂ ON ₂ films exhibit very similar physical and chemical properties to each other. The slight difference is that the melting point of the Hf ₂ ON ₂ film is higher than that of the Zr ₂ ON ₂ film by about 100 ° C., so that in the annealing used for orienting the crystals of Hf ₂ ON ₂ in the first embodiment, the annealing temperature A similar orientation can be produced by slightly lowering. In addition, when producing a Zr ₂ ON ₂ film by sputtering, it has been published in various specialized literatures that the sputtering rate of Zr is slightly lower than the sputtering rate of Hf. It can be easily estimated by a person skilled in the art that it is necessary. In the crystal structure, the position of O atoms and N atoms does not change only by replacing Hf atoms with Zr atoms, so that it can be easily assumed that the direction of easy dielectric breakdown is the same and acts as an electric resistance change film.

It can also be easily estimated that what can be done with such Hf ₂ ON ₂ will also be possible with the Ce ₂ ON ₂ film. That is, the crystal structure is the same type only by replacing the Hf atom with Ce atom, and the physical and chemical properties are similar, such as a melting point that is close to 200 ° C. It is the same, and the direction of easy dielectric breakdown is the same, and it can be easily estimated that it acts as an electric resistance change film.

  Similarly to the first embodiment, the semiconductor element of this embodiment can provide a semiconductor element that can be programmed as a logic operation and can also operate as a nonvolatile memory element, and a manufacturing method thereof.

(Third embodiment)
Next, a semiconductor device according to a third embodiment of the present invention will be described.

  The electrical resistance change film used in the semiconductor element of the first embodiment or the second embodiment may be any material in terms of operation principle as long as it is an electrical resistance change film that forms a low resistance filament inside the film. It may be used. Therefore, in this embodiment, the first embodiment uses a material having an electric conductivity anisotropy as the material of the electric resistance change film. In this case, it is possible to reduce the proportion of defects that cause filaments to be generated in an unfavorable direction during forming. More preferably, a material in which the direction in which dielectric breakdown is likely to occur matches the direction connecting the source electrode 8 and the drain electrode 10 is used for the electric resistance change film.

As a material having such a direction that facilitates dielectric breakdown, for example, other than Hf ₂ ON ₂ , a material that can easily break down in a uniaxial direction is, for example, CuIr ₂ (S _1-x Se _x ) ₄ (0.05 <x A quasi-one-dimensional material such as ≦ 1) is known. For example, it is preferable to select a material that changes resistance from candidate substances that exhibit the CDW phenomenon, which is a typical substance of the quasi-one-dimensional material. In addition, a layered material having a high resistance in an under-doped region such as La _2-x Sr _x CuO ₄ (0 <x ≦ 0.05) that is likely to cause dielectric breakdown in the in-plane direction is also a variable resistance material. Be a candidate. In the case of a layered material, an orientation in which the in-plane direction in which dielectric breakdown is likely to occur coincides with the film surface direction is preferable.

  Similarly to the first embodiment, the semiconductor element of this embodiment can provide a semiconductor element that can be programmed as a logic operation and can also operate as a nonvolatile memory element, and a manufacturing method thereof.

(Fourth embodiment)
Next, a semiconductor device according to a fourth embodiment of the present invention will be described.

  In the first to third embodiments, the mutual arrangement of the source electrode 8, the drain electrode 10, and the gate electrode 14 is important. That is, in forming, it is desirable to form a low-resistance filament between the source electrode 8 and the drain electrode 10, but when the gate electrode 14 is too close to the source electrode 8, the gate electrode 14 is completely floated during forming. Unless it is in a state, there is a high risk that a filament will be formed between the source electrode 8 or the drain electrode 12 and the gate electrode 14. If so, the device does not operate.

  On the other hand, if the gate electrode 14 is too far away from the source electrode 8 or the drain electrode 10, it is difficult for the above-described forming failure to occur. However, when the logic operation is performed, the gate electrode 14 is turned on by the voltage applied to the gate electrode 14. It becomes difficult to switch off. In other words, it is necessary to take measures to increase the voltage applied to the gate electrode 14 or to compensate for the low on / off ratio by the peripheral circuit, which is contrary to scaling.

  Therefore, in the semiconductor element of this embodiment, the distance between the source electrode 8 and the gate electrode 10, the distance between the drain electrode 10 and the gate electrode 14, and the distance between the gate electrode 14 and the source electrode 8 are as follows. The arrangement is almost the same. By configuring in this way, an optimal arrangement is obtained that avoids the above problems.

  Preferably, the distance between the electrodes is not a mere spatial distance but an electrical distance divided by the relative dielectric constant of the material existing between the electrodes is substantially equal. However, such a structure is difficult as a method for manufacturing an integrated circuit. In reality, this positional relationship is not always necessary, and the gate electrode 14 must be used in a situation where the distance between the other two electrodes 8 and 10 is short.

  Therefore, in order to satisfy the two conditions of being easy to manufacture as an integrated circuit and easy to form, it is very preferable that the electric resistance change film 6 has an electric conductivity and anisotropy of dielectric breakdown. .

  Similarly to the first embodiment, the semiconductor element of this embodiment can provide a semiconductor element that can be programmed as a logic operation and can also operate as a nonvolatile memory element, and a manufacturing method thereof.

(Fifth embodiment)
Next, FIG. 14 shows a cross section of a semiconductor device according to the fifth embodiment of the present invention.

  The semiconductor elements of the first to fourth embodiments have a lateral structure in which the source electrode 8 and the drain electrode 10 are arranged in the lateral direction of the electrical resistance change film 6, that is, the film surface direction. The semiconductor element 1 </ b> A of this embodiment has a vertical structure in which the source electrode 8 and the drain electrode 10 are arranged in the vertical direction of the electric resistance change film 6, that is, in the film thickness direction. However, the operation is the same as that of the lateral semiconductor element of the first to fourth embodiments.

  In the semiconductor element 1A of this embodiment, an insulating film 4 is formed on a semiconductor substrate 2, and a source electrode wiring 20b and a contact 18b connected to the source electrode wiring 20b are formed in the insulating film 4. A source electrode 8 is formed on the insulating film 4 so as to be electrically connected to the contact 18 b, and an electric resistance change film 6 is formed on the source electrode 8. A drain electrode 10 is formed on the electric resistance change film 6. A gate insulating film 12 is provided so as to cover the side surface of the laminated film including the source electrode 8, the electric resistance change film 6, and the drain electrode 10. Further, a gate electrode 14 is provided on the side surface of the laminated film including the source electrode 8, the electric resistance change film 6, and the drain electrode 10 so as to sandwich the gate insulating film 12. An interlayer insulating film 16 is formed so as to cover the upper surface of the laminated film including the source electrode 8, the electric resistance change film 6, and the drain electrode 10, the gate insulating film 12, and the gate electrode 14. A contact 18c and a contact 18a connected to the drain electrode 10 and the gate electrode 14 are provided. The drain electrode 10 and the gate electrode 14 are connected to the drain electrode wiring 20c and the gate electrode wiring 20a provided on the interlayer insulating film 16 through the contact 18c and the contact 18a. In the present embodiment, as in the first embodiment, a filament 7 having a thin line structure connecting the source electrode 8 and the drain electrode 10 is formed in the electrical resistance change film 6. The filament 7 is formed by forming.

  Next, a method for manufacturing the semiconductor element 1A of the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 15, the insulating film 4 in which the source electrode wiring 20 b is embedded on the substrate 2 is produced. The creation procedure is as follows. A first insulating film is formed on the substrate 2. This first insulating film may be a deposited film or an oxide film of the substrate. A wiring mask pattern is formed on the first insulating film, and an unmasked portion of the first insulating film is dug by dry etching using plasma or the like to form a wiring groove. Subsequently, the wiring material is deposited. At this time, the wiring material can be deposited while leaving the mask, and the wiring material is deposited after removing the mask and exposing the insulating film. Is also possible. The wiring material employs a method such as collimated sputtering, and forming a film so as not to be deposited on the side wall of the groove facilitates the subsequent process. However, even if it is deposited on the side wall of the groove by employing a CVD method or the like, it does not hinder the subsequent process.

  For example, when the wiring material is formed on the bottom of the groove by the collimated sputtering method while leaving the mask, the lift-off method is used to remove the mask after the second insulating film is deposited on the groove by the collimated sputtering method or the like. By using it, it is possible to easily form an insulating film in which the wiring 20b is embedded. However, in this case, since the material peeled off by the lift-off method causes particle contamination, there is a drawback that it takes time to remove the material.

  On the other hand, if the wiring material is formed by CVD after removing the mask, the surface is flattened by CMP (Chemical Mechanical Polishing) after film formation, so that the wiring material is embedded only in the groove portion. Can be. After that, if a second insulating film is deposited, it is possible to produce the insulating film 4 in the form of embedded wiring. This process increases the manufacturing cost because the number of steps is increased as compared with the case where the mask is not removed, but it is suitable for microfabrication because there are few problems of particle contamination.

  Next, as shown in FIG. 15, a low resistance polycrystalline silicon film 14 to be a gate electrode is formed on the insulating film 4. As a method of forming a low-resistance polycrystalline silicon film, for example, a method of forming a polycrystalline silicon film by a CVD method using silane gas or the like, implanting a dopant by an ion implantation method, etc., and activating it by a heat treatment at 800 ° C. or higher. It may be used. Alternatively, a method may be used in which amorphous silicon is sputter-deposited from a silicon target in which the dopant is contained at the upper limit of the solid solubility limit or above the solid solubility limit, and activated by heat treatment at about 600 ° C.

  Next, a mask pattern (not shown) is formed on the polycrystalline silicon film 14, and the polycrystalline silicon film is etched by dry etching or the like, thereby forming an opening 15 through which the insulating film 4 is exposed on the bottom surface (FIG. 15). The opening 15 becomes an element region of the semiconductor element of this embodiment.

Next, as shown in FIG. 16, the exposed surface of the polycrystalline silicon film 14 is oxidized to form a SiO ₂ oxide film to be the gate insulating film 12 on the upper surface of the polycrystalline silicon film 14 and the side surface on the opening side. At the same time, a gate electrode 14 made of low-resistance polycrystalline silicon is formed.

  Next, as shown in FIG. 17, the contact 18 b and the source electrode 8 that reach the source electrode wiring 20 b in the insulating film 4 from the bottom surface of the opening 15 are formed. The contact 18b is formed by forming a hole reaching the source electrode wiring 20b in the insulating film 4 from the bottom surface of the opening 15, and filling the hole with a metal, for example, Pt. Thereafter, the source electrode 8 is formed by depositing a metal film. Further, for example, after forming a mask pattern, after forming a contact hole reaching the source electrode wiring 20b by a method such as dry etching, the mask pattern is removed, and then a Pt metal film is formed by, for example, collimated sputtering. Then, the contact 18b connected to the source electrode wiring 20b and the source electrode 8 are formed simultaneously.

  The contact 18b can be formed before the low-resistance polycrystalline silicon film 14 is formed. In that case, there is an advantage that a method of flattening by CMP can be used. However, in the heat treatment for activating the low-resistance polycrystalline silicon film 14, there is a problem that the metal constituting the contact 18b reacts with silicon to form silicide, so that the low-resistance silicon film is made amorphous by the above sputtering method. A method of activating at a low temperature of about 600 ° C. after forming silicon is more preferable.

  After forming the source electrode 8 on the contact 18b in this way, a resistance change material is deposited on the source electrode 8 by a collimated sputtering method or the like to form the electrical resistance change film 6 (see FIG. 17). Subsequently, a metal film made of, for example, Pt is formed so as to be sufficiently higher than the upper surface of the polycrystalline silicon film 14 by a collimated sputtering method or the like (see FIG. 17).

  Next, it is planarized by CMP, and the upper surface of the gate electrode 14 is exposed as shown in FIG. Thereby, the drain electrode 10 is formed on the electric resistance change film 6.

  Next, as shown in FIG. 19, an interlayer insulating film 16 is deposited so as to cover the upper surfaces of the gate electrode 14, the gate insulating film 12, and the drain electrode 10, and the gate electrode 14 and the drain electrode 10 are formed on the interlayer insulating film 16. The contacts 18a and 18c connected to are formed. Thereafter, a gate electrode wiring 20a and a drain electrode wiring 20c connected to the contacts 18a and 18c are formed on the interlayer insulating film 16 (see FIG. 19). Thereafter, forming is performed to form a filament 7 having a thin wire structure connecting the source electrode 8 and the drain electrode 10 in the electrical resistance change film 6, thereby completing the vertical semiconductor device of this embodiment shown in FIG. 14. To do.

  In the present embodiment, the source electrode 8 is formed below the electric resistance change film 6 and the drain electrode 10 is formed above the electric resistance change film 6. However, the source electrode 8 is formed above the electric resistance change film 6. Alternatively, the drain electrode 10 may be formed below the electric resistance change film 6.

  Similarly to the first embodiment, the semiconductor element of this embodiment can provide a semiconductor element that can be programmed as a logic operation and can also operate as a nonvolatile memory element, and a manufacturing method thereof. In addition, it is possible to manufacture a semiconductor element only by a process for manufacturing a logic circuit, and there is an advantage that miniaturization can be easily promoted due to the operation principle of the element. Further, the semiconductor element of this embodiment can also be used as a nonvolatile memory element even when the power is turned off.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. Sectional drawing which shows the manufacturing process of the semiconductor element of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 1st Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 1st Embodiment. Sectional drawing explaining the filament of an electrical resistance change film. Photograph showing the crystal structure of Hf ₂ ON ₂ film. A photograph showing a cross section of the crystal of the Hf ₂ ON ₂ film in the (111) direction The figure explaining operation | movement of the semiconductor element of 1st Embodiment. The graph which shows the characteristic of the source-drain current with respect to the gate voltage of the semiconductor element of 1st Embodiment. The graph which shows the characteristic of the source-drain current with respect to the gate voltage of the semiconductor element of 1st Embodiment. The block diagram which shows the structure of FPGA. The block diagram which shows the structure of CLB using the semiconductor element of 1st Embodiment. Sectional drawing which shows the semiconductor element by 2nd Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor element of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 2nd Embodiment. Sectional drawing which shows the manufacturing process of the semiconductor element of 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 1A Semiconductor element 2 Substrate 4 Insulating film 6 Electric resistance change film 7 Low resistance filament 8 Source electrode 10 Drain electrode 12 Gate insulating film 14 Gate electrode 16 Interlayer insulating films 18a, 18b, 18c Contacts 20a, 20b, 20c Wiring

Claims (9)

An electrical resistance change film having first and second surfaces facing each other and a third surface different from the first and second surfaces;
A first electrode provided in contact with the first surface of the electrical resistance change film;
A second electrode provided in contact with the second surface of the electrical resistance change film;
An insulating film provided in contact with the third surface of the electrical resistance change film;
A third electrode provided across the insulating film on the third surface of the electrical resistance change film;
A semiconductor device comprising: A substrate,
A first insulating film provided on the substrate;
An electrical resistance change film provided on the first insulating film;
A first electrode provided on and in contact with the one side surface of the electric resistance change film on the first insulating film on one side surface of both side surfaces of the electric resistance change film;
A second electrode provided on and in contact with the other side surface of the electrical resistance change film on the first insulating film on the other side surface of both side surfaces of the electrical resistance change film;
A second insulating film provided on the electric resistance change film;
A third electrode provided on the second insulating film;
A semiconductor device comprising: A substrate,
A first insulating film provided on the substrate;
A laminated film having a first electrode provided on the first insulating film, an electrical resistance change film provided on the first electrode, and a second electrode provided on the electrical resistance change film;
A second insulating film covering a side surface of the laminated film;
A third electrode provided on a side surface of the laminated film so as to sandwich the second insulating film;
A semiconductor device comprising:   The electrical resistance change film includes a filament that has the lowest electrical resistivity in the electrical resistance change film and connects the first electrode and the second electrode. The semiconductor element in any one.   The electrical resistance change film has anisotropy that facilitates dielectric breakdown, and has an easy direction of dielectric breakdown of the electrical resistance change film and a direction connecting the first electrode and the second electrode. 5. The semiconductor device according to claim 1, wherein the semiconductor elements are substantially coincident with each other. The electric resistance change film is made of any one of Hf ₂ ON ₂ , Zr ₂ ON ₂ , and Ce ₂ ON ₂ that are 111-oriented in the film thickness direction. Semiconductor element.   The electrical resistance change film is in a low resistance state when a voltage higher than the first voltage value is applied between the first electrode and the second electrode, and is lower than the first voltage value and second. The semiconductor element according to claim 1, wherein when a voltage higher than a voltage value is applied, the semiconductor element is in a high resistance state.   A constant voltage is applied between the first electrode and the second electrode, and a current flowing between the first electrode and the second electrode changes according to a voltage applied to the third electrode. The semiconductor element according to claim 1.   9. A semiconductor integrated circuit, wherein the semiconductor element according to claim 1 is used as an element of a logic circuit whose operation program can be reconstructed.