JP2008235513A - Semiconductor device and its design and manufacturing methods - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem that a difference is generated in a transmission time of a control signal between output buffer elements and input buffer elements. <P>SOLUTION: A plurality of the output buffer elements and a plurality of the input buffer elements are disposed so that the total length of wiring among the buffer elements, output ports, input ports and input buffer elements is substantially the same over a first macro-block and a second macro-block. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which an output buffer element or an input buffer element is provided for each of a plurality of macroblocks having a plurality of functions that should be possessed by a solid-state imaging device such as a CMOS imaging device. The present invention relates to a design method and a method for manufacturing the semiconductor device.

  As shown in FIG. 3, in the conventional semiconductor device SD10, the first macroblock MB10 has a first processing circuit PR10 that performs processing for controlling the operation of a solid-state imaging device (not shown). First and second output buffer elements OB10 and OB20 for outputting the first control signal CS10 and the second control signal CS20 are provided. Further, the second macroblock MB20 located at the subsequent stage of the first macroblock MB10 receives the control signals CS10 and CS20 and receives the control signals CS10 and CS20 from the operation of the solid-state imaging device. There are provided a first input buffer element IB10 and a second input buffer element IB20 for delivery to the second processing circuit PR20 that performs other processing for controlling the above.

  Similar to “equalizing timings between input / output terminals” which is a main configuration described in Patent Documents 1 to 3 below, the conventional method for designing a semiconductor device SD10 uses the solid-state imaging device. For this reason, it is necessary that the length of the path for transmitting the first control signal CS10 and the length of the path for transmitting the second control signal CS20 are equal. For this purpose, the length of the wiring LN10 between the first input buffer element IB10 and the first output buffer element OB10 related to the first control signal CS10 and the second control signal CS20 related to the second control signal CS20. The length of the wiring LN20 between the input buffer element IB20 and the second output buffer element OB20 needs to be equal.

JP 2002-222229 A Japanese Patent Laid-Open No. 9-246388 Japanese Patent Laid-Open No. 5-268016

  However, in the conventional semiconductor device design method, the control signals CS10 and CS20 are used as the first macro for reasons such as restrictions on the use of tools (software) for P & R (Placement & Routing) used in the design method. The first output port OP10 and the second output port OP20 that are terminals for outputting from the block MB10 cannot be provided at free positions on the first macroblock MB10. For the same reason, the first and second input ports IP10 and IP20, which are terminals for receiving the control signals CS10 and CS20 by the second macroblock MB20, can be freely set on the second macroblock MB20. Can not be placed in position.

  In the conventional semiconductor device SD10, as shown in FIG. 4, due to restrictions on the arrangement of the first and second output ports OP10 and OP20 and the first and second input ports IP10 and IP20 as described above. The length of the wiring LN30 between the first output buffer element OB10 and the first input buffer element IB10 is different from the length of the wiring LN40 between the second output buffer element OB20 and the second input buffer element IB20. As a result, a difference occurs in the transmission time of the control signals CS10 and CS20 between the first and second output buffer elements OB10 and OB20 and the first and second input buffer elements IB10 and IB20. There has been a problem that the operation of the solid-state imaging device cannot be controlled as desired.

The method for designing a semiconductor device according to the present invention is to solve the above-described problems. (1) The semiconductor device comprising a plurality of layers is related to the function that should be placed in the first macroblock that assumes the function that the semiconductor device should have. A plurality of output buffer elements for outputting a signal to be transmitted; and (2) receiving the input of the signals from the plurality of output buffer elements to be arranged in a second macroblock subsequent to the first macroblock. (3) (3a) each output port is provided at a position fixed in advance in the first macroblock, and of the plurality of output buffer elements, A plurality of output ports corresponding to one, and (3b) each input port is provided at a position fixed in advance in the second macroblock, and is connected to the plurality of input buffer elements. And a plurality of input ports corresponding to one of the plurality of output ports, and a design method of a semiconductor device to be connected via,
(1) The plurality of output buffer elements are arranged such that each output buffer element is assigned to one of the plurality of layers, and the plurality of input buffer elements are each input buffer element, An arrangement step of arranging so that an output buffer element corresponding to the input buffer element is allocated to the arranged layer, wherein (2) each total wiring length is assigned to one output buffer element and one output buffer element A length of the first wiring between the corresponding one output port, a second input buffer element corresponding to the one output port, and a second length between the one input port corresponding to the one input buffer element. The plurality of output buffer elements and the plurality of input buffer elements are arranged such that a plurality of total wiring lengths, which is the total of the wiring lengths, are substantially equal to each other. And a step,
(1) wiring between the plurality of output buffer elements and the plurality of output ports so that the one output buffer element and the one output port are connected; and (2) the plurality of input buffer elements and Wiring between the plurality of input ports so that the one input buffer element and the one input port are connected; and (3) between the plurality of output ports and the plurality of input ports. And a wiring step of wiring so that the output port and the one input port are connected.

  According to the semiconductor device design method of the present invention described above, in the third arrangement step, the total wiring length of the length of the first wiring and the length of the second wiring is substantially equal to each other. The plurality of output buffer elements and the plurality of input buffer elements to be equal to each other, and in the wiring step, the plurality of output buffer elements, the plurality of output ports, the plurality of input ports, and By performing wiring between the plurality of input buffer elements, it is possible to avoid a difference in transmission time between the plurality of output buffer elements and the input buffer elements.

A semiconductor device according to the present invention includes:
In the first macroblock that bears a function that a semiconductor device composed of a plurality of layers should have, each output buffer element is allocated and arranged in one of the plurality of layers, and A plurality of output buffer elements for outputting a signal to be transmitted;
In the second macroblock subsequent to the first macroblock, each input buffer element is allocated and arranged in a layer in which an output buffer element corresponding to the input buffer element is arranged, and the plurality of output buffers A plurality of input buffer elements for receiving the input of the signal from the element;
Each output port is provided at a position fixed in advance in the first macroblock, and a plurality of output ports corresponding to one of the plurality of output buffer elements;
Each input port is provided at a position fixed in advance in the second macroblock, and corresponds to one of the plurality of input buffer elements and one of the plurality of output ports. Multiple input ports to
A plurality of first buffer lines connecting the plurality of output buffer elements and the plurality of output ports so that one output buffer element and one output port corresponding to the one output buffer element are connected;
A plurality of second wirings connecting the plurality of input buffer elements and the plurality of input ports so that one input buffer element and one input port corresponding to the one input buffer element are connected;
A third plurality of wirings connecting the plurality of output ports and the plurality of input ports so that the one output port and the one input port are connected; and
Among the first plurality of wirings, the second plurality of wirings, and the third plurality of wirings, the total lengths of the corresponding wirings are substantially equal to each other.

A method for manufacturing a semiconductor device according to the present invention includes:
(1) a plurality of output buffer elements for outputting a signal related to the function, which are to be arranged in a first macroblock having a function that the semiconductor device having a plurality of layers should have; A plurality of input buffer elements for receiving the signal input from the plurality of output buffer elements, which are to be arranged in a second macroblock subsequent to the first macroblock, are (3) and (3a) each output port. Are provided at positions fixed in advance in the first macroblock, and a plurality of output ports corresponding to one of the plurality of output buffer elements, and (3b) each input port is , Provided in a predetermined position in the second macroblock, and a plurality of ones corresponding to one of the plurality of input buffer elements and one of the plurality of output ports. A method of manufacturing a semiconductor device to be connected through a power port, and
(1) The plurality of output buffer elements are arranged such that each output buffer element is assigned to one of the plurality of layers, and the plurality of input buffer elements are each input buffer element, An arrangement step of arranging so that an output buffer element corresponding to the input buffer element is allocated to the arranged layer, wherein (2) each total wiring length is assigned to one output buffer element and one output buffer element A length of the first wiring between the corresponding one output port, a second input buffer element corresponding to the one output port, and a second length between the one input port corresponding to the one input buffer element. The plurality of output buffer elements and the plurality of input buffer elements are arranged such that a plurality of total wiring lengths, which is the total of the wiring lengths, are substantially equal to each other. And a step,
(1) wiring between the plurality of output buffer elements and the plurality of output ports so that the one output buffer element and the one output port are connected; and (2) the plurality of input buffer elements and Wiring between the plurality of input ports so that the one input buffer element and the one input port are connected; and (3) between the plurality of output ports and the plurality of input ports. And a wiring step of wiring so that the output port and the one input port are connected.

In the above-described semiconductor device design method, semiconductor device, and semiconductor device manufacturing method according to the present invention,
The lengths of the first wirings are substantially equal to each other, and the lengths of the second wirings are substantially equal to each other.

<Example>
Embodiments of a semiconductor device design method according to the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration of a semiconductor device according to the embodiment, FIG. 2A is a cross-sectional view of the semiconductor device according to the embodiment, and FIG. 2B is a plan view of the semiconductor device according to the embodiment.

  The semiconductor device SD1 according to the embodiment has an upper layer UL1 and a lower layer LL1 as shown in FIG. 2A to control the operation of a solid-state imaging device (not shown) such as a CCD image sensor and a CMOS image sensor. As shown in FIG. 1, it includes a first macroblock MB1 and a second macroblock MB2. The first and second macroblocks MB1 and MB2 are provided on a semiconductor substrate (not shown) constituting the gate array.

  The first macro block MB1 includes a first processing circuit PR1, first and second output buffer elements OB1 and OB2, and first and second output ports OP1 and OP2. The first processing circuit PR1 performs processing for controlling the operation of the solid-state imaging device, and the first and second output buffer elements OB1 and OB2 perform first control from the first processing circuit PR1. The signal CS1 and the second control signal CS2 are buffered, and the first and second output ports OP1 and OP2 output the first and second control signals CS1 and CS2 to the second macroblock MB2. Functions as a terminal.

  The second macro block MB2 includes first and second input ports IP1 and IP2, first and second input buffer elements IB1 and IB2, and a second processing circuit PR2. The first and second input ports IP1 and IP2 function as terminals for receiving the first and second control signals CS1 and CS2 from the first macroblock MB1, and the first and second input buffer elements IB1. IB2 buffers the first and second control signals CS1 and CS2, and the second processing circuit PR2 is performed by the first processing circuit PR1 for controlling the operation of the solid-state imaging device. A process different from the process is performed.

  The method for designing a semiconductor device according to the embodiment includes the following steps.

  Step S1: As shown in FIG. 1, the first processing circuit PR1 is arranged at an arbitrary position on the first macroblock MB1, and similarly, an arbitrary one on the second macroblock MB2 is arranged. The second processing circuit PR2 is disposed at the position.

  Step S2: As shown in FIG. 1 and FIG. 2A, the first output port OP1 is arranged at a predetermined position in the upper layer UL1 of the first macroblock MB1, and the first macroblock The second output port OP2 is arranged at a position corresponding to the position of the first output port OP1 in the lower layer LL1 of the block MB1.

  Similarly, the first input port IP1 is arranged at a predetermined position in the upper layer UL1 of the second macroblock MB2, and the first input port in the lower layer LL1 of the second macroblock MB2 is arranged. The second input port IP2 is arranged at a position corresponding to the position of IP1. With the above arrangement, the length of the wiring LN1 between the first output port OP1 and the first input port IP1 and the second output port OP2 as shown in FIGS. And the length of the wiring LN2 between the second input ports IP2 is made equal.

  Step S3: As shown in FIG. 1, the length of the wiring LN3 between the first output buffer element OB1 and the first output port OP1, and the first input buffer element IB1 and the first input port IP1 The total length (= LN3 + LN5) of the wiring LN5 between them, the length of the wiring LN4 between the second output buffer element OB2 and the second output port OP2, and the second input buffer element The first macroblock MB1 and the second macroblock MB2 are arranged on the first macroblock MB1 and the second macroblock MB2 so that the total length of the wiring LN6 between the IB2 and the second input port IP2 is equal (= LN4 + LN6). The first and second output buffer elements OB1 and OB2 and the first and second input buffer elements IB1 and IB2 are arranged.

  Step S4: On the first macroblock MB1, a wiring LN3 is provided between the first output buffer element OB1 and the first output port OP1, and the second output buffer element OB2 and the second output buffer element OB2 are provided. A wiring LN4 is provided between the output ports OP2, and a wiring LN5 is provided between the first input buffer element IB1 and the first input port IP1 on the second macro block MB2, and the second input A wiring LN6 is provided between the buffer element IB2 and the second input port IP2.

  By providing the wirings LN3, LN4, LN5 and LN6, the length of the wiring between the first output buffer element OB1 and the first input buffer element IB1 (= LN3 + LN1 + LN5) and the second output buffer are consequently obtained. The length of the wiring between the element OB2 and the second input buffer element IB2 (= LN4 + LN2 + LN6) becomes equal.

  As described above, in the semiconductor device design method according to the embodiment, the wiring LN1 between the first output port OP1 and the first input port IP1, and the wiring between the second output port OP2 and the second input port IP2 are used. With LN2 equal, the length of the wiring LN3 between the first output buffer element OB1 and the first output port OP1 and the length of the wiring LN5 between the first input buffer element IB1 and the first output port OP1 And the total length (= LN3 + LN5) is the length of the wiring LN4 between the second output buffer element OB2 and the second output port OP2, and between the second input buffer element IB2 and the second output port OP2. The total length (= LN4 + LN6) with the length of the wiring LN6 is made equal. As a result, the length of the wiring between the first output buffer element OB1 and the first input buffer element IB1 (= LN3 + LN1 + LN5) and the length of the wiring between the second output buffer element OB2 and the second input buffer element IB2 Since (= LN4 + LN2 + LN6) is equal, unlike the prior art, it is possible to cause the solid-state imaging device to perform a desired operation.

<Modification>
As described above, the total length of the wiring LN3 and the wiring LN5 and the total length of the wiring LN4 and the wiring LN6 are made equal between the first macroblock MB1 and the second macroblock MB2. Instead, in the first macroblock MB1, the length of the wiring LN3 and the length of the wiring LN4 are made equal, and in the second macroblock MB2, the length of the wiring LN5 and the length of the wiring LN6 are made equal. Also, the same effect as described above can be obtained. In addition, for example, with respect to the arrangement of the first macro block MB1, the effect can be obtained by following the first macro block MB1 as in the embodiment, that is, the length of the wiring LN3 + the length of the wiring LN5. = The length of the wiring LN4 + the second macroblock MB2 having the wiring LN4 and the wiring LN6 satisfying the wiring LN6 is not required, and the length of the wiring LN4 simply satisfies the wiring LN6 Since a macroblock (not shown) other than the second macroblock MB2 having the wiring LN4 and the wiring LN6 can be obtained, the first macroblock MB1 itself is arranged. In addition, regarding the arrangement of other macroblocks around the first macroblock MB1, the degree of freedom is improved as compared with the embodiment. Theft is possible.

FIG. 6 illustrates a structure of a semiconductor device of an example. Sectional drawing and top view of the semiconductor device of an Example. The figure which shows the structure of the conventional original semiconductor device. The figure which shows the structure of the conventional actual semiconductor device.

Explanation of symbols

  SD1 ... Semiconductor device; MB1 ... First macroblock; MB2 ... Second macroblock; OB1, OB2 ... First and second output buffer elements; OP1, OP2 ... First, second output ports; IP2 ... first and second input ports; IB1, IB2 ... first and second input buffer elements.

Claims (6)

(1) a plurality of output buffer elements for outputting a signal related to the function, which are to be arranged in a first macroblock having a function that the semiconductor device having a plurality of layers should have; A plurality of input buffer elements for receiving the signal input from the plurality of output buffer elements, which are to be arranged in a second macroblock subsequent to the first macroblock, are (3) and (3a) each output port. Are provided at positions fixed in advance in the first macroblock, and a plurality of output ports corresponding to one of the plurality of output buffer elements, and (3b) each input port is , Provided in a predetermined position in the second macroblock, and a plurality of ones corresponding to one of the plurality of input buffer elements and one of the plurality of output ports. The method for designing a semiconductor device to be connected through a power port, and
(1) The plurality of output buffer elements are arranged such that each output buffer element is assigned to one of the plurality of layers, and the plurality of input buffer elements are each input buffer element, An arrangement step of arranging so that an output buffer element corresponding to the input buffer element is allocated to the arranged layer, wherein (2) each total wiring length is assigned to one output buffer element and one output buffer element A length of the first wiring between the corresponding one output port, a second input buffer element corresponding to the one output port, and a second length between the one input port corresponding to the one input buffer element. The plurality of output buffer elements and the plurality of input buffer elements are arranged such that a plurality of total wiring lengths, which is the total of the wiring lengths, are substantially equal to each other. And a step,
(1) wiring between the plurality of output buffer elements and the plurality of output ports so that the one output buffer element and the one output port are connected; and (2) the plurality of input buffer elements and Wiring between the plurality of input ports so that the one input buffer element and the one input port are connected; and (3) between the plurality of output ports and the plurality of input ports. And a wiring step of wiring so that the output port and the one input port are connected to each other.   2. The method of designing a semiconductor device according to claim 1, wherein the lengths of the first wirings are substantially equal to each other, and the lengths of the second wirings are substantially equal to each other. . In the first macroblock that bears a function that a semiconductor device having a plurality of layers should have, each output buffer element is allocated and arranged in one of the plurality of layers, and is related to the function A plurality of output buffer elements for outputting a signal to be transmitted;
In the second macroblock subsequent to the first macroblock, each input buffer element is allocated and arranged in a layer in which an output buffer element corresponding to the input buffer element is arranged, and the plurality of output buffers A plurality of input buffer elements for receiving the input of the signal from the element;
Each output port is provided at a position fixed in advance in the first macroblock, and a plurality of output ports corresponding to one of the plurality of output buffer elements;
Each input port is provided at a position fixed in advance in the second macroblock, and corresponds to one of the plurality of input buffer elements and one of the plurality of output ports. Multiple input ports to
A plurality of first buffer lines connecting the plurality of output buffer elements and the plurality of output ports so that one output buffer element and one output port corresponding to the one output buffer element are connected;
A plurality of second wirings connecting the plurality of input buffer elements and the plurality of input ports so that one input buffer element and one input port corresponding to the one input buffer element are connected;
A third plurality of wirings connecting the plurality of output ports and the plurality of input ports so that the one output port and the one input port are connected; and
A total length of corresponding wires among the first plurality of wires, the second plurality of wires, and the third plurality of wires is substantially equal to each other. .   4. The semiconductor device according to claim 3, wherein the length of the first plurality of wirings is substantially equal to each other, and the length of the second plurality of wirings is substantially equal to each other. apparatus. (1) a plurality of output buffer elements for outputting a signal related to the function, which are to be arranged in a first macroblock having a function that the semiconductor device having a plurality of layers should have; A plurality of input buffer elements for receiving the signal input from the plurality of output buffer elements, which are to be arranged in a second macroblock subsequent to the first macroblock, are (3) and (3a) each output port. Are provided at positions fixed in advance in the first macroblock, and a plurality of output ports corresponding to one of the plurality of output buffer elements, and (3b) each input port is , Provided in a predetermined position in the second macroblock, and a plurality of ones corresponding to one of the plurality of input buffer elements and one of the plurality of output ports. A method of manufacturing a semiconductor device to be connected through a power port, and
(1) The plurality of output buffer elements are arranged such that each output buffer element is assigned to one of the plurality of layers, and the plurality of input buffer elements are each input buffer element, A step of arranging so that an output buffer element corresponding to the input buffer element is assigned to a layer on which the input buffer element is arranged, and (2) each total wiring length corresponds to one output buffer element and the one output buffer element The length of the first wiring between the one output port, the one input buffer element corresponding to the one output port, and the second wiring between the one input port corresponding to the one input buffer element The plurality of output buffer elements and the plurality of input buffer elements are arranged such that a plurality of total wiring lengths, which are the total length of the plurality of input buffer elements, are substantially equal to each other. And a step,
(1) wiring between the plurality of output buffer elements and the plurality of output ports so that the one output buffer element and the one output port are connected; and (2) the plurality of input buffer elements and Wiring between the plurality of input ports so that the one input buffer element and the one input port are connected; and (3) between the plurality of output ports and the plurality of input ports. And a wiring step of wiring so that the output port and the one input port are connected to each other.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the lengths of the first wirings are substantially equal to each other, and the lengths of the second wirings are substantially equal to each other. .

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