JP2008235436A - Semiconductor element, method for manufacturing the same, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element capable of equalizing the resistance values of a plurality of semiconductor elements without increasing the number of components when using the plurality of semiconductor elements different in kind, thereby simplifying a circuit. <P>SOLUTION: The wafer bonding semiconductor element 1 includes first and second wafers 10, 20 which are mutually bonded by wafer bonding. A bonding interface 30 between the first and second wafers 10, 20 has resistance. The resistance value of the bonding interface 30 is controlled, thereby performing adjustment to allow a whole driving voltage to be larger than a value which is obtained by adding the voltage intrinsic to the first wafer 10 to the voltage intrinsic to the second wafer 20. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor element used in, for example, an electric decoration device, a guidance display board device, a lighting fixture, and the like, a method for manufacturing the semiconductor element, and a semiconductor device having the semiconductor element.

  In recent years, manufacturing technology of a semiconductor light-emitting diode (hereinafter referred to as “LED”), which is one of semiconductor elements, has advanced rapidly, and since the development of blue LEDs in particular, LEDs of three primary colors of light have been prepared. Therefore, it became possible to produce light of all wavelengths by the combination of the three primary color LEDs. Therefore, it has been widely used in outdoor lighting, and recently it has been widely enjoyed in general households.

  In general, LEDs of three colors, red, green, and blue, each have different voltages required to pass the same current, which largely depends on the material. Therefore, it is inconvenient to place three color LEDs on the same substrate.

  For example, when a simple parallel circuit in which an AlGaInP red LED, an InGaN green LED, and an InGaN blue LED are mounted on the same substrate and the three colors are lit at a constant voltage drive, Since the current flows in proportion to the ratio of the resistance values, only the red LED shines at a voltage of 2 to 2.5V, while the current exceeding the absolute maximum rating flows to the red LED at a voltage of 3V or more. The red LED is destroyed.

Therefore, conventionally, constant voltage elements (zener diodes) that operate at a constant voltage are connected in parallel to the LEDs so that a uniform voltage can be applied to each LED, and the light sources emit light uniformly (Japanese Patent Application Laid-Open No. 2004-281279). Gazette: see Patent Document 1).
JP 2004-281279 A

  However, in the conventional semiconductor device, when three color LEDs are lit, it is necessary to separately connect a resistance component to the low resistance LED, which causes a problem that the circuit becomes complicated and the cost is increased.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device that can simplify the circuit by aligning the resistance values of the plurality of semiconductor devices without increasing the number of components when using a plurality of different types of semiconductor devices. Is to provide.

In order to solve the above problems, the semiconductor element of the present invention is
Having a first wafer and a second wafer bonded together by wafer bonding;
The bonding interface between the first wafer and the second wafer has a resistance;
The resistance value of the bonding interface is controlled so that the overall driving voltage becomes larger than the value obtained by adding the intrinsic voltage of the first wafer and the intrinsic voltage of the second wafer. It is characterized by being.

  According to the semiconductor element of the present invention, the first wafer and the second wafer are bonded to each other by wafer bonding, and the bonding interface between the first wafer and the second wafer has resistance. The semiconductor element includes a resistor, and there is no need to separately connect a resistance component to the semiconductor element.

  In addition, the resistance value of the bonding interface is controlled so that the entire driving voltage becomes larger than the value obtained by adding the intrinsic voltage of the first wafer and the intrinsic voltage of the second wafer. Therefore, the driving voltage of the semiconductor element can be adjusted with a simple configuration.

  Therefore, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be made uniform by controlling the resistance at the bonding interface, and the circuit can be simplified.

  In one embodiment, the first wafer has a light emitting layer.

  According to the semiconductor device of this embodiment, since the first wafer has the light emitting layer, it can be applied to the semiconductor light emitting device.

  In one embodiment, the second wafer has translucency.

  According to the semiconductor element of this embodiment, since the second wafer has translucency, the second wafer transmits the light emitted from the first wafer and the light extraction efficiency is improved. .

  In one embodiment, the first wafer includes a group III-V semiconductor layer in which gallium, aluminum, indium, phosphorus, arsenic, and nitrogen are combined.

  According to the semiconductor element of this embodiment, since the first wafer includes the III-V group semiconductor layer, the emission wavelength of the light emitting layer can be selected from a wide range from the infrared region to the near ultraviolet region.

  In one embodiment, the first wafer and the second wafer contain at least two of zinc, tellurium, sulfur, nitrogen, silicon, carbon, and oxygen as dopants.

  Also, in the method of manufacturing a semiconductor device according to the present invention, the first wafer and the second wafer are bonded to each other by wafer bonding so that the bonding interface between the first wafer and the second wafer has a resistance. It is characterized by doing.

  According to the semiconductor device manufacturing method of the present invention, the first wafer and the second wafer are bonded to each other by wafer bonding so that the bonding interface between the first wafer and the second wafer has a resistance. Therefore, the semiconductor element includes a resistor, and it is not necessary to separately connect a resistance component to the semiconductor element.

  Therefore, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be made uniform by controlling the resistance at the bonding interface, and the circuit can be simplified.

  In one embodiment of the method of manufacturing a semiconductor device, the resistance value of the bonding interface is controlled, and the overall drive voltage is determined as the specific voltage of the first wafer and the specific voltage of the second wafer. Adjust so that it is larger than the value obtained by adding and.

  According to the method of manufacturing a semiconductor device of this embodiment, the resistance value of the bonding interface is controlled so that the overall driving voltage is determined as the intrinsic voltage of the first wafer and the intrinsic voltage of the second wafer. Therefore, the driving voltage of the semiconductor device can be adjusted by a simple method.

  In one embodiment of the semiconductor device manufacturing method, the resistance value of the bonding interface is controlled according to the type of carrier of each bonding layer of the first wafer and the second wafer.

  According to the semiconductor element manufacturing method of this embodiment, the resistance value of the bonding interface is controlled by the type of carrier of each bonding layer of the first wafer and the second wafer. Thus, the driving voltage of the semiconductor element can be adjusted.

  In one embodiment of the method for manufacturing a semiconductor device, at least one bonding layer of the first wafer and the second wafer is a GaP epitaxial layer doped with Mg or Zn.

  In one embodiment of the method for manufacturing a semiconductor device, the driving voltage is adjusted by controlling the resistance value of the bonding interface by a combination of Mg and Zn, which are dopants of the epitaxial layer.

  According to the method of manufacturing a semiconductor device of this embodiment, the driving voltage is adjusted by controlling the resistance value of the bonding interface by a combination of Mg and Zn which are dopants of the epitaxial layer. Thus, the driving voltage of the semiconductor element can be adjusted.

  In one embodiment, at least one bonding layer of the first wafer and the second wafer has a surface doped with Mg or Zn by ion implantation or diffusion.

  According to the method of manufacturing a semiconductor device of this embodiment, at least one bonding layer of the first wafer and the second wafer has a surface doped with Mg or Zn by ion implantation or diffusion. The bonding interface resistance can be controlled by optimizing the carrier concentration of the bonding layer.

In one embodiment of the method for manufacturing a semiconductor device,
Each bonding layer of the first wafer and the second wafer has a surface doped with Mg or Zn by ion implantation or diffusion,
The drive voltage is adjusted by controlling the resistance value of the bonding interface according to the carrier concentration of the bonding layer of each of the first wafer and the second wafer.

  According to the method for manufacturing a semiconductor device of this embodiment, each bonding layer of the first wafer and the second wafer has a surface doped with Mg or Zn by ion implantation or diffusion. According to the carrier concentration of the bonding layer of each of the first wafer and the second wafer, the resistance value of the bonding interface is controlled and the driving voltage is adjusted. Therefore, by optimizing the carrier concentration of the bonding layer, The resistance of the bonding interface can be controlled.

In one embodiment of the method for manufacturing a semiconductor device,
The bonding layer of the first wafer is a GaP layer doped with Zn having a concentration of 2.5 to 3.5 × 10 ¹⁸ cm ⁻³ ,
The bonding layer of the second wafer is a GaP layer doped with Zn having a concentration of 0.5 to 1.5 × 10 ¹⁸ cm ⁻³ .
The driving voltage is set to 3 to 3.5 V by controlling the resistance value of the bonding interface.

According to the method for manufacturing a semiconductor element of this embodiment, the bonding layer of the first wafer is a GaP layer doped with Zn having a concentration of 2.5 to 3.5 × 10 ¹⁸ cm ⁻³ , and the second The bonding layer of the wafer is a GaP layer doped with Zn having a concentration of 0.5 to 1.5 × 10 ¹⁸ cm ⁻³ , the resistance value of the bonding interface is controlled, and the driving voltage is set to 3 to 3 Therefore, when the semiconductor element is a red light emitting element, the red light emitting element can be substantially matched to the driving voltage of the light emitting elements of other colors such as blue and green. Blue and green can be lit simultaneously.

  In one embodiment of the method for manufacturing a semiconductor device, the resistance value at the bonding interface is controlled by the pressure at the time of wafer bonding between the first wafer and the second wafer.

  According to the semiconductor element manufacturing method of this embodiment, the resistance value of the bonding interface is controlled by the pressure at the time of wafer bonding between the first wafer and the second wafer. The drive voltage of the semiconductor element can be adjusted.

  In one embodiment of the semiconductor device manufacturing method, the resistance value of the bonding interface is controlled by the temperature at the time of wafer bonding between the first wafer and the second wafer.

  According to the semiconductor element manufacturing method of this embodiment, the resistance value of the bonding interface is controlled by the temperature at the time of wafer bonding between the first wafer and the second wafer. The drive voltage of the semiconductor element can be adjusted.

  In one embodiment of the semiconductor device manufacturing method, the resistance value of the bonding interface is controlled according to the time of wafer bonding between the first wafer and the second wafer.

  According to the semiconductor element manufacturing method of this embodiment, the resistance value of the bonding interface is controlled by the time of wafer bonding between the first wafer and the second wafer. The drive voltage of the semiconductor element can be adjusted.

The semiconductor device of the present invention is
Having a plurality of semiconductor elements arranged in parallel with each other;
At least one of the plurality of semiconductor elements is the semiconductor element according to claim 1,
The at least one semiconductor element is characterized in that the resistance value of the bonding interface is controlled so as to have a driving voltage that substantially matches the driving voltage of the other semiconductor elements.

  According to the semiconductor device of the present invention, the resistance value of the bonding interface is controlled so that the at least one semiconductor element has a driving voltage that substantially matches the driving voltage of the other semiconductor element. Therefore, the resistance values of the plurality of semiconductor elements can be made uniform by controlling the resistance of the bonding interface, and the circuit can be simplified.

  In other words, by controlling the resistance value of the bonding interface so as to match the high resistance value of the other semiconductor element, the driving voltage of the semiconductor element can be made uniform without providing a separate resistance component. .

  According to the semiconductor device of the present invention, the first wafer and the second wafer are bonded to each other by wafer bonding, and the bonding interface between the first wafer and the second wafer has a resistance. The resistance value of the bonding interface is controlled so that the entire driving voltage is larger than the value obtained by adding the intrinsic voltage of the first wafer and the intrinsic voltage of the second wafer. Since it is adjusted, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be aligned without increasing the number of components, and the circuit can be simplified.

  According to the semiconductor device manufacturing method of the present invention, the first wafer and the second wafer are bonded to each other by wafer bonding so that the bonding interface between the first wafer and the second wafer has a resistance. Therefore, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be aligned without increasing the number of components, and the circuit can be simplified.

  According to the semiconductor device of the present invention, the resistance value of the bonding interface is controlled so that the at least one semiconductor element has a driving voltage that substantially matches the driving voltage of the other semiconductor element. Therefore, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be made uniform without increasing the number of components, and the circuit can be simplified.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  FIG. 1 is a simplified configuration diagram showing an embodiment of a semiconductor device according to the present invention. A semiconductor element 1 of the present invention (hereinafter referred to as a wafer bonding type semiconductor element 1) has a first wafer 10 and a second wafer 20, and the first wafer 10 and the second wafer 20 are: They are bonded to each other by wafer bonding.

  The first wafer 10 and the second wafer 20 have bonding layers 11 and 21, respectively. The bonding interface 30 between the first wafer 10 and the second wafer 20 has a resistance.

  The first wafer 10 has a light emitting layer. The second wafer 20 has translucency. That is, the wafer bonding type semiconductor device 1 is a semiconductor light emitting device.

  The first wafer 10 includes a group III-V semiconductor layer in which gallium, aluminum, indium, phosphorus, arsenic, and nitrogen are combined.

  The first wafer 10 and the second wafer 20 contain at least two of zinc, tellurium, sulfur, nitrogen, silicon, carbon, and oxygen as dopants.

  The resistance value of the bonding interface 30 is controlled so that the entire driving voltage becomes larger than the value obtained by adding the intrinsic voltage of the first wafer 10 and the intrinsic voltage of the second wafer 20. It has been adjusted.

  The resistance value R of the wafer bonding type semiconductor element 1 is R = (resistance value of the first wafer 10) + (resistance value of the second wafer 20) + (resistance of the bonding interface 30).

The voltage of the first wafer 10 and _{E 10,} the voltage of the second wafer 20 and _{E 20,} when the voltage of the bonded interface 30 and _{E 30,} the total voltage E _{is, E} = E 10 _{+ E 20} + _{E 30,} and the by adjusting the voltage _{E 30} (i.e., it in adjusting the resistance value R), the total voltage _E, so that the _{E> E} 10 _{+ E 20,} is adjusted. The voltages E ₁₀ and E ₂₀ are unique values depending on the materials and structures of the first wafer 10 and the second wafer 20.

  Here, as shown in FIG. 2, conventionally, a semiconductor device is manufactured by arranging a first semiconductor element 2 that is not a wafer bonding type and a second semiconductor element 3 that is not a wafer bonding type in parallel with each other. When the resistance value R2 of the first semiconductor element 2 is larger than the resistance value R3 of the second semiconductor element 3, the first semiconductor element 2 does not emit light, and the second semiconductor element 3 had a large current.

  Therefore, as shown in FIG. 3, by using the wafer bonding type semiconductor element 1 instead of the second semiconductor element 3, the resistance value R2 of the first semiconductor element 2 is increased to the wafer bonding type semiconductor element. The resistance value R1 of the element 1 can be matched. That is, the resistance value R1 of the wafer bonding semiconductor element 1 is equal to the resistance value R3 of the second semiconductor element 3 plus the resistance value of the bonding interface 30.

  In short, the resistance value of the bonding interface 30 is controlled so that the wafer bonding type semiconductor element 1 has a driving voltage that substantially matches the driving voltage of the first semiconductor element 2.

  Therefore, since the current flows equally between the wafer bonding type semiconductor element 1 and the first semiconductor element 2, the problem described with reference to FIG. 2 is solved.

  For example, when an InGaN blue LED chip or lamp is used for the first semiconductor element 2, an AlGaInP wafer bonding red LED chip or lamp is used for the wafer bonding semiconductor element 1.

  The wafer bonding type semiconductor element 1 is selected in accordance with the driving voltage in the operating current range of the first semiconductor element 2.

  For example, when it is desired to use the operating current IF at 20 mA, if the driving voltage VF of the first semiconductor element 2 is 3.2 V, the wafer bonding type semiconductor element 1 is connected to the driving voltage when the operating current IF is 20 mA. An element having a VF close to 3.2V is used.

  When three or more semiconductor elements are connected in parallel, if a wafer bonding type semiconductor element is used for the other semiconductor elements in accordance with the semiconductor element having the highest driving voltage, no resistance component is required. .

  Next, a method for manufacturing the wafer bonding semiconductor element 1 will be described.

First, the first wafer 10 is formed. As shown in FIG. 4, an n-type GaAs buffer layer 13, an Al _0.6 Ga _0.4 As current diffusion layer 14, an n-type Al _0.5 In _0.5 P are formed on an n-type GaAs substrate 12 by MOCVD. The clad layer 15, the AlGaInP active layer 16, the p-type Al _0.5 In _0.5 P clad layer 17, the p-type GaInP intermediate layer 18 and the p-type GaP contact layer 19 are laminated in this order, and the first An LED structure wafer is prepared as one wafer 10.

The AlGaInP active layer 16 has a quantum well structure. More specifically, the AlGaInP active layer 16 includes an (Al _0.05 Ga _0.95 ) _0.5 In _0.5 P well layer and an (Al _0.5 Ga _0.5 ) _0.5 In _0.5. It is formed by alternately stacking P barrier layers. The number of pairs of the well layer and the barrier layer is, for example, 4 pairs.

The n-type GaAs substrate 12 has a thickness of 250 μm, the n-type GaAs buffer layer 13 has a thickness of 1.0 μm, and the Al _0.6 Ga _0.4 As current diffusion layer 14 has a thickness of 5 μm. The thickness of the n-type AlGaInP clad layer 15 is 1.0 μm, the thickness of the AlGaInP active layer 16 is 0.5 μm, and the p-type Al _0.5 In _0.5 P clad is The layer 17 has a thickness of 1.0 μm, the p-type GaInP intermediate layer 18 has a thickness of 1.0 μm, and the p-type GaP contact layer 19 has a thickness of 4.0 μm.

  In each of the above layers 12 to 19, Si is used as an n-type dopant. On the other hand, Mg or Zn is used as a p-type dopant of other layers excluding the GaP contact layer 19.

  Thereafter, as shown in FIG. 5, the second wafer 20 is directly bonded to the first wafer 10 using a wafer bonding jig 50. As the second wafer 20, a p-type GaP translucent substrate is used.

  The wafer bonding jig 50 is made of, for example, quartz, and includes a lower base 51 that supports the wafers 10 and 20, a pressing plate 52 that covers the upper surface of the second wafer 20, and a force having a predetermined magnitude. And a pressing portion 53 that presses the pressing plate 52.

  The pressing portion 53 is guided in the vertical direction by a frame body 54 formed in a substantially U shape when viewed from the front. The frame body 54 engages with the lower base 51 and appropriately transmits a force to the pressing plate 52 positioned between the lower base 51 and the pressing portion 53.

  The first wafer 10 is placed on the lower base 51 so that the bonding layer of the first wafer 10 faces upward, and the second wafer 10 is placed on the bonding layer of the first wafer 10. The second wafer 20 is overlaid on the first wafer 10 so that the bonding layer of the wafer 20 contacts.

  As shown in FIGS. 1 and 4, in the first wafer 10, the p-type GaP contact layer 19 includes a bonding layer 11. On the other hand, in the second wafer 20, the p-type GaP translucent substrate includes a bonding layer 21.

  Using the wafer bonding jig 50, the first wafer 10 and the second wafer 20 are brought into contact with each other, and a force is applied to the pressing portion 53, whereby the first wafer 10 and the second wafer 20 are contacted. A compressive force is applied to the contact surface with the wafer 20. A carbon plate 29 is disposed between the pressing plate 52 and the second wafer 20.

  In this state, the first wafer 10 and the second wafer 20 are set in a heating furnace together with the wafer bonding jig 50 and heated in a hydrogen atmosphere. Thus, the first wafer 10 and the second wafer 20 are bonded to each other by wafer bonding.

  Thereafter, AnBe / Au is selected as the material for the p-type electrode, AuSi / Au is selected as the material for the n-type electrode, and these materials are stacked, and an arbitrary photolithography method and wet etching are performed. Process into shape. Then, an n-type electrode is formed on the n-type GaAs substrate 12 of the first wafer 10 and a p-type electrode is formed on the second wafer 20, and then divided into a desired chip size by dicing or the like. Then, the semiconductor light emitting device as the wafer bonding type semiconductor device 1 is manufactured by dividing the chip.

  In this wafer bonding type semiconductor element 1, a light transmitting substrate is used as the second wafer 20. Therefore, when a red LED is used as the wafer bonding type semiconductor element 1, the light transmitting substrate is bonded. Before the light emitting output, the light emission output of the absorption substrate type element is 0.8 mW, and after the light-transmitting substrate is bonded, the light emission output is about 8 mW, which is 10 times larger, and the external emission efficiency of light emission is increased. Was confirmed to be improved.

Here, in order to further increase the light emission efficiency of the wafer bonding type semiconductor element 1, an absorption substrate removing step is added. That is, after the first wafer 10 and the second wafer 20 that are directly bonded are cooled, the first wafer 10 and the second wafer 20 are taken out from a heating furnace, and then ammonia water, hydrogen peroxide The n-type GaAs substrate 12 and the n-type GaAs buffer layer 13 are dissolved and removed with a mixed solution of water and water. Thereafter, an n-type electrode is formed on the Al _0.6 Ga _0.4 As current diffusion layer 14 of the first wafer 10, and a p-type electrode is formed on the second wafer 20.

  Although the n-type GaAs substrate 12 and the n-type GaAs buffer layer 13 absorb light from the AlGaInP active layer 16, the n-type GaAs substrate 12 and the n-type GaAs buffer layer 13 are removed. The n-type substrate and the n-type buffer layer made of a material that does not absorb light from the AlGaInP active layer 16 need not be removed.

  In the present invention, the first wafer 10 and the second wafer 20 are bonded to each other by wafer bonding so that the bonding interface 30 between the first wafer 10 and the second wafer 20 has a resistance. To do.

  The resistance value of the bonding interface 30 is controlled so that the overall drive voltage becomes larger than the value obtained by adding the intrinsic voltage of the first wafer 10 and the intrinsic voltage of the second wafer 20. To adjust.

  More specifically, the resistance value of the bonding interface 30 is controlled by the types of carriers of the bonding layer 11 of the first wafer 10 and the bonding layer 21 of the second wafer 20.

  The bonding layer 11 of the first wafer 10 and the bonding layer 21 of the second wafer 20 are GaP epitaxial layers doped with Mg or Zn. The drive voltage is adjusted by controlling the resistance value of the bonding interface 30 by a combination of Mg and Zn which are dopants of the epitaxial layer.

  The bonding layer 11 of the first wafer 10 and the bonding layer 21 of the second wafer 20 may have surfaces doped with Mg or Zn by ion implantation or diffusion.

For example, as shown in FIGS. 6A and 6B, when the second wafer 20 is a Zn-doped GaP single crystal substrate and the bonding layer of the first wafer 10 is a p-type GaP contact layer 19, FIG. As shown in FIG. 6, when the dopant to the bonding layer of the first wafer 10 is Zn, the resistance value of the bonding interface is reduced, while the bonding layer of the first wafer 10 is shown in FIG. 6B. It was confirmed that the resistance value of the bonding interface tends to increase when the dopant is Mg. At this time, the concentration of Zn dopant in the second wafer 20 is 5 × 10 ¹⁷ cm ⁻³ , and the concentration of Zn dopant in the first wafer 10 is 3 × 10 ¹⁸ cm ⁻³ . The concentration of the Mg dopant in the first wafer 10 is 3 × 10 ¹⁸ cm ⁻³ .

FIG. 7 shows the relationship between the type and concentration of dopant in the bonding layer of the first wafer 10 and the driving voltage VF (V) of the semiconductor element at 20 mA. In FIG. 7, the pressure (tightening torque) of the pressing portion 53 shown in FIG. 5 is set to 0.5 Nm ⁻¹ .

  As can be seen from FIG. 7, when the dopant concentration is the same, the Mg dopant has a higher driving voltage (that is, the resistance value at the bonding interface) than the Zn dopant. In the Zn dopant, the driving voltage (that is, the resistance value of the bonding interface) decreases as the dopant concentration increases.

  That is, by adjusting the driving voltage by controlling the resistance value of the bonding interface 30 according to the carrier concentration of the bonding layer 11 of the first wafer 10 and the bonding layer 21 of the second wafer 20, The drive voltage can be set more finely.

For example, the bonding layer of the first wafer 10 is a GaP layer doped with Zn having a concentration of 2.5 to 3.5 × 10 ¹⁸ cm ⁻³ , and the bonding layer of the second wafer 20 is a concentration of As a GaP layer doped with 0.5 to 1.5 × 10 ¹⁸ cm ⁻³ of Zn, the resistance value of the bonding interface 30 is controlled to set the driving voltage to 3 to 3.5V.

  Therefore, when this semiconductor element is a red light emitting element, the red light emitting element can be substantially aligned with the driving voltage of the light emitting elements of other colors such as blue and green, and red, blue and green can be obtained. Can be lit simultaneously.

  More specifically, in order to simultaneously turn on the red, blue and green light emitting elements, the blue and green light emitting elements are often InGaN-based, the use current If is 20 mA, and the driving voltage VF is 3 to 3. About 5V is common.

  At this time, the red light emitting element is often used in combination because the InGaAlP system is bright. In this case, the InGaAlP system usually has a use current If of 20 mA and a drive voltage VF of 1.9 to 2. Since the voltage is about 0.0 V, the driving voltage can be set to 3 to 3.5 V when the operating current If is 20 mA by using a wafer bonding type semiconductor element for the red light emitting element.

FIG. 8 shows a relationship between the pressure (Nm ⁻¹ ) of the pressing portion 53 shown in FIG. In FIG. 8, the concentration of the dopant of Zn of the second wafer 20 is 5 × ¹⁰ 17 ^{cm -3,} the concentration of dopant of Mg of the first wafer 10 is 3 × ¹⁰ 18 cm ^{- 3} .

  As can be seen from FIG. 8, the driving voltage of the semiconductor element (that is, the resistance value of the bonding interface) decreases as the pressure of the pressing portion 53 increases.

  As described above, the resistance value of the bonding interface 30 can be controlled by the pressure at the time of wafer bonding between the first wafer 10 and the second wafer 20, and a simple method can be used. The drive voltage can be adjusted.

  Note that the resistance value of the bonding interface 30 may be controlled by the temperature at the time of wafer bonding between the first wafer 10 and the second wafer 20, and the driving voltage of the semiconductor element can be controlled by a simple method. Can be adjusted.

  Further, the resistance value of the bonding interface 30 may be controlled according to the time of wafer bonding between the first wafer 10 and the second wafer 20, and the driving voltage of the semiconductor element can be controlled by a simple method. Can be adjusted.

  According to the semiconductor element having the above configuration, the first wafer 10 and the first wafer 20 are bonded to each other by wafer bonding, and the bonding interface 30 between the first wafer 10 and the second wafer 20 is Since the semiconductor element includes a resistor, it is not necessary to separately connect a resistance component to the semiconductor element.

  Further, the resistance value of the bonding interface 30 is controlled so that the entire driving voltage is larger than the value obtained by adding the unique voltage of the first wafer 10 and the unique voltage of the second wafer 20. Since it is adjusted, the driving voltage of the semiconductor element can be adjusted with a simple configuration.

  Therefore, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be made uniform by controlling the resistance of the bonding interface 30 and the circuit can be simplified.

  Further, since the first wafer 10 has a light emitting layer, it can be applied to a semiconductor light emitting element.

  Further, since the second wafer 20 has translucency, the second wafer 20 transmits the light emitted from the first wafer 10 and the light extraction efficiency is improved.

  In addition, since the first wafer 10 includes a group III-V semiconductor layer, the emission wavelength of the light emitting layer can be selected from a wide range from the infrared region to the near ultraviolet region.

  According to the method for manufacturing a semiconductor device having the above-described configuration, the first wafer 10 and the second wafer 20 are bonded so that the bonding interface 30 between the first wafer 10 and the second wafer 20 has a resistance. Since they are bonded to each other by wafer bonding, the semiconductor element includes a resistor, and there is no need to separately connect a resistance component to the semiconductor element.

  Therefore, when a plurality of different types of semiconductor elements are used, the resistance values of the plurality of semiconductor elements can be made uniform by controlling the resistance of the bonding interface 30 and the circuit can be simplified.

  Further, the resistance value of the bonding interface 30 is controlled so that the overall drive voltage is larger than the value obtained by adding the unique voltage of the first wafer 10 and the unique voltage of the second wafer 20. Therefore, the drive voltage of the semiconductor element can be adjusted by a simple method.

  In addition, since the resistance value of the bonding interface 30 is controlled according to the types of carriers of the bonding layers 11 and 21 of the first wafer 10 and the second wafer 20, a simple method can be used. The drive voltage can be adjusted.

  Further, since the driving voltage is adjusted by controlling the resistance value of the bonding interface 30 by the combination of Mg and Zn which are dopants of the epitaxial layer, the driving voltage of the semiconductor element can be adjusted by a simple method.

  Since at least one of the bonding layers 11 and 21 of the first wafer 10 and the second wafer 20 has a surface doped with Mg or Zn by ion implantation or diffusion, The resistance of the bonding interface 30 can be controlled by optimizing the carrier concentration.

  The bonding layers 11 and 21 of the first wafer 10 and the second wafer 20 have surfaces doped with Mg or Zn by ion implantation or diffusion, respectively. Since the driving voltage is adjusted by controlling the resistance value of the bonding interface 30 according to the carrier concentration of each of the bonding layers 11 and 21 of the second wafer 20, the carrier concentration of the bonding layers 11 and 21 is optimized. Thus, the resistance of the bonding interface 30 can be controlled.

  According to the semiconductor device having the above configuration, the resistance value of the bonding interface 30 is controlled so that the at least one semiconductor element has a driving voltage that substantially matches the driving voltage of the other semiconductor element. Therefore, the resistance values of the plurality of semiconductor elements can be made uniform by controlling the resistance of the bonding interface 30 and the circuit can be simplified.

  In other words, by controlling the resistance value of the bonding interface 30 so as to match the high resistance value of the other semiconductor element, the driving voltage of the semiconductor element can be adjusted without providing a separate resistance component. it can.

  In addition, this invention is not limited to the above-mentioned embodiment. For example, the first wafer and the second wafer may have a single layer or a multilayer structure. Needless to say, the present invention is not limited to a light emitting diode having a quaternary AlGaInP light emitting layer, but can be applied to any semiconductor light emitting element having a light emitting layer made of a semiconductor crystal.

It is a simplified lineblock diagram showing one embodiment of a semiconductor device of the present invention. It is a circuit diagram of the conventional semiconductor device. It is a circuit diagram of a semiconductor device of the present invention. It is a simplified block diagram which shows a 1st wafer. It is a simplified block diagram which shows the jig | tool for wafer bonding. It is explanatory drawing explaining the bonding of the 1st wafer and the 2nd wafer when the dopant to the bonding layer of the 1st wafer is Zn. It is explanatory drawing explaining the bonding of the 1st wafer and the 2nd wafer when the dopant to the bonding layer of the 1st wafer is Mg. It is a graph which shows the relationship between the kind and density | concentration of the dopant to the bonding layer of a 1st wafer, and the drive voltage of a semiconductor element in 20 mA. It is a graph which shows the relationship between the pressure at the time of wafer bonding with a 1st wafer and a 2nd wafer, and the drive voltage of a semiconductor element in 20 mA.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 (Wafer bonding type semiconductor element of this invention) 2 1st semiconductor element which is not wafer bonding type 3 2nd semiconductor element which is not wafer bonding type 10 1st wafer 11 Bonding layer 20 2nd wafer 21 Bonding layer 30 Bonding interface 50 Jig for wafer bonding

Claims (17)

Having a first wafer and a second wafer bonded together by wafer bonding;
The bonding interface between the first wafer and the second wafer has a resistance;
The resistance value of the bonding interface is controlled so that the overall driving voltage becomes larger than the value obtained by adding the intrinsic voltage of the first wafer and the intrinsic voltage of the second wafer. A semiconductor element characterized by being made. The semiconductor device according to claim 1,
The semiconductor element, wherein the first wafer has a light emitting layer. The semiconductor device according to claim 2,
The semiconductor element, wherein the second wafer has translucency. The semiconductor device according to claim 2,
The first wafer includes a group III-V semiconductor layer in which gallium, aluminum, indium, phosphorus, arsenic, and nitrogen are combined. The semiconductor device according to claim 1,
The first and second wafers contain at least two of zinc, tellurium, sulfur, nitrogen, silicon, carbon, and oxygen as dopants.   A method of manufacturing a semiconductor device, wherein the first wafer and the second wafer are bonded to each other by wafer bonding so that a bonding interface between the first wafer and the second wafer has a resistance. In the manufacturing method of the semiconductor device according to claim 6,
By controlling the resistance value of the bonding interface, the overall drive voltage is adjusted to be larger than the sum of the unique voltage of the first wafer and the unique voltage of the second wafer. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, comprising: controlling a resistance value of the bonding interface according to a carrier type of each bonding layer of the first wafer and the second wafer. In the manufacturing method of the semiconductor device according to claim 6,
A method of manufacturing a semiconductor device, wherein at least one bonding layer of the first wafer and the second wafer is an epitaxial layer of GaP doped with Mg or Zn. In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the driving voltage is adjusted by controlling a resistance value of the bonding interface by a combination of Mg and Zn as dopants of the epitaxial layer. In the manufacturing method of the semiconductor device according to claim 6,
The method for manufacturing a semiconductor device, wherein at least one bonding layer of the first wafer and the second wafer has a surface doped with Mg or Zn by ion implantation or diffusion. In the manufacturing method of the semiconductor device according to claim 6,
Each bonding layer of the first wafer and the second wafer has a surface doped with Mg or Zn by ion implantation or diffusion,
A method of manufacturing a semiconductor device, wherein the driving voltage is adjusted by controlling the resistance value of the bonding interface according to the carrier concentration of each bonding layer of the first wafer and the second wafer. . In the manufacturing method of the semiconductor device according to claim 6,
The bonding layer of the first wafer is a GaP layer doped with Zn having a concentration of 2.5 to 3.5 × 10 ¹⁸ cm ⁻³ ,
The bonding layer of the second wafer is a GaP layer doped with Zn having a concentration of 0.5 to 1.5 × 10 ¹⁸ cm ⁻³ .
A method of manufacturing a semiconductor device, wherein the driving voltage is set to 3 to 3.5 V by controlling a resistance value of the bonding interface. In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor element, wherein a resistance value of the bonding interface is controlled by a pressure at the time of wafer bonding between the first wafer and the second wafer. In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, comprising: controlling a resistance value of the bonding interface according to a temperature at the time of wafer bonding between the first wafer and the second wafer. In the manufacturing method of the semiconductor device according to claim 7,
A method of manufacturing a semiconductor device, comprising: controlling a resistance value of the bonding interface according to a wafer bonding time between the first wafer and the second wafer. Having a plurality of semiconductor elements arranged in parallel with each other;
At least one of the plurality of semiconductor elements is the semiconductor element according to claim 1,
A semiconductor device, wherein the resistance value of the bonding interface is controlled so that the at least one semiconductor element has a driving voltage that substantially matches the driving voltage of the other semiconductor element.

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