JP2008234433A - Processor including oscillator circuit and constant voltage power source circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for making an oscillator circuit stably oscillate when a constant voltage power source circuit for oscillator circuit intermittently operates. <P>SOLUTION: A processor connected to an external device is provided with: a first constant voltage power source circuit for generating a first power supply voltage; an oscillator circuit for generating an oscillation signal by operating with the first power supply voltage; and an operation control circuit for controlling the operation of the first constant voltage power supply voltage circuit. The operation control circuit makes the first constant voltage power source circuit intermittently operate in a first period, and makes the first constant voltage power source circuit continuously operate in a second period when a data signal is transmitted between the processor and an external device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a processing apparatus including an oscillation circuit and a constant voltage power supply circuit.

  Electronic devices such as personal computers are usually provided with a timekeeping device called an RTC (real time clock). Even when the main power supply of the electronic device is set to an off state, the time measuring device performs time measuring processing using a battery for the time measuring device built in the electronic device.

  The timing device usually includes an oscillation circuit and a constant voltage power supply circuit. The constant voltage power supply circuit operates at a relatively high first power supply voltage, generates a relatively low second power supply voltage, and supplies the second power supply voltage to the oscillation circuit. Then, the oscillation circuit operates with the second power supply voltage and generates an oscillation signal.

  If the constant voltage power supply circuit is operated intermittently, more specifically, if the constant voltage power supply circuit is operated intermittently using the first power supply voltage, the power consumption of the timer circuit can be reduced. Can do.

JP 2000-232728 A JP 2002-91583 A JP-A-8-272463 JP-A-10-160867

  By the way, when the constant voltage power supply circuit operates intermittently, there is a possibility that stable oscillation of the oscillation circuit may be difficult. Specifically, the oscillation of the oscillation circuit may become unstable or stop.

  Note that the above problem is not a problem specific to the timing device, but a problem common to processing devices including an oscillation circuit and a constant voltage power supply circuit for the oscillation circuit.

  The present invention has been made to solve the above-described problems in the prior art, and has an object to stably oscillate an oscillation circuit when a constant voltage power supply circuit for the oscillation circuit operates intermittently. To do.

In order to solve at least a part of the problems described above, a first apparatus of the present invention is a processing apparatus connected to an external device,
A first constant voltage power supply circuit for generating a first power supply voltage;
An oscillation circuit that operates with the first power supply voltage to generate an oscillation signal;
An operation control circuit for controlling the operation of the first constant voltage power supply circuit;
With
The operation control circuit includes:
In the first period, the first constant voltage power supply circuit is intermittently operated,
In the second period in which a data signal is transmitted between the processing device and the external device, the first constant voltage power supply circuit is continuously operated.

  In the first period, since the first constant voltage power supply circuit operates intermittently, the power consumption of the processing apparatus can be reduced. In the second period, the first power supply voltage is likely to fluctuate, and stable oscillation of the oscillation circuit may be difficult. However, in the second period, since the first constant voltage power supply circuit operates continuously, the oscillation circuit can oscillate stably.

In the above device,
The operation control circuit further includes:
It is preferable that the first constant voltage power supply circuit is continuously operated in a period immediately after the end of the second period.

  The first power supply voltage is likely to fluctuate immediately after the end of the second period. However, with the above configuration, the oscillation circuit can oscillate stably even in the period immediately after the end of the second period.

In the above device,
The operation control circuit further includes:
It is preferable that the first constant voltage power supply circuit is continuously operated during a third period in which a clock signal based on the oscillation signal is output from the processing device to the external device.

  In the third period, the first power supply voltage is likely to fluctuate, and stable oscillation of the oscillation circuit may be difficult. However, with the above configuration, the oscillation circuit can oscillate stably even in the third period.

In the above apparatus,
The operation control circuit further includes:
It is preferable that the first constant voltage power supply circuit is continuously operated in a period immediately after the end of the third period.

  The first power supply voltage is likely to fluctuate immediately after the end of the third period. However, with the above configuration, the oscillation circuit can oscillate stably even in the period immediately after the end of the third period.

In the above apparatus,
A clock signal output circuit for outputting the clock signal;
The clock signal output circuit includes:
Prohibiting the output of the clock signal in a first partial period of the third period immediately after the start of the third period;
In the third period, it is preferable that the output of the clock signal is permitted in a second partial period after the end of the first partial period.

  If the output of the clock signal is allowed immediately after the start of the third period, stable oscillation of the oscillation circuit may be difficult. However, with the above configuration, the oscillation circuit can oscillate stably even in the first partial period immediately after the start of the third period.

In the above device,
The clock signal output circuit includes:
It is preferable that the output of the clock signal output circuit is set in a high impedance state during the first partial period of the third period.

In the above apparatus,
A voltage increasing circuit for increasing the first power supply voltage output from the first constant voltage power supply circuit;
The operation control circuit includes:
It is preferable that the first constant voltage power supply circuit is continuously operated during a fourth period in which the voltage increase circuit increases the first power supply voltage output from the first constant voltage power supply circuit.

  In the fourth period, if the first constant voltage power supply circuit operates continuously, the first power supply voltage can be increased quickly and sufficiently. Therefore, when it is difficult to stably oscillate the oscillation circuit immediately before the fourth period, the oscillation circuit can oscillate stably and quickly in the fourth period.

In the above device,
The operation control circuit further includes:
It is preferable that the first constant voltage power supply circuit is continuously operated in a period immediately after the end of the fourth period.

  Immediately after the end of the fourth period, the first power supply voltage decreases, and there is a possibility that stable oscillation of the oscillation circuit may be difficult. However, with the above configuration, the oscillation circuit can oscillate stably even in the period immediately after the end of the fourth period.

In the above apparatus,
A detection circuit for detecting a stop of oscillation of the oscillation circuit;
The fourth period preferably includes a period in which the detection circuit detects a stop of oscillation.

  In this way, when the oscillation stop is detected, the oscillation circuit can start oscillation quickly and reliably.

In the above device,
The fourth period preferably includes a period immediately after the start of supply of the external power supply voltage to the processing apparatus.

  Before the supply of the external power supply voltage to the processing device is started, the oscillation of the oscillation circuit is stopped. According to the above configuration, the oscillation circuit can start oscillation quickly and reliably after the supply of the external power supply voltage is started.

In the above apparatus,
A second constant voltage power supply circuit for generating a second power supply voltage;
A frequency divider that operates with the second power supply voltage and divides the oscillation signal;
With
The operation control circuit includes:
During the period in which the first constant voltage power circuit is operated intermittently, the second constant voltage power circuit is operated intermittently;
The second constant voltage power supply circuit may be continuously operated during a period in which the first constant voltage power supply circuit is continuously operated.

  In this apparatus, since the first constant voltage power supply circuit and the second constant voltage power supply circuit operate intermittently or continuously at the same time, low power consumption of the processing apparatus including the frequency divider circuit can be realized. In addition, the frequency divider circuit can be operated stably. In addition, since the first constant voltage power supply circuit for the oscillation circuit and the second constant voltage power supply circuit for the frequency divider circuit are provided independently, noise is generated between the oscillation circuit and the frequency divider circuit. Can be prevented from propagating.

A second apparatus of the present invention is a processing apparatus connected to an external device,
A first constant voltage power supply circuit for generating a first power supply voltage;
An oscillation circuit that operates with the first power supply voltage to generate an oscillation signal;
An operation control circuit for controlling the operation of the first constant voltage power supply circuit;
With
The operation control circuit includes:
In the first period, the first constant voltage power supply circuit is intermittently operated,
In response to a request from the external device, the first constant voltage power supply circuit is continuously operated during a second period in which a signal is transmitted between the processing apparatus and the external device. To do.

  The second device has the same operation and effect as the first device, and can oscillate stably in the oscillation circuit.

  The signal may include data written into the processing device or data read from the processing device. The signal may include a clock signal based on the oscillation signal.

  The present invention can be realized in various forms, for example, a processing device such as a time measuring device, an electronic device including the processing device, a control method of the processing device, and a function or method of these devices. For example, a recording medium storing the computer program, a data signal including the computer program and embodied in a carrier wave, and the like.

Next, embodiments of the present invention will be described in the following order based on examples.
A. Configuration of RTC module:
B. Intermittent operation:
B-1. Oscillator circuit regulator configuration:
B-2. Divider circuit configuration:
B-3. Logic circuit regulator configuration:
B-4. Configuration of the reference voltage generation circuit:
B-5. Operation according to the operation control signal:
B-6. Configuration and operation of operation control signal generation circuit:
C. Prohibition of intermittent operation:
C-1. Interruption of intermittent operation due to data communication processing:
C-2. Interruption of intermittent operation due to clock output processing:
C-3. Interruption of intermittent operation when oscillation is stopped:
C-4. Prohibition of intermittent operation at power-on:
C-5. Execution and prohibition of intermittent operation:
D. Regulator separation:

A. Configuration of RTC module:
FIG. 1 is an explanatory diagram showing an internal configuration of an RTC (real time clock) module 100 provided in an electronic apparatus. In FIG. 1, an RTC module 100 and a CPU 600 provided outside the RTC module 100 are depicted. Note that examples of the electronic device include a personal computer, a digital camera, a mobile phone, and a portable information terminal.

  In the drawing, the bold line indicates the power supply voltage applied to each circuit in the RTC module 100. Reference sign “VD” indicates an external power supply voltage supplied from outside the RTC module 100 (for example, a battery for the RTC module). Reference numerals “VRO”, “VRD”, and “VRL” indicate internal power supply voltages generated inside the RTC module 100. In this embodiment, the external power supply voltage VD is set to about 5.0V. The three internal power supply voltages VRO, VRD, and VRL are set to about 0.7V, about 1.0V, and about 1.8V, respectively. Each circuit is provided with a power supply voltage on the high voltage side indicated by reference signs “VD”, “VRO”, “VRD”, and “VRL”, and a power supply voltage on the low voltage side indicated by reference sign “VS”. (About 0V) is given.

  The RTC module 100 includes an oscillation circuit 110, a frequency divider circuit 120, a logic circuit 130, an oscillator circuit regulator 210, a frequency divider circuit regulator 220, and a logic circuit regulator 230. The RTC module 100 also includes a reference voltage generation circuit 240, an oscillation stop detection circuit 360, a power-on reset circuit 370, and an interface (IF) circuit 400.

  The three regulators 210, 220, and 230 are constant voltage power supply circuits that operate on the external power supply voltage VD and generate three types of internal power supply voltages VRO, VRD, and VRL. The oscillation circuit regulator 210 generates the first internal power supply voltage VRO and supplies it to the oscillation circuit 110. The frequency divider regulator 220 generates the second internal power supply voltage VRD and supplies it to the frequency divider 120. The logic circuit regulator 230 generates the third internal power supply voltage VRL and supplies it to the logic circuit 130.

  The reference voltage generation circuit 240 generates a reference voltage Vref and supplies it to the three regulators 210, 220, and 230. The reference voltage Vref is applied to a constant current circuit provided in each regulator 210, 220, 230 as will be described later. The reference voltage generation circuit 240 includes a level shift circuit 242 described later. The level shift circuit 242 may be provided outside the reference voltage generation circuit 240.

  The oscillation circuit 110 is connected to a crystal resonator 101 provided in the RTC module 100, generates a reference clock signal FS, and supplies the reference clock signal FS to the frequency dividing circuit 120. As is well known, the oscillation circuit 110 includes an inverting amplifier connected in parallel to the crystal resonator 101 and a feedback resistor connected in parallel to the crystal resonator 101. In this embodiment, the reference clock signal FS has a frequency of about 32 kHz (exactly 32768 Hz).

  The frequency dividing circuit 120 divides the reference clock signal FS having a relatively high frequency to generate two divided clock signals FD1 and FD2 having a relatively low frequency. Further, the frequency dividing circuit 120 outputs a clock signal FD0 having the same frequency as the reference clock signal FS. The three clock signals FD0, FD1, and FD2 are supplied to the logic circuit 130. In the present embodiment, the two frequency-divided clock signals FD1, FD2 have frequencies of about 4 kHz (exactly 4096 Hz) and 1 kHz (exactly 1024 Hz), respectively.

  Level shift circuits (not shown) are provided in the input stage and the output stage in the frequency dividing circuit 120. The level shift circuit in the input stage can exchange signals between the oscillation circuit 110 operating at the power supply voltage VRO and the frequency dividing circuit 120 operating at the power supply voltage VRD. The level shift circuit at the output stage enables transmission / reception of signals between the frequency dividing circuit 120 operating at the power supply voltage VRD and the logic circuit 130 operating at the power supply voltage VRL. As can be seen from this description, the voltage levels of the clock signals FD0 to FD2 output from the frequency dividing circuit 120 are higher than the voltage level of the reference clock signal FS input to the frequency dividing circuit 120. Note that the level shift circuits of the input stage and the output stage may be provided outside the frequency dividing circuit 120.

  The logic circuit 130 includes a timer circuit 302, an operation control signal generation circuit 310, and a boost signal generation circuit 320.

  The timer circuit 302 includes a frequency dividing circuit and a counter. The frequency dividing circuit uses the clock signals FD0, FD1, and FD2 having relatively high frequencies to generate various clock signals having relatively low frequencies. The counter counts seconds, minutes, hours, days, days of the week, years, etc. using the generated clock signal.

  The operation control signal generation circuit 310 generates an operation control signal LPW for controlling operations of the four circuits 210, 220, 230, and 240. The operation control signal LPW is given to the level shift (LS) circuit 242, and the LS circuit 242 generates two switch signals LPV and XLPV having different logic levels in accordance with the operation control signal LPW. The two switch signals LPV and XLPV are supplied to the three regulators 210, 220 and 230 and the reference voltage generation circuit 240. Note that the LS circuit 242 enables transmission and reception of signals between the logic circuit 130 operating at the power supply voltage VRL and the circuits 210, 220, 230, and 240 operating at the power supply voltage VD.

  The boost signal generation circuit 320 generates a boost signal BST for adjusting the two internal power supply voltages VRO and VRD generated by the two regulators 210 and 220. The boost signal BST is generated based on the detection signal FSTOP provided from the oscillation stop detection circuit 360 and is supplied to the two regulators 210 and 220. When boost signal BST is set active (H level), output voltage VRO of oscillation circuit regulator 210 and output voltage VRD of frequency divider circuit regulator 220 both increase.

  The boost signal generation circuit 320 generates a detection clock signal SPCLK using the clock signals FD0, FD1, and FD2, and supplies the detection clock signal SPCLK to the oscillation stop detection circuit 360.

  The oscillation stop detection circuit 360 detects the oscillation stop of the oscillation circuit 110. Specifically, the oscillation stop detection circuit 360 includes a charge pump circuit (not shown), and generates the detection signal FSTOP using the detection clock signal SPCLK supplied from the boost signal generation circuit 320. And supplied to the boost signal generation circuit 320. When the stop of oscillation is detected, the detection signal FSTOP is set to active (H level).

  The power-on reset circuit 370 generates a power-on reset signal POR and supplies it to the logic circuit 130 when the external power supply voltage VD is turned on, more specifically, when a battery is connected to the RTC module 100. The power-on reset signal POR is changed from the L level to the H level after the power supply voltage VD is sufficiently increased.

  The IF circuit 400 is connected to the logic circuit 130 and the CPU 600 provided outside the RTC module 100. As will be described later, the IF circuit 400 includes a data interface (IF) circuit and a clock interface (IF) circuit. The logic circuit 130 can perform data communication with the CPU 600 in response to a request from the CPU 600 via the data IF circuit. The logic circuit 130 can supply a clock signal prepared in the logic circuit 130 to the CPU 600 in response to a request from the CPU 600 via the clock IF circuit.

  The IF circuit 400 includes a level shift circuit (not shown). The level shift circuit allows signals to be exchanged between the logic circuit 130 that operates at the power supply voltage VRL and the CPU 600 that operates at another power supply voltage equal to the power supply voltage VD.

B. Intermittent operation:
B-1. Oscillator circuit regulator configuration:
FIG. 2 is an explanatory diagram showing the internal configuration of the oscillator circuit regulator 210. The oscillator circuit regulator 210 includes two power switch circuits SW1 and SW2, a differential amplifier circuit DA, an output & feedback circuit QF, and four capacitors C1 to C4. Among the plurality of transistors M11 to M12, M21 to M25, and M31 to M35, some of the transistors M11, M24 to M25, and M31 to M34 are p-channel MOS transistors, and the other transistors M12, M21 to M23, M35 is an n-channel MOS transistor.

  The power switch circuits SW1 and SW2 include transistors M11 and M12, respectively, and whether or not to supply the power supply voltage VD to the oscillator circuit regulator 210, more specifically, each of the oscillator circuit regulators 210 includes It is determined whether or not a drain current is allowed to flow through the transistor. The power supply voltage VD is supplied to the source terminal of the first transistor M11, and the first switch signal LPV is supplied to the gate terminal. The power supply voltage VS is supplied to the source terminal of the second transistor M12, and the second switch signal XLPV is supplied to the gate terminal. When the two transistors M11 and M12 are both turned on, drain current flows through the other transistors.

  The differential amplifier circuit DA includes five transistors M21 to M25. The first transistor M21 functions as a constant current circuit, and the reference voltage Vref generated by the reference voltage generation circuit 240 is applied to its gate terminal. The second and third transistors M22 and M23 function as a differential input circuit. The gate terminal of the second transistor M22 corresponds to the positive input terminal of the differential amplifier, and is supplied with a reference voltage Vref. The gate terminal of the third transistor M23 corresponds to the negative input terminal of the differential amplifier, and a feedback voltage FB described later is applied. The fourth and fifth transistors M24 and M25 function as a load circuit (current mirror circuit), and an equal drain current flows through the two transistors M24 and M25.

  The output & feedback circuit QF includes six transistors M31 to M36. The first transistor M31 is an output transistor, and the drain terminal of the first transistor M31 constitutes the output terminal of the oscillator circuit regulator 210. A power supply voltage VD is applied to the source terminal of the first transistor M31. The gate terminal of the first transistor M31 is connected to the output terminal of the differential amplifier circuit DA, specifically, the drain terminal of the transistor M22. The fifth transistor M35 functions as a constant current circuit, and a reference voltage Vref is applied to its gate terminal. Between the first transistor M31 and the fifth transistor M32, second and third transistors M32 and M33 and a fourth transistor M34 connected in parallel are connected in series. The second and third transistors M32 and M33 are a voltage adjustment circuit MD (described later) that adjusts the output voltage VRO. The second transistor M32 is a switch circuit, and a boost signal BST is given to its gate terminal. The third transistor M33 is diode-connected. The fourth transistor M34 is diode-connected. The voltage of the drain terminal of the fourth transistor M34, that is, the drain terminal of the fifth transistor M35 is given to the gate terminal (negative input terminal) of the transistor M23 included in the differential amplifier circuit DA as the feedback voltage FB. Yes.

  The first capacitor C1 is provided to hold the reference voltage Vref. The second capacitor C2 is provided to hold the gate voltage of the output transistor M31. The third capacitor C3 is provided between the gate and drain of the output transistor M31 and is a phase compensation capacitor. The fourth capacitor C4 is provided to hold the output voltage VRO.

  By adopting this configuration, when the two transistors M11 and M12 constituting the power switch circuits SW1 and SW2 are set to the on state, the oscillation circuit regulator 210 can output a stable voltage VRO. it can. In this case, a drain current flows through all the transistors.

  On the other hand, when the two transistors M11 and M12 constituting the power switch circuits SW1 and SW2 are set to the off state, the oscillation circuit regulator 210 outputs the voltage VRO held by the fourth capacitor C4. In this case, the drain current flows only in the output transistor M31, and no drain current flows in the other transistors.

  Incidentally, the two transistors M32 and M33 connected in parallel included in the output & feedback circuit QF constitute the voltage adjusting circuit MD as described above. Since the output & feedback circuit QF is provided with a transistor M35 as a constant current circuit, the sum of drain currents flowing through the two transistors M32 and M33 connected in parallel is constant.

  In the first case where the boost signal BST is set to L level (inactive) and the second transistor M32 is set to the on state, the current mainly flows through the second transistor M32. On the other hand, in the second case where the boost signal BST is set to the H level (active) and the second transistor M32 is set to the OFF state, the current flows only through the third transistor M33. As a result, the output voltage VRO increases in the second case than in the first case. Note that the output voltage VRO in the first case is set to a value (for example, about 0.7 V) that is substantially equal to the sum of the two drain-source voltages of the two transistors M34 and M35. On the other hand, the output voltage VRO in the second case is set to a value (for example, about 1.2 V) substantially equal to the sum of the three drain-source voltages of the three transistors M33, M34, and M35. That is, by switching the second transistor M32 from the on state to the off state, the output voltage VRO increases by the threshold voltage (about 0.5 V) of the diode-connected third transistor M33.

B-2. Divider circuit configuration:
FIG. 3 is an explanatory diagram showing the internal configuration of the frequency divider regulator 220. The frequency divider regulator 220 is substantially the same as the oscillator circuit regulator 210 (FIG. 2), but the output & feedback circuit QF is changed.

  As can be seen by comparing FIG. 2 and FIG. 3, in the frequency divider regulator 220, a diode-connected p-channel MOS transistor M37 is added between the two transistors M32 and 33 and the transistor M34 connected in parallel. Has been.

  The frequency divider regulator 220 operates in the same manner as the oscillator circuit regulator 210. That is, when the power switch circuits SW1 and SW2 are set to the on state, the frequency divider circuit regulator 220 can output a stable voltage VRD. On the other hand, when the power switch circuits SW1 and SW2 are set to the off state, the frequency divider circuit regulator 220 outputs the voltage VRD held by the fourth capacitor C4.

  In the frequency divider regulator 220, as described above, the transistor M37 is added, so that the output voltage VRD becomes larger than the output voltage VRO. Specifically, in the first case where boost signal BST is set to L level (inactive), output voltage VRD is a relatively small value, more specifically, three transistors M34, M35, and M37. Is set to a value substantially equal to the sum of the three drain-source voltages (for example, about 1.0 V). On the other hand, in the second case where boost signal BST is set to H level (active), output voltage VRD is a relatively large value, more specifically, four transistors M33, M34, M35, and M37. It is set to a value approximately equal to the sum of the voltages between the two drains and the source (eg, about 1.5 V).

  In the frequency divider regulator 220, the source voltage of the transistor M34 included in the output & feedback circuit QF is output as the bias voltage VB, and the bias voltage VB is supplied to the logic circuit regulator 230.

B-3. Logic circuit regulator configuration:
FIG. 4 is an explanatory diagram showing the internal configuration of the logic circuit regulator 230. The logic circuit regulator 230 is substantially the same as the oscillation circuit regulator 210 (FIG. 2). However, the bias voltage VB supplied from the frequency divider circuit regulator 220 is applied to the gate terminal of the transistor M22 included in the differential amplifier circuit DA instead of the reference voltage Vref.

  Further, as can be seen by comparing FIG. 2 and FIG. 4, in the logic circuit regulator 230, the output & feedback circuit QF is changed. Specifically, the voltage regulator circuit MD (see FIG. 2) is not provided in the logic circuit regulator 230, and instead of the three transistors M32 to M34 of the oscillator circuit regulator 210, two diode-connected P-channel MOS transistors M38 and M39 are provided.

  The logic circuit regulator 230 operates in the same manner as the oscillation circuit regulator 210. That is, when the power switch circuits SW1 and SW2 are set to the on state, the logic circuit regulator 230 can output a stable voltage VRL. On the other hand, when the power switch circuits SW1 and SW2 are set to the OFF state, the logic circuit regulator 230 outputs the voltage VRL held by the fourth capacitor C4.

  In the logic circuit regulator 230, since the bias voltage VB is applied to the gate terminal of the transistor M22 and the transistors M38 and M39 are provided as described above, the output voltage VRL is higher than the output voltage VRD. Specifically, the output voltage VRL includes the sum of the three drain-source voltages of the three transistors M35, M38, and M39, and the drain-source voltage of the transistor M34 included in the divider circuit regulator 220. Is set to a value (for example, about 1.8 V) substantially equal to the sum of

B-4. Configuration of the reference voltage generation circuit:
The reference voltage generation circuit 240 generates a reference voltage Vref and supplies it to the three regulators 210, 220, and 230. In addition, the reference voltage generation circuit 240 has two power switches that determine whether or not to supply the power supply voltage VD to the reference voltage generation circuit 240, similarly to the three regulators 210, 220, and 230 shown in FIGS. A circuit and a capacitor for holding the reference voltage Vref.

B-5. Operation according to the operation control signal:
As described above, the four circuits 210, 220, 230, and 240 include two power switch circuits SW1 and SW2, respectively. By setting the power supply switch circuits SW1 and SW2 to the on state, the power supply voltage VD can be supplied to the four circuits 210, 220, 230, and 240 to output stable voltages VRO, VRD, VRL, and Vref. However, in this embodiment, in order to reduce the power consumption of the four circuits 210, 220, 230, and 240, the power switch circuits SW1 and SW2 are intermittently set to the on state.

  In the present embodiment, the four circuits 210, 220, 230, and 240 operate according to two operation modes. The first operation mode is an intermittent operation mode, and the power switch circuits SW1 and SW2 are intermittently set to an on state during the period in which the intermittent operation mode is executed (intermittent operation period). The second operation mode is a continuous operation mode, and the power supply switch circuits SW1 and SW2 are steadily set to an on state during a period (continuous operation period) in which the continuous operation mode is executed. In this embodiment, the four circuits 210, 220, 230, and 240 normally operate in the intermittent operation mode, and operate in the continuous operation mode in specific cases.

  FIG. 5 is an explanatory diagram showing three signals LPW, LPV, and XLPV in the intermittent operation period and the continuous operation period. FIG. 5A shows the operation control signal LPW generated by the operation control signal generation circuit 310 (FIG. 1). FIGS. 5B and 5C show the first switch signal LPV and the second switch signal XLPV generated by the LS circuit 242 (FIG. 1), respectively. As described above, the two switch signals LPV and XLPV are supplied to the two power switch circuits SW1 and SW2 included in the four circuits 210, 220, 230, and 240, respectively (see FIGS. 2 to 4).

  The logic level of the first switch signal LPV is the same as the logic level of the operation control signal LPW (FIG. 5A), but the logic level of the second switch signal XLPV (FIG. 5C) is the operation level. This is opposite to the logic level of the control signal LPW. However, the operation control signal LPW is a signal output from the operation control signal generation circuit 310 that operates at the power supply voltage VRL, and the voltage level of the signal is relatively low. On the other hand, the switch signals LPV and XLPV are signals output from the LS circuit 242 operating with the power supply voltage VD, and the voltage level of the signals is relatively high.

  In the continuous operation period, the operation control signal LPW is constantly set to the L level. The first switch signal LPV is constantly set to the L level, and the second switch signal XLPV is constantly set to the H level. At this time, the power switch circuits SW1 and SW2 included in the four circuits 210, 220, 230, and 240 are constantly set to an on state. Therefore, the power supply voltage VD is supplied to the four circuits 210, 220, 230, and 240, and a drain current flows through each transistor.

  On the other hand, in the intermittent operation period, the operation control signal LPW includes an H level pulse generated at a predetermined cycle. The first switch signal LPV includes an H level pulse generated at a predetermined cycle, and the second switch signal XLPV includes an L level pulse generated at a predetermined cycle.

  In the first partial period in which the operation control signal LPW is set to L level during the intermittent operation period, the power switch circuits SW1, SW2 included in the four circuits 210, 220, 230, 240 are the same as in the continuous operation period. Is set to the on state. On the other hand, in the second partial period in which the operation control signal LPW is set to the H level during the intermittent operation period, the power switch circuits SW1 and SW2 included in the four circuits 210, 220, 230, and 240 are set to the off state. Is done. At this time, the power supply voltage VD is not supplied to the four circuits, and no drain current flows through each transistor. However, drain currents corresponding to currents consumed by the corresponding three circuits 110, 120, and 130 flow through the output transistors M31 included in the three circuits (regulators) 210, 220, and 230.

  In the first partial period, the four voltages VRO, VRD, VRL, and Vref output from the four circuits 210, 220, 230, and 240 are stable. However, in the second partial period, the four voltages VRO, VRD, VRL, Vref can vary. For example, when the power supply voltage VD varies, the four voltages VRO, VRD, VRL, and Vref also vary.

  Therefore, in this embodiment, as described later, by intermittently operating the four circuits 210, 220, 230, and 240, the power consumption of the four circuits is reduced, and the intermittent operation is prohibited as necessary. The four circuits are continuously operated.

B-6. Configuration and operation of operation control signal generation circuit:
FIG. 6 is an explanatory diagram showing the internal configuration of the operation control signal generation circuit 310. As shown in the figure, the operation control signal generation circuit 310 includes three OR circuits 312, 314, 318, a delay circuit 313, and a counter 316.

  The first OR circuit 312 is a three-input OR circuit, and is provided with three signals ICE, IFOE, and BST. Note that these three signals ICE, IFOE, and BST will be described later.

  The delay circuit 313 is a shift register including two flip-flops. An output signal Q312 output from the first OR circuit 312 is supplied to the data terminal of the delay circuit 313, and a clock signal F1Hz having a frequency of 1 Hz generated by the timer circuit 302 is supplied to the clock terminal. It has been. The output signal Q313 of the delay circuit 313 is a signal obtained by delaying the output signal Q312 of the first OR circuit 312 by about 1 to about 2 seconds. Note that the delay circuit 313 may be configured using a capacitor and a resistor.

  The second OR circuit 314 is a two-input OR circuit. The second OR circuit 314 is supplied with the output signal Q312 from the first OR circuit 312 and the output signal Q313 from the delay circuit 313.

  The counter 316 functions as a frequency dividing circuit. The clock terminal of the counter 316 is supplied with a clock signal F8 kHz having a frequency of about 8 kHz (exactly 8192 Hz) generated by the timer circuit 302, and the reset terminal receives a second OR circuit as a reset signal. An output signal Q314 from 314 is provided. The counter 316 has a first clock signal Fa having a frequency of about 4 kHz (exactly 4096 Hz), a clock signal Fb having a frequency of about 2 kHz (exactly 2048 Hz), and about 1 kHz (exactly 1024 Hz). And a clock signal Fc having a frequency.

  The third OR circuit 318 is a three-input OR circuit. The third OR circuit 318 is supplied with three clock signals Fa, Fb, and Fc having different frequencies. The output signal from the third OR circuit 318 is the operation control signal LPW.

  FIG. 7 is a timing chart showing the operation of the operation control signal generation circuit 310 (FIG. 6). FIG. 7A shows one of three signals ICE, IFOE, and BST. FIGS. 7B to 7D show the output signals Q312, Q313, and Q314, respectively. FIG. 7E shows the operation control signal LPW.

  When any of the three signals ICE, IFOE, and BST is set to H level, the output signal Q312 of the first OR circuit 312 is immediately set to H level, and the output signal Q313 of the delay circuit 313 is The H level is set with a delay (FIGS. 7A to 7C). The output signal Q314 of the second OR circuit 314 is set to the H level in a period longer by the delay period TA than the period T in which the output signal Q312 of the first OR circuit 312 is set to the H level (FIG. 7 (d)).

  As shown in FIGS. 7D and 7E, the counter 316 operates in a period during which the reset signal (output signal of the second OR circuit 314) Q314 is set to L level (that is, intermittent operation period). Therefore, the operation control signal LPW includes an H level pulse generated at a predetermined cycle Tc. In the present embodiment, the predetermined period Tc is set to about 0.001 second (exactly 1/1024 (Hz) second), and the H level period is set to 7/8 of one period Tc. Yes.

  On the other hand, during the period when reset signal Q314 is set to H level (that is, the continuous operation period), the three output signals of counter 316 are set to L level, so that operation control signal LPW is set to L level.

C. Prohibition of intermittent operation:
C-1. Interruption of intermittent operation due to data communication processing:
As described above, the logic circuit 130 can perform data communication with the CPU 600 in response to a request from the CPU 600 via the IF circuit 400 (more specifically, a data IF circuit). However, when the data communication process is performed, it is difficult to cause the oscillation circuit 110 to oscillate stably as will be described later. For this reason, in this embodiment, the intermittent operation is interrupted during the data communication process.

  FIG. 8 is an explanatory diagram showing a circuit for data communication processing. In FIG. 8, the logic circuit 130, the IF circuit 400, and the CPU 600 are drawn by paying attention to the data communication processing. As illustrated, the IF circuit 400 includes a data IF circuit 410. Data IF circuit 410 includes an LS circuit (not shown).

  The data IF circuit 410 receives the communication enable signal CE from the CPU 600 and supplies it to the logic circuit 130 as the internal communication enable signal ICE. Similarly, the data IF circuit 410 receives the timing signal CLK from the CPU 600 and supplies it to the logic circuit 130 as the internal timing signal ICLK. Further, the data IF circuit 410 receives the input data signal DI from the CPU 600, supplies it to the logic circuit 130 as the internal input data signal IDI, receives the internal output data signal IDO from the logic circuit 130, and receives it as the output data signal DO to the CPU 600. Supply. In this embodiment, a common wiring is used for transmission of the input data signal DI and the output data signal DO.

  FIG. 9 is a timing chart showing the operation of the circuit (FIG. 8) for data communication processing. 9A to 9C show the communication enable signals CE and ICE, the timing signals CLK and ICLK, and the data signals DI, DO, IDI, and IDO, respectively. FIG. 9D shows the operation control signal LPW.

  When the CPU 600 requests the logic circuit 130 to input (write) data, the CPU 600 sets the communication enable signal CE to H level (active) and supplies the timing signal CLK to the logic circuit 300 (FIG. 9). (A), (b)). Then, the CPU 600 supplies the input data signal DI to the logic circuit 300 (FIG. 9C). The input data signal DI includes a processing mode M, an address A, and significant data D. Here, the processing mode M is a writing mode. The significant data D includes, for example, data indicating the current time supplied from the CPU 600. Logic circuit 130 receives internal input data signal IDI in accordance with internal timing signal ICLK, and writes significant data D to the register designated by address A.

  Even when the CPU 600 requests the output (reading) of data from the logic circuit 130, the CPU 600 sets the communication enable signal CE to H level (active) and supplies the timing signal CLK to the logic circuit 300 (FIG. 9 (a), (b)). Then, the CPU 600 supplies the input data signal DI to the logic circuit 130 (FIG. 9C). The input data signal DI includes a processing mode M and an address A. Here, the processing mode M is a reading mode. The logic circuit 130 receives the internal input data signal IDI according to the internal timing signal ICLK, and reads significant data D from the register designated by the address A. The significant data D includes, for example, data indicating the current time measured by the time measuring circuit 302. Next, the logic circuit 130 supplies the CPU 600 with the internal output data signal IDO including the read significant data D in accordance with the internal timing signal ICLK (FIG. 9C).

  As shown in FIG. 9D, the operation control signal LPW is set to L level when the communication enable signals CE and ICE are set to H level. Specifically, the continuous operation period in which the intermittent operation is prohibited includes a communication enable period T1 in which the communication enable signals CE and ICE are set to H level, and an additional period T1A immediately after that.

  Note that the operation control signal LPW is generated by the operation control signal generation circuit 310 using the internal communication enable signal ICE (FIG. 9A) as described with reference to FIG. That is, the communication enable period T1 corresponds to the period T in FIG. 7, and the additional period T1A corresponds to the delay period TA in FIG.

  As described above, in the present embodiment, the intermittent operation of the four circuits 210, 220, 230, and 240 is prohibited in the communication enable period T1 and the additional period T1A, so that even when data signals are transmitted. The four circuits 210, 220, 230, and 240 can be stably operated. In particular, since the oscillation circuit 110 can oscillate stably, the timing circuit 302 can stably measure time.

  Specifically, in the communication enable period T1, the current flowing through the data IF circuit 410 varies greatly according to the variation in the level of the data signals DI and DO, and as a result, the power supply voltage VD can vary greatly. When the power supply voltage VD fluctuates, the power supply voltage VRO also fluctuates, so that stable oscillation of the oscillation circuit 110 may be difficult. That is, the oscillation of the oscillation circuit 110 may become unstable or stop. However, in this embodiment, the intermittent operation of the oscillation circuit regulator 210 is interrupted during the communication enable period T1. For this reason, in the communication enable period T1, it is possible to suppress the oscillation of the oscillation circuit 110 from becoming unstable or stop and to cause the oscillation circuit 110 to oscillate stably.

  Further, even in the additional period T1A immediately after the communication enable period T1, the power supply voltages VD and VRO are likely to vary. However, in this embodiment, the intermittent operation of the oscillation circuit regulator 210 is interrupted even in the additional period T1A. Therefore, the oscillation circuit 110 can oscillate stably even during the additional period T1A.

C-2. Interruption of intermittent operation during clock output processing:
As described above, the logic circuit 130 supplies the CPU 600 with the clock signal generated by the RTC module 100 in response to a request from the CPU 600 via the IF circuit 400 (more specifically, the clock IF circuit). it can. However, when the clock output process is performed, it is difficult to cause the oscillation circuit 110 to oscillate stably as will be described later. For this reason, in this embodiment, the intermittent operation is interrupted during the clock output process.

  FIG. 10 is an explanatory diagram showing a circuit for clock output processing. In FIG. 10, paying attention to the clock output processing, the logic circuit 130, the IF circuit 400, and the CPU 600 are drawn. As illustrated, the IF circuit 400 includes a clock IF circuit 420. The clock IF circuit 420 includes an LS circuit (not shown). Further, as shown in the figure, the logic circuit 130 is provided with a high impedance (HIZ) setting signal generation circuit 380.

  The clock IF circuit 420 receives the clock enable signal FOE from the CPU 600 and supplies it to the logic circuit 130 as the internal clock enable signal IFOE.

  The HIZ setting signal generation circuit 380 generates the high impedance setting signal HIZ using the internal clock enable signal IFOE. When the logic circuit 130 receives the internal clock enable signal IFOE, the logic circuit 130 outputs the internal clock signal IFOUT prepared by the timer circuit 302.

  The clock IF circuit 420 receives the internal clock signal IFOUT from the logic circuit 130 and supplies it to the CPU 600 as the clock signal FOUT. However, when the high impedance setting signal HIZ received by the clock IF circuit 420 is active (L level), the output of the clock IF circuit 420 is set to a high impedance state.

  In this embodiment, the clock signals IFOUT and FOUT have the same frequency as the clock signal FD0 described above, but may have a frequency lower than that of the clock signal FD0. The frequencies of the clock signals IFOUT and FOUT may be selectable from a plurality of types of frequencies (for example, 32768 Hz, 1024 Hz, 32 Hz, and 1 Hz).

  FIG. 11 is a timing chart showing the operation of the circuit (FIG. 10) for clock output processing. FIG. 11A shows the clock enable signals FOE and IFOE, and FIG. 11B shows the high impedance setting signal HIZ. FIG. 11C shows the clock signal FOUT. FIG. 11D shows the operation control signal LPW.

  When the CPU 600 requests the clock output from the logic circuit 130, the CPU 600 sets the clock enable signal FOE to H level (active) (FIG. 11A). When the internal clock enable signal IFOE is set to H level (active), the HIZ setting signal generation circuit 380 sets the high impedance setting signal HIZ to H level (inactive) (FIG. 11B). Further, when the internal clock enable signal IFOE is set to H level (active), the logic circuit 130 outputs the internal clock signal IFOUT prepared by the timer circuit 302. Then, the clock IF circuit 420 outputs the clock signal FOUT during the period when the high impedance setting signal HIZ is set to H level (inactive) (FIG. 11C).

  As shown in FIG. 11D, the operation control signal LPW is set to L level when the clock enable signal FOE is set to H level. Specifically, the continuous operation period in which the intermittent operation is prohibited includes a clock enable period T2 in which the clock enable signals FOE and IFOE are set to the H level, and an additional period T2A immediately thereafter. The clock enable period T2 includes a first partial period T21 in which the clock signal FOUT is not output and a second partial period T22 in which the clock signal FOUT is output.

  Note that the operation control signal LPW is generated by the operation control signal generation circuit 310 using the internal clock enable signal IFOE (FIG. 11A) as described in FIG. That is, the clock enable period T2 corresponds to the period T in FIG. 7, and the additional period T2A corresponds to the delay period TA in FIG.

  As described above, in this embodiment, the intermittent operation of the four circuits 210, 220, 230, and 240 is prohibited in the clock enable period T2 and the additional period T2A. The four circuits 210, 220, 230, and 240 can be stably operated. In particular, the oscillation circuit 110 can oscillate stably, and as a result, the timing circuit 302 can stably oscillate.

  Specifically, in the clock enable period T2, the current flowing through the clock IF circuit 420 varies greatly according to the variation in the level of the clock signal FOUT, and as a result, the power supply voltage VD can vary greatly. As described above, when the power supply voltage VD fluctuates, the power supply voltage VRO also fluctuates, so that stable oscillation of the oscillation circuit 110 may be difficult. However, in this embodiment, the intermittent operation of the four circuits 210, 220, 230, and 240 is interrupted during the clock enable period T2. For this reason, in the clock enable period T2, the oscillation of the oscillation circuit 110 can be suppressed from becoming unstable or stopped, and the oscillation circuit 110 can oscillate stably.

  Further, even in the additional period T2A immediately after the clock enable period T2, the power supply voltages VD and VRO are likely to fluctuate. However, in this embodiment, the intermittent operation of the oscillation circuit regulator 210 is interrupted even in the additional period T2A. Therefore, the oscillation circuit 110 can oscillate stably even during the additional period T2A.

  By the way, in this embodiment, in the first partial period T21 immediately after the start of the clock enable period T2, the output of the clock signal from the clock IF circuit 420 is prohibited, and the second partial period immediately after the end of the first partial period T21. In the partial period T22, the output of the clock signal FOUT from the clock IF circuit 420 is permitted.

  When the output of the clock IF circuit 420 is changed from the high impedance state to the output state of the clock signal FOUT, the power supply voltages VD and VRO are likely to fluctuate. For this reason, when the output of the clock signal FOUT is allowed immediately after the start of the clock enable period T2, stable oscillation of the oscillation circuit 110 may be difficult. However, in the present embodiment, the output of the clock IF circuit 420 is changed from the high impedance state to the output state of the clock signal FOUT after the first partial period T21 has elapsed since the intermittent operation was interrupted. Therefore, the oscillation circuit 110 can oscillate stably even in the first partial period T21 immediately after the start of the clock enable period T2.

  FIG. 12 is an explanatory diagram showing the internal configuration of the high impedance (HIZ) setting signal generation circuit 380 (FIG. 10). As illustrated, the HIZ setting signal generation circuit 380 includes a delay circuit 382 and an AND circuit 384.

  The delay circuit 382 is a shift register including two flip-flops. An internal clock enable signal IFOE is supplied to the data terminal of the delay circuit 382, and a clock signal F1Hz having a frequency of 1 Hz generated by the timer circuit 302 is supplied to the clock terminal. The output signal Q382 of the delay circuit 382 is a signal obtained by delaying the internal clock enable signal IFOE by about 1 to about 2 seconds. Note that the delay circuit 382 may be configured using a capacitor and a resistor.

  The AND circuit 384 is supplied with an internal clock enable signal IFOE and an output signal Q382 from the delay circuit 382. An output signal from the AND circuit 384 is a high impedance setting signal HIZ.

  The delay circuit 382 generates a high impedance setting signal HIZ according to the internal clock enable signal IFOE. Note that the delay period of the delay circuit 382 is the above-described first partial period T21 (FIG. 11).

  FIG. 13 is an explanatory diagram showing the internal configuration of the clock IF circuit 420 (FIG. 10). As illustrated, the clock IF circuit 420 includes two buffer circuits 421a and 421b, two LS circuits 423a and 423b, a NAND circuit 424, an inverter circuit 425, and a NOR circuit 426 connected in series. A channel MOS transistor 427a and an n channel MOS transistor 427b.

  A high impedance setting signal HIZ is given to the first LS circuit 423a via the first buffer circuit 421a. The output of the first LS circuit 423a is given to the NAND circuit 424 and also to the NOR circuit 426 via the inverter circuit 425.

  The second LS circuit 423b is supplied with the internal clock signal IFOUT via the second buffer circuit 421b. The output of the second LS circuit 423b is supplied to the NAND circuit 424 and also to the NOR circuit 426.

  The power supply voltage VD is supplied to the source terminal of the first transistor 427a, and the output of the NAND circuit 424 is supplied to the gate terminal. The power supply voltage VS is supplied to the source terminal of the second transistor 427b, and the output of the NOR circuit 426 is supplied to the gate terminal. The drain terminals of the two transistors 427 a and 427 b are connected to each other and constitute an output terminal of the clock IF circuit 420.

  The circuits 421a and 421b shown on the left side of FIG. 13 operate using the power supply voltage VRL, and the circuits 424 to 426, 427a and 427b shown on the right side operate using the power supply voltage VD. . The LS circuits 423a and 423b operate using two power supply voltages VRL and VD.

  When the high impedance setting signal HIZ is at L level (active), the output of the NAND circuit 424 is set to H level and the output of the NOR circuit 426 is set to L level. For this reason, the two transistors 427a and 427b are set to an off state, and as a result, the output of the clock IF circuit 420 is set to a high impedance (see FIGS. 11B and 11C).

  On the other hand, when the high impedance setting signal HIZ is at the H level (inactive), the output of the NAND circuit 424 and the output of the NOR circuit 426 are both set to a logic level opposite to that of the internal clock signal IFOUT. Therefore, when the internal clock signal IFOUT is at the L level, only the second transistor 427b is set to the on state, and the output of the clock IF circuit 420 is set to the L level. Conversely, when the internal clock signal IFOUT is at the H level, only the first transistor 427a is set to the on state, and the output of the clock IF circuit 420 is set to the H level (FIG. 11 (b), (See (c)).

  As described above, when the high impedance setting signal HIZ is set to L level (active), the output of the clock IF circuit 420 is in a high impedance state, and the high impedance setting signal HIZ is set to H level (inactive). When set, the clock IF circuit 420 outputs the clock signal FOUT.

C-3. Interruption of intermittent operation when oscillation is stopped:
In this embodiment, in order to reduce the power consumption of the oscillation circuit 110, the power supply voltage (that is, the output voltage of the oscillation circuit regulator 210) VRO of the oscillation circuit 110 is set to a considerably low value. Specifically, the power supply voltage VRO is set to a value higher by about 0.1 V than the voltage at which the oscillation of the oscillation circuit 110 stops.

  If the power supply voltage VRO decreases and the oscillation of the oscillation circuit 110 stops, it is necessary to increase the output voltage VRO of the oscillation circuit regulator 210 in order to oscillate the oscillation circuit 110 again. If the intermittent operation is performed during the period for increasing the output voltage VRO (boost period), it is difficult to increase the voltage VRO quickly and sufficiently. For this reason, in the present embodiment, the intermittent operation is interrupted when the boost process is executed as the oscillation stops.

  FIG. 14 is a timing chart showing the operation of the circuit when oscillation is stopped. FIG. 14A shows the detection signal FSTOP output from the oscillation stop detection circuit 360. FIG. 14B shows the boost signal BST output from the boost signal generation circuit 320. FIG. 14C shows the output voltage VRO of the oscillation circuit regulator 210, and FIG. 14D shows the output voltage VRD of the frequency divider circuit regulator 220. FIG. 14E shows the operation control signal LPW.

  When the output voltage VRO of the oscillation circuit regulator 210 decreases ((c) in FIG. 14) and the oscillation of the oscillation circuit 110 stops, the oscillation stop detection circuit 360 detects the oscillation stop of the oscillation circuit 110, The detection signal FSTOP is set to H level (active) (FIG. 14A) The boost signal generation circuit 320 sets the boost signal BSTOP to a period T3 described later when the detection signal FSTOP is set to H level (active). The boost signal BST is supplied to the oscillator circuit regulator 210 and the frequency divider circuit regulator 220 as described with reference to FIG. When the signal BST is set to H level (active), the voltages of the two regulators 210 and 220 as described with reference to FIGS. The transistor M32 included in the regulator circuit MD is set to an off state, and the output voltages VRO and VRD of the two regulators 210 and 220 are increased by about 0.5 V, respectively (FIGS. 14C and 14D). When the output voltage VRO of the oscillation circuit regulator 210 increases, the oscillation of the oscillation circuit 110 is resumed, and when the oscillation stop detection circuit 360 detects the resumption of oscillation, the detection signal FSTOP is set to the L level (non-level). 14A when the boost signal BST returns to the L level (inactive) (FIG. 14B), the output voltages VRO and VRD of the regulators 210 and 220 are reduced to normal. Return to the value of.

  As shown in FIG. 14E, the operation control signal LPW is set to L level when the boost signal BST is set to H level (active). Specifically, the continuous operation period in which the intermittent operation is prohibited includes a boost period T3 in which the boost signal BST is set to the H level, and an additional period T3A immediately after that.

  Note that the operation control signal LPW is generated by the operation control signal generation circuit 310 using the boost signal BST (FIG. 14B) as described in FIG. That is, the boost period T3 corresponds to the period T in FIG. 7, and the additional period T3A corresponds to the delay period TA in FIG.

  As described above, in this embodiment, the intermittent operation of the four circuits 210, 220, 230, and 240 is prohibited in the boost period T3 and the additional period T3A. It can be operated stably. In particular, the oscillation circuit 110 can oscillate stably, and as a result, the timing circuit 302 can stably oscillate.

  Specifically, since the intermittent operation is interrupted in the boost period T3 after the oscillation is stopped, the output voltage VRO of the oscillation circuit regulator 210 can be increased quickly and sufficiently. For this reason, the oscillation circuit 110 can restart oscillation quickly and reliably. Further, by prohibiting the intermittent operation in the additional period T3A immediately after the boost period T3, the intermittent operation is not resumed immediately after the output voltage VRO of the oscillation circuit regulator 210 decreases and returns to the normal value. That's it. Therefore, the oscillation circuit 110 can oscillate stably even during the additional period T3A.

  In the present embodiment, in the boost period T3, the output voltage VRD of the frequency divider circuit regulator 220 is increased together with the output voltage VRO of the oscillator circuit regulator 210. This is because the output voltage VRD of the divider circuit regulator 220 is always set higher than the output voltage VRO of the oscillator circuit regulator 210. If the voltage VRO becomes higher than the voltage VRD during the boost period T3, the level shift circuit in the input stage included in the frequency dividing circuit 120 may not receive the reference clock signal FS from the oscillation circuit 110 well. Therefore, in this embodiment, in the boost period T3, the output voltage VRO is increased and the output voltage VRD is increased.

  FIG. 15 is an explanatory diagram showing the internal configuration of the boost signal generation circuit 320. As shown in the figure, the boost signal generation circuit 320 includes an inverter circuit 322 and three reset set flip-flops (RS-FF) 324, 326, and 328. Each of the first and third RS-FFs 324 and 328 includes two NAND circuits, and the second RS-FF 326 includes two NOR circuits.

  A detection signal FSTOP is given to the inverter circuit 322. An output signal Q322 of the inverter circuit 322 is given to the first RS-FF 324. The output signal Q324 of the first RS-FF 324 is given to the second RS-FF 326, and the output signal Q326 of the second RS-FF 326 is given to the third RS-FF 328. The three flip-flops 324, 326, and 328 are supplied with a clock signal F2 Hz having a frequency of 2 Hz generated by the timer circuit 302. The output signal from the third RS-FF 328 is the boost signal BST.

  FIG. 16 is an explanatory diagram showing a timing chart showing the operation of the boost signal generation circuit 320 (FIG. 15). 16A shows the detection signal FSTOP, and FIG. 16B shows the output signal Q322 of the inverter circuit 322. FIG. 16C shows the clock signal F2 Hz. FIGS. 16D and 16E show output signals Q324 and Q326 of the first and second RS-FFs 324 and 326, respectively. FIG. 16F shows the boost signal BST.

  Immediately before the detection signal FSTOP is set to H level (active), since the oscillation of the oscillation circuit 110 is stopped, the logic level of the clock signal F2 Hz is set to either H level or L level. When stoppage of transmission is detected and detection signal FSTOP is set to H level (active), boost signal BST is set to H level (active). Thereby, since the oscillation of the oscillation circuit 110 starts, the logic level of the clock signal F2 Hz is periodically set to the H level and the L level.

  As shown in FIGS. 16A and 16F, in this embodiment, the boost signal BST is immediately set to H level (active) and detected when the detection signal FSTOP is set to H level (active). After the signal FSTOP is set to L level (inactive), it is set to L level (inactive). That is, in this embodiment, the boost period T3 described in FIG. 14 is set to be longer than the period in which the detection signal FSTOP is set to H level (active).

C-4. Prohibition of intermittent operation at power-on:
When the RTC module 100 is turned on, more specifically, when the RTC module 100 is first connected to the battery, the output voltage VRO is increased in order to reliably start the oscillation of the oscillation circuit 110. It is preferable to make it. As described above, if the intermittent operation is performed during the period for increasing the output voltage VRO (boost period), it is difficult to increase the voltage VRO quickly and sufficiently. For this reason, in this embodiment, intermittent operation is prohibited when boost processing is executed when power is turned on.

  FIG. 17 is a timing chart showing the operation of the circuit when the power is turned on. FIG. 17A shows the power supply voltage VD supplied to the RTC module 100. FIG. 17B shows the output voltage VRL of the logic circuit regulator 230. FIGS. 17C and 17D show the output voltages VRO and VRD of the oscillator circuit and frequency divider regulators 210 and 220, respectively. FIG. 17E shows a power-on reset signal POR output from the power-on reset circuit 370. FIG. 17F shows the detection signal FSTOP output from the oscillation stop detection circuit 360. FIG. 17G shows the boost signal BST output from the boost signal generation circuit 320. FIG. 17H shows the operation control signal LPW.

  As shown in the figure, when the power is turned on to the RTC module 100 at time t0, the power supply voltage VD gradually increases, and accordingly, the output voltages VRO, VRD, VRL of the regulators 210, 220, 230 also increase gradually. (FIGS. 17A to 17D). The power-on reset circuit 370 changes the power-on reset signal POR from the L level to the H level at time t1 after the power supply voltage VD reaches a predetermined voltage (FIG. 17 (e)). Immediately after the power is turned on, since the oscillation of the oscillation circuit 110 is stopped, the oscillation stop detection circuit 360 sets the detection signal FSTOP to H level (active) (FIG. 17 (f)). Then, when the detection signal FSTOP is set to H level (active), the boost signal generation circuit 320 sets the boost signal BST to H level (active) (FIG. 17 (g)). At this time, the output voltages VRO and VRD of the regulators 210 and 220 increase to a value higher than the normal value (FIGS. 17C and 17D). When the output voltage VRO of the oscillation circuit regulator 210 increases, the oscillation of the oscillation circuit 110 is started. Then, the oscillation stop detection circuit 360 sets the detection signal FSTOP to L level (inactive) at time t2 when the start of oscillation is detected (FIG. 17 (f)). Thereafter, when boost signal BST is set to inactive (L level) at time t3 (FIG. 17 (g)), output voltages VRO and VRD of regulators 210 and 220 are lowered and set to normal values.

  As shown in FIG. 17H, the operation control signal LPW is set to the L level until time t4 when the boost signal BST is set to the H level (active). Specifically, the continuous operation period in which the intermittent operation is prohibited includes a boost period T4 in which the boost signal BST is set to the H level and an additional period T4A immediately after that.

  Note that the operation control signal LPW is generated by the operation control signal generation circuit 310 using the boost signal BST (FIG. 17G) as described in FIG. That is, the boost period T4 corresponds to the period T in FIG. 7, and the additional period T4A corresponds to the delay period TA in FIG.

  As described with reference to FIGS. 15 and 16, the boost signal generation circuit 320 uses the detection signal FSTOP to generate the boost signal BST even when the power is turned on.

  As described above, in this embodiment, the intermittent operation of the four circuits 210, 220, 230, and 240 is prohibited in the boost period T4 and the additional period T4A. It can be operated stably. In particular, the oscillation circuit 110 can oscillate stably, and as a result, the timing circuit 302 can stably oscillate.

  Specifically, since the intermittent operation is prohibited during the boost period T4 when the power is turned on, the output voltage VRO of the oscillation circuit regulator 210 can be increased quickly and sufficiently. Therefore, the oscillation circuit 110 can start oscillating promptly and reliably. Further, by prohibiting the intermittent operation also in the additional period T4A immediately after the boost period T4, the intermittent operation is not started immediately after the output voltage VRO of the oscillation circuit regulator 210 decreases and returns to the normal value. That's it. Therefore, the oscillation circuit 110 can oscillate stably even in the additional period T4A.

C-5. Execution and prohibition of intermittent operation:
FIG. 18 is an explanatory diagram showing an intermittent operation period and a continuous operation period during the operation of the RTC module 100. FIG. 18A shows communication enable signals CE and ICE. FIG. 18B shows the clock enable signals FOE and IFOE. FIG. 18C shows the clock signal FOUT. FIG. 18D shows the boost signal BST. FIG. 18E shows whether or not an intermittent operation is being performed. In the figure, the “ON” period indicates an intermittent operation period, and the “OFF” period indicates a continuous operation period in which the intermittent operation is prohibited.

  When power is applied to the RTC module 100 at time ta1, the stop of oscillation of the oscillation circuit 110 is detected and the boost signal BST is set to H level (active) as described with reference to FIG. Operation is prohibited. When boost signal BST is set to L level (inactive) at time ta2, intermittent operation is started at time ta3 after the additional period has elapsed.

  When data communication is requested by the CPU 600 at time tb1 and the communication enable signals CE and ICE are set to H level (active), the intermittent operation is interrupted and data communication is performed as described with reference to FIG. When the communication enable signals CE and ICE are set to L level (inactive) at time tb2, the intermittent operation is resumed at time tb3 after the additional period has elapsed.

  When a clock output is requested by the CPU 600 at time tc1 and the clock enable signals FOE and IFOE are set to H level (active), the intermittent operation is interrupted as described with reference to FIG. However, the output of the clock IF circuit 420 is maintained in a high impedance state, and the output of the clock signal FOUT is started at the subsequent time tc2. When the clock enable signals FOE and IFOE are set to L level (inactive) at time tc3, the intermittent operation is resumed at time tc4 after the additional period has elapsed.

  When the stop of oscillation of the oscillation circuit 110 is detected at time td1, as described with reference to FIG. 14, the boost signal BST is set to H level (active), and the intermittent operation is interrupted. When resumption of oscillation of the oscillation circuit 110 is detected at time td2, the boost signal BST is set to L level (inactive), and the intermittent operation is resumed at time td3 after the additional period has elapsed.

  When clock output is requested by CPU 600 at time te1 and clock enable signals FOE and IFOE are set to H level (active), the intermittent operation is interrupted. However, the output of the clock IF circuit 420 is maintained in a high impedance state, and the output of the clock signal FOUT is started at the subsequent time te2. As can be seen from the waveform of the clock signal FOUT in FIG. 18C, in this example, the oscillation of the oscillation circuit 110 is stopped during the clock enable period. When stop of oscillation of the oscillation circuit 110 is detected at time te3, the boost signal BST is set to H level (active), and as a result, oscillation of the oscillation circuit 110 is resumed. Then, when restart of oscillation of oscillation circuit 110 is detected at time te4, boost signal BST is set to L level (inactive). In the period from time te3 to time te4, since the clock enable signals FOE and IFOE are maintained at the H level, the intermittent operation is prohibited.

  Further, when data communication is requested by CPU 600 at time te5 and communication enable signals CE and ICE are set to H level (active), data communication is started. At time te6, the clock enable signals FOE and IFOE are set to L level (inactive), and the output of the clock signal FOUT is completed. However, at time te6, since the communication enable signals CE and ICE are maintained at the H level (active), the intermittent operation remains prohibited. When the communication enable signals CE and ICE are set to the L level at time te7, the intermittent operation is resumed at time te8 after the additional period has elapsed.

  In FIG. 18, both the two signals IFOE (FOE) and BST are set to H level (active), and the two signals ICE (CE) and IFOE (FOE) are both set to H level (active). The period to be played is shown. Although not shown, the period in which the other two signals ICE (CE) and BST are both set to the H level (active) and the three signals ICE (CE), IFOE (FOE), and BST are both H. In the period set to the level (active), the intermittent operation is prohibited in the same manner as described above. Note that the data communication process can be continued even when the period during which the communication enable signals CE and ICE are set to H level (active) and the period during which the boost signal BST is set to H level (active) overlap. This is because the data communication process is executed according to the timing signal CLK given from the external CPU 600.

D. Regulator separation:
In this embodiment, as shown in FIG. 1, the oscillation circuit 110 is supplied with the first internal power supply voltage VRO from the oscillation circuit regulator 210, and the frequency divider circuit 120 is supplied with the first voltage from the frequency divider circuit regulator 220. 2 internal power supply voltage VRD is supplied.

  As described above, in this embodiment, the two regulators 210 and 220 are provided for the oscillation circuit 110 and the frequency dividing circuit 120. For example, when the two voltages VRO and VRD are the same, the oscillation is performed. A single regulator may be provided for the circuit 110 and the frequency dividing circuit 120.

  However, when a single regulator is provided for the oscillation circuit 110 and the frequency dividing circuit 120, a high voltage side power supply line of the oscillation circuit 110, a high voltage side power supply line of the frequency dividing circuit 120, Are electrically connected. For this reason, noise easily propagates between the oscillation circuit 110 and the frequency dividing circuit 120. For example, switching noise generated in the frequency dividing circuit 120 propagates to the oscillation circuit 110 via power supply lines connected to each other. In this case, jitter (swing) may occur in the reference clock signal FS output from the oscillation circuit 110.

  However, in this embodiment, the oscillator circuit regulator 210 and the frequency divider circuit regulator 220 are provided separately, and the high voltage side power supply line of the oscillation circuit 110 and the high voltage side power supply of the frequency divider circuit 120 are provided. The line is not electrically connected. For this reason, it is possible to suppress the propagation of noise between the oscillation circuit 110 and the frequency dividing circuit 120. For example, switching noise generated in the frequency dividing circuit 120 can be prevented from propagating to the oscillation circuit 110 via the power supply line, and as a result, occurrence of jitter in the reference clock signal FS can be suppressed. Can do.

  Similarly, in this embodiment, the logic circuit 130 is supplied with the third internal power supply voltage VRL from the logic circuit regulator 230. For this reason, it is possible to suppress the propagation of noise between the oscillation circuit 110 and the logic circuit 130 and between the frequency divider circuit 120 and the logic circuit 130.

  As described above, in the present embodiment, since the four circuits 210, 220, 230, and 240 operate intermittently, the power consumption of the RTC module 100 can be reduced.

  In particular, in this embodiment, in response to a request from the CPU 600, the intermittent operation of the oscillation circuit regulator 210 is performed during periods T1 and T2 in which signals (data signals and clock signals) are transmitted between the RTC module 100 and the CPU 600. Is prohibited, and the oscillator circuit regulator 210 operates continuously. In addition, the oscillation circuit regulator 210 continuously operates in the additional periods T1A and T2A immediately after the end of the periods T1 and T22. Therefore, the oscillation circuit 110 can oscillate stably during these periods T1, T2, T1A, and T2A where stable oscillation of the oscillation circuit 110 is difficult.

  Further, in this embodiment, the stop of oscillation of the oscillation circuit 110 is detected, and the intermittent operation of the oscillation circuit regulator 210 is prohibited during the periods T3 and T4 during which the output voltage VRO of the oscillation circuit regulator 210 is increased. The circuit regulator 210 operates continuously. Therefore, in these periods T3 and T4, the oscillation circuit 110 can start oscillating stably and quickly and reliably. In addition, the oscillation circuit regulator 210 continuously operates in the additional periods T3A and T4A immediately after the end of the periods T3 and T4. Therefore, the oscillation circuit 110 can oscillate stably during these periods T3A and T4A where stable oscillation of the oscillation circuit 110 is difficult.

  As can be seen from the above description, the operation control signal generation circuit 310, the LS circuit 242 and the power switch circuits SW1 and SW2 included in the oscillation circuit 110 correspond to the operation control circuit of the present invention. The HIZ setting signal generation circuit 380 and the clock IF circuit 420 in this embodiment correspond to a clock signal output circuit. Furthermore, the boost signal generation circuit 320 and the voltage adjustment circuit MD included in the oscillation circuit regulator 210 in this embodiment correspond to a voltage increase circuit.

  In addition, this invention is not restricted to said Example and embodiment, In the range which does not deviate from the summary, it can be implemented in a various aspect, For example, the following deformation | transformation is also possible.

(1) In the above embodiment, as described with reference to FIG. 7, the H level period of the operation control signal LPW is set to 7/8 of one cycle Tc. It may be set to 3/4, 1/2, or the like. Further, the H level period of the operation control signal LPW may be changed in response to a request from the CPU 600, for example.

(2) In the above embodiment, as described with reference to FIGS. 7, 9, 11, 14, and 17, the continuous operation period includes the additional period, but the additional period can be omitted. However, if the continuous operation period includes the additional period, the oscillation circuit 110 can stably oscillate in the additional period as described above.

(3) In the above embodiment, the four circuits 210, 220, 230, and 240 can execute the intermittent operation. However, it is sufficient that at least the oscillation circuit regulator 210 can execute the intermittent operation.

  In the above embodiment, the four circuits 210, 220, 230, and 240 can perform an intermittent operation, and the intermittent operation of the four circuits is prohibited at the same time, but at least the intermittent operation of the oscillation circuit regulator 210 is performed. It should be prohibited.

  However, when the four circuits 210, 220, 230, and 240 operate intermittently or continuously at the same time as in the above embodiment, the power consumption of the RTC module 100 can be considerably reduced and the four circuits There is an advantage that the circuit can be operated stably at the same time.

(4) In the above embodiment, as described with reference to FIG. 11, the output of the clock IF circuit 420 is set to the high impedance state during the period in which the clock signal FOUT is not output. The logic level (L level or H level) may be set. In this case, the output of the clock IF circuit 420 may be set to a constant logic level also in the first partial period T21.

  In general, in the first partial period T21 immediately after the start of the clock enable period T2, the output of the clock signal FOUT whose logic level is periodically changed may be prohibited.

  In the above-described embodiment, the clock enable period T2 includes the first partial period T21 in which the output of the clock signal FOUT is prohibited. However, the first partial period T21 can be omitted.

(5) In the above embodiment, as shown in FIGS. 14 and 17, when the output voltage VRO of the oscillation circuit regulator 210 is increased, the output voltage VRD of the frequency divider regulator 220 is also increased. However, when the output voltage VRD of the divider circuit regulator 220 is always higher than the output voltage VRO of the oscillator circuit regulator 210 during the boost period, the output voltage VRD of the divider circuit regulator 220 does not have to be increased. Also good. In this case, the voltage adjustment circuit MD of the frequency divider circuit regulator 220 can be omitted.

(6) In the above embodiment, as shown in FIGS. 14 and 17, when the stop of oscillation of the oscillation circuit 110 is detected during the operation after starting the supply of the external power supply voltage and immediately after the supply of the external power supply voltage is started. In addition, the boost signal generation circuit 320 sets the boost signal BST to active (H level). However, boost signal generation circuit 320 may set boost signal BST to active (H level) regardless of whether or not oscillation stop is detected. For example, the boost signal generation circuit 320 may set the boost signal BST to active (H level) immediately after the start of supply of the external power supply voltage, regardless of the logic level of the detection signal FSTOP. Further, boost signal generation circuit 320 may set boost signal BST to active (H level) in response to a request from CPU 600.

  In general, the oscillation circuit regulator 210 may be operated continuously during a period in which the power supply voltage VRO output from the oscillation circuit regulator 210 is increased.

(7) In the above embodiment, the crystal unit 101 is provided inside the RTC module 100. However, instead of this, the crystal unit 101 may be provided outside the RTC module. In the above-described embodiment, the oscillation circuit 110 uses the crystal resonator 101. However, instead of this, a ceramic resonator may be used. Further, in the above embodiment, the RTC module 100 is provided with the oscillation circuit 110 that uses the vibrator. Instead of this, the oscillation circuit 110 that uses CR (capacitor and resistor) or LC (inductor) And other types of oscillation circuits such as an oscillation circuit using a capacitor) may be provided.

(8) In the above embodiment, the present invention is applied to the RTC module 100 as a time measuring device, but the present invention can also be applied to other processing devices including an oscillation circuit and an oscillation circuit regulator. In other words, the processing device may not have a function of measuring the seconds, minutes, hours, days, days of the week, years, and the like.

2 is an explanatory diagram showing an internal configuration of an RTC (real time clock) module 100 provided in the electronic apparatus. FIG. 3 is an explanatory diagram showing an internal configuration of an oscillation circuit regulator 210. FIG. It is explanatory drawing which shows the internal structure of the regulator 220 for frequency dividers. 3 is an explanatory diagram showing an internal configuration of a logic circuit regulator 230. FIG. It is explanatory drawing which shows three signals LPW, LPV, and XLPV in an intermittent operation period and a continuous operation period. 3 is an explanatory diagram showing an internal configuration of an operation control signal generation circuit 310. FIG. 7 is a timing chart showing the operation of the operation control signal generation circuit 310 (FIG. 6). It is explanatory drawing which shows the circuit for a data communication process. It is a timing chart which shows operation | movement of the circuit (FIG. 8) for a data communication process. It is explanatory drawing which shows the circuit for a clock output process. 11 is a timing chart showing an operation of a circuit (FIG. 10) for clock output processing. FIG. 11 is an explanatory diagram showing an internal configuration of a high impedance (HIZ) setting signal generation circuit 380 (FIG. 10). It is explanatory drawing which shows the internal structure of the clock IF circuit 420 (FIG. 10). It is a timing chart which shows operation | movement of the circuit at the time of an oscillation stop. 3 is an explanatory diagram showing an internal configuration of a boost signal generation circuit 320. FIG. FIG. 16 is an explanatory diagram showing a timing chart showing the operation of the boost signal generation circuit 320 (FIG. 15). It is a timing chart which shows operation | movement of the circuit at the time of power activation. 4 is an explanatory diagram showing an intermittent operation period and a continuous operation period during the operation of the RTC module 100. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... RTC module 101 ... Crystal oscillator 110 ... Oscillator circuit 120 ... Divider circuit 130 ... Logic circuit 210 ... Regulator for oscillator circuit 220 ... Regulator for divider circuit 230 ... Regulator for logic circuit 240 ... Reference voltage generation circuit 242 ... Level Shift (LS) circuit 300 ... Logic circuit 302 ... Timer circuit 310 ... Operation control signal generation circuit 312, 314, 318 ... OR circuit 313 ... Delay circuit 316 ... Counter 320 ... Boost signal generation circuit 322 ... Inverter circuit 324,326,328 ... reset set flip-flop 360 ... oscillation stop detection circuit 370 ... power-on reset circuit 380 ... high impedance (HIZ) setting signal generation circuit 382 ... delay circuit 384 ... AND circuit 400 ... interface (IF) circuit 410 ... data Data interface (IF) circuit 420 ... Clock interface (IF) circuit 421a, 421b ... Buffer circuit 423a, 423b ... Level shift (LS) circuit 424 ... NAND circuit 425 ... Inverter circuit 426 ... NOR circuit 427a, 427b ... Transistor 600 ... CPU
C1 to C4: Capacitors M11 to M12, M21 to M25, M31 to M35, M37 to M39 ... Transistors SW1, SW2 ... Power switch circuit DA ... Differential amplifier circuit QF ... Output & feedback circuit MD ... Voltage adjustment circuit

Claims (17)

A processing device connected to an external device,
A first constant voltage power supply circuit for generating a first power supply voltage;
An oscillation circuit that operates with the first power supply voltage to generate an oscillation signal;
An operation control circuit for controlling the operation of the first constant voltage power supply circuit;
With
The operation control circuit includes:
In the first period, the first constant voltage power supply circuit is intermittently operated,
The processing apparatus, wherein the first constant voltage power supply circuit is continuously operated in a second period in which a data signal is transmitted between the processing apparatus and the external device. The processing apparatus according to claim 1,
The operation control circuit further includes:
A processing apparatus for continuously operating the first constant voltage power supply circuit in a period immediately after the end of the second period. The processing apparatus according to claim 1 or 2, wherein
The operation control circuit further includes:
A processing apparatus that continuously operates the first constant voltage power supply circuit in a third period in which a clock signal based on the oscillation signal is output from the processing apparatus to the external device. The processing apparatus according to claim 3, wherein
The operation control circuit further includes:
A processing apparatus for continuously operating the first constant voltage power supply circuit in a period immediately after the end of the third period. The processing apparatus according to claim 3 or 4, further comprising:
A clock signal output circuit for outputting the clock signal;
The clock signal output circuit includes:
Prohibiting the output of the clock signal in a first partial period of the third period immediately after the start of the third period;
A processing apparatus that allows the output of the clock signal during a second partial period after the end of the first partial period in the third period. The processing apparatus according to claim 5, wherein
The clock signal output circuit includes:
The processing apparatus, wherein an output of the clock signal output circuit is set to a high impedance state during the first partial period of the third period. The processing apparatus according to any one of claims 1 to 6, further comprising:
A voltage increasing circuit for increasing the first power supply voltage output from the first constant voltage power supply circuit;
The operation control circuit includes:
A processing apparatus, wherein the first constant voltage power supply circuit is continuously operated during a fourth period in which the voltage increase circuit increases the first power supply voltage output from the first constant voltage power supply circuit. The processing apparatus according to claim 7,
The operation control circuit further includes:
A processing apparatus for continuously operating the first constant voltage power supply circuit in a period immediately after the end of the fourth period. The processing apparatus according to claim 7 or 8, further comprising:
A detection circuit for detecting a stop of oscillation of the oscillation circuit;
The processing apparatus, wherein the fourth period includes a period in which the detection circuit detects a stop of oscillation. The processing apparatus according to any one of claims 7 to 9,
The processing apparatus, wherein the fourth period includes a period immediately after the start of supply of an external power supply voltage to the processing apparatus. The processing apparatus according to any one of claims 1 to 10, further comprising:
A second constant voltage power supply circuit for generating a second power supply voltage;
A frequency divider that operates with the second power supply voltage and divides the oscillation signal;
With
The operation control circuit includes:
During the period in which the first constant voltage power circuit is operated intermittently, the second constant voltage power circuit is operated intermittently;
The processing apparatus which operates the said 2nd constant voltage power supply circuit continuously in the period which operates the said 1st constant voltage power supply circuit continuously. A control method for a processing apparatus connected to an external device, comprising: a first constant voltage power supply circuit that generates a first power supply voltage; and an oscillation circuit that operates with the first power supply voltage to generate an oscillation signal. Because
(A) intermittently operating the first constant voltage power supply circuit in a first period;
(B) continuously operating the first constant voltage power supply circuit in a second period in which a data signal is transmitted between the processing apparatus and the external device;
A control method comprising: A processing device connected to an external device,
A first constant voltage power supply circuit for generating a first power supply voltage;
An oscillation circuit that operates with the first power supply voltage to generate an oscillation signal;
An operation control circuit for controlling the operation of the first constant voltage power supply circuit;
With
The operation control circuit includes:
In the first period, the first constant voltage power supply circuit is intermittently operated,
In response to a request from the external device, the first constant voltage power supply circuit is continuously operated during a second period in which a signal is transmitted between the processing apparatus and the external device. Processing equipment. The processing apparatus according to claim 13, comprising:
The operation control circuit further includes:
A processing apparatus for continuously operating the first constant voltage power supply circuit in a period immediately after the end of the second period. The processing apparatus according to claim 13 or 14,
The processing device, wherein the signal includes data written into the processing device or data read from the processing device. The processing apparatus according to any one of claims 13 to 15,
The processing device, wherein the signal includes a clock signal based on the oscillation signal. A control method for a processing apparatus connected to an external device, comprising: a first constant voltage power supply circuit that generates a first power supply voltage; and an oscillation circuit that operates with the first power supply voltage to generate an oscillation signal. Because
(A) intermittently operating the first constant voltage power supply circuit in a first period;
(B) A step of continuously operating the first constant voltage power supply circuit in a second period in which a signal is transmitted between the processing device and the external device in response to a request from the external device. When,
A control method comprising:

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