JP2008218666A - Evaluation method and evaluation system for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine the manufacturing variation of a physical amount regarding wiring, with high accuracy. <P>SOLUTION: A method for evaluating the manufacturing variations from the designed value of a wiring structure in a semiconductor device is provided. The evaluation method comprises (a) a step for creating an approximation formula, showing the manufacturing variation as the function of a parameter σ, (b) a step for actually measuring the distribution of wiring resistance and capacitance, with respect to the wiring structure, and (c) a step for determining the parameter σ so that the distribution can be reproduced by the approximation formula with a predetermined probability. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to evaluation and design of semiconductor devices. In particular, the present invention relates to evaluation and design of semiconductor devices in consideration of manufacturing variations.

  In designing a semiconductor device, after logical design is performed, layout design is performed based on a net list. When the layout is determined, various verifications are performed as to whether the layout satisfies a design rule (Design Rule) and whether a design circuit having the layout operates normally. As one of the processes performed in the verification process, LPE (Layout Parameter Extraction) is known.

  In the LPE process, extraction of wiring resistance / wiring capacity (hereinafter sometimes referred to as “parasitic RC”) related to the wiring in the obtained layout is performed. Such a parasitic RC is a parameter that can be determined only after a layout is obtained, and is not included in the above-described netlist. Therefore, the extracted parasitic RC is added to the net list, and as a result, a net list to which the parasitic RC is added (hereinafter referred to as “net list with parasitic RC”) is created.

  Thereafter, the operation verification of the design circuit is performed by using the obtained net list with parasitic RC. Examples of the operation verification include delay verification and timing verification. If the result of the operation verification is “fail”, the layout process is executed again. Then, the LPE process is executed again, and the operation verification is executed again. The above operations are repeated until the layout “passes” the operation verification. When the result of the operation verification is “pass”, final layout data is determined.

  In an actual manufacturing process of a semiconductor device, the wiring structure may not be manufactured as intended. In other words, the wiring width, the thickness of the wiring layer, the thickness of the interlayer insulating film, and the like may vary from desired values. Such variation is hereinafter referred to as “manufacturing variability”. Manufacturing variability affects the delay in the circuit. That is, manufacturing variations may occur, and even if the designed layout passes the operation verification on the computer, the actual product may not operate normally.

  Therefore, it is desirable that the operation verification is performed in consideration of manufacturing variations. However, taking into account manufacturing variations means that the conditions to be cleared in the operation verification become severe. As the conditions become more severe, the result of the operation verification is more likely to fail, and the number of layout corrections increases. This leads to an increase in the time required for circuit design.

  Patent Document 1 describes a technique that can suppress an increase in the time required for circuit design while considering manufacturing variations. According to the prior art, a pattern of manufacturing variation that is impossible in practice is excluded from consideration. For example, when the width and thickness of the wiring can vary within a range of ± 3σ (σ: standard deviation) from the design value, the probability that the width and thickness vary at the same time to the maximum is extremely small. When such an extreme situation is taken into consideration, it is necessary to support the extreme situation, and the number of layout and verification re-execution increases. Therefore, according to the technique described in Patent Document 1, such an extreme situation is excluded from consideration. Such a device is hereinafter referred to as “statistical relaxation”.

  More specifically, the parasitic RC under the corner condition is calculated for each of various wiring structure patterns (cross-sectional structures). Here, the corner condition means a condition in which the delay time is maximum and minimum. The above-mentioned “statistical relaxation” is taken into consideration when obtaining the parasitic RC under the corner condition. Parasitic RC under the corner condition calculated for each wiring structure pattern is provided as a library. That library is referenced during the LPE process. Specifically, it is determined which wiring structure pattern the wiring to be processed matches, and the parasitic RC associated with the matching pattern is read from the library.

JP 2006-209702 A

  In the above-described prior art, the range ± 3σ of variations in wiring width and wiring film thickness has been treated as a known parameter. That is, the standard deviation σ of the distribution of physical quantities related to wiring is a known parameter. The calculation method of the standard deviation σ is not described. In general, a scanning electron microscope (SEM) is used to directly observe the physical structure of wiring. By observing the same wiring structure in a large number of manufactured semiconductor chips with an SEM, the standard deviation σ of the distribution of the wiring width and wiring film thickness can be obtained.

  However, observation of physical quantities using SEM takes time. In order to collect observation data to a certain level of statistical significance, it takes an enormous amount of time and costs increase. On the other hand, when the number of observation data is small, the accuracy of the standard deviation σ is deteriorated. If the accuracy of the standard deviation σ itself is poor, the reliability of the LPE process and operation verification taking into account the above-described manufacturing variations also decreases. As a result, the yield of manufactured semiconductor chips is also reduced.

  According to the present invention, instead of the physical quantity related to the wiring, the electric quantity (parasitic RC) related to the wiring is actually measured. Then, from the distribution of the measured electric quantity, the manufacturing variation of the physical quantity related to the wiring is estimated.

  In one aspect of the present invention, a method for evaluating manufacturing variability from a design value of a wiring structure in a semiconductor device is provided. The evaluation method includes: (a) creating an approximate expression that expresses wiring resistance and wiring capacitance (parasitic RC) related to a wiring structure as a function of a parameter indicating manufacturing variation of the wiring structure; and (b) relating to the wiring structure. Measuring the distribution of the parasitic RC, and (c) determining the parameters so that the actual distribution is reproduced with a predetermined probability using the approximate expression.

For example, the wiring structure includes a wiring film thickness T, a wiring width W, and an interlayer film thickness H. The variation ΔT of the wiring film thickness T from the design value T0 exists in the range of −σ _T to + σ _{T with} the predetermined probability. The variation ΔW of the wiring width W from the design value W0 exists in the range of −σ _W to + σ _{W with} the predetermined probability. The fluctuation amount ΔH of the interlayer film thickness H from the design value H0 exists in the range of −σ _H to + σ _{H with} the predetermined probability. The wiring resistance and the wiring capacity depend on the fluctuation amounts ΔT, ΔW, and ΔH. At this time, the parameters indicating the manufacturing variation of the wiring structure are σ _T , σ _W , and σ _H.

Thus, according to the present invention, instead of the physical quantities (T, W, H) related to the wiring, the electric quantities (R, C) related to the wiring are actually measured. Unlike the measurement of physical quantities using SEM, a large number of observation data can be easily collected when measuring the quantity of electricity using a probe or the like. Then, parameters σ _T , σ _W , and σ _H indicating manufacturing variations are determined so that the measured distribution of electricity is reproduced. That is, it is possible to indirectly determine the manufacturing variation of the physical quantities (T, W, H) related to the wiring with high accuracy. Furthermore, since it is not necessary to perform observation by SEM, the processing time is reduced and the processing cost is reduced.

The parameters σ _T , σ _W , and σ _H indicating the manufacturing variation obtained by the above method are used in the evaluation and design of the semiconductor device. For example, a statistical static timing analysis (SSTA) of a design circuit is performed using the parameters σ _T , σ _W , and σ _H at a certain timing in the design flow. Since the parameters σ _T , σ _W , and σ _H are highly accurate, the accuracy and reliability of the SSTA are also improved.

In addition, by using the parameters σ _T , σ _W , and σ _H , LPE processing and operation verification considering manufacturing variation may be performed. For example, based on the parameters σ _T , σ _W , and σ _H , a delay variation parameter indicating the variation range of the delay in the wiring structure is calculated. By referring to the delay variation parameter, delay verification after LPE processing is performed. Since the parameters σ _T , σ _W , and σ _H are highly accurate, the accuracy and reliability of the delay variation parameter are improved, and in turn, the accuracy and reliability of delay verification after LPE processing are also improved. As a result, the yield of manufactured semiconductor chips is also improved.

  According to the present invention, it is possible to determine manufacturing variations of physical quantities related to wiring with high accuracy without using an SEM. Since it is not necessary to perform observation by SEM, processing time is reduced and processing costs are reduced.

  A method for evaluating and designing a semiconductor device according to the present invention will be described with reference to the accompanying drawings. In the present invention, there are provided a method for evaluating manufacturing variations of a semiconductor device and a design method considering the manufacturing variations.

1. Manufacturing Variation of Physical Structure First, “manufacturing variation” handled in the present invention will be described in detail. In an actual manufacturing process of a semiconductor device, the wiring structure may not be manufactured as intended. That is, the wiring width, wiring film thickness, interlayer insulating film thickness, and the like may vary from desired design values.

  FIG. 1A shows a certain wiring structure pattern (cross-sectional structure), and shows a desired pattern in design. The wiring structure pattern includes the target wiring 10. The target wiring 10 is formed in the wiring layer M1, and wirings 11a to 11c are formed around the target wiring 10 via an insulating film. An interlayer insulating film 12 is formed between the wiring layer M1 and the wiring layer M2. As shown in FIG. 1A, the design film thickness and design width of the target wiring 10 and the design film thickness of the interlayer insulating film 12 are represented by T0, W0, and H0, respectively. These design values are hereinafter referred to as “center conditions”.

  In general, the actually manufactured wiring structure deviates from the center condition. FIG. 1B shows an example of a wiring structure pattern that is actually manufactured, and a dotted line in the drawing represents a center condition. As shown in FIG. 1B, the manufacturing film thickness and manufacturing width of the target wiring 10 and the manufacturing film thickness of the interlayer insulating film 12 are T, W, and H different from the above design values (T0, W0, H0). . These wiring film thickness T, wiring width W, and interlayer film thickness H are expressed by the following equations.

T = T0 + ΔT
W = W0 + ΔW
H = H0 + ΔH

  In the above relational expression, ΔT, ΔW, and ΔH are fluctuation amounts (manufacturing variations) of the wiring film thickness T, the wiring width W, and the interlayer film thickness H from the design values T0, W0, and H0. The following points should be noted regarding these fluctuation amounts ΔT, ΔW, and ΔH.

  First, there is no correlation between the fluctuation amount ΔT and the fluctuation amount ΔW. That is, the phenomenon of “variation of wiring film thickness T” and the phenomenon of “variation of wiring width W” are independent of each other. This is apparent from the fact that the step of determining the wiring film thickness T and the step of determining the wiring width W are different in a general manufacturing process of a semiconductor device. The wiring film thickness T is determined by a film deposition process and a CMP (Chemical Mechanical Polishing) process. On the other hand, the wiring width W is determined by a lithography process.

  Furthermore, there is no correlation between the fluctuation amount ΔH and the other fluctuation amounts ΔT and ΔW. In other words, the event “variation in interlayer film thickness H” and the event “variation in wiring film thickness T and wiring width W” are independent of each other. This is apparent from the fact that the step of forming the interlayer insulating film and the step of forming the wiring are different in a general manufacturing process of a semiconductor device.

  Thus, the wiring film thickness T, the wiring width W, and the interlayer film thickness H vary independently of each other. That is, the fluctuation amounts ΔT, ΔW, and ΔH are independent variables. These fluctuation amounts ΔT, ΔW, and ΔH are expressed in the following ranges with a predetermined probability.

-Σ _T ≤ ΔT ≤ + σ _T
-Σ _W ≤ ΔW ≤ + σ _W
-Σ _H ≤ ΔH ≤ + σ _H

In the above relational expression, the parameters σ _T , σ _W , and σ _H are parameters that define the statistical distribution of the fluctuation amounts ΔT, ΔW, and ΔH, and manufacture the wiring film thickness T, the wiring width W, and the interlayer film thickness H. This parameter indicates the degree of variation. The parameters σ _T , σ _W , and σ _H may be, for example, standard deviation, three times the standard deviation, or (maximum value−minimum value) / 2. It can be said that the fluctuation amount ΔT exists in the range of −σ _T to + σ _T with a predetermined probability. Further, it can be said that the variation ΔW exists in a range of −σ _W to + σ _W with a predetermined probability. Further, it can be said that the fluctuation amount ΔH exists in the range of −σ _H to + σ _H with a predetermined probability. Also, the parameters σ _T , σ _W , and σ _H can be different values. Hereinafter, these parameters σ _T , σ _W , and σ _H may be collectively referred to as “variation parameters σ”. It is one of the objects of the present invention to accurately determine the variation parameter σ without using SEM.

2. FIG. 2 is a flowchart showing a method for determining the variation parameter σ. The flow shown in FIG. 2 is executed for each wiring structure pattern. As an example, the process for determining the variation parameter σ for the wiring structure pattern shown in FIGS. 1A and 1B will be described.

Step S1: Approximate Expression of RC In Step S1, an expression that generally represents the wiring resistance R and the wiring capacitance C related to the wiring structure pattern is given. First, the wiring resistance R per unit length of the target wiring 10 is given by the following equation.

  Here, the parameter ρ is an electrical resistivity (unit: Ωm) and depends on the wiring material, temperature, amount of impurities, and the like. Here, aluminum is used as the wiring material, and the temperature is 25 ° C. As shown in Equation (1), the wiring resistance R is obtained by dividing the electrical resistivity ρ by the wiring cross-sectional area (T × W), and is given by the function f (ΔT, ΔW) of the fluctuation amounts ΔT, ΔW. It is done.

  Further, an expression representing the wiring capacitance (parasitic capacitance) C of the target wiring 10 is obtained as follows. First, various combinations of fluctuation amounts ΔT, ΔW, and ΔH are conceivable. The fluctuation amounts ΔT, ΔW, ΔH are selected based on, for example, the process manufacturing management width. And the wiring capacity C in the case of the various combinations is calculated by capacity simulation. In the capacity simulation, a predetermined capacity simulator performs electromagnetic field analysis of a given wiring structure pattern and calculates a wiring capacity C related to the target wiring 10. Thereafter, fitting processing of various calculated wiring capacitances C is performed by using a second-order or higher order polynomial. For example, the following equation is used as the polynomial.

In the above mathematical formula (2), the parameters c1 to c3 are integers of 0 or more and are appropriately determined. Β _c1c2c3 is a coefficient corresponding to the parameters c1 to c3. For example, a response surface function (variable = ΔT, ΔW, ΔH; response = C) is obtained based on RSM (Response Surface Methodology). By such fitting processing, the coefficient β _c1c2c3 is determined so that various wiring capacities C can be approximated by the polynomial. The wiring capacitance C depends on the fluctuation amounts ΔT, ΔW, and ΔH, and is given by a function g (ΔT, ΔW, ΔH).

  In this way, polynomials (1) and (2) representing the wiring resistance R and the wiring capacitance C as functions of the fluctuation amounts ΔT, ΔW, and ΔH are obtained. These polynomials (1) and (2) are second or higher order polynomials. In the following description, the wiring resistance R and the wiring capacitance C of the target wiring 10 may be collectively referred to as “parasitic RC”.

Step S2: Generation of First-Order Approximation Formula Next, the second-order and higher-order polynomials (1) and (2) are converted into a first-order approximation expression by approximation calculation. As a result, the parasitic RC related to the wiring structure pattern is given by the following first-order approximation equations (f1 (ΔT, ΔW), g1 (ΔT, ΔW, ΔH)). In the following mathematical formula (3), α, β, γ, δ, and ε are coefficients. R0 and C0 are the wiring resistance R and the wiring capacitance C in the case of the center condition (T0, W0, H0), respectively.

Step S3: Statistical relaxation As described above, the fluctuation amounts ΔT, ΔW, and ΔH are independent variables. This means that the probability (ΔT = ± σ _T , ΔW = ± σ _W , ΔH = ± σ _H ) that the fluctuation amounts ΔT, ΔW, ΔH are maximized simultaneously is extremely small. For example, it is considered that manufacturing variations such as ΔT = + σ _T , ΔW = + σ _W , and ΔH = −σ _H are substantially impossible. Such extreme cases may be excluded from consideration, and only events that occur with a predetermined probability or higher need be considered. That is, “statistical relaxation” is also performed in the present invention.

FIG. 3 is a diagram for explaining statistical relaxation. In FIG. 3, each of the three axes orthogonal to each other indicates the wiring width W, the wiring film thickness T, and the interlayer film thickness H. The origin O indicates the center condition (W0, T0, H0). The distance from the origin O means fluctuation amounts ΔW (= −σ _W to + σ _W ), ΔT (= −σ _T to + σ _T ), ΔH (= −σ _H to + σ _H ). Each distribution of the fluctuation amounts ΔW, ΔT, and ΔH is assumed to be a normal distribution. In such a space, “Joint Probability Density Function” (JPDF) of the fluctuation amounts ΔW, ΔT, and ΔH can be defined. JPDF is sometimes called “JDF (Joint Distribution Function)”.

JPDF defines probabilities at each point (ΔW, ΔT, ΔH) in the space shown in FIG. Here, since the fluctuation amounts ΔW, ΔT, and ΔH are independent variables, the probability p1 (ΔW = ± σ _W , ΔT = 0, ΔH = 0), the probability p2 (ΔW = 0, ΔT = ± σ _T , ΔH = 0) and the probability p3 (ΔW = 0, ΔT = 0, ΔH = ± σ _H ) are equal. There are many other points that occur with a probability equal to the probabilities p1 to p3. A set of points generated with the same probability is the curved surface shown in FIG. 3, and is hereinafter referred to as a “JPDF equal probability curved surface”. The probabilities of manufacturing variations corresponding to the points P (ΔW, ΔT, ΔH) on the equiprobability curved surface are all equal. Note that the equiprobability curved surface is “spherical” when the variation is assumed to be a normal distribution and the absolute values of the variation parameters σ _W , σ _T , and σ _H are all equal. "

According to the invention, only points within the equiprobability curved surface are considered. That is, only events that occur with a probability equal to or higher than the probabilities p1 to p3 are considered. For example, an extreme case such as a point Q (ΔW = + σ _W , ΔT = + σ _T , ΔH = −σ _H ) in FIG. 3 is excluded from consideration. That is, “statistical relaxation” is performed. The point P (ΔW, ΔT, ΔH) on the equiprobability curved surface is given by the following equation in polar coordinate display.

It is assumed that the distributions of the fluctuation amounts ΔW, ΔT, and ΔH are normal distributions. It can be said that the relational expression given by the mathematical formula (4) represents a “constraint” given between the fluctuation amounts ΔT, ΔH, and ΔW due to statistical relaxation. By substituting this mathematical formula (4) into the above-mentioned primary approximate expression (3), the following approximate expressions (f2 (σ _T , σ _W , θ, φ), g2 (σ _T , σ) regarding the parasitic RC are obtained. _W , σ _H , θ, φ)).

  The approximate expression given by Equation (5) is a function of the variation parameter σ (unknown number) and the angles θ and φ. This approximate expression can be said to be an approximate expression of the parasitic RC in consideration of “statistical relaxation”.

Step S4: Actual measurement of RC In step S4, “measurement” of the wiring resistance R and the wiring capacitance C regarding the wiring structure pattern being processed is performed. FIG. 4 is a plan view of the wafer. A plurality of semiconductor chips 20 are formed on the wafer. The semiconductor chip 20 may be a TEG (Test Element Group) for characteristic evaluation. Each semiconductor chip 20 has various wiring structure patterns. For example, in FIG. 4, a circle indicates the first wiring structure pattern 21, and a cross indicates the second wiring structure pattern 22.

  Of these, it is assumed that the first wiring structure pattern 21 is the wiring structure pattern shown in FIGS. 1A and 1B. Accordingly, the first wiring structure pattern 21 included in each of the plurality of semiconductor chips 20 is an observation target. The parasitic RC related to each first wiring structure pattern 21 is actually measured by the probe. As a result, an actual parasitic RC distribution (hereinafter referred to as “RC distribution”) is obtained.

  In addition, one semiconductor chip 20 may have the same wiring structure pattern at a plurality of different positions. Therefore, a plurality of first wiring structure patterns 21 included in one semiconductor chip 20 may be an observation target. Even in that case, the parasitic RC regarding each 1st wiring structure pattern 21 is actually measured by a probe, and a certain RC distribution is obtained. Which RC distribution is used may be determined as appropriate according to the method of utilizing the variation parameter σ calculated later.

  FIG. 5 shows an example of the measured RC distribution. Each of the vertical axis and the horizontal axis represents the measured wiring resistance R and wiring capacitance C. Each point in the figure represents a set of a wiring resistance R and a wiring capacitance C. A point Pc (C0, R0) in the figure corresponds to the center condition. RC distribution data OBS indicating such RC distribution is stored in a predetermined storage device. Step S4 may be performed before steps S1 to S3.

Step S5: Calculation of σ Next, the variation parameter σ is determined so that the RC distribution described above is reproduced with a predetermined probability by the above-described approximate expression (5).

  First, at least two arbitrary points are extracted from the RC distribution. The first point is, for example, a point where the wiring resistance R becomes the maximum value Rm. In this case, it is assumed that the wiring capacitance C is Cm. That is, the point Pa (Cm, Rm) in FIG. 5 is the first point. The second point is that, for example, the wiring resistance R is the center value (design value) R0, and the wiring capacitance C is the maximum value Ck. That is, the point Pb (Ck, R0) in FIG. 5 is the second point. The variation parameter σ is determined so that these two points Pa and Pb are reproduced at least by the approximate expression (5).

  With respect to the first point Pa (Cm, Rm), the following equation is obtained. The wiring resistance R depends only on the wiring width W and the wiring film thickness T. Therefore, the point where the wiring resistance R becomes the maximum value Rm on the equiprobability curved surface shown in FIG. 3 exists on the circumference in the case of φ = 0. Further, it is assumed that the angle θ when the wiring resistance R is the maximum value Rm is θm. By substituting these angles (φ = 0, θ = θm) and the actually measured resistance value Rm into the approximate expression (5), the following expression (6) is obtained.

  Furthermore, since the resistance value Rm is the maximum, the following equations (7) and (8) are obtained.

  On the other hand, the following equation (9) is obtained by substituting the angle (φ = 0, θ = θm) and the actually measured capacitance value Cm into the approximate equation (5).

  With respect to the second point Pb (Ck, R0), the following equation is obtained. Assume that the angles θ and φ when the wiring resistance R is the center value R0 and the wiring capacitance C is the maximum value Ck are θk and φk, respectively. By substituting these angles (θ = θk, φ = φk) and the center value R0 into the approximate expression (5), the following expressions (10) and (11) are obtained.

  On the other hand, the following equation (12) is obtained by substituting the angle (θ = θk, φ = φk) and the actually measured capacitance value Ck into the approximate equation (5).

  Furthermore, since the capacitance value Ck is the maximum, the following equations (13) and (14) are obtained.

Of the equations thus obtained, six equations (6), (8), (9), (11), (12), and (14) are considered. There are six unknowns appearing in these six equations: σ _T , σ _W , σ _H , θm, θk, and φk. Therefore, six unknowns can be obtained by solving simultaneous equations consisting of six equations. That is, the variation parameters σ (σ _T , σ _W , σ _H ) can be approximately obtained so that the measured RC indicated by the two points Pa and Pb is reproduced by the approximate expression (5). The simultaneous equations can be solved using, for example, a Newton method.

  By substituting the obtained approximate variation parameter σ into the approximate expression (5), the parasitic RC corresponding to the equiprobability curved surface can be calculated. By changing the angles θ and φ in various ways, a plurality of sets of parasitic RCs are calculated. FIG. 6 is a diagram in which a plurality of calculated sets are plotted over the RC distribution. In FIG. 6, dotted line ARC represents a plurality of calculated sets, and represents a parasitic RC corresponding to an equiprobability curved surface. A region (RC region) surrounded by a dotted line ARC represents a parasitic RC (approximate distribution) that can be reproduced by the approximate expression (5). It is difficult to create a plot directly without using an approximate solution.

  When the RC region surrounded by the dotted line ARC can sufficiently reproduce the actually measured RC distribution, the current variation parameter σ is determined as the final variation parameter σ. In the case of the example shown in FIG. 6, the RC region can reproduce most of the RC distribution, but cannot reproduce a part of the RC distribution. In such a case, fine adjustment of the approximate variation parameter σ may be performed. Each time the variation parameter σ is finely adjusted, the dotted line ARC is gradually shifted.

  For example, when 3 times the standard deviation is required as the variation parameter σ, fine adjustment is performed so that 99.7% of the RC distribution is included in the RC region (approximate distribution) surrounded by the dotted line ARC. Alternatively, when (maximum value−minimum value) / 2 is required as the variation parameter σ, fine adjustment is performed so that the entire RC distribution is included in the RC region (approximate distribution) surrounded by the dotted line ARC. As described above, fine adjustment is performed when the probability of the RC distribution included in the approximate distribution is smaller than the predetermined probability.

  FIG. 7 shows the plot after fine adjustment. In FIG. 7, the dotted line ARC changes to a dotted line ARC ′, and the dotted line ARC ′ represents a parasitic RC corresponding to an equiprobability curved surface. As shown in FIG. 7, the RC region surrounded by the dotted line ARC ′ can sufficiently reproduce the actually measured RC distribution with a predetermined probability. Therefore, the variation parameter σ after fine adjustment is determined as the final variation parameter σ.

  The plot shown in FIG. 6 and the plot shown in FIG. 7 are displayed on a display, for example. The designer can perform fine adjustment while referring to the plot displayed on the display. Further, the fine adjustment may be automatically performed by EDA.

Step S6: Determination of σ In this way, the variation parameter σ (σ _T , σ _W , σ _H ) is determined so that the approximate expression (5) can reproduce the RC distribution with a predetermined probability. According to the present invention, it is not necessary to actually measure the physical structure using the SEM. What is actually measured in the present invention is not the physical quantities (T, W, H) related to the wiring but the electric quantities (R, C) related to the wiring. Unlike the measurement of physical quantities by SEM, it is possible to easily collect a large number of observation data when measuring the quantity of electricity. Therefore, it is possible to indirectly determine the variation parameter σ, that is, the production variation of the physical quantity related to the wiring with high accuracy. In addition, since it is not necessary to perform observation by SEM, the processing time is reduced and the processing cost is reduced.

Step S7: High-accuracy RC formula By substituting the determined variation parameter σ into the above-described formula (4), relational expressions of the fluctuation amounts ΔT, ΔW, and ΔH can be obtained. By further substituting these relational expressions into RC approximation expressions (1) and (2) before the primary approximation, an expression that expresses the parasitic RC with high accuracy can be obtained. The high precision RC formula is a function of the angles θ and φ.

  Since the variation parameter σ calculated in the present invention is highly accurate, the parasitic RC given by the above equation (15) is also highly accurate. The flow shown in FIG. 2 is executed for each wiring structure pattern, and the variation parameter σ and the high-accuracy RC equation (15) are obtained for each wiring structure pattern. For example, the semiconductor chip 20 shown in FIG. 4 includes the wiring structure patterns 21 and 22, and the variation parameter σ is calculated for each of the wiring structure patterns 21 and 22. The variation parameter σ may indicate a manufacturing variation among a plurality of semiconductor chips 20 or may indicate a manufacturing variation within one semiconductor chip 20.

3. Delay Analysis FIG. 8 is a flowchart showing a delay analysis using the calculated variation parameter σ. As described above, the highly accurate RC equation (15) is obtained using the calculated variation parameter σ (step S7). Then, by using the high-accuracy RC formula (15), it is possible to simulate a delay in the target wiring 10 in the wiring structure pattern (step S8).

  FIG. 9 schematically shows a circuit model 30 used in circuit simulation. The circuit model 30 includes a circuit in which the driver 31 drives the load cell 32 through the target wiring 10. The parameter Rdrv is the output resistance (impedance) of the driver 31. The parameter Cin is the gate input capacity (load capacity) of the load cell 32. The parameters Rwire and Cwire are the wiring resistance R and the wiring capacitance C given by the high precision RC equation (15). By using the circuit model 30 and a circuit simulator such as SPICE, delay analysis relating to the target wiring 10 can be performed.

  Alternatively, the delay can be estimated by referring to a predetermined delay approximation formula instead of the circuit simulation. As the delay approximation formula, for example, the well-known “Elmore delay approximation formula” is used. In that case, the delay value Tpd in the target wiring 10 is expressed by the following equation. The parameter L is the wiring length of the target wiring 10, and is set to a unit length, for example.

  The delay value Tpd in the target wiring 10 is calculated by circuit simulation or a delay approximation formula. FIG. 10 shows an example of the calculation result of the delay value Tpd. Although the delay value Tpd varies depending on the angles θ and φ, only the dependence of the delay value Tpd on the angle θ is shown in FIG. 10 for simplicity. The vertical axis represents the calculated delay value Tpd, and the horizontal axis represents the angle θ. The delay value Tpd0 means a delay value (design value) in the case of the center condition (Rwire = R0, Cwire = C0).

  As shown in FIG. 10, the delay value Tpd varies from the design value Tpd0 according to the manufacturing variation of the physical structure. That is, the delay value Tpd varies within a certain range including the design value Tpd0. Therefore, the fluctuation range ΔTpd of the delay value Tpd can be defined. In other words, the variation width of the delay value Tpd in the target wiring 10 can be “estimated”. The variation range ΔTpd of the delay value Tpd depends on the variation parameter σ, and the variation range ΔTpd increases as the variation parameter σ increases.

  With respect to the variation parameter σ of the physical structure, the variation range ΔTpd is hereinafter referred to as “delay variation parameter”. In particular, when the variation parameter σ represents a manufacturing variation in one semiconductor chip 20, the delay variation parameter ΔTpd is called an “OCV (On-Chip Variation) coefficient”. The OCV coefficient indicates a delay variation width ΔTpd between a plurality of the same wiring structure patterns included in one chip. On the other hand, when the variation parameter σ represents the manufacturing variation among the plurality of semiconductor chips 20, the delay variation parameter ΔTpd is larger than the OCV coefficient.

  The delay value Tpd is maximum or minimum at a certain angle θ, φ. In the example shown in FIG. 10, the delay value Tpd is maximized when the angle is θ1, and the delay value Tpd is minimized when the angle is θ2. By substituting these angles θ and φ into the above-described high-accuracy RC equation (15), it is possible to calculate (estimate) the parasitic RC when the delay value Tpd is maximum / minimum.

  The parasitic RC when the delay value Tpd is maximum / minimum is hereinafter referred to as “corner RC”. The corner RC is calculated for each wiring structure pattern. That is, as in the prior art disclosed in Patent Document 1, it is possible to create an “RC library” indicating a corner RC for each wiring structure pattern. In the present invention, since the accuracy of the variation parameter σ is higher than that of the prior art, the accuracy and reliability of the RC library is also higher than that of the prior art.

  As described above, the delay variation parameter (OCV coefficient) ΔTpd and the corner RC are calculated by using the variation parameter σ and the high-accuracy RC equation (15) (step S9). The delay variation parameter ΔTpd and the corner RC are calculated for each wiring structure pattern. Similar to the variation parameter σ, the delay variation parameter ΔTpd and the corner RC can also be said to be parameters related to the manufacturing variation of the design circuit. These variation parameter σ, delay variation parameter ΔTpd, and corner RC can be used for evaluation and design of a semiconductor device as described below.

4). Semiconductor Device Design / Manufacturing Method FIG. 11 is a flowchart showing a semiconductor device design / manufacturing method according to the present invention. First, referring to FIG. 11, the design / manufacturing flow of the semiconductor device is overviewed.

Step S10:
First, after logic design of the semiconductor device is performed, logic synthesis is performed. As a result, a net list NET of the design circuit is created. The netlist NET is data indicating a connection relationship between logic elements in the design circuit. FIG. 12 conceptually shows an example of the connection relationship indicated by the netlist NET.

Step S20:
Further, the timing analysis of the design circuit is performed by using the netlist NET and a predetermined circuit simulator. For example, static timing analysis (STA) is performed. If the predetermined delay constraint is satisfied, the process proceeds to the next step.

Step S30:
Next, the layout of the design circuit is determined based on the netlist NET, and layout data LAY indicating the layout is created. FIG. 13 shows a layout example of the wiring between the elements shown in FIG. The wiring is formed over the wiring layers M1 and M2.

Step S40:
When the layout is determined, various verifications are performed as to whether the layout satisfies the design rule (Design Rule) and whether the design circuit having the layout operates normally. Therefore, layout data LAY and netlist NET are read out.

Step S50:
In order to perform delay verification and operation verification in consideration of the layout, it is necessary to know the parasitic RC of the wiring in the layout. Therefore, the LPE process is performed by referring to the layout data LAY. By the LPE process, the parasitic RC is extracted for all the wirings included in the layout.

Step S60:
The extracted parasitic RC is added to the netlist NET. As a result, a “net list with parasitic RC NET-RC” relating to the design circuit is created. FIG. 14 conceptually shows a net list with parasitic RC NET-RC corresponding to the net list NET shown in FIG.

Step S70:
By using the net list with parasitic RC NET-RC, delay calculation of the design circuit and delay / timing verification are performed. In the delay / timing verification, circuit simulation or STA is performed.

Steps S80 and S90:
When the result of the delay verification is “fail” (step S80; No), steps S30 to S70 are executed again. That is, the layout is corrected based on the verification result. When the result of the delay verification is “pass” (step S80; Yes), the layout data LAY created in step S30 is determined as final layout data (step S90).

Step S100:
The designed semiconductor device is manufactured based on the layout data LAY. Specifically, mask data is created by processing the layout data LAY. Next, a reticle (mask) is created based on the created mask data. A desired semiconductor device is manufactured by a photolithography technique using the reticle.

4-1. Application of Delay Variation Parameter For example, the delay variation parameter ΔTpd described above can be applied to delay verification (step S70). The delay value calculated from the net list with parasitic RC NET-RC corresponds to the design value Tpd0 shown in FIG. As described above, as a result of manufacturing variations, the delay value Tpd can vary within a certain range ΔTpd including the design value Tpd0. By referring to the delay variation parameter ΔTpd indicating the range ΔTpd in the delay verification, the delay verification becomes more precise. In other words, it is possible to realize highly accurate delay verification in consideration of manufacturing variations in the design circuit.

  As a comparison, consider a case where manufacturing variations are not considered in step S70. In that case, even if the designed layout passes the delay verification on the computer, the actual product may not operate normally. This means a decrease in yield. On the other hand, by performing delay verification in consideration of manufacturing variations as in the present invention, the yield and reliability of manufactured semiconductor chips are improved.

  Furthermore, in the present invention, “statistical relaxation” is performed when the variation parameter σ is determined, and manufacturing variations that cannot be practically excluded are excluded from consideration. Therefore, the result of the delay verification is prevented from being “failed” unnecessarily. Since it is not necessary to modify the layout so as to support a substantially impossible case, an increase in design time is suppressed.

4-2. Application of Corner RC Alternatively, the above-described corner RC can be applied to the LPE process (step S50). That is, similarly to the conventional technique disclosed in Patent Document 1, it is possible to perform LPE processing in consideration of manufacturing variations. Specifically, the RC library indicating the corner RC for each wiring structure pattern is referred to during the LPE process. It is determined which wiring structure pattern the wiring to be processed matches, and the corner RC associated with the matching pattern is read from the RC library. Then, the read corner RC is added to the netlist NET, and a netlist with parasitic RC NET-RC is created.

  In this example, manufacturing variations are taken into account at the time of LPE processing. As for the net list with parasitic RC NET-RC created as a result, manufacturing variations are taken into consideration. Therefore, the delay verification (step S70) using the net list with parasitic RC NET-RC is also a delay verification considering manufacturing variations. That is, highly accurate delay verification can be realized. As a result, the yield and reliability of the manufactured semiconductor chip are improved. Furthermore, an increase in the design time of the semiconductor device is suppressed.

4-3. Other Applications Statistical static timing analysis (SSTA) may be performed at a certain timing in the design flow shown in FIG. SSTA is an STA that takes into account manufacturing variations. For example, SSTA is executed in step S20 in the design flow shown in FIG. Therefore, the variation parameter σ calculated by the method according to the present invention can be applied to the SSTA. Since the variation parameter σ is highly accurate, the accuracy and reliability of the SSTA are also improved. In addition, the variation parameter σ can also be used for variation management in the production line.

5. System Configuration The calculation of the variation parameter σ, the delay analysis, and the evaluation / design of the semiconductor device described above are realized by a computer system (CAD; Computer Aided Design). FIG. 15 is a block diagram illustrating an example of the circuit design / evaluation system 100. The circuit design / evaluation system 100 includes a storage device 110, a processor (MPU) 120, an input device 130, and an output device 140. Examples of the storage device 110 include a hard disk drive and a RAM. Examples of the input device 130 include a keyboard and a mouse. An example of the output device 140 is a display.

  Various data are stored in the storage device 110. Specifically, the storage device 110 includes a wiring structure file STR, an RC approximate expression file EQU, RC distribution data OBS, variation data 40, delay variation parameter 50, RC library 60, netlist NET, layout data LAY, parasitic RC. The attached netlist NET-RC and the like are stored.

  The wiring structure file STR is a file showing various wiring structure patterns (see FIGS. 1A and 1B). The RC approximate expression file EQU is a file indicating an approximate expression (see the above-described mathematical expression) of the parasitic RC. The RC distribution data OBS is data indicating the RC distribution obtained in step S4 (see FIG. 5). The variation data 40 is data indicating the variation parameter σ calculated by the method of the present invention. The delay variation parameter 50 corresponds to the above-described delay variation parameter ΔTpd. The RC library 60 is a library showing corners RC for various wiring structure patterns.

  Furthermore, a design program group 70 is stored in the storage device 110. The design program group 70 is software executed by the processor 120. The design program group 70 may be stored in a computer-readable recording medium. The design program group 70 includes a capacity simulator 71, a variation determination tool 72, a circuit simulator 73, a layout tool 74, an LPE tool 75, a verification tool 76, and the like.

  The capacity simulator 71 is a tool that executes capacity simulation in step S1. Specifically, the capacity simulator 71 performs an electromagnetic field analysis of the wiring structure pattern given by the wiring structure file STR, and calculates the wiring capacity C of the target wiring 10. The variation determination tool 72 is a tool for executing the processing shown in FIG. That is, the variation determination tool 72 creates the variation data 40 based on the RC approximate expression file EQU and the RC distribution data OBS. The circuit simulator 73 is a tool that executes the processing shown in FIG. That is, the circuit simulator 73 creates the delay variation parameter 50 and the RC library 60 based on the RC approximate expression file EQU and the variation data 40. The layout tool 74 and the verification tool 76 execute steps S30, S50, and S70 shown in FIG. 11, respectively.

  The processor 120 implements the processing according to the present invention by executing the design program group 70. That is, the processor 120 executes the design program group 70, reads necessary data from the storage device 110, and writes the created data to the storage device 110. Thereby, calculation of variation parameter σ, delay analysis, and evaluation / design of the semiconductor device according to the present invention are realized.

FIG. 1A is a cross-sectional view showing a design pattern of a certain wiring structure. FIG. 1B is a cross-sectional view showing a manufacturing pattern of the wiring structure. FIG. 2 is a flowchart showing a method for determining the variation parameter σ according to the present invention. FIG. 3 is a conceptual diagram showing an equiprobability curved surface of a joint probability density function (JPDF). FIG. 4 is a top view showing an example of a wafer. FIG. 5 is a graph showing the actually measured RC distribution. FIG. 6 is a graph showing the actually measured RC distribution and the RC region reproduced by the approximate expression. FIG. 7 is a graph showing the actually measured RC distribution and the RC region reproduced by the approximate expression after fine adjustment. FIG. 8 is a flowchart showing delay analysis according to the present invention. FIG. 9 is a schematic diagram showing a circuit model used in the circuit simulation in the flow shown in FIG. FIG. 10 is a graph showing an example of a circuit simulation result. FIG. 11 is a flowchart showing a method for designing and manufacturing a semiconductor device. FIG. 12 is a conceptual diagram for explaining a netlist. FIG. 13 is a conceptual diagram for explaining layout data. FIG. 14 is a conceptual diagram for explaining a net list with parasitic RC. FIG. 15 is a block diagram showing a configuration example of a circuit design / evaluation system according to the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Target wiring 11 Wiring 12 Interlayer insulation film 20 Semiconductor chip 21 1st wiring structure pattern 22 2nd wiring structure pattern 30 Simulation circuit model 31 Driver 32 Load cell 40 Variation data 50 Delay variation parameter 60 RC library 70 Design program group 71 Capacity simulator 72 Variation determination tool 73 Circuit simulator 74 Layout tool 75 LPE tool 76 Verification tool 100 Circuit design / evaluation system 110 Storage device 120 Processor 130 Input device 140 Output device STR Wiring structure file EQU RC approximate expression file OBS RC distribution data NET Netlist LAY Layout data NET-RC Parasitic RC netlist

Claims (17)

A method for evaluating a semiconductor device for evaluating manufacturing variation from a design value of a wiring structure in a semiconductor device,
(A) creating an approximate expression representing the wiring resistance and the wiring capacitance related to the wiring structure as a function of a parameter indicating the manufacturing variation;
(B) measuring the distribution of the wiring resistance and the wiring capacitance related to the wiring structure;
(C) determining the parameters so that the distribution is reproduced with a predetermined probability in the approximate expression. A method for evaluating a semiconductor device. A method for evaluating a semiconductor device according to claim 1, comprising:
The wiring structure includes a wiring film thickness T, a wiring width W, and an interlayer film thickness H,
The variation ΔT of the wiring film thickness T from the design value T0 exists in a range of −σ _T to + σ _{T with} the predetermined probability,
The variation ΔW of the wiring width W from the design value W0 exists in the range of −σ _W to + σ _{W with} the predetermined probability,
The variation ΔH of the interlayer film thickness H from the design value H0 exists in the range of −σ _H to + σ _{H with} the predetermined probability,
The wiring resistance and the wiring capacitance fluctuate according to the fluctuation amounts ΔT, ΔW, ΔH,
The parameter indicating the manufacturing variation is the σ _T , σ _W , or σ _{H. The} semiconductor device evaluation method. A method for evaluating a semiconductor device according to claim 2, comprising:
The fluctuation amounts ΔT, ΔW, and ΔH satisfy the relationship expressed by points on an equiprobability curved surface of a joint probability density function (JPDF).
In the step (a), the approximate expression is created as a function of the parameters σ _T , σ _W , and σ _H. A method for evaluating a semiconductor device according to claim 2, comprising:
When the origin is the design values T0, W0, H0, and a space in which the three axes represent the wiring film thickness T, the wiring width W, and the interlayer film thickness H is considered,
The fluctuation amounts ΔT, ΔW, ΔH are displayed in polar coordinates,
ΔT = σ _T × cosφ × cosθ
ΔW = σ _W × cosφ × sinθ
ΔH = σ _H × sinφ
Satisfy the relationship
In the step (a), the approximate expression is created as a function of the parameters σ _T , σ _W , and σ _H. A method for evaluating a semiconductor device according to claim 3, wherein:
The step (a) includes:
(A1) creating a second or higher order polynomial expressing the wiring resistance and the wiring capacitance as a function of the fluctuation amounts ΔT, ΔW, ΔH;
(A2) converting the second or higher order polynomial into a first order polynomial by approximation calculation;
(A3) A method for evaluating a semiconductor device, comprising: creating the approximate expression based on the first-order polynomial and the relationship satisfied by the variation amounts ΔT, ΔW, and ΔH. A method for evaluating a semiconductor device according to claim 5, comprising:
The step (c) includes:
(C1) extracting two sets of the wiring resistance and the wiring capacitance from the distribution;
(C2) A step of determining the parameters in the approximate expression so that the two sets are reproduced. A method for evaluating a semiconductor device. A method for evaluating a semiconductor device according to claim 6, comprising:
One of the two sets is a set of the wiring resistance and the wiring capacitance when the wiring resistance is maximized,
The other of the two sets is a set of the wiring resistance and the wiring capacitance when the wiring resistance is a design value and the wiring capacitance is maximized. A method for evaluating a semiconductor device according to claim 6, wherein:
The step (c) further includes the step (c3) of obtaining an approximate distribution of the wiring resistance and the wiring capacitance with respect to the wiring structure using the approximate expression and the parameter determined in the step (c2). A method for evaluating a semiconductor device. A method for evaluating a semiconductor device according to claim 8, comprising:
The step (c) further includes a step (c4) of superimposing the distribution obtained in the step (b) and the distribution obtained in the step (c3) and displaying them on a display. . A method for evaluating a semiconductor device according to claim 8 or 9, wherein
The step (c) further includes a step (c5) of adjusting the parameter determined in the step (c2) when the probability of the distribution included in the approximate distribution is smaller than the predetermined probability. Device evaluation method. A method for evaluating a semiconductor device according to claim 1,
(D) A semiconductor device evaluation method further comprising a step of performing a statistical static timing analysis (SSTA) using the parameter indicating the manufacturing variation determined in the step (c). A method for evaluating a semiconductor device according to claim 1,
(E) A method for evaluating a semiconductor device, further comprising the step of creating an expression indicating the wiring resistance and the wiring capacitance related to the wiring structure, using the parameter indicating the manufacturing variation determined in the step (c). A method for evaluating a semiconductor device according to claim 12, comprising:
(F) analyzing a delay in a wiring included in the wiring structure by a circuit simulation using the formula created in the step (e);
(G) calculating a delay variation parameter indicating the variation range of the delay based on the result of the delay analysis; and a method for evaluating a semiconductor device. A method for evaluating a semiconductor device according to claim 13, comprising:
(A) determining a layout of the design circuit based on a netlist of the design circuit;
(B) performing an LPE (Layout Parameter Extraction) process based on the layout and extracting a wiring resistance and a wiring capacitance related to the wiring in the layout;
(C) using the net list and the extracted wiring resistance and wiring capacitance, and further performing a delay verification of the design circuit,
In the step (C), the delay verification is performed by referring to the delay variation parameter. Semiconductor device evaluation method. A method for evaluating a semiconductor device according to claim 12, comprising:
(F) analyzing a delay in a wiring included in the wiring structure by a circuit simulation using the formula created in the step (e);
(H) A method of evaluating a semiconductor device, further comprising: calculating a corner RC that is the wiring resistance and the wiring capacitance when the delay is maximum and minimum. A method for evaluating a semiconductor device according to claim 15, comprising:
(A) determining a layout of the design circuit based on a netlist of the design circuit;
(B) performing an LPE (Layout Parameter Extraction) process based on the layout and extracting a wiring resistance and a wiring capacitance relating to the wiring in the layout;
(C) using the net list and the extracted wiring resistance and wiring capacitance, further comprising performing a delay verification of the design circuit,
In the step (B), the LPE process is performed by referring to the corner RC. Semiconductor device evaluation method. A semiconductor device evaluation system for evaluating manufacturing variation from a design value of a wiring structure in a semiconductor device,
A processor;
A storage device for storing measured RC data indicating distribution of measured values of wiring resistance and wiring capacitance related to the wiring structure;
The processor creates an approximate expression that represents the wiring resistance and the wiring capacitance related to the wiring structure as a function of a parameter indicating the manufacturing variation, and the distribution indicated by the measured RC data in the approximate expression is a predetermined value. A semiconductor device evaluation system that determines the parameters so that the parameters are reproduced with probability.

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