JP2008218453A - Solid-state imaging apparatus and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of obtaining a stable dynamic range where positional deviation hardly occurs by restricting the times of exposure at only once, and to provide a manufacturing method thereof. <P>SOLUTION: In the solid-state imaging apparatus, an n-well 13 having the same depth over the entire pixel is formed on the surface of an epitaxial layer 12 and a p<SP>-</SP>region 16 is formed in the n-well 13. Separation regions 17, 18, 19 each having the density higher than that of the p<SP>-</SP>region 16 are formed by photolithography separately from one another in a horizontal direction so as to overlap the buried p<SP>-</SP>region 16. The one-time photolithography defines the relationship between a photoelectric conversion region (buried p<SP>-</SP>region 16) and a ring transistor portion. A source neighborhood region 47, an n<SP>-</SP>type barrier region 20 and a p<SP>+</SP>region 21 are formed so as to overlap the p<SP>-</SP>region 16 in the ring transistor portion of an amplifier element. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof, and more particularly, a solid-state imaging device in which a plurality of pixels each including a photoelectric conversion region and an amplification element that amplifies and outputs an optical signal obtained in the photoelectric conversion region are arranged regularly. And its manufacturing method.

  Conventionally, a plurality of pixels composed of a photoelectric conversion region that photoelectrically converts incident light from a subject and an amplification element that amplifies and outputs an optical signal (optical carrier signal) obtained in the photoelectric conversion region are regularly arranged. An amplification type solid-state imaging device has been proposed (see, for example, Patent Document 1). In this solid-state imaging device, a p-type region is formed in the entire surface of a pixel in an n-well of a substrate, a ring-shaped gate electrode is formed thereon, a source and a drain are formed by self-alignment with the gate electrode, and a ring transistor Is forming. Further, a channel stopper layer is formed by self-alignment.

  This channel stopper layer has a separation effect between pixels, and when incident light is very strong, the signal charge generated excessively overflows from the pixel and mixes into adjacent pixels and signal lines, etc. Prevent blooming. Light entering the p-type region through the gate electrode of the ring transistor undergoes photoelectric conversion, accumulates in the p-type region, and the ring transistor outputs a signal corresponding to the amount of accumulation. However, in the solid-state imaging device described in Patent Document 1, since light enters through the gate electrode of the ring transistor, there is a problem that the light is absorbed by the gate electrode and sensitivity is lowered. For this reason, the present inventors have invented and disclosed a solid-state imaging device having a structure in which a photoelectric conversion unit and a transistor are separated (see, for example, Patent Document 2).

FIG. 5 shows an element structure diagram of one pixel of the conventional solid-state imaging device described in Patent Document 2, wherein FIG. 5A is a top view and FIG. 5B is an XX of FIG. 'Shows a longitudinal section along the line. As shown in FIGS. 5A and 5B, in the solid-state imaging device, a p ⁻ type epitaxial layer 42 is grown on a p ⁺ type substrate 41, and an n well 43 is provided on the surface of the epitaxial layer 42. On the n-well 43, a gate electrode 45 having a ring shape as a first gate electrode is formed with a gate oxide film 44 interposed therebetween.

An n ⁺ -type source region 46 is formed on the surface of the n-well 43 corresponding to the center portion of the ring-shaped gate electrode 45, a source vicinity p-type region 47 is formed adjacent to the source region 46, and An n ⁺ -type drain region 48 is formed at a position apart from the source region 46 and the p-type region 47 near the source. Further, a buried p ⁻ -type region 49 is present in the n-well 43 below the drain region 48. The buried p ⁻ -type region 49 and the n-well 43 constitute the buried photodiode 50 shown in FIG.

  Between the embedded photodiode 50 and the ring-shaped gate electrode 45, there is a transfer gate electrode 51 which is a second gate electrode. The drain region 48, the ring-shaped gate electrode 45, the source region 46, and the transfer gate electrode 51 include a drain electrode wiring 52, a ring-shaped gate electrode wiring 53, a source electrode wiring (output line) 54, and a transfer gate electrode, which are metal wirings, respectively. A wiring 55 is connected. Further, as shown in FIG. 5B, a light shielding film 56 is formed above each of the above components, and an opening 57 is formed at a position corresponding to the embedded photodiode 50 in the light shielding film 56. Has been. The light shielding film 56 is formed of a metal or an organic film. The light reaches the embedded photodiode 50 through the opening 57 and is photoelectrically converted.

  Next, the pixel structure of the global CMOS sensor 112 and the structure of the entire imaging device will be described with reference to FIG. In the figure, first, pixels are arranged in a pixel spread area 61 in m rows and n columns. In FIG. 6, one pixel 62 of s rows and t columns among these m rows and n columns pixels is represented by an equivalent circuit. The pixel 62 includes a ring-shaped gate MOSFET 63, a photodiode 64, and a transfer gate MOSFET 65. The drain of the ring-shaped gate MOSFET 63 is the n-side terminal of the photodiode 64 and the drain electrode wiring 66 (corresponding to 52 in FIG. 5). , The source of the transfer gate MOSFET 65 is connected to the p-side terminal of the photodiode 64, and the drain is connected to the back gate of the ring-shaped gate MOSFET 63.

In FIG. 5B, the ring-shaped gate MOSFET 63 has a p-type region 47 near the source directly below the ring-shaped gate electrode 45 as a gate region, and an n ⁺ -type source region 46 and an n ⁺ -type drain region 48. An n-channel MOSFET. In FIG. 5B, the transfer gate MOSFET 65 has an n well 43 just below the transfer gate electrode 51 as a gate region, a p ⁻ type region 49 embedded with a photodiode 50 as a source region, and a p-type region 47 near the source. A p-channel MOSFET serving as a drain.

  In FIG. 6, in order to read a signal for one frame from each pixel of m rows and n columns, there is a circuit 67 for generating a frame start signal for giving a signal to start reading. The frame start signal may be given from outside the image sensor. This frame start signal is supplied to the vertical shift register 68. The vertical shift register 68 outputs a signal indicating which row of pixels is read out from each pixel of m rows and n columns.

  The pixels in each row are connected to a control circuit that controls the potentials of the ring-shaped gate electrode, transfer gate electrode, and drain electrode, and these control circuits are supplied with the output signal of the vertical register 68. For example, the ring-shaped gate electrode of each pixel in the s-th row is connected to the ring-shaped gate potential control circuit 70 via a ring-shaped gate electrode wiring 69 (corresponding to 53 in FIG. 5), and the transfer gate electrode of each pixel is Are connected to the transfer gate potential control circuit 72 via the transfer gate electrode wiring 71 (corresponding to 55 in FIG. 5), and the drain electrode of each pixel is drained via the drain electrode wiring 66 (corresponding to 52 in FIG. 5). It is connected to the potential control circuit 73. Each control circuit 70, 72, 73 is supplied with an output signal from the vertical shift register 68.

  The source electrode of the ring-shaped gate MOSFET 63 of the pixel 62 is branched into two via a source electrode wiring 74 (corresponding to 54 in FIG. 5), one of which is supplied to a source potential control circuit 75 that controls the source electrode potential via a switch SW1. The other is connected to the signal readout circuit 76 via the switch SW2. When reading the signal, the switch SW1 is turned off and the switch SW2 is turned on. When the source potential is controlled, the switch SW1 is turned on and the switch SW2 is turned off. Since the signal is output in the vertical direction, the wiring direction of the source electrode is set to be vertical.

  The signal readout circuit 76 is configured as follows. The output of the pixel 62 is performed from the source of the ring-shaped gate MOSFET 63, and a load, for example, a current source 77 is connected to the output line 74. Therefore, it is a source follower circuit. One end of each of the capacitor C1 and the capacitor C2 is connected to the current source 77 via the switch sc1 and the switch sc2. One end of each of the capacitors C1 and C2 whose other ends are grounded is connected to the inverting input terminal and the non-inverting input terminal of the differential amplifier 78, and the potential difference between the capacitors C1 and C2 is output from the differential amplifier 78. It is like that.

  Such a signal readout circuit 76 is called a CDS circuit (correlated double sampling circuit), and various circuits other than the method described here have been proposed, and the circuit is not limited to this circuit. The signal output from the signal readout circuit 76 is output via the output switch swt. The output switches swt in the same column are subjected to switching control by a signal output from the horizontal shift register 79.

Next, a driving method of the global CMOS sensor 112 shown in FIG. 6 will be described with reference to the timing chart of FIG. First, in the period shown in FIG. 7A, light is incident on the embedded photodiode (50 in FIG. 5A, 64 in FIG. 6 and the like), and an electron / hole pair is generated by the photoelectric conversion effect. Holes are accumulated in the buried p ⁻ -type region 49 of the diode. At this time, the potential of the transfer gate electrode 51 is the same as the drain potential Vdd, and the transfer gate MOSFET 65 is off. These accumulations are performed at the same time as the previous frame read operation is being performed.

In the subsequent period shown in FIG. 7 (2), when the reading of the previous frame is completed, a new frame start signal is transmitted as shown in FIG.
First, all the pixels are performed simultaneously from the photodiode (50 in FIG. 5A, 64 in FIG. 6) to the p-type region (47 in FIG. 5) near the source of the ring-shaped gate electrode (45 in FIG. 5). It is to transfer the hole. Therefore, as shown in FIG. 7B, the transfer gate control signal output from the transfer gate potential control circuit 72 falls from Vdd to Low2, the potential of the transfer gate electrode (41 in FIG. 5) becomes Low2, and the transfer gate MOSFET 65 Turns on.

  At this time, the potential of the ring-shaped gate electrode wiring 69 controlled by the ring-shaped gate potential control circuit 70 changes from Low to Low1 as shown in FIG. 7C, but Low2 is larger than Low1. Low1 may be the same as Low. Most simply, Low1 = Low = 0 (V) is set.

  On the other hand, the source potential of all the pixels including the source potential supplied from the source potential control circuit 75 to the source of the ring-shaped gate MOSFET 63 from the source electrode wiring 74 through the switch SW1 is as shown in FIG. The potential is set to S1. S1> Low1, which keeps the ring-shaped gate MOSFET 63 off and prevents current from flowing. As a result, charges (holes) accumulated in the photodiodes of all the pixels are transferred all at once under the ring-shaped gate electrodes of the corresponding pixels.

  In the region below the ring-shaped gate electrode 45 shown in FIG. 5 (B), the p-type region 47 near the source has the lowest potential, so the holes accumulated in the photodiode reach the p-type region 47 near the source. Accumulated in. As a result of the accumulation of holes, the potential of the p-type region 47 near the source rises.

Subsequently, in the period shown in FIG. 7 (3), as shown in FIG. 7 (B), the transfer gate electrode becomes Vdd again, and the transfer gate MOSFET 65 is turned off. As a result, in the photodiode (50 in FIG. 5A, 64 in FIG. 6 and the like), electron-hole pairs are generated again due to the photoelectric conversion effect, and holes start to be accumulated in the buried p ⁻ -type region 49 of the photodiode. This accumulation operation is continued until the next charge transfer.

  On the other hand, since the reading operation is sequentially performed in units of rows, the potential of the ring-shaped gate electrode is low as shown in FIG. 7C in the period (3) in which the first to (s−1) th rows are read. In this state, a standby state is entered with holes accumulated in the p-type region 47 near the source. The source potential can take various values depending on the value of the signal from the pixel while the signal is read from another row. The ring-shaped gate electrode potential can take various values for each row, but is set to Low in the s-th row, and the ring-shaped gate MOSFET 63 is in an off state.

  In the subsequent period shown in FIGS. 7 (4) to (6), pixel signal readout is performed. This signal readout operation will be described representatively for the pixel 62 in the s-th row and the t-th column. First, in the state where holes are accumulated in the p-type region 47 near the source, the vertical shift register 68 shown in FIG. In the period (4) in which the output signal is at a low level as shown in FIG. 5H, the ring-shaped gate electrode 45 is controlled by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. Is increased from Low to Vg1, as shown in FIG.

Here, the potential Vg1 is between the potentials Low, Low1, and Vdd described above.
Low ≦ Low1 ≦ Vg1 ≦ Vdd (where Low <Vdd)
Is an electric potential that holds the inequality. In the period (4), the switch SW1 is turned off as shown in FIG. 7I, the switch SW2 is turned on as shown in FIG. 7J, and the switch sc1 is turned on as shown in FIG. The switch sc2 is turned off as shown in FIG.

  As a result, the source follower circuit connected to the source of the ring-shaped gate MOSFET 63 works, and the source potential of the ring-shaped gate MOSFET 63 becomes S2 (= Vg1-Vth1) in the period (4) as shown in FIG. Become. Here, Vth1 is a threshold voltage of the ring-shaped gate MOSFET 63 in a state in which there is a hole in the back gate (p-type region 47 near the source). The source potential S2 is stored in the capacitor C1 through the switch sc1 that is turned on.

  In the subsequent period shown in FIG. 7 (5), the potential of the ring-shaped gate electrode 45 is set as shown in FIG. 7 (K) by the control signal output from the ring-shaped gate potential control circuit 70 to the ring-shaped gate electrode wiring 69. At the same time as raising to High1, the switch SW1 is turned on and the switch SW2 is turned off as shown in FIGS. 1I and 1J, and the source potential output from the source potential control circuit 75 is shown in FIG. Raise to Highs as shown. Here, High1 and Highs> Low1.

  The values of the potentials High1 and Highs may be the same or different, but High1 and Highs ≦ Vdd are desirable for simplicity of design. In a simple setting, High1 = Highs = Vdd. Further, it is desirable to set the potential so that the ring-shaped gate MOSFET 63 is turned on and no current flows. As a result, the potential of the p-type region 47 near the source rises, and holes are discharged to the epitaxial layer 42 beyond the barrier of the n-well 43 (reset).

In the subsequent period shown in FIG. 7 (6), the same signal readout state as in the period (4) is set again.
However, unlike the period (4), as shown in FIGS. 7M and 7N, the switch sc1 is turned off and the switch sc2 is turned on. The ring-shaped gate electrode has the same Vg1 as that in the period (4) as shown in FIG. However, in this period (6), holes are discharged to the substrate in the immediately preceding period (5), and no holes exist in the p-type region 47 near the source, so the source potential of the ring-shaped gate MOSFET 63 is as shown in FIG. L), the period (6) is S0 (= Vg1-Vth0). Here, Vth0 is the threshold voltage of the ring-shaped gate MOSFET 63 in a state where there is no hole in the back gate (p-type region 47 near the source).

  The source potential S0 is stored in the capacitor C2 through the switch sc2 that is turned on. The differential amplifier 78 outputs the potential difference between the capacitors C1 and C2. That is, the differential amplifier 78 outputs (Vth0−Vth1). This output value (Vth0-Vth1) is a change in threshold value due to hole charge. Thereafter, among the pulses shown in FIG. 7F output from the horizontal shift register 79, the output switch swt shown in FIG. 6 is turned on based on the output pulse in the t-th column shown in FIG. In the ON period, as schematically shown by hatching in FIG. 7P, the threshold value change due to the Hall charge from the differential amplifier 78 is output to the outside of the sensor as the output signal Vout of the pixel 62.

  Subsequently, in the period indicated by (7) in FIG. 7, the potential of the ring-shaped gate electrode 45 is set to low again as shown in FIG. 7B, and all of the p-type region 47 near the source has no holes. It waits until the signal processing of the next row is completed (until the readout of pixels of the s + 1 row to the nth row is completed). During these readout periods, the photodiode 64 is accumulating holes due to the photoelectric conversion effect. Thereafter, the process returns to the period (1) and repeats from the hole transfer. As a result, the output signal shown in FIG. 7G is read from each pixel. When signals are read from all pixels, the next frame is started again.

  5A and 5B, the ring-shaped gate MOSFET 63 having the ring-shaped gate electrode 45 is an amplification MOSFET, and as shown in FIG. It is a kind of CMOS sensor in the sense that it has an amplifying MOSFET. In this CMOS sensor, the charge (hole) accumulated in the photodiode is transferred to the p-type region 47 in the vicinity of the source under the ring-shaped gate electrode of the corresponding pixel at the same time. Is realized.

  Note that there is a method other than the supply of the potential of the source electrode wiring 74 at the time of reset in the period (5) of FIG. In the period (5), both SW1 and SW2 are turned off to make the source electrode wiring floating. Here, when the potential of the ring-shaped gate electrode wiring 69 is High1, the ring-shaped gate MOSFET 63 is turned on, current is supplied from the drain to the source potential, and the source electrode potential rises. As a result, the potential of the p-type region 47 in the vicinity of the source is raised, and holes are discharged to the p-type epitaxial layer 42 beyond the barrier of the n-well 43 (reset). The source electrode potential when the holes are completely discharged can be High1-Vth0, and the chip area can be reduced.

Next, a method for manufacturing this conventional solid-state imaging device will be described together with the element cross-sectional views of FIGS. First, as shown in FIG. 8A, an oxide film 81 is formed on a wafer in which a p ⁻ epitaxial layer 42 is stacked on a p ⁺ type substrate 41. The oxide film 81 functions as a sacrificial oxide film. Subsequently, as shown in FIG. 8B, the wafer is divided into a sensor region 82 that senses light and converts it into an electrical optical signal, and an amplifying element region 83 in which the transistor operates. An n-well 43 is formed by selectively ion-implanting impurities such as phosphorus by a known method using photolithography. At this time, the implantation energy of the n-well 43 is increased so that the sensor region 82 is deeper than the amplifying element region 83. For example, the amplifying element region 83 is ion-implanted at 300 to 600 keV and the sensor region 82 is 600 keV to ² MeV and 1E11 cm ^{−2 to} 1E12 cm ⁻² .

Subsequently, as shown in FIG. 9A, the p ⁻ implantation region 84 and the ring transistor portion implantation region 85 are selected by photolithography, and ion implantation is performed. In the p ⁻ implantation region 84, a p ⁻ region 49 to be a photoelectric conversion region is formed in the n well 43 by ion implantation. For example, a dose of about 3E11cm ^-2 ~1E12cm ^-2 in 70~400keV boron as p-type impurity ion implantation, the concentration is ion-implanted to be higher than n-well 43. On the other hand, the ring transistor unit implanted region 85, boron ions are implanted at a dose of about 1E12cm ^-2 ~5E12cm ^-2 in 25~120keV as p-type impurity is ion-implanted, a source neighboring p-type region 47 n-well 43 The p ⁺ -type region 86 is formed by implanting boron into the back of the n-well 43 at a dose of about 5E12 to 1E14 cm ⁻² at 300 keV to 500 keV.

  Subsequently, as shown in FIG. 9B, after removing the oxide film 81 in FIG. 9A, a gate oxide film 44 is formed by a known oxide film forming method, and a polysilicon film is formed thereon. Then, a ring-shaped gate electrode 45 is formed by etching a predetermined region. After further oxidation, a second polysilicon film is formed, and a predetermined region is etched to form a transfer gate electrode 51.

Subsequently, as shown in FIG. 10A, diffusion layers to be n ⁺ -type drains 48 and sources 46 are formed by ion implantation by self-alignment using ring-shaped gate electrode 45 and transfer gate electrode 51 as a mask. To do. Thereafter, as shown in FIG. 10B, after the drain electrode wiring 52, the ring-shaped gate electrode wiring 53, the source electrode wiring (output line) 54, and the transfer gate electrode wiring 55 are formed by a known wiring layer forming method. The entire surface of the element is covered with an insulating film 87, and a light shielding film 56 is formed thereon. In the light shielding film 56, an opening 57 is formed at a position corresponding to the upper side of the p ⁻ type buried region 49.

JP-A-9-191098 JP 2006-1000076 A1

However, the structure of the conventional solid-state imaging device shown in FIG. 5 and the manufacturing method described with FIGS. 6 to 10 have the following problems. First, the buried p ⁻ region 49 serving as a photoelectric conversion region is formed by further performing p ⁻ implantation by photolithography in an n well 43 formed selectively deep by photolithography. When the photolithography process is performed twice in this way, a positional shift occurs due to process variations. At this time, if the pixel is large, the problem is unlikely to occur. However, as the pixel is miniaturized, this positional deviation becomes a problem.

Specifically, when the implantation of p ⁻ is shifted to the amplification transistor side (that is, the ring transistor side having the ring-shaped gate electrode 45), the n well 43 between the p ⁻ region 49 and the p ⁻ epitaxial layer 42 If the width becomes narrower than the width of the depletion layer, holes in the buried p ⁻ region 49 leak to the substrate (p ⁻ epitaxial layer 42). As a result, the optical signal obtained by photoelectric conversion in the buried p ⁻ region 49 constituting the photodiode is transferred, and the accumulation amount in the p-type region 47 near the source that accumulates the optical signal is a predetermined carrier accumulation. A problem arises in that the signal level of the optical signal is reduced and the dynamic range is lowered.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a solid-state imaging device capable of obtaining a stable dynamic range in which positional deviation is unlikely to occur and a manufacturing method thereof.

  In order to achieve the above object, a solid-state imaging device of the present invention includes a photoelectric conversion region that photoelectrically converts incident light from a subject, and an amplification element that amplifies and outputs an optical signal obtained by the photoelectric conversion region. In a solid-state imaging device in which a plurality of pixels are regularly arranged, a first conductivity type well formed at the same depth on the entire surface of the pixel on a substrate and a second conductivity type well formed in the well An impurity layer, and a plurality of first conductivity type isolation regions formed in the depth direction so as to overlap with the well and the impurity layer and spaced apart from each other in a direction orthogonal to the depth direction. And the positional relationship between the photoelectric conversion region formed by the impurity layer and the region for the amplifier element formed based on the impurity layer is defined by the plurality of separation regions.

  In order to achieve the above object, the method for manufacturing a solid-state imaging device according to the present invention amplifies and outputs a photoelectric conversion region for photoelectrically converting incident light from a subject, and an optical signal obtained by the photoelectric conversion region. In a method of manufacturing a solid-state imaging device in which a plurality of pixels each including an amplification element are regularly arranged, a first step of forming a first conductivity type well at the same depth on the entire surface of the pixel on the substrate; A first conductivity type impurity is selectively implanted by photolithography into a region excluding the photoelectric conversion region and the amplification element region, and a second step of forming a second conductivity type impurity layer therein. And a third step of forming a plurality of isolation regions overlapping the well and the impurity layer in the depth direction and spaced apart from each other in a direction perpendicular to the depth direction.

  In the solid-state imaging device and the manufacturing method thereof according to the present invention, the solid-state imaging device includes a first conductivity type well formed in the same depth on the entire surface of the pixel and a second conductivity type formed in the well. A plurality of isolation regions formed in the depth direction so as to overlap each of the impurity layers and spaced apart from each other in a direction orthogonal to the depth direction, and the photoelectric conversion region by the impurity layer and the above-described Since the positional relationship with the region for the amplifying element formed based on the impurity layer is defined, only the isolation region can be formed by implantation after exposure by photolithography, and the number of exposures is one. The position of the mask used for photolithography does not shift, and the depth of the impurity layer does not change even if the isolation region shifts to the region for the amplifying element.

  According to the present invention, only the separation region can be formed by implantation after exposure by photolithography, the number of exposures is one, and there is no displacement of the mask used for photolithography, and the separation region is amplified. Since the depth of the impurity layer does not change even if it is shifted to the element region side, it is possible to obtain a solid-state imaging device capable of obtaining a stable dynamic range free from a positional shift problem.

Next, an embodiment of the present invention will be described with reference to the drawings. In the conventional method for manufacturing a solid-state imaging device, the photoelectric conversion region is formed by performing photolithography (ion implantation) twice or more on the n-well and the p ⁻ region. Therefore, in the present invention, the two-time ion implantation is stopped, and the photoelectric conversion region is formed by the ion implantation performed on the entire surface of the pixel and the one-time ion implantation that forms the separation region, thereby eliminating the problem of positional deviation and stable. A dynamic range.

1A and 1B are element structural diagrams for one pixel of an embodiment of a solid-state imaging device according to the present invention, where FIG. 1A is a top view and FIG. 1B is an XX in FIG. 'Shows a longitudinal section along the line. In FIG. 1, the same components as those in FIG. In the solid-state imaging device of the present embodiment shown in FIG. 1, a p ⁻ type epitaxial layer 12 is grown on a p ⁺ type substrate 11, and an n well 13 having the same depth over the entire pixel is formed on the surface of the epitaxial layer 12. At the same time, a p ⁻ region 16 is formed in the n well 13. Further, isolation regions (n-type) 17, 18, 19 having a higher concentration than the p ⁻ region 16 are formed so as to overlap with the embedded p ⁻ region 16 and spaced apart from each other in the horizontal direction. The ring transistor portion of the amplifying element has no isolation region, and instead overlaps with the p ⁻ region 16 at a higher concentration than the buried p ⁻ region 16, so as to overlap the source vicinity region 47, the n ⁻ type barrier region 20, and the p ⁺ region. 21 is formed.

This is possible because the buried p ⁻ region 16 has a smaller amount of p ⁻ implantation than other portions, and other portions can be formed simply by overlapping implantation into the p ⁻ region 16.

Next, a method for manufacturing the solid-state imaging device according to the present embodiment will be described with reference to the element cross-sectional views of FIGS. First, as shown in FIG. 2A, an oxide film 14 is formed by a known method on a wafer on which a p ⁻ epitaxial layer 12 is grown on a p ⁺ type substrate 11. The oxide film 14 functions as a sacrificial oxide film. Through this oxide film 14, an n-type impurity such as phosphorus is applied to the entire surface of the pixel portion by a known method using photolithography. Through the oxide film 14, for example, in the range of about 300 keV to 1.5 MeV, 1E11 cm ^{−2 to} 1E12 cm ^−2. The n-well 13 is formed by implanting ions in the p ⁻ epitaxial layer a plurality of times within the range of the above-mentioned range while changing the implantation energy. As a result, an n-well 13 having the same depth in the pixel portion is formed on the p ⁻ epitaxial layer 12 as shown in FIG.

Subsequently, for the element shown in FIG. 2A, for example, boron as a p-type impurity is ion-implanted through the oxide film 14 with an acceleration energy of 70 to 400 keV and a dose of about 3E11 cm ^{−2 to} 1E12 cm ^−2. Perform on the entire surface. At this time, ion implantation is performed so that the impurity concentration is higher than that of the n-well 13. As a result, as shown in FIG. 2B, the n-well 13 has a structure in which the p ⁻ region 16 having a predetermined depth is formed on the n ⁻ portion 15.

2B, a photoresist is applied to the upper surface of the element, and then a portion of the photoresist corresponding to the separation implantation region is opened with a region other than the photoelectric conversion region and the ring transistor portion as a separation implantation region. Then, after ion-implanting n-type impurities through the opening, the photoresist is removed, so that the n-type isolation regions 17, 18, 19 is formed. At this time, p ^- so that the impurity concentration of the isolation region 17, 18, 19 than the region 16 darker, as n-type impurity such as phosphorus acceleration energy 50～2MeV, a dose of 1E12cm ^-2 ~1E13cm ^-2 Ion implantation. The positional relationship between the photoelectric conversion region and the ring transistor portion is defined by one photolithography.

Subsequently, the region (region between the isolation regions 18 and 19) to be the ring transistor portion in FIG. 3A is selected by photolithography, and the selected p ⁻ region 16 and n ^{− in} FIG. Ions are implanted so as to overlap with the region of the portion 15 to form the source vicinity p-type region 47, the n ⁻ barrier portion 20, and the p ⁺ region 21, as shown in FIG. For example, the p-type region 47 near the source has impurity boron, acceleration energy of 15 to 100 KeV, and a dose amount of 2E12 to 1E13 cm ⁻² , and the n ⁻ barrier portion 20 has impurity phosphorus, acceleration energy of 150 to 600 KeV, and dose. The amount is 2E12 to 5E12 cm ⁻² , and the p ⁺ region 21 is impurity boron, acceleration energy is 300 to 1 MeV, and dose is about 3E12 to 5E13 cm ⁻² .

  Subsequently, after removing the oxide film 14 in FIG. 3B, a gate oxide film 44 is formed on the upper surface of the element by a known oxide film formation method as shown in FIG. 4A, and polysilicon is formed thereon. A ring-shaped gate electrode 45 is formed by forming a film and etching a predetermined region. After further oxidation, a second polysilicon film is formed, and a predetermined region is etched to form a transfer gate electrode 51.

Thereafter, each of the diffusion layers to be the n ⁺ -type drain 48 and source 46 is formed by ion implantation by self-alignment using the ring-shaped gate electrode 45 and the transfer gate electrode 51 as a mask. Thereafter, as shown in FIG. 4B, after the drain electrode wiring 52, the ring-shaped gate electrode wiring 53, the source electrode wiring (output line) 54, and the transfer gate electrode wiring 55 are formed by a known wiring layer forming method. The entire surface of the element is covered with an insulating film 23, and a light shielding film 56 is formed thereon. The light shielding film 56 has an opening 57 at a position corresponding to the upper side of the p ⁻ type buried region 16. The p ⁻ type buried region 16 corresponds to the p ⁻ type buried region 49 in FIG. 5 and constitutes a part of the photoelectric conversion region.

Conventionally, when ion implantation is performed by performing exposure in the photolithography process twice in the separation region and the photoelectric conversion region, positional deviation occurs due to process variations. In contrast, according to this embodiment, as described above, the photoelectric conversion region p ^- type of the embedding region (p ^- region) 16 on the entire surface injection and entirely injected into the pixel portion p ^- region 16, Since only the separation regions 17, 18, 19 are overlapped and selectively injected into the n ⁻ portion 15 after exposure, the number of exposures is one, and even if the separation regions 17, 18, 19 are shifted to the ring transistor side, n It is possible to obtain a solid-state imaging device in which the well width is not narrowed and a stable dynamic range without a problem of positional deviation can be obtained.

The difference between the structure of the conventional solid-state imaging device shown in FIG. 5 and the structure of the present embodiment shown in FIG. 1 can be confirmed by secondary ion mass spectrometry (SIMS). In this embodiment, since the isolation regions 17 to 19 are implanted in the p ⁻ region 16 so as to overlap, when the impurity profile of the isolation regions 17 to 19 is obtained by SIMS analysis, the p ⁻ region 16 is formed. Impurities are detected from the isolation regions 17-19. However, in the conventional element structure, even if the n well region 43 other than the buried p ⁻ region 49 is subjected to SIMS analysis, p ⁻ type impurities cannot be detected. Conventionally, photolithography is performed twice to form the photoelectric conversion region. However, in the present embodiment, only one photolithography is required, so that it is possible to save a photolithography mask.

It is an element structure figure for 1 pixel of one embodiment of the solid-state imaging device of the present invention. It is element sectional drawing (the 1) explaining the manufacturing method of one Embodiment of the solid-state imaging device of this invention. It is element sectional drawing (the 2) explaining the manufacturing method of one Embodiment of the solid-state imaging device of this invention. It is element sectional drawing (the 3) explaining the manufacturing method of one Embodiment of the solid-state imaging device of this invention. It is an element structure figure for 1 pixel of an example of the conventional solid-state imaging device. FIG. 6 is a diagram illustrating a pixel structure of the solid-state imaging device of FIG. 5 and an electrical equivalent circuit of the entire imaging device. 7 is a timing chart for explaining the operation of the electrical equivalent circuit shown in FIG. 6. FIG. 6 is an element cross-sectional view (part 1) for explaining a method of manufacturing the conventional solid-state imaging device of FIG. 5; FIG. 6 is an element cross-sectional view (No. 2) for explaining the method for manufacturing the conventional solid-state imaging device in FIG. 5; FIG. 7 is an element cross-sectional view (part 3) illustrating the method for manufacturing the conventional solid-state imaging device of FIG. 5;

Explanation of symbols

11 p ⁺ type substrate 12 p ⁻ type epitaxial layer 13 n well 15 n ⁻ part 16 p ⁻ type buried region (p ⁻ region)
17, 18, 19 Separation region 20 n ^- barrier portion 21 p ⁺ region 45 ring-shaped gate electrode 46 source region 47 near source p-type region 48 drain region 50 photodiode 51 transfer gate electrode

Claims (2)

In a solid-state imaging device in which a plurality of pixels including a photoelectric conversion region that photoelectrically converts incident light from a subject and an amplification element that amplifies and outputs an optical signal obtained by the photoelectric conversion region are arranged in a regular manner,
A first conductivity type well formed at the same depth on the entire surface of the pixel on the substrate, a second conductivity type impurity layer formed in the well, and the well and the impurity layer overlap each other. A plurality of isolation regions of the first conductivity type formed in the depth direction and spaced apart from each other in a direction orthogonal to the depth direction, and the impurity layer is formed by the plurality of isolation regions. A solid-state imaging device characterized in that a positional relationship between the photoelectric conversion region and the region for the amplification element formed based on the impurity layer is defined. Manufacture of a solid-state imaging device in which a plurality of pixels including a photoelectric conversion region that photoelectrically converts incident light from a subject and an amplification element that amplifies and outputs an optical signal obtained from the photoelectric conversion region are arranged regularly In the method
A first step of forming a well of the first conductivity type at the same depth on the entire surface of the pixel on the substrate;
A second step of forming a second conductivity type impurity layer in the well;
A first conductivity type impurity is selectively implanted by photolithography in a region excluding the photoelectric conversion region and the amplification element region, and overlaps the well and the impurity layer in the depth direction, and And a third step of forming a plurality of separation regions spaced apart from each other in a direction orthogonal to the depth direction.

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