JP2008217994A - Flat panel type image forming device, and spacer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flat panel type image forming device having a spacer, and the spacer which can simultaneously satisfy resistance temperature characteristics, voltage endurance, beam deflection suppressing effect. <P>SOLUTION: The image forming device includes a cathode substrate provided with an electron source, an anode substrate provided with a phosphor for emitting light when receiving electrons emitted from the electron source, and the spacer arranged between the cathode substrate and anode substrate for supporting both of the substrates. The spacer comprises a glass substrate, a first metallic oxide thin film directly formed on a side surface of the glass substrate and exhibiting semiconductor like electrical conductivity, a second metallic oxide thin film formed outside the first metallic oxide thin film and exhibiting metallic electrical conductivity, and a third metallic oxide thin film formed outside the second metallic oxide thin film and exhibiting semiconductor-like electrical conductivity. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a flat image forming apparatus and a spacer used therefor.

  In recent years, with the improvement in image quality of information processing devices or television broadcasting, it has high luminance and high definition characteristics, and can be reduced in weight and space, so that it can be used as a flat panel display (FPD). Interest is growing. Typical examples of the flat type image forming apparatus are a liquid crystal display device and a plasma display device, and a field emission display (hereinafter referred to as FED) which has been attracting attention recently.

  The FED is a self-luminous display device having an electron source in which electron emitters of cold cathode elements are arranged in a matrix. Known electron-emitting devices include surface conduction electron-emitting devices (SED type), field emission devices (FE type), metal / insulating film / metal-type emitting devices (MIM type), and the like. As the FE type, a Spindt type made of a metal such as molybdenum or a semiconductor material such as silicon, or a CNT type using a carbon nanotube as an electron source is known.

  In the FED, a space is provided between the cathode panel on the back side where the electron source is formed and the anode panel on the front side where a phosphor that emits light when excited by electrons emitted from the electron source is formed. It is necessary to keep the space in a vacuum atmosphere. In order to allow the space maintained in a vacuum to withstand atmospheric pressure, a support member called a spacer is usually disposed between the two panels.

  In the FED, a voltage is usually applied to the anode so that the potential difference between the electron source and the anode is about several to several tens of kV. The higher the applied voltage, the higher the luminance and the longer the life of the panel, but the more easily the spacer is charged. When the spacer is charged, a phenomenon occurs in which the electron beam flying from the cathode to the anode is attracted to the spacer side or repels away from the spacer. As a result, the brightness changes, and the shadow of the spacer is displayed on the screen, resulting in a problem that the image quality is deteriorated. In addition, discharge tends to occur, causing a problem that the cathode and other structural parts are destroyed.

One method for avoiding such a problem is to use an electron conductive glass material having a specific resistance of about 10 ⁷ Ωcm as the spacer material. VWPO glass is known as such an electron conductive glass (see Non-Patent Document 1). As another method, there is a method in which an insulating glass substrate is used as a spacer base material and a thin film for promoting electron conduction is formed thereon. As such a thin film, it is known to form an oxide cermet film containing a noble metal having a negative resistance temperature coefficient (see Patent Document 1). By using this oxide cermet film, it is possible to suppress so-called thermal runaway in which an excessive current flows because the resistance value continues to decrease due to a temperature rise due to power consumed on the spacer surface.

A. Mansingh, J. K. Valid, R. P. Tandon, `` DC conductivity of molybdenum phosphate glasses '', J. Phys. C, Solid State Phys., Vol 10, 4061-4066 (1977) Japanese Patent No. 3745078

  Non-Patent Document 1 describes the use of V—W—P—O-based electron conductive glass, but this electron conductive glass exhibits semiconducting properties, and electronic conduction is hopping conduction. As a result, the temperature coefficient of electrical resistance is extremely large. Moreover, as a semiconductor property, the higher the temperature, the more carriers and the lower the resistance. For this reason, thermal runaway tends to occur. In addition, because of the hopping conduction mechanism, there is a problem that the higher the temperature, the higher the energy of molecules that can be hopped, the higher the probability of hopping, the significant decrease in resistance with increasing temperature, and the positive and large resistance temperature coefficient.

  Patent Document 1 discloses that an oxide cermet film formed by dispersing a noble metal in an insulator matrix is formed on an insulator glass substrate. Since this oxide cermet film has a negative resistance temperature coefficient, thermal runaway can be suppressed. However, since a current flows only in the thin film due to a high voltage of about 10 kV applied to the anode substrate and the cathode substrate, there is a problem that abnormal discharge occurs in the spacer due to application of the high voltage, and the panel is easily broken. In addition, this oxide cermet film uses an insulator matrix, and the portion of the matrix is positively charged by electron irradiation, so that the electrons irradiated from the electron source near the spacer are attracted by the charged portion. Is likely to occur.

  As described above, it has been difficult to obtain a flat image forming apparatus having a spacer that simultaneously satisfies the resistance temperature characteristics, the withstand voltage, and the beam deflection preventing effect of the spacer.

  An object of the present invention is to provide a planar image forming apparatus and a spacer having a spacer that can simultaneously satisfy the resistance temperature characteristics, the withstand voltage, and the beam deflection suppressing effect.

  The present invention relates to a cathode substrate having an electron source, an anode substrate having a phosphor that emits light upon receiving electrons emitted from the electron source, and both the substrates disposed between the cathode substrate and the anode substrate. In the flat type image forming apparatus having a supporting spacer, the spacer is formed on the outside of the glass substrate, the first metal oxide thin film which is directly formed on the side surface and exhibits semiconducting electrical conductivity. A second metal oxide thin film exhibiting metallic electrical conductivity and a third metal oxide thin film exhibiting semiconducting electrical conductivity formed on the outside thereof. To do.

  The present invention is a spacer disposed between a back panel and a front panel of a flat-type image forming apparatus, and includes a glass substrate and a first metal having a semiconducting electrical conductivity directly formed on the side surface thereof. An oxide thin film, a second metal oxide thin film formed on the outer side and exhibiting metallic electrical conductivity, and a third metal oxide thin film formed on the outer side and exhibiting semiconductor electrical conductivity. It is comprised from these.

In the image forming apparatus of the present invention and the spacer used therefor, the second metal oxide thin film has a configuration in which particles exhibiting metal conductivity are dispersed in a metal oxide matrix. In the second metal oxide thin film, the particles exhibiting metal conductivity are preferably selected from Au, Pt, Ag, Cr and Cu, and the metal oxide matrix is SiO ₂ , Ga ₂ O ₃ , Cr ₂ O _3. Fe ₂ O ₃ , a composite oxide of Fe ₂ O ₃ and Ga ₂ O ₃ , an oxide selected from Al ₂ O ₃ and Ta ₂ O ₅ are preferable.

The first metal oxide and the third metal oxide may be the same oxide or different oxides. These oxides are preferably selected from Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , Fe ₂ O ₃ and Ga ₂ O ₃ composite oxides.

  The glass substrate of the spacer is preferably glass having electron conductivity.

  In the present invention, “showing metallic electrical conductivity” means that the electrical conduction mechanism is due to electronic conduction, and the resistance value tends to increase with increasing temperature. That is, in metal, electron conduction due to free electrons causes the lattice vibration of the crystal lattice to increase as the temperature rises, thereby inhibiting the electron conduction and lowering the mobility. Therefore, the electrical conductivity decreases with increasing temperature, and the resistance increases.

  Also, “showing semiconducting electrical conductivity” means that the concentration of electrons (carriers) excited from the valence band to the conduction band increases exponentially with increasing temperature and decreases with increasing temperature. Refers to resistance.

  According to the present invention, it has been possible to provide a flat-type image forming apparatus having a high-performance spacer that is excellent in withstand voltage characteristics and has a small amount of resistance change and temperature with respect to temperature.

  Hereinafter, although the case where the spacer of the present invention is applied to the MIM type FED will be described, the present invention is not limited to the MIM type.

  FIG. 1 shows a schematic diagram of a cross section of a spacer according to the present embodiment. In FIG. 1, 211 is an anode substrate, 212 is a black matrix, 114 and 115 are glass materials for spacer bonding, 110 is a spacer, 222 is a wiring electrode, 403 is an electrode thin film formed on the spacer end surface, and 221 is a cathode substrate. . The spacer 110 includes a glass substrate 401 and a metal oxide thin film 410. Although the metal oxide thin film 410 has a three-layer structure, each layer is omitted in FIG. The thickness of the metal oxide thin film 410 is preferably in the range of 20 to 100 nm. 2 shows a perspective view of the MIM type FED, and FIG. 3 shows a part of a cross section in the direction of the line AA of FIG.

  The front panel 210 has a black matrix 212 as a light shielding film and a phosphor layer 213 on the inner surface side of an anode substrate 211 as a base material of the panel. Further, the back panel 220 has a wiring electrode 222 and an electron source 223 that is an emitter on the inner surface side of a cathode substrate 221 that is a base material of the panel.

  A large number of spacers 110 are arranged between the black matrix 212 formed on the front panel 210 and the wiring electrodes 222 formed on the back panel 220. These spacers are bonded to the front panel via a spacer bonding glass material 114 and bonded to the rear panel via a spacer bonding glass material 115. As the spacer bonding glass materials 114 and 115, a conductive material is usually used because a minute current flows through the spacer.

A sealing frame 230 is provided on the inner peripheral edge of the anode substrate 211 and the cathode substrate 221, and this sealing frame is bonded to the anode substrate and the cathode substrate with an adhesive, whereby, between the back panel and the front panel. A space portion is formed, and this space portion becomes a display area. The distance between the front panel and the rear panel is usually about 3 to 5 mm, and the space is usually kept in a vacuum atmosphere at a pressure of 10 ⁻⁵ to 10 ⁻⁷ Torr.

  In the FED configured as described above, when an acceleration voltage of about several to several tens of kV is applied between the back panel 220 and the front panel 210, electrons are emitted from an electron source as an emitter, and the phosphor layer 213 is generated by the acceleration voltage. Is excited to emit light having a predetermined frequency to the outside of the front panel 210. Thereby, an image is displayed.

The film formed on the glass substrate surface of the spacer is irradiated with electrons emitted from an electron source as an emitter, reflected electrons or secondary electrons from an anode or other components. For this reason, the film is required to have a low resistance so as to suppress charging due to irradiated electrons and not bend the trajectory of the electron beam. However, if the resistance is too low, the amount of current that flows due to the voltage applied between the anode substrate and the cathode substrate increases, and the risk of thermal runaway tends to occur. Therefore, it is necessary to adjust to an appropriate resistance value, and the surface resistance is preferably in the range of 1 × 10 ¹⁰ Ω / □ to 1 × 10 ¹³ Ω / □. Thermal runaway means that the spacer generates heat due to the spacer current flowing between the anode substrate and the cathode substrate, resulting in a high temperature state. As a result, the resistance value of the spacer itself decreases and a larger current flows, resulting in a higher temperature. By repeating the phenomenon that the resistance decreases, the spacer itself becomes a temperature higher than its own softening temperature and melts.

  FIG. 4 is a schematic diagram of a cross section of the spacer 110 manufactured in this example. The spacer 110 is formed on the side surface of the glass substrate 401 in order from the glass substrate side in order of the first metal oxide thin film 411 that exhibits semiconductive electrical conductivity, and the second metal oxide thin film that exhibits metallic conductivity. 412 and a third metal oxide thin film 413 exhibiting semiconducting electrical conductivity.

Here, VW-Mo-P-Ba-O-based electron conductive glass was used for the glass substrate 401 of the spacer 110. The reason why the conductive glass is used is that since a current flows through the glass substrate, the withstand voltage can be increased, and a bright image quality can be obtained. For the first metal oxide thin film 411, Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , a composite oxide of Fe ₂ O ₃ and Ga ₂ O ₃ was used. For the second metal oxide thin film 412 exhibiting metallic conduction, metal particles made of Au, Pt, Ag, Cr, Cu are made of SiO ₂ , Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , Fe _2. A thin film dispersed in an oxide matrix such as a composite oxide of O ₃ and Ga ₂ O ₃ , Al ₂ O ₃ , Ta ₂ O ₅ was used. The third metal oxide film 413 using the composite oxide of _{Ga 2 O 3, Cr 2 O} 3, Fe2O 3, Fe 2 O 3 and _Ga 2 _{O 3.}

  These films were formed by sputtering. In this embodiment, the film is formed by the sputtering method. However, the film forming method may be a coating and baking method using a solution such as a spray method, a dip method, a sol-gel method, a dice method, or a spin coating method. .

A film formation method by sputtering performed in this embodiment will be described. The first and third metal oxide thin films were formed by rf sputtering using a sintered metal oxide having a desired composition as a target material. As a film forming gas, a mixed gas of Ar + O _{2 obtained} by adding 5% by volume of oxygen to high purity Ar gas having a purity of 99.9999% was used. An rf magnetron power source was used as the power source, and a high voltage of about 700 W was applied to the sintered metal oxide target. The vacuum pressure in the film formation chamber before film formation was 4.0 × 10 ⁵ Pa.

The second metal oxide thin film is formed by using a 10 mm square metal chip such as Au, Pt, Ag, Cr, or Cu, SiO ₂ , Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , Fe _2. A film is mounted on the erosion region of a sintered body target made of a metal oxide such as a composite oxide of O ₃ and Ga ₂ O ₃ , Al ₂ O ₃ , or Ta ₂ O ₅ to have a desired film composition. Went. A high purity Ar gas having a purity of 99.9999% was used as the film forming gas. An rf magnetron power source was used as the power source, and a high voltage of about 700 W was applied to the sintered metal oxide target. The vacuum pressure in the film formation chamber before film formation was 4.0 × 10 ⁵ Pa.

  In addition, the size of the metal oxide sintered compact target used in order to form a 1st, 2nd, 3rd thin film is 152.4 mmphi * 5mmt.

  In order to analyze the composition after film formation, a film was formed on a polyimide film to a thickness of about 200 nm, and composition analysis was performed using ICP spectroscopy.

  A coating material was formed on a VW-Mo-P-Ba-O-based electron conductive glass substrate to a thickness of 20 to 50 nm under the above sputtering conditions. The size of the glass substrate was 110 mm × 3 mm × 0.15 mm, and a film was formed on a 110 mm × 3 mm portion. Since the sputtering rate of the film differs depending on the composition, the film was formed while calculating the rate for each composition. After the film formation on one side was completed, the sample was once taken out into the atmosphere, and after the upper and lower surfaces were switched, film formation on the back surface was performed. In this way, film formation under the same conditions was performed on both surfaces of the spacer.

  After the film formation was completed, Cr was formed to a thickness of about 100 nm as a metal film on both end faces (110 × 0.15 mm portions) of the spacers that are to be joined to the anode substrate and the cathode substrate.

  As a comparative example, a spacer having a thin film structure shown in FIGS. FIG. 5 shows an example in which a first metal oxide thin film 411 having semiconducting electrical conductivity is formed on a spacer base material. FIG. 6 shows an example in which a second metal oxide thin film 412 having metallic conductivity is formed on a spacer base material. In FIG. 7, a first metal oxide thin film 411 showing semiconducting electrical conductivity is first formed on a spacer substrate, and then a second metal oxide thin film 412 showing metallic conductivity is formed. This is an example of a layer structure. Further, in FIG. 8, a second metal oxide thin film 412 showing metallic conductivity is first formed on a spacer base material, and then a third metal oxide thin film 413 showing semiconductor electric conductivity is formed. This is an example of a two-layer structure.

The FED panel shown in FIG. 2 was manufactured using the spacer having the structure shown in FIGS. 4 to 8, and the panel's emission deterioration, beam deflection, temperature dependency of the beam deflection, withstand voltage, and deterioration with time were evaluated. Table 1 shows the evaluation results of the spacers. In Table 1, the complex oxide is described as, for example, Fe ₂ O ₃ —Ga ₂ O ₃ .

  In Table 1, the emission deterioration is the difference between the emission current value at the emitter arranged in the first row adjacent to the gate electrode on which the spacer is formed and the emission current value from the emitter 20 rows away from the spacer. A value ΔIe normalized with the emission current value from the emitters away from each other was evaluated. Formula 1 shows the calculation formula for ΔIe.

In Equation 1, Ie ₍₂₀₎ is an emission current value from the emitter 20 rows away from the spacer, and Ie ₍₁₎ is an emission current in the emitter arranged in the first row immediately adjacent to the gate electrode on which the spacer is formed. Value.

  As for the beam deflection amount, the deviation amount of the beam deflection was quantitatively evaluated with a magnifying glass, and a numerical value of the deviation amount was described. A beam deflection amount of 20 μm or less is preferable because a black band due to deviation is not observed in human eyes.

  In beam deflection, when the electrical resistance value of the spacer is high and the secondary electron emission coefficient is larger or smaller than 1, positive charges and negative charges are accumulated on the spacer surface, and the charges accumulated on this surface are emitted. A phenomenon that occurs when an electron beam is irradiated to a position deviated from the center of the phosphor on the anode substrate formed immediately above the emitter, which is attracted when the current is positive, for example, and repelled when it is negative. It is. When beam deflection occurs, a region in which the phosphor does not emit light is generated, and therefore, a line-shaped black band is observed along the spacer, which is not preferable.

  Further, the temperature dependence of the beam deflection is due to the temperature dependence of the resistance of the spacer, and occurs depending on the temperature difference between the anode substrate and the cathode substrate. If the temperature difference between the anode substrate and the cathode substrate is 1 μm or less per 1 ° C., the temperature difference between the anode and the cathode is preferably 20 μm or less even when the temperature difference between the anode and the cathode is 20 ° C. In Table 1, the temperature difference between the anode and the cathode indicates the beam deflection amount per 1 ° C. The temperature of the anode and cathode was measured using an infrared radiation thermometer. Further, the temperature of the cathode was kept constant at 25 ° C., and the temperature of the anode was raised with a hot air heater to form a temperature difference, and measurement was performed.

  With respect to the withstand voltage, a voltage of 4 kV to 10 kV was applied to the anode and the cathode of the manufactured panel, and a voltage at which a defect such as a spark or a thermal runaway of the spacer began to occur was shown. Practically, the withstand voltage is preferably 10 kV or more.

  Deterioration with time is 20,000 hours of continuous lighting experiment. If the above-mentioned emission deterioration, beam deflection, spark, thermal runaway, etc. did not occur, these problems occurred over time. When it worsened, it marked as x.

The above results are summarized in FIG. As shown in Table 1 and FIG. 16, in the spacer in which the first, second, and third thin films are sequentially formed, in all items of emission deterioration, beam deflection, beam deflection temperature dependency, withstand voltage, and aging deterioration. It was found to have excellent characteristics. In the comparative example shown in FIG. 5, since the second metal oxide thin film showing the metal conductivity is not formed, the temperature dependence of the beam deflection is not preferable. In the comparative examples of FIGS. 6 and 7, the beam deflection and the withstand voltage are not preferable because SiO ₂ which is an insulator is used for the matrix of the second thin film exhibiting metallic electrical conductivity. When this matrix was changed from an insulator to a semiconductor oxide, deterioration with time occurred and thermal runaway was likely to occur due to a decrease in resistance.

  In the spacer shown in FIG. 8 in which the second metal oxide thin film and the third metal oxide thin film were sequentially formed on the glass substrate, the withstand voltage was not good.

  The spacers shown in FIGS. 6 to 8 having poor withstand voltage were taken out and examined with a transmission electron microscope. The metal particles dispersed in the second metal oxide thin film exhibiting metal conductivity were found to be glass-based. A phenomenon of diffusion on the surface of the material or segregation due to migration of metal particles on the surface of the glass substrate was observed. This is considered to be caused by the heating process at the time of producing the panel. It is considered that the resistance is lowered due to this segregation, and the thermal runaway occurs because the current flows too much when a high voltage is applied.

In the spacer of the present invention shown in FIG. 4, semiconductor thin films exist on the front and back of the second layer made of an oxide thin film containing metal nanoparticles. For this reason, even when metal particles migrate due to heating during panel manufacture and the metal nanoparticles diffuse into the semiconductor thin film, they are not deposited on the surface or the glass substrate interface by the first and third layers. Therefore, thermal runaway due to segregation is not caused. Furthermore, since a thin film exhibiting metallic conduction is not exposed on the outermost surface, it is preferable that an insulator such as SiO ₂ is not directly charged and charged.

FIG. 9 shows a schematic diagram of a cross-sectional nanostructure when a cross section of an Au—SiO ₂ thin film produced as an example of the second metal oxide thin film 412 showing metallic conductivity is observed with a transmission electron microscope. A transmission electron microscope HF-2000 manufactured by Hitachi, Ltd. was used as the transmission electron microscope. The acceleration voltage was 200 kV. Further, the FIB method (Focused Ion Beam method) was used for the preparation of the sample. The second metal oxide thin film 412 is composed of Au particles 4121 and a SiO ₂ matrix 4122. In this embodiment, the composition was analyzed by ICP was _{50Au-50SiO 2 (mol%)} .

As shown in the schematic diagram of FIG. 9, it was observed that Au was dispersed as nanoparticles in the SiO ₂ matrix. In this example, the particle size of the Au nanoparticles was about 10 nm. Further, when forming the _{50Au-50 (70Ga 2 O 3} -30Fe 2 O 3) (mol%) film as a separate thin film, particle system of Au was found to be very fine particles and about 2 nm. In addition, or in the case of using Pt, Ag, Cr, Cu as the metal _{particles, 50Au-50 (70Ga 2 O} 3 -30Fe 2 O 3) as an oxide _{matrix, Al 2 O 3, Ta 2} O 5, Ga 2 O ₃ , Fe ₂ O _3, etc., nanoparticles were observed in the same manner as the Au—SiO ₂ thin film.

From the above, it is considered that the electric conduction of the second metal oxide thin film 412 exhibiting metallic conductivity is governed by the metal conduction in the metal nanoparticles and the conduction of the oxide matrix layer. When a material having a high resistance of about 10 ¹⁴ Ωcm such as SiO ₂ , Al ₂ O ₃ , Ta ₂ O ₅ or the like is used as the material of the oxide matrix layer, it is considered that hopping conduction occurs between particles. Further, when the resistance of the oxide matrix layer is semiconducting, it is considered that electrical conduction is performed by a conduction mechanism such as hopping conduction in the matrix.

About the produced 2nd metal oxide thin film 412 which shows metallic conductivity, the temperature dependence of electrical resistance was evaluated. FIG. 10 shows a schematic diagram of the shape of the spacer sample used for this measurement. A second metal oxide thin film 412 exhibiting metallic conductivity was formed on the side surface of the glass substrate 401, and 100 nm of metal chromium was formed as an electrode thin film 403 on the end surface. Volume resistance was measured by applying a high voltage of about 500 V between the electrode thin films. The sample size was 3 mm in height, 0.110 mm in width, and 10 mm in length. This sample was sandwiched between electrodes for applying a high voltage, and the whole was held in a thermostatic layer capable of being heated to 125 ° C., and the volume resistance value at each temperature was measured while changing the temperature. First, the temperature of the sample was raised to 125 ° C., and the resistance was measured in the temperature lowering process. The sample used for the measurement was a 50 Au-50 SiO ₂ (mol%) thin film on the side surface of a glass substrate made of VW-Mo-P-Ba-O-based electron conductive glass with a thickness of 20 nm, 50 nm, and 100 nm. Formed.

FIG. 11 shows the temperature change of the volume resistivity of the measured sample. The temperature change of the volume resistivity of the glass substrate simple substance which does not form a thin film as a comparative example is shown. It can be seen that in the thin film on which the Au—SiO ₂ thin film is formed, the temperature change of the volume resistance value is small and almost constant at room temperature. On the other hand, in the comparative example in which no film was formed, the temperature change of the resistance was very large up to around room temperature.

FIG. 12 shows the temperature change of the resistance temperature coefficient (α (% / ° C.)) of a sample in which an Au—SiO ₂ thin film is formed to 50 nm. Moreover, the resistance temperature coefficient of the sample which does not form a thin film as a comparative example is shown. The temperature coefficient of resistance was calculated using Equation 2.

In Equation 2, R is the volume resistivity at temperature T, and R ₀ is the volume resistivity at room temperature (T ₀ ). In this measurement was room temperature T ₀ and 25 ° C.. The temperature coefficient of resistance at 25 ° C. to 40 ° C. in the comparative example was about −3.3% / ° C., but in the example, it was greatly improved to about −1.57% / ° C.

  It was found that when the absolute value of the resistance temperature coefficient is a value within 2, the change in deflection amount when the temperature changes by 1 ° C. is 1 μm or less. In this case, when the temperature difference between the anode and the cathode is 20 ° C. or more, the deflection amount exceeds 20 μm, so that a shadow of the spacer is seen on the screen. Even when the temperature difference of the cathode is 20 ° C., the deflection amount is preferably 20 μm or less, which is preferable.

The mechanism for improving the temperature coefficient of resistance when an Au—SiO ₂ thin film is formed will be described with reference to FIG.

  FIG. 13 shows the temperature change of the volume resistivity for the spacer substrate made of electron conductive glass and the metallic conductive thin film. The volume resistivity of the thin film exhibiting metallic conductivity hardly changes near room temperature, and the volume resistivity of the electron conductive glass spacer decreases by about two orders of magnitude from room temperature to 90 ° C.

Now, assuming that the volume resistivity of the electron conductive glass spacer at room temperature is 10 ⁹ Ωcm and the volume resistivity of the metal conductive thin film is 10 ⁸ Ωcm, the total volume resistivity of the spacer is generally the volume with the lower resistance. Since it is determined by the resistivity, it is equivalent to the volume resistivity of the metal conductive thin film. Therefore, the total volume resistivity of the spacer is substantially equal to the metal conductive thin film up to a temperature at which the volume resistivity of the electron conductive glass spacer is equal to the volume resistivity of the metal conductive thin film. Therefore, a very low resistance temperature coefficient can be obtained near room temperature.

  On the other hand, when the temperature rises and the volume resistivity of the electron conductive glass spacer substrate falls below the volume resistivity of the metal conductive thin film, the total volume resistivity of the spacer becomes close to the volume resistivity of the electron conductive glass spacer substrate. . Therefore, it is considered that the resistance temperature coefficient increases.

  From the above, in order to use the temperature change of the good resistance of the thin film as the temperature change of the net spacer resistance, it is necessary that the electric resistance of the thin film is not more than the resistance of the spacer base material in the operating temperature range of the panel. . That is, when the electrical resistance of the thin film is Rf and the electrical resistance of the glass substrate is Rs, it is preferable that the relationship of Rf ≦ Rs is satisfied.

  On the other hand, reducing the electrical resistance Rf of the thin film has an advantage in that the temperature change of the resistance can be reduced, but if the resistance value is made too small compared to the resistance Rs of the spacer base material, it is applied to the spacer. The current flowing inside the spacer is concentrated on the thin film due to the applied voltage, and the thin film may be broken to cause dielectric breakdown. Therefore, the dielectric breakdown voltage was plotted against the resistance value Rf of the thin film, and the optimum resistance value was obtained.

  FIG. 14 plots the breakdown voltage against the ratio Rf of the resistance Rs of the substrate and the resistance of the thin film. In this example, thin films having different resistance values were prepared by adjusting the amount of Au and the film thickness contained in the thin film. In the measurement, a high voltage was applied to the spacer, and the voltage at which dielectric breakdown occurred was plotted. The measurement points were measured on five samples, and the average value of the voltage at which dielectric breakdown occurred was plotted.

  Each resistance of Rf and Rs was calculated | required as follows. First, Rs was measured without forming a thin film. Next, a thin film was formed on both ends of the substrate to produce a spacer as shown in FIG. Thereafter, the volume resistance Rt of the entire spacer was measured, and the resistance value Rf of the thin film was obtained by an equivalent circuit as shown in FIG.

  The relationship between Rt, Rf, and Rs is as shown in Equation 3, Equation 4, and Equation 5. Therefore, Rf is obtained from Equation 6.

  From FIG. 14, the smaller the Rf is, the lower the dielectric breakdown voltage is. When the Rf is large, the dielectric breakdown does not occur. Now, assuming that the voltage applied during normal image reproduction is 10 V, it was found that Rf / Rs when dielectric breakdown occurs at an applied voltage of 10 V or higher is 0.01 or higher. Therefore, the electrical resistance Rf of the thin film is preferably 0.01Rs ≦ Rf.

  Further, from the above two formulas of Rf ≦ Rs and 0.01Rs ≦ Rf, it was found that the relationship between the electric resistance of the thin film and the electric resistance of the substrate is preferably 0.01Rs ≦ Rf ≦ Rs.

It is sectional drawing which showed the structure of the spacer by this invention. It is the perspective view which showed the external appearance of the MIM type | mold FED. It is sectional drawing which showed a part of the AA line direction of FIG. It is a schematic diagram of the cross section of the spacer by the Example of this invention. It is a schematic diagram of the cross section of the spacer shown as a comparative example. It is a schematic diagram of the cross section of the spacer shown as another comparative example. It is a schematic diagram of the cross section of the spacer by another comparative example. It is a schematic diagram of the cross section of the spacer by another comparative example. It is a schematic diagram of the cross section of the metal oxide thin film which disperse | distributed the metal particle. It is a schematic diagram of the cross section of the spacer which formed the oxide thin film on the surface. It is a figure which shows the temperature change of volume resistivity. It is a figure which shows the temperature change of a resistance temperature coefficient. It is the figure which showed the temperature change of the volume resistivity of an electronic conductive glass spacer board | substrate and a metallic conductive thin film. It is a figure which shows the dielectric breakdown voltage with respect to ratio Rf of resistance Rs of a base material, and resistance of a thin film. It is a figure which shows the equivalent circuit of the spacer which formed the thin film. It is a characteristic comparison figure of an Example and a comparative example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 110 ... Spacer, 114 ... Spacer bonding glass material, 115 ... Spacer bonding glass material, 210 ... Front panel, 211 ... Anode substrate, 212 ... Black matrix, 213 ... Phosphor layer, 220 ... Back panel, 221 ... Cathode substrate 222 ... wiring electrode, 230 ... sealing frame, 401 ... glass substrate, 410 ... metal oxide thin film, 411 ... first metal oxide thin film, 412 ... second metal oxide thin film, 413 ... third Metal oxide thin film, 4121... Au particles, 4122... SiO ₂ matrix.

Claims (10)

  A cathode substrate having an electron source; an anode substrate having a phosphor that emits light upon receiving electrons emitted from the electron source; and a spacer that is disposed between the cathode substrate and the anode substrate and supports both substrates. In the planar image forming apparatus provided, the spacer includes a glass substrate, a first metal oxide thin film having a semiconducting electrical conductivity directly formed on a side surface thereof, and a metallic material formed on the outside thereof. A flat image characterized by comprising a second metal oxide thin film exhibiting excellent electrical conductivity and a third metal oxide thin film exhibiting semiconducting electrical conductivity formed on the outside thereof Forming equipment.   The flat image forming apparatus according to claim 1, wherein the second metal oxide thin film has a configuration in which particles exhibiting metal conductivity are dispersed in a metal oxide matrix. The particles exhibiting metal conductivity are metal particles selected from Au, Pt, Ag, Cr, Cu, and the metal oxide matrix is SiO ₂ , Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , The flat image forming apparatus according to claim 2, wherein the image forming apparatus is an oxide selected from a complex oxide of Fe ₂ O ₃ and Ga ₂ O ₃ , Al ₂ O ₃ , and Ta ₂ O ₅ . At least one of the first metal oxide and the third metal oxide is selected from a composite oxide of Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , Fe ₂ O ₃ and Ga ₂ O _3. 2. The flat image table forming apparatus according to claim 1, wherein the flat image table forming apparatus is an oxide.   The flat image forming apparatus according to claim 1, wherein the glass substrate is glass having electron conductivity.   A spacer disposed between a back panel and a front panel of a flat-type image forming apparatus, a glass substrate, and a first metal oxide thin film having semiconducting electrical conductivity directly formed on the side surface thereof A second metal oxide thin film formed on the outside and showing a metallic electrical conductivity, and a third metal oxide thin film formed on the outside and showing a semiconductive electrical conductivity. A spacer for a flat-type image display device.   The planar image forming apparatus spacer according to claim 6, wherein the second metal oxide thin film has a configuration in which particles exhibiting metal conductivity are dispersed in a metal oxide matrix. The particles exhibiting metal conductivity are metal particles selected from Au, Pt, Ag, Cr, Cu, and the metal oxide matrix is SiO ₂ , Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , The spacer for a flat type image forming apparatus according to claim 7, wherein the spacer is a composite oxide of Fe ₂ O ₃ and Ga ₂ O ₃ , an oxide selected from Al ₂ O ₃ and Ta ₂ O ₅ . At least one of the first metal oxide and the third metal oxide is selected from a composite oxide of Ga ₂ O ₃ , Cr ₂ O ₃ , Fe ₂ O ₃ , Fe ₂ O ₃ and Ga ₂ O _3. The spacer for a flat type image table forming apparatus according to claim 6, wherein the spacer is an oxide.   The planar image forming apparatus spacer according to claim 6, wherein the glass substrate is glass having electron conductivity.

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