JP2008217523A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of performing a desired data processing while preventing the erroneous operation of a circuit. <P>SOLUTION: The semiconductor integrated circuit 100 is provided with: a source voltage monitoring circuit 2 for outputting a clock stop signal when source voltage is a threshold or below and outputting a clock operation signal when the source voltage is larger than the threshold; a clock gating circuit 3 for stopping outputs of the clock signal input from outside in accordance with the clock stop signal and outputting the clock signal in accordance with the clock operation signal; a processor 4 for which source voltage is supplied and which operates synchronous with the clock signal output by the clock gating circuit 3; and a data buffer 5 for temporarily storing data input from outside in accordance with an output signal of the source voltage monitoring circuit 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit to which a voltage is supplied from the outside, for example.

  The operating frequency of the processing circuit (processor) in the LSI is determined by several parameters used when designing the processing circuit. There are two main causes for lowering the operating frequency: a low operation guarantee lower limit voltage and a variation in voltage within the chip.

  Therefore, when designing a high-performance processing circuit, it is important to bring the operation guarantee lower limit voltage as close as possible to the average operating voltage and to further reduce IR-Drop that causes variations in the voltage in the chip.

  While LSIs for portable terminals require a very large processing capacity, the power consumption allowed during low load or standby is very small.

  LSI current consumption includes, for example, switching current consumed in proportion to the amount of load and leakage current consumed regardless of the amount of load. The leakage current becomes a problem at low load.

  In order to achieve both high processing capability and low power consumption at low load, a multiprocessor architecture having individual power cut-off switches is effective.

  As described above, in a high-performance circuit, it is necessary to keep IR-Drop small in order to keep the operating frequency high. However, the resistance of the wiring between the pin and the pad and the power cut-off switch increase IR-Drop.

  In order to prevent this increase in IR-Drop, it is necessary to prepare many pin pads and increase the size of the switch. However, these measures increase manufacturing costs.

  Thus, it is conceivable to provide a power supply circuit for each processor in the chip. This eliminates the need to consider the IR-Drop that occurs between the pin and pad and at the power shutoff switch.

  However, when the power supply circuit is provided in the chip, it is impossible to increase the capacitance of the capacitor for stabilizing the supply voltage. For this reason, when the processing circuit operates and the amount of current used increases rapidly, the voltage supplied to the processing circuit is greatly reduced. When the supplied voltage becomes lower than the operation guarantee voltage, the processing circuit may malfunction.

  The frequency at which the amount of current used by the processing circuit increases rapidly is not so high.

  However, assuming the worst case, the operation guaranteed lower limit voltage cannot be set high, and the operating frequency cannot be increased. Therefore, there is a problem that the processing circuit cannot perform desired data processing.

  Here, the conventional technique includes a system circuit (processing circuit) that performs an arithmetic processing operation by a clock signal output from the oscillation circuit, detects a power supply voltage supplied from the power supply circuit to the system circuit, and from the oscillation circuit. There is a computer provided with control means for controlling the supply operation of the clock signal to the system circuit. This computer stops the supply of the clock signal to the system circuit when the power supply voltage drops (see, for example, Patent Document 1).

  The conventional technology prevents malfunction of the system circuit by the configuration as described above.

However, when the system circuit is stopped due to the stop of the clock signal, the above prior art cannot process the data even if data or the like is input from the outside during the period when the system is stopped.
JP 2001-42977 A

  An object of the present invention is to provide a semiconductor integrated circuit capable of performing desired data processing while preventing malfunction of the circuit.

A semiconductor integrated circuit according to an embodiment of one aspect of the present invention includes:
A power supply voltage is compared with a preset threshold value, a clock stop signal is output when the power supply voltage is less than or equal to the threshold value, and a clock operation signal is output when the power supply voltage is greater than the threshold value. Power supply voltage monitoring circuit to output,
A clock gating circuit that stops output of a clock signal in response to the clock stop signal and outputs the clock signal in response to the clock activation signal;
A processor that is supplied with the power supply voltage and operates in synchronization with the clock signal output from the clock gating circuit;
Provided in one-to-one correspondence with the processor, and temporarily store or pass data input from the outside according to the output signal of the power supply voltage monitoring circuit, and output the data to the processor And a data buffer for
The data buffer is
According to the clock stop signal output from the power supply voltage monitoring circuit, the data input from the outside is temporarily stored, and then stored according to the clock operation signal output from the power supply voltage monitoring circuit. The processed data is output to the processor.

  According to the semiconductor integrated circuit of the present invention, desired data processing can be performed while preventing malfunction of the circuit.

  Embodiments according to the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating a configuration of a main part of a semiconductor integrated circuit 100 according to a first embodiment which is an aspect of the present invention.

  As shown in FIG. 1, the IC chip semiconductor integrated circuit 100 includes an internal power supply circuit 1, a power supply voltage monitoring circuit 2, a clock gating circuit 3, a processor 4, and a data buffer 5.

  The internal power supply circuit 1 is provided in one-to-one correspondence with the processor 4. The internal power supply circuit 1 controls the voltage supplied from the external external power supply circuit 200 via the pin 100a and the pad 100b. The internal power supply circuit 1 supplies the controlled voltage to the processor 4 as the power supply voltage V1.

  As a result, power is allocated to each processor 4, and power shutdown of each processor 4 can be realized without IR-Drop.

  The internal power supply circuit 1 may supply the power supply voltage V1 for each of the plurality of processors 4. In this case, the power shutdown for each of the plurality of processors 4 can be realized without IR-Drop.

  The power supply voltage monitoring circuit 2 compares the power supply voltage V1 with a preset threshold value, and outputs a clock stop signal when the power supply voltage V1 is equal to or lower than the threshold value. The power supply voltage monitoring circuit 2 outputs a clock operation signal when the power supply voltage V1 is larger than a threshold value.

  In response to the clock stop signal, the clock gating circuit 3 stops the output of a clock signal input from the outside of the processor 4, for example. The clock gating circuit 3 outputs an input external clock signal as the clock signal in response to the clock operation signal. The external clock signal is generated by a PLL, for example.

  The processor 4 stores a cache memory 4a for storing data input from a main memory (not shown) via the data buffer 5, and outputs a control signal to the main memory to output the data, and the cache memory 4a And a CPU 4b that performs arithmetic processing on the stored data.

  The processor 4 is supplied with the power supply voltage V1 and operates in synchronization with the clock signal output from the clock gating circuit 3.

  The data buffer 5 is provided in one-to-one correspondence with the processor. The data buffer 5 temporarily stores or passes data input from the outside in synchronization with the external clock signal in accordance with the output signal of the power supply voltage monitoring circuit 2, and passes the data to the processor 4. To output. As the data buffer 5, for example, a FIFO (First In First Out) buffer is selected.

  In addition, the data buffer 5 can store at least data corresponding to the cache line of the processor 4.

  Next, the operation of the semiconductor integrated circuit 100 having the above configuration will be described.

  First, an external clock signal is input to the processor 4 via the clock gating circuit 3, and the processor 4 starts operation.

  When current is consumed by the operation of the processor 4 and the power supply voltage V1 becomes equal to or lower than the threshold value, the power supply voltage monitoring circuit 2 outputs a clock stop signal. The clock gating circuit 3 stops the output of the clock signal input from the outside in response to the clock stop signal. As a result, the operation of the processor 4 is stopped. On the other hand, the data buffer 5 temporarily stores the data input from the outside in response to the clock stop signal output from the power supply voltage monitoring circuit 2.

  Thereafter, when the power supply voltage V1 exceeds the threshold value, the power supply voltage monitoring circuit 2 outputs a clock operation signal. The processor 4 resumes the operation in response to the clock activation signal. On the other hand, in response to the clock operation signal, the data buffer 5 outputs the stored data to the processor 4 in synchronization with the external clock signal.

  Thus, the operations of the processor 4 and the data buffer 5 are controlled according to the power supply voltage V1.

  As a result, it is possible to suppress a decrease in the power supply voltage V1 when the current consumption increases rapidly due to the operation of the processor 4. Therefore, it is possible to prevent the malfunction of the processor 4 caused by the decrease in the power supply voltage V1.

  Further, since the data input to the semiconductor integrated circuit 100 when the processor 4 is temporarily stopped is stored in the data buffer 5, desired data processing can be performed.

  Here, for example, in a general arithmetic processing circuit, since the amount of data input while the clock is stopped is not determined, an infinitely large buffer is required, which is not practical. However, in the case of a processor, the amount of data input from the outside while the clock signal is stopped is about the cache line. Therefore, as described above, the capacity of the data buffer 5 can be suppressed to a practical size (for the cache line).

  In the processor 4, the current consumption increases abruptly even at the time of cache miss refill. For this reason, if the power supply voltage V1 drops at that time, the output of the clock signal from the clock gating circuit 3 may be stopped. The processor 4 cannot receive the refilled data from the bus while the clock signal is stopped, but the data buffer 5 temporarily stores the data.

  Here, a change in the power supply voltage supplied to the processor is considered.

  First, as a comparative example, a power supply voltage supplied to a processor of a conventional semiconductor integrated circuit is examined.

  FIG. 2A is a diagram illustrating a clock signal when the processor of the conventional semiconductor integrated circuit makes a transition from the stopped state to the operating state. FIG. 2B is a diagram showing a supply current and a consumption current when the processor of the conventional semiconductor integrated circuit transitions from the stop state to the operation state. FIG. 2C is a diagram showing a power supply voltage when the processor of the conventional semiconductor integrated circuit makes a transition from the stopped state to the operating state.

  As shown in FIG. 2A, when an external clock signal is input, the processor starts operation. As a result, as shown in FIG. 2B, the current consumption in the processor increases sharply. On the other hand, the supply current supplied from the external power supply circuit gradually increases due to the characteristics of the capacitor of the external power supply circuit.

  Therefore, as shown in FIG. 2C, when the consumption current exceeds the supply current, the charge of the capacitor decreases and the power supply voltage decreases. On the other hand, when the consumption current is lower than the supply current, the charge of the capacitor increases and the power supply voltage rises.

  As described above, in the conventional semiconductor integrated circuit, when the processor transitions to the operating state, the power supply voltage drops from, for example, about 1.0 V to about 0.87 V.

  Next, the power supply voltage supplied to the processor of the semiconductor integrated circuit according to the present embodiment will be considered.

  FIG. 3A is a diagram illustrating a clock signal when the processor of the semiconductor integrated circuit according to the present embodiment transitions from the stopped state to the operating state. FIG. 3B is a diagram illustrating a supply current and a consumption current when the processor of the semiconductor integrated circuit according to the present embodiment transitions from the stop state to the operation state. FIG. 3C is a diagram illustrating the power supply voltage when the processor of the semiconductor integrated circuit according to the present embodiment transitions from the stopped state to the operating state.

  As shown in FIG. 3A, when an external clock signal is input, the processor starts operation. As a result, as shown in FIG. 3B, the current consumption in the processor increases sharply. In contrast, the supply current supplied from the external power supply circuit gradually increases due to the characteristics of the capacitor of the external power supply circuit. Here, as shown in FIG. 3C, when the power supply voltage falls below the threshold value (0.97 V in this case), the output of the clock signal is stopped (FIG. 3A), which temporarily stops the operation of the processor and consumes it. The current decreases (FIG. 3B). Thereafter, as shown in FIG. 3C, when the power supply voltage rises and exceeds 0.97 V, the output of the clock signal is resumed (FIG. 3A), thereby operating the processor and increasing the current consumption (FIG. 3B). Thereafter, the same operation is repeated.

  As described above, in the semiconductor integrated circuit according to the present embodiment, the decrease in the power supply voltage when the processor transitions to the operating state is suppressed to about 0.96V.

  As described above, according to the semiconductor integrated circuit of this embodiment, desired data processing can be performed while preventing malfunction of the circuit.

It is a figure which shows the structure of the principal part of the semiconductor integrated circuit 100 which concerns on Example 1 which is 1 aspect of this invention. FIG. 8A is a diagram illustrating a clock signal when a processor of a conventional semiconductor integrated circuit transitions from a stopped state to an operating state. FIG. 7B is a diagram illustrating a supply current and a consumption current when a processor of a conventional semiconductor integrated circuit transitions from a stopped state to an operating state. C is a diagram illustrating a power supply voltage when a processor of a conventional semiconductor integrated circuit transitions from a stopped state to an operating state. A is a figure which shows a clock signal when the processor of the semiconductor integrated circuit concerning a present Example changes from a halt condition to an operation state. B is a diagram illustrating a supply current and a consumption current when the processor of the semiconductor integrated circuit according to the present embodiment transitions from the stop state to the operation state. C is a diagram illustrating a power supply voltage when the processor of the semiconductor integrated circuit according to the present embodiment transitions from a stopped state to an operating state.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Internal power supply circuit 2 Power supply voltage monitoring circuit 3 Clock gating circuit 4 Processor 4a Cache memory 4b CPU
5 Data Buffer 100 Semiconductor Integrated Circuit 100a Pin 100b Pad 200 External Power Supply Circuit

Claims (4)

A power supply voltage is compared with a preset threshold value, a clock stop signal is output when the power supply voltage is less than or equal to the threshold value, and a clock operation signal is output when the power supply voltage is greater than the threshold value. Power supply voltage monitoring circuit to output,
A clock gating circuit that stops output of a clock signal in response to the clock stop signal and outputs the clock signal in response to the clock activation signal;
A processor that is supplied with the power supply voltage and operates in synchronization with the clock signal output from the clock gating circuit;
Provided in one-to-one correspondence with the processor, and temporarily store or pass data input from the outside according to the output signal of the power supply voltage monitoring circuit, and output the data to the processor And a data buffer for
The data buffer is
According to the clock stop signal output from the power supply voltage monitoring circuit, the data input from the outside is temporarily stored, and then stored according to the clock operation signal output from the power supply voltage monitoring circuit. And outputting the processed data to the processor.   The semiconductor integrated circuit according to claim 1, further comprising an internal power supply circuit for controlling a voltage supplied from the outside and supplying the power supply voltage to the processor.   3. The semiconductor integrated circuit according to claim 2, wherein the internal power supply circuit is provided in one-to-one correspondence with the processor.   4. The semiconductor integrated circuit according to claim 1, wherein the data buffer is capable of storing at least data corresponding to a cache line of the processor.

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