JP2008217154A - Data processor and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To more improve operation frequency, and to more suppress power consumption than a conventional manner in a data processor for quickly and simultaneously executing a plurality of mechanical word instructions. <P>SOLUTION: A data processor is provided with a VLIW instruction queue 140 for storing the set of a plurality of source register numbers and destination register numbers in predetermined storage positions corresponding to the execution sequence of mechanical word instructions to designate the source register numbers and the destination register numbers; and an input stand-by register 170 for extracting and storing the value of the source register included in the mechanical word instruction whose execution sequence is the earliest and the destination register number included in the mechanical word instruction stored in the VLIW instruction queue 140. Thus, it is possible to issue only the mechanical word instruction whose execution sequence is the earliest, and to improve the operation frequency of the whole data processor. Also, it is possible to suppress the size of the storage region by storing only the register number. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing apparatus and a data processing method for simultaneously executing a plurality of machine language instructions at high speed.

  In recent portable terminal devices and embedded systems, it has become common to simultaneously execute programs such as an OS (operating system) that cannot expect instruction level parallelism and programs that can expect high instruction level parallelism such as multimedia processing. Yes. In general, it is preferable to use an industry standard processor for a control program such as an OS, while it is preferable to use a low-power processor with high parallel processing performance for multimedia processing. Therefore, programs that are executed simultaneously are not necessarily based on the same instruction set architecture.

  As a processing method for executing a plurality of instructions simultaneously, a superscalar method is generally used. A general superscalar pipeline structure will be described with reference to FIG. FIG. 9 is a block diagram showing each stage of the pipeline. As shown in FIG. 9, in this example, an instruction is executed through seven stages.

  First, in stage S1, instruction fetch (IF) is performed. That is, an instruction is fetched from an instruction cache (not shown). Next, in stage S2, instruction decode processing (HOST-D) is performed. That is, the source register number and destination register number of the fetched instruction are extracted. Here, the source register is a register that stores a value to be calculated. The destination register is a register for storing the operation result.

  Next, in stage S3, a dependency check (MAP) between instructions is performed. In other words, in order to eliminate the register dependency between instructions, mapping from a logical register to a physical register (register renaming) is performed.

  Next, in stage S4, instruction waiting and instruction issuance (SEL / RD) are performed. Next, in stage S5, the source register value is input to the calculator and the calculation is executed. Here, four types of arithmetic units, such as an arithmetic logic unit (ALU), a shift arithmetic unit (Shift), an address arithmetic unit (Addr), and a cache (Cache) are exemplified. Note that the present invention is not limited to the above four types of arithmetic units. For example, another arithmetic logic unit may be provided.

Next, in stage S6, the operation result is written to the register (WR). Finally, in stage S7, the register is updated (RETIRE). That is, when the execution of the instruction is completed, the mapped physical register is released, and the logical register is updated.
(Prior art 1)
Next, a conventional data processing apparatus (see Non-Patent Documents 1 to 3) that simultaneously executes a plurality of instructions by the superscalar method will be described with reference to FIG. FIG. 10 is a block diagram showing a configuration of a conventional data processing apparatus 500. As shown in FIG.

  Here, it is assumed that the data processing apparatus 500 executes four instructions at the same time. In addition, the data processing device 500 includes one arithmetic logic unit 581 (ALU), one shift unit 582 (Shift), one address unit 583 (Addr), and one cache 584 (Cache) as arithmetic units. It shall be prepared one by one. In addition, the above four types of arithmetic units all perform arithmetic using the three-operand method, that is, values specified by two source registers, and store the arithmetic results in the destination register. Note that the 4-operand or 5-operand operation may be divided into three-operand operations.

  With reference to FIG. 10, the flow of processing in which the data processing apparatus 500 simultaneously executes four instructions will be described for each stage. In FIG. 10, the stage for performing instruction fetch (IF), the stage for performing instruction decoding (HOST-D), and the stage for performing register update (RETIRE) are not shown.

  First, an outline of processing performed in each stage shown in FIG. 10 is shown below. In the Rename stage 501, the register dependency between instructions is canceled. Next, in the Read stage 502, the temporary register value after the dependency relationship is canceled is read. In the Dispatch stage 503, the register value is registered in the reservation station 551 for waiting for an instruction until a predetermined condition is satisfied. Finally, in the Execute stage 504, the register value is input from the reservation station 551 to each calculator, and the calculation is executed.

  Next, details of processing performed in each stage shown in FIG. 10 are shown below. In the Rename stage 501, the register dependency between instructions is canceled. For this purpose, first, the dependency checking unit 515 inputs a set of the source register number and destination register number of each instruction decoded by the decoding unit 510, and performs a process of eliminating the register dependency between instructions. Then, a set of the source register number and the destination register number for which the dependency relationship is eliminated is output. In this example, for each instruction, a set 511, 512, 513, 514 of two source register numbers (s) and destination register numbers (d) is input to the dependency checking unit 515. Then, the dependency relationship inspecting unit 515 outputs a set 516, 517, 518, 519 of the source register number (S) and the destination register number (D) after canceling the register dependency.

  Next, in the Read stage 502, eight registers are read at a time. That is, the values 541 to 544 of the two source registers (S) of the sets 516, 517, 518, and 519 for which the dependency relationship has been eliminated are read via the input wait register 536.

  Next, in the Dispatch stage 503, the source register number (S) of each instruction, the read source register values 541 to 544, and the destination register number (D) are registered in the reservation station 551 that is a queue. Here, the reservation station 551 is provided for each computing unit (arithmetic logic computing unit 581, shift computing unit 582, address computing unit 583, cache 584). Here, the number of entries in the reservation station 551 is four. That is, the reservation station 551 can wait for four instructions for each computing unit. The number of entries is not limited to four, and may be more than four or less than four.

  Each of the source register numbers registered in the reservation station 551 is provided with a forwarding 590 for receiving a signal from the pipeline registers 585 to 588 in which the calculation result of the preceding instruction is stored. The forwarding 590 is used to compare the source register number waiting in the reservation station 551 with the register numbers of pipeline registers 585 to 588 in which the operation result of the preceding instruction is stored. If the numbers match as a result of comparing them, it means that the operation of the preceding instruction using the source register used by the waiting instruction as the destination register is completed. In this case, for example, a flag (for example, “1”) indicating that the value of the source register can be input to the arithmetic unit is set.

  Then, in the Execute stage 504, when the flag “1” is set in any of the two source registers that are waiting in the reservation station 551, the two source register values that are waiting are input to the arithmetic unit. Execute. For this purpose, wiring is provided from all the entries in the reservation station 551 to the computing unit.

Then, the calculation result of the calculator is written into the pipeline registers 585 to 588 and simultaneously transmitted to all the source registers waiting in the reservation station 551 via the forwarding 590. At the same time, the operation result is stored in the input wait register 536 and is read out by the read stage 502.
(Prior art 2)
Next, another conventional data processing apparatus (see Non-Patent Document 4) that simultaneously executes a plurality of instructions by the superscalar method will be described with reference to FIG. FIG. 11 is a block diagram showing the configuration of another conventional data processing apparatus 505. As shown in FIG.

  Here, the data processing device 505 will be described as executing four instructions at the same time. Further, the data processing device 505 includes one arithmetic logic unit 581 (ALU), a shift unit 582 (Shift), an address unit 583 (Addr), and a cache 584 (Cache) as arithmetic units. It shall be prepared one by one. In addition, the above four types of arithmetic units all perform arithmetic using the three-operand method, that is, values specified by two source registers, and store the arithmetic results in the destination register. It should be noted that a 4-operand or 5-operand operation may be executed after being decomposed into a 3-operand operation.

  With reference to FIG. 11, the flow of processing in which the data processing device 505 executes four instructions simultaneously will be described for each stage. In FIG. 11, the stage for performing instruction fetch (IF), the stage for performing instruction decoding (HOST-D), and the stage for performing register update (RETIRE) are not shown.

  First, an outline of processing performed in each stage shown in FIG. 11 is shown below. In the Rename stage 506, register dependency between instructions is canceled and registered in the instruction window. Next, in the Select & Read stage 507, the determined instruction is taken out from the instruction window. Finally, the Execute stage 508 executes an operation.

  Next, details of processing performed in each stage shown in FIG. 11 are shown below. In the Rename stage 506, processing similar to that in the Rename stage 501 is performed to eliminate the register dependency between instructions. In this example, a set 511, 512, 513, and 514 of two source register numbers (s) and destination register numbers (d) is input to the dependency relationship checking unit 515 for every four instructions. Then, the dependency relationship inspecting unit 515 registers the pair of the source register number (S) and the destination register number (D) after canceling the register dependency relationship for each in the instruction window 520.

  The instruction window 520 is a queue for waiting for an instruction to be issued until a predetermined condition is satisfied, and registers a pair of a source register number (S) and a destination register number (D) after the dependency relationship is canceled. Wait. Note that, unlike the reservation station 551 in FIG. 10, no register value is registered. Here, the number of entries in the instruction window 520 is four. That is, the command window 520 can register 16 commands. The number of entries is not limited to four, and may be more than four or less than four.

  Each of the two source registers registered in the instruction window 520 includes a pipeline register 585 to 588 in which the operation result of the preceding instruction is stored, and a destination register of an instruction to be executed in the next cycle. A tag update (TagUpdate) 591 for connecting numbers 545 to 548 is provided.

  The tag update 591 is first used to compare the source register number of the instruction waiting in the instruction window 520 with the register numbers of the pipeline registers 585 to 588 in which the operation result of the preceding instruction is stored. If the numbers match as a result of comparison, it means that the operation of the preceding instruction using the source register used by the waiting instruction as the destination register is completed. In this case, a flag (for example, “1”) indicating that the value of the source register can be input to the arithmetic unit is set.

  Further, the tag update 591 is used to compare the source register number of the instruction waiting in the instruction window 520 with the destination register numbers 545 to 548 of the instruction to be operated in the next cycle. If the numbers match as a result of comparison, it means that an instruction using the source register used by the waiting instruction as the destination register is executed in the next cycle. In this case, a flag (for example, “1”) indicating that the value of the source register can be input to the arithmetic unit is set.

  Then, in the Select & Read stage 507, out of the source register numbers waiting in the instruction window 520, the one having the flag “1” in both of the two source registers is taken out. Then, as a register value corresponding to the extracted source register number, 1) an operation result of a preceding instruction stored in the input wait register 536, or 2) an operation result stored in the pipeline registers 585 to 588. One of them is selected and set as the source register values 551 to 554 of the instruction to be operated in the next cycle.

  Next, in the Execute stage 508, the value stored in the input waiting register 536 is input to the arithmetic unit, and the operation is executed. Then, the calculation result is written in the pipeline registers 585 to 588. Then, in the next cycle, it transmits to all the source register numbers waiting in the instruction window 520 via the tag update 591. At the same time, the calculation result is stored in the input wait register 536 and is read out by the Select & Read stage 507.

Based on the value stored in the input wait register 536, which instruction is taken out from the instruction window 520 and the operation result is obtained without waiting for the next cycle by providing the bypass 592, the subsequent instruction. Does not have to wait for the execution of the preceding instruction to complete. Therefore, even if there is a register dependency between the preceding instruction that completes the operation in one cycle and the succeeding instruction, the succeeding instruction can be executed in the cycle following the cycle in which the preceding instruction is executed. It becomes.
David B. Papworth, "Tuning the Pentium Pro microarchitecture", IEEE Micro, Vol.16, No.2, p.8-15 (1996) L. Gwennap, "Intel's P6 Uses Decoupled Superscalar Design", Microprocessor Report, Vol.9, Np.2, p.9-15 (1995) Glenn Hinton, Dave Sager, Mike Upton, Darrell Boggs, Doug Carmean, Alan Kyker, Patrice Roussel, "The Microarchitecture of the Pentium4 Processor", Intel Technology Journal, Q1 (2001) Yasuhiko Nakajima, “Instruction Decomposed Superscalar for ARM Architecture”, IEICE Technical Report, IEICE, June 2006, 2006-ARC-168, p.77-82

  As described above, the data processing devices disclosed in Non-Patent Documents 1 to 4 can simultaneously execute a plurality of instructions. However, in the data processing devices disclosed in Non-Patent Documents 1 to 3, in the Execute stage 504, the delay time for selecting an instruction that can be issued from the reservation station 551 is large.

  In other words, the operation result is written to the pipeline registers 585 to 588, and at the same time, the operation result is transmitted to all the source registers of the instruction waiting in the reservation station 551 via the forwarding 590. Then, the source register number waiting in the reservation station 551 is compared with the register numbers of the pipeline registers 585 to 588 in which the calculation result of the preceding instruction is stored, and an instruction that can be input to the calculator is selected.

  As described above, since there are many processes that must be executed in one cycle, there is a problem that the operating frequency of the entire data processing apparatus cannot be improved.

  Also, all entries in the reservation station 551 are configured to hold two source register numbers and values, and a destination register number. For example, the source register number and the destination register number are each 5 bits long, and the source register value is 32 bits long. Since there are a total of 48 source register numbers and destination register numbers that can wait in the reservation station 551 and a total of 32 source register values, the storage area of the reservation station 551 has at least 1264 bits (5 bits × 48 + 32 bits). × 32) or more are required.

  Further, the forwarding 590 transmits to all the source register values of the instructions waiting in the reservation station 551. That is, 1024 (32 bits × 32) signal lines for the forwarding 590 are required.

  As described above, there is a problem that the storage area of the reservation station 551 becomes large, and a problem that the number of signals of the forwarding 590 increases.

  Further, the reservation station 551 is configured to receive the calculation result via the forwarding 590 for each cycle. Therefore, there is a problem that this increases power consumption.

  Next, in the data processing device disclosed in Non-Patent Document 4, since there is no reservation station or forwarding, the configuration of the Execute stage 508 is simplified, and the processing load on the Execute stage 508 is reduced. However, instead, in the Select & Read stage 507, an instruction that can be issued is selected from an arbitrary position in the instruction window 520, and at the same time, register reading using the register designation field in the selected instruction is completed in one cycle. For this reason, there is a problem that the processing delay time in the Select & Read stage 507 is large and the operating frequency of the entire data processing apparatus cannot be improved.

  As described above, in the conventional data processing device that improves the instruction level parallelism by the instruction issue mechanism such as the reservation station and the instruction window and the forwarding, the configuration of the circuit around the arithmetic unit becomes complicated, and the operating frequency of the entire device There is a problem that the power consumption cannot be improved or the power consumption cannot be suppressed.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to improve the operating frequency as compared with the prior art and to reduce power consumption. An object of the present invention is to provide a data processing apparatus and a data processing method capable of simultaneously executing word instructions at a high speed.

  In order to solve the above problems, a data processing apparatus according to the present invention includes a source operand field that specifies a source register number that stores a value used for a predetermined operation, and a destination register that stores a result of the operation. A data processing apparatus for simultaneously interpreting and executing a plurality of machine language instructions including a destination operand field for designating a number, the source register number and the destination designated by the source operand field included in the plurality of machine language instructions First instruction storage means for storing a set of destination register numbers specified by the operand field, and a plurality of source register numbers and destination register numbers acquired from the first instruction storage means Source operation that specifies the register number Stored in a predetermined storage location according to the execution order of the machine language instruction including the destination field and the destination operand field for designating the destination register number, and not storing the pair of the source register number and the destination register number The second instruction storage means for storing empty information at the position, and the value of the source register specified by the source operand field contained in the machine language instruction stored in the second instruction storage means and having the earliest execution order And a third instruction storage means for storing the destination register number specified by the destination operand field included in the machine language instruction, and a predetermined value based on the value of the source register obtained from the third instruction storage means Perform an operation and obtain the operation result from the third instruction storage means. A destination that has been stored in the second instruction storage means, the source register number obtained from the first instruction storage means, and a plurality of instruction operation means for storing in the register specified by the obtained destination register number When dependent on the register number, the second instruction storage means indicates the execution order of the machine language instruction including the source operand field specifying the source register number, and the machine including the destination operand field specifying the destination register number. The order is determined to be later than the execution order of the word instructions, and the storage position corresponding to the determined execution order, where the empty information is stored, is stored in the source register number specified by the source operand field. To a machine language instruction containing the source operand field A combination with a destination register number designated by a destination operand field included is stored.

  The data processing method according to the present invention also includes a source operand field that specifies the number of a source register that stores a value used for a predetermined operation, and a destination register that specifies the number of a destination register that stores the result of the operation. A data processing method for simultaneously interpreting and executing a plurality of machine language instructions including an operand field, which is specified by a source register number and a destination operand field specified by a source operand field included in the plurality of machine language instructions. A first instruction storing step for storing a set of destination register numbers, and a plurality of sets of source register numbers and destination register numbers stored in the first instruction storing step are acquired, and the source register numbers are obtained. Source operand to specify A storage location in which a pair of the source register number and the destination register number is not stored, and stored in a predetermined storage location corresponding to the execution order of the machine language instruction including the field and the destination operand field for designating the destination register number Includes a second instruction storing step for storing empty information, a value of a source register specified by a source operand field stored in the machine instruction having the earliest execution order stored in the second instruction storing step, A third instruction storing step for storing a destination register number specified by the destination operand field included in the machine language instruction, and a source specified by the source operand field stored in the third instruction storing step Get register value A plurality of instruction operation steps for performing a predetermined operation and storing the operation result in a register specified by a destination register number specified by a destination operand field stored in a third instruction storage step. When the source register number specified by the source operand field acquired in the second instruction storage step depends on the destination register number specified by the destination operand field stored in the second instruction storage step The execution order of the machine language instruction including the source operand field is determined to be slower than the execution order of the machine language instruction including the destination operand field, and the storage position is in accordance with the determined execution order, Free information is stored A set of a source register number specified by the source operand field and a destination register number specified by the destination operand field included in the machine language instruction including the source operand field It is characterized by.

  According to the above configuration, when the source register number acquired from the first instruction storage unit depends on the destination register number stored in the second instruction storage unit, the source operand field that specifies the source register number Is determined to be later than the execution order of the machine language instruction including the destination operand field for designating the destination register number. Then, a set of the source register number and the destination register number acquired from the first instruction storing means together with the source register number is stored in a storage position corresponding to the execution order.

  Further, the destination register specified by the destination operand field included in the machine language instruction is subjected to a predetermined operation based on the value of the source register specified by the source operand field included in the machine language instruction having the earliest execution order. Stores the operation result in the register specified by the number.

  Therefore, the source register number specified by the source operand field included in the machine language instruction and the destination register number specified by the destination operand field so that a machine language instruction having a dependency relationship can be extracted according to the execution order. The set can be stored in the second instruction storage means. Only the machine language instruction with the earliest execution order can be issued.

  Therefore, since the data processing device is not configured to select and issue a machine language instruction from an arbitrary storage location, the delay time of instruction execution processing can be suppressed, and the operating frequency of the entire data processing device can be improved. There is an effect that can be.

  In addition, since only the register number is stored in the second instruction storage unit, the size of the storage area can be reduced.

  Furthermore, in the data processing apparatus according to the present invention, in the configuration described above, the second instruction storage means, for each source register number to be stored, indicates whether or not the value of the source register can be input to the instruction arithmetic means. And when all of the information on whether or not the source register number specified by the source operand included in the machine language instruction stored in the second instruction storage means and included in the machine language instruction having the earliest execution order can be input, the source register May be obtained and stored in the third instruction storage means.

  According to the above configuration, for each source register number specified by the source operand field included in the machine language instruction, the availability information indicating whether or not the value of the source register can be input to the instruction arithmetic means is provided.

  Therefore, it is possible to determine whether or not the machine language instruction can be issued by checking the availability information of the source register numbers specified by all the source operands included in the machine language instruction.

  Therefore, the machine language instruction with the earliest execution order can be input to the instruction calculation means after determining that it can be issued.

  Furthermore, in the data processing apparatus according to the present invention, in the above configuration, when the source register number acquired from the first instruction storage unit depends on the destination register number stored in the second instruction storage unit, The instruction storage unit 2 sets the source register number input enable / disable information to “not input”, and the second instruction storage unit stores the machine language instruction that has been stored in the second instruction storage unit and has the earliest execution order. When the value of the source register specified by the included source operand field is acquired and stored in the third instruction storage means, the destination register number specified by the destination operand field included in the machine language instruction; The destination register is compared with the source register number that is set to “unavailable” for the availability information. When the No. and the source register numbers match, may set the charged permission information of the source register number and the input accepted.

  According to the above configuration, the value of the source register specified by the source operand field included in the machine language instruction having the earliest execution order stored in the second instruction storage unit is further stored in the third instruction storage unit. When storing, the availability information of the source register number that matches the destination register number specified by the destination operand field included in the machine language instruction is set to be acceptable.

  Therefore, when the value of the source register specified by the source operand field included in the machine language instruction with the earliest execution order is stored in the third instruction storage unit, it is included in the machine language instruction depending on the machine language instruction at the same time. Information indicating whether or not the source register number specified by the source operand field to be input can be input.

  Accordingly, it can be recognized that the preceding machine language instruction is executed in the next cycle, and the subsequent machine language instruction depending on the preceding machine language instruction can be issued in the next cycle. That is, the subsequent machine language instruction depending on the preceding machine language instruction can be issued without waiting for the execution of the preceding machine language instruction, so that the operating frequency of the entire data processing apparatus can be improved. There is an effect.

  Furthermore, in the data processing apparatus according to the present invention, in the configuration described above, when the instruction calculation unit stores the calculation result in the register specified by the destination register number acquired from the third instruction storage unit, the destination The register number is compared with the source register number already stored in the second instruction storage means, and when the destination register number and the source register number match, the availability information of the source register number can be entered. It is good also as a structure to set.

  According to the above configuration, the second instruction that matches the destination register number specified by the destination operand field included in the machine language instruction in which the instruction operation means stores the operation result of the machine language instruction. The information on whether or not the source register number already stored in the storage means can be input is set to enable.

  Therefore, at the same time that the instruction operation means completes the operation of the machine language instruction, the source register number specified by the source operand field included in the machine language instruction using the operation result of the machine language instruction is stored in the third instruction storage means. You can register.

  Therefore, since the subsequent machine language instruction depending on the preceding machine language instruction can be issued before the execution result of the preceding machine language instruction is acquired in the next cycle, the operating frequency of the entire data processing apparatus is improved. There is an effect that can be made.

  Further, the data processing device according to the present invention, in the above configuration, obtains a set of a plurality of source register numbers and destination register numbers from the first instruction storage means, and the source register number and the destination register number And a second instruction storage unit that includes a combination of a plurality of source register numbers and destination register numbers from which the dependency relationship has been canceled. It is good also as a structure which acquires.

  According to the above configuration, the dependency cancellation means further depends on the source register number specified by the source operand field included in the plurality of machine language instructions and the destination register number specified by the destination operand field. Cancel the relationship.

  Therefore, the dependency relationship between a plurality of machine language instructions can be eliminated.

  Therefore, there is an effect that a plurality of machine language instructions can be executed simultaneously.

  Furthermore, in the data processing apparatus according to the present invention, in the above configuration, the second instruction storage means stores a set of a plurality of source register numbers and destination register numbers acquired from the first instruction storage means. Specify the source operand field and destination register number that specify the source register number included in the multiple sets based on the dependency relationship between the source register number and the destination register number obtained from the dependency relationship cancellation means The execution order of the machine language instruction including the destination operand field to be determined is determined, and the plurality of source register numbers and the storage position corresponding to the determined execution order are stored in the storage position where the empty information is stored. A new instruction registration system that stores pairs with destination register numbers Means may further comprise configure.

  According to the above configuration, the new instruction registration control unit further stores data in accordance with the determined execution order based on the dependency relationship between the source register number and the destination register number acquired from the dependency relationship canceling unit. A set of a plurality of source register numbers and destination register numbers acquired from the first instruction storage means is stored in the second instruction storage means at the position.

  Therefore, in consideration of the dependency of a pair of a plurality of source register numbers and destination register numbers newly stored in the second instruction storage means, the pair of the source register number and the destination register number is set to the second It can be stored in the instruction storage means.

  Therefore, there is an effect that an appropriate execution order of machine language instructions can be determined in consideration of a dependency relationship between machine language instructions newly waiting.

  Furthermore, the data processing apparatus according to the present invention is stored in the second instruction storage means in the above configuration even when the operation result in the instruction operation means cannot be stored in the register in one cycle. All of the source register number input availability information specified by the source operand included in the machine language instruction with the earliest execution order can be input, and none of the source register numbers could store the operation result When not depending on the destination register number, the value of the source register and the destination register number specified by the destination operand field included in the machine language instruction may be stored in the third instruction storage means. Good.

  According to the above configuration, the source register number that does not match the destination register number specified by the destination operand field included in the preceding machine language instruction that has an execution delay such that the operation result cannot be stored in the register. If the availability information of the source register number specified by all the source operands included in the subsequent machine language instruction including the specified source operand can be input, the value of the source register and the subsequent machine language instruction And the destination register number designated by the destination operand field included in the third instruction storage means.

  Therefore, a subsequent machine language instruction that does not depend on the preceding machine language instruction can be issued regardless of the execution delay of the preceding machine language instruction.

  Therefore, even if there is an execution delay in the preceding machine language instruction, the subsequent machine language instruction that does not depend on the preceding machine language instruction can be continuously executed.

  Furthermore, in the data processing apparatus according to the present invention, in the above configuration, the source register number of the set of the source register number and the destination register number acquired by the second instruction storage unit from the first instruction storage unit is When the instruction operation means depends on a destination register number that is expected to be unable to store an operation result in one cycle, a source operand field that specifies the source register number and a destination that specifies the destination register number The execution order of the machine language instruction including the operand field is a predetermined order from the execution order of the machine language instruction including the destination operand field for designating the destination register number for which it is expected that the operation result cannot be stored in one cycle. slow Determining the ordinal a storage position corresponding to the execution order in which the determined, in the storage position in which empty data is stored may be configured to store a set of the said source register number and a destination register number.

  According to the above configuration, the source register number that matches the destination register number specified by the destination operand field included in the preceding machine language instruction that has an execution delay such that the operation result cannot be stored in the register is further obtained. The execution order of the subsequent machine language instruction including the specified source operand is set to an execution order that is later than the execution order of the preceding machine language instruction by a predetermined order.

  Therefore, it is possible to delay the issuance of the subsequent machine language instruction depending on the preceding machine language instruction having the execution delay for a certain period of time from the other subsequent instructions.

  Therefore, even if there is an execution delay in the preceding machine language instruction, it is possible to prevent the execution of the subsequent machine language instruction from being interrupted immediately.

  Furthermore, in the data processing apparatus according to the present invention, in the above configuration, the first instruction storage means includes a source register number specified by a source operand field included in a machine language instruction that can be executed in one cycle, and a destination. A combination with a destination register number specified by the operand field may be stored.

  According to the above configuration, the combination of the source register number specified by the source operand field included in the machine language instruction executable in one cycle and the destination register number specified by the destination operand field is the first. 1 instruction storage means.

  Therefore, the instruction calculation means can reliably complete the execution of the instruction in one cycle.

  Therefore, issuing the subsequent machine language instruction depending on the preceding machine language instruction without waiting for the completion of the execution of the preceding machine language instruction has an effect that it can be surely executed.

  Furthermore, in the data processing apparatus according to the present invention, in the above configuration, a set of a source register number specified by the source operand field included in the machine language instruction and a destination register number specified by the destination operand field is obtained. A set of a source register number specified by the source operand field and a destination register number specified by the destination operand field, which are managed in accordance with the execution order of the machine language instruction and are executed. It may be configured to further include a reorder buffer for managing

  According to the above configuration, the reorder buffer further manages the machine language instructions according to the execution order, and manages the machine language instructions that have been executed.

  Therefore, when an execution delay occurs in the preceding machine language instruction, the execution order of the machine language instruction using the operation result of the preceding machine language instruction can be changed using the reorder buffer.

  Therefore, the execution order of the machine language instructions can be guaranteed.

  Furthermore, the data processing apparatus according to the present invention further comprises a plurality of first instruction storage means in the above configuration, wherein the second instruction storage means obtains a plurality of sources acquired from the plurality of first instruction storage means. A combination of register numbers and destination register numbers may be stored in a mixed state.

  According to the above configuration, the set of a plurality of source register numbers and destination register numbers acquired from the plurality of first instruction storage means is further stored in the second instruction storage means.

  Therefore, the source register number specified by the source operand field included in the machine language instructions constituting the different instruction streams (a series of instructions to be executed successively) in the plurality of first instruction storage means, and the destination When a pair with the destination register number specified by the operand field is stored, it can be mixed and stored in the second instruction storage means.

  Therefore, it is possible to execute a plurality of different instruction streams in a mixed manner.

  Furthermore, in the data processing apparatus according to the present invention, in the above configuration, a set of a plurality of source register numbers and destination register numbers stored in the plurality of first instruction storage means is used as the second instruction storage means. When not in a storable format, the second instruction storage means can store a combination of a plurality of source register numbers and destination register numbers acquired from the plurality of first instruction storage means in the second instruction storage means. It is good also as a structure converted into a various format.

  According to the above configuration, a set of a plurality of source register numbers and destination register numbers acquired from the first instruction storage unit is further converted into a format that can be stored in the second instruction storage unit.

  Therefore, a plurality of first instruction storage means are designated by a source register number designated by a source operand field included in a machine language instruction constituting an instruction stream conforming to different instruction sets and a destination operand field. Even when a pair with the destination register number is stored, they can be mixed and stored in the second instruction storage means.

  Therefore, it is possible to execute a plurality of instruction streams conforming to different instruction sets in a mixed manner.

  As described above, the data processing apparatus according to the present invention specifies the source operand field that specifies the number of the source register that stores the value used for a predetermined operation, and the number of the destination register that stores the result of the operation. A data processing device that simultaneously interprets and executes a plurality of machine language instructions including a destination operand field, and includes a source register number and a destination operand field specified by the source operand field included in the plurality of machine language instructions. First instruction storage means for storing a set of designated destination register numbers, and a set of a plurality of source register numbers and destination register numbers acquired from the first instruction storage means Source operand fee to be specified And a storage location in which the pair of the source register number and the destination register number is not stored, according to the execution order of the machine language instruction including the destination operand field for designating the destination register number and the destination register number. Includes a second instruction storage means for storing empty information, a value of a source register specified by a source operand field included in a machine language instruction stored in the second instruction storage means and having the earliest execution order, and , A third instruction storage means for storing the destination register number designated by the destination operand field included in the machine language instruction, and a predetermined operation based on the value of the source register obtained from the third instruction storage means And the operation result is obtained from the third instruction storage means. A destination register number stored in the second instruction storage means, the source register number acquired from the first instruction storage means, and stored in the register specified by the destination register number. The second instruction storage means includes the execution order of the machine instruction including the source operand field specifying the source register number, and the machine instruction including the destination operand field specifying the destination register number. And a storage location corresponding to the determined execution order, where the empty information is stored, and a source register number specified by the source operand field, and Death in machine language instructions that include a source operand field Stores a pair with the destination register number specified by the destination operand field.

  The data processing method according to the present invention also includes a source operand field that specifies the number of a source register that stores a value used for a predetermined operation, and a destination register that specifies the number of a destination register that stores the result of the operation. A data processing method for simultaneously interpreting and executing a plurality of machine language instructions including an operand field, which is specified by a source register number and a destination operand field specified by a source operand field included in the plurality of machine language instructions. A first instruction storing step for storing a set of destination register numbers, and a plurality of sets of source register numbers and destination register numbers stored in the first instruction storing step are acquired, and the source register numbers are obtained. Source operand to specify A storage location in which a pair of the source register number and the destination register number is not stored, and stored in a predetermined storage location corresponding to the execution order of the machine language instruction including the field and the destination operand field for designating the destination register number Includes a second instruction storing step for storing empty information, a value of a source register specified by a source operand field stored in the machine instruction having the earliest execution order stored in the second instruction storing step, A third instruction storing step for storing a destination register number specified by the destination operand field included in the machine language instruction, and a source specified by the source operand field stored in the third instruction storing step Get register value A plurality of instruction operation steps for performing a predetermined operation and storing the operation result in a register specified by a destination register number specified by a destination operand field stored in a third instruction storage step. When the source register number specified by the source operand field acquired in the second instruction storage step depends on the destination register number specified by the destination operand field stored in the second instruction storage step The execution order of the machine language instruction including the source operand field is determined to be slower than the execution order of the machine language instruction including the destination operand field, and the storage position is in accordance with the determined execution order, Free information is stored A set of the source register number specified by the source operand field and the destination register number specified by the destination operand field included in the machine language instruction including the source operand field is stored in the storage location.

  Therefore, the source register number specified by the source operand field included in the machine language instruction and the destination register number specified by the destination operand field so that a machine language instruction having a dependency relationship can be extracted according to the execution order. The set can be stored in the second instruction storage means. Only the machine language instruction with the earliest execution order can be issued.

  Therefore, since the data processing device is not configured to select and issue a machine language instruction from an arbitrary storage location, the delay time of instruction execution processing can be suppressed, and the operating frequency of the entire data processing device can be improved. There is an effect that can be.

  In addition, since only the register number is stored in the second instruction storage unit, the size of the storage area can be reduced.

  In the embodiment, when a description is given with a specific example, the data processing apparatus according to the embodiment describes a mode in which a process of simultaneously executing four instructions is processed. Of course, the number of instructions simultaneously executed by the data processing apparatus according to the embodiment is not limited to four, and may be more or less than four.

  In the embodiment, when a specific example is described, the data processing apparatus according to the embodiment performs an operation using a 3-operand instruction, that is, a value specified by two source registers. A mode of processing an instruction for storing the result in one destination register will be described.

  A data processing apparatus according to an embodiment of the present invention will be described below with reference to FIGS.

  A data processing apparatus 100 according to the present embodiment will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of a data processing apparatus 100 according to the present embodiment.

  The data processing apparatus 100 executes instructions through several stages. That is, first, after instruction fetch (IF) and instruction decode (HOST-D) (not shown), the Rename & Schedule stage 101 registers an instruction in which the register dependency between instructions is eliminated in a queue. Next, in the Dispatch & Read stage 102, an appropriate instruction is taken out from the queue. In the Execute stage 103, the calculation is executed. Finally, the register is updated (RETIRE) (not shown).

  Next, the configuration of the data processing apparatus 100 will be described. As shown in FIG. 1, the data processing apparatus 100 includes a decoding unit 110, a decoding storage unit 120, a dependency checking unit 130, a VLIW instruction queue 140, a reorder buffer 150, an input waiting register 170, an arithmetic unit 180, and an operation result storage unit. 191 to 194, a bypass 195, a tag update 196, a register write 197, a cache miss occurrence management unit 198, and an instruction registration delay unit 199.

  The decoding unit 110 decodes the source register number and the destination register number of each instruction by a general method. Then, a set of the source register number (s) and the destination register number (d) of each instruction after decoding is stored in the decode storage unit 120.

  The decode storage unit 120 holds a set of the source register number (s) and the destination register number (d) of each instruction decoded by the decode unit 110. That is, the decode storage unit 120 holds combinations 121 to 124 of s and d. As will be described later, it is desirable that each instruction is stored in the decode storage unit 120 in a state of being broken down into units completed in one cycle.

  The dependency checking unit 130 receives a set of the source register number (s) and the destination register number (d) of each decoded instruction held in the decoding storage unit 120 as an input, Remove register dependency. Then, a set of the source register number (S) and the destination register number (D) after the dependency relationship is canceled is output to the VLIW instruction queue 140 described later.

The dependency checking unit 130 transmits the execution order of instructions for which the dependency is canceled to a reorder buffer 150 (to be described later). The VLIW instruction queue 140 is a VLIW (very long instruction window) type queue. The pair of the source register number (S) and the destination register number (D) after the instruction dependency relationship is resolved is registered at an appropriate position in the queue by a method described later. Then, it waits until an instruction can be issued.

  The VLIW instruction queue 140 includes four queues. Each of the four queues registers an instruction to be input to each arithmetic unit. That is, the VLIW instruction queue 140 registers a queue 141 for registering an instruction to be input to the arithmetic logic unit 181, a queue 142 for registering an instruction to be input to the shift arithmetic unit 182, and an instruction to be input to the address calculator 183. And a queue 144 for registering instructions to be input to the cache 184. The detailed configuration of the VLIW instruction queue 140 will be described later.

  In the following, an instruction newly registered in the queue 141 is “instruction A”, an instruction newly registered in the queue 142 is “instruction B”, and an instruction newly registered in the queue 143 is “instruction C”. An instruction newly registered in the queue 144 is referred to as “instruction D”.

  The reorder buffer 150 holds the execution order of instructions. It also stores up to which instruction execution has been completed. For this purpose, the reorder buffer 150 receives and holds the register number of the instruction whose dependency relationship has been canceled from the dependency relationship checking unit 130. In addition, calculation results are received from calculation result storage units 191 to 194, which will be described later, and the fact that execution has been completed is managed for each register number. The reorder buffer 150 is used to guarantee a logically correct execution order regardless of whether a cache miss occurs in the cache 140 or the execution order is changed.

  The input waiting register 170 is a source register that is input to the arithmetic unit 180 and a register that stores an operation result of the instruction. For this purpose, the output of the source register number of entries 141 to 144 described later in the VLIW instruction queue 140 is connected to the input waiting register 170. The outputs of the calculation result storage units 191 to 194 are connected to the input waiting register 170 via a register write 197 described later.

  Note that source register values 175 to 178 of an instruction to be executed in the next cycle are output via the input wait register 170.

  The computing unit 180 includes four computing units. That is, the arithmetic unit 180 includes one arithmetic logic unit 181 (ALU), one shift arithmetic unit 182 (Shift), one address arithmetic unit 183 (Addr), and one cache 184 (Cache). Each of the arithmetic units performs a calculation using a value specified by the two operand registers, that is, two source registers, and stores the calculation result in the calculation result storage unit 190. It should be noted that all 4-operand and 5-operand operations are decomposed into three-operand methods and executed.

  Note that the arithmetic units included in the data processing apparatus 100 are not limited to the four types of arithmetic units. For example, another arithmetic logic unit or the like may be provided.

  The calculation result storage units 191 to 194 store the results calculated by the calculator 180. That is, the calculation result storage unit 191 stores the result calculated by the arithmetic logic unit 181. The calculation result storage unit 192 stores the result calculated by the shift calculator 182. The calculation result storage unit 193 stores the result calculated by the address calculator 183. The calculation result storage unit 194 stores the result calculated by the cache 184.

  The bypass 195 is a signal line that connects the operation result storage units 191 to 194 to the arithmetic logic unit 181, the shift operation unit 182, the address operation unit 183, and the cache 184 in order to use the result of the operation for the operation to be executed immediately after. It is.

  The tag update 196 is a signal line for connecting the operation result storage units 191 to 194 and the destination register numbers 171 to 174 of instructions scheduled to be executed in the next cycle to the VLIW instruction queue 140.

  Then, using the tag update 196, first, the source register number waiting in the VLIW instruction queue 140 is compared with the destination register numbers of the operation result storage units 191 to 194 in which the operation result of the preceding instruction is stored. . If the numbers match as a result of comparing them, it means that the operation of the preceding instruction using the source register used by the waiting instruction as the destination register is completed. Therefore, for example, a flag (for example, “1”) indicating that the value of the source register can be issued to the computing unit is set.

  Further, the tag update 196 is used to compare the source register number of the instruction waiting in the VLIW instruction queue 140 with the destination register numbers 171 to 174 of the instruction scheduled to be executed in the next cycle. If the numbers match as a result of comparing them, it means that an instruction using the source register used by the waiting instruction as the destination register is to be executed in the next cycle. In this case, a flag (for example, “1”) indicating that the value of the source register can be input to the arithmetic unit is set.

  Then, out of the instructions waiting in the VLIW instruction queue 140, an instruction having the flag “1” set in both of the two source registers is taken out. Then, as a register value corresponding to the extracted source register number, 1) an operation result of a preceding instruction stored in the input wait register 170, or 2) a destination register bypassed by a register write 197 described later One of the operation results stored in 191 to 194 is selected, and the source register values 175 to 178 of the instruction to be executed in the next cycle are set. The calculation result of 2) is preferentially selected.

  The register write 197 is a signal line for connecting the outputs of the calculation result storage units 191 to 194. In order to write the execution results stored in the operation result storage units 191 to 194 to the input wait register 170, and to bypass the execution results stored in the operation result storage units 191 to 194 in the cycle before writing. use.

  The cache miss occurrence management unit 198 manages an instruction that causes a cache miss in the cache 184. Then, based on the frequency of occurrence of cache misses, an instruction that is likely to cause a cache miss is predicted and transmitted to the instruction registration delay unit 199.

  The instruction registration delay unit 199 receives an instruction that is highly likely to cause a cache miss from the cache miss occurrence management unit 198. This delays the registration of the pair of the source register number (S) and the destination register number (D) in the VLIW instruction queue 140 for a predetermined period after the dependency relation of the instruction using the operation result of the instruction is resolved.

  Next, the VLIW instruction queue 140 will be described in detail with reference to FIG. FIG. 2 is a schematic block diagram showing the configuration of the VLIW instruction queue 140.

  As described above, the VLIW instruction queue 140 includes the queue 141, the queue 142, the queue 143, and the queue 144.

  Each of the queues 141 to 144 includes four entries so that four instructions scheduled to be input to the computing unit can be registered. That is, for example, the queue 141 includes entries 1411 to 1414. Similarly, the queue 142 includes entries 1421-1424. Similarly, the queue 143 includes entries 1431 to 1434. Similarly, queue 144 includes entries 1441-1444. Note that the number of entries is not limited to four, and may be more than four or fewer than four.

  Next, each entry includes three register holding units that hold register numbers. Specifically, each entry includes two source register holding units that hold source register numbers and one destination register holding unit that holds destination register numbers. For example, the entry 1411 includes source register holding units 151 and 155 and a destination register holding unit 159. Similarly, the entry 1412 includes source register holding units 152 and 156 and a destination register holding unit 160. Similarly, the entry 1413 includes source register holding units 153 and 157 and a destination register holding unit 160. Similarly, the entry 1414 includes source register holding units 154 and 158 and a destination register holding unit 162.

  Then, the instruction after the dependency relation cancellation output from the dependency relation inspecting unit 130 is registered in the entry determined by the new instruction registration control unit 301 described later. That is, the source register number (S) and the destination register number (D) of the instruction are registered in the source register holding unit and the destination register holding unit included in the determined entry.

  Then, the value held by each entry is shifted to a subsequent entry via a selector described later. For example, when an instruction held in the entry 1414 is issued and leaves the queue 141, the value held in the entry 1413 is shifted to the entry 1414 via the selector, and the value held in the entry 1412 is changed to the entry 1413 via the selector. The value held in the entry 1411 is shifted to the entry 1412 via the selector. Only the entry 1414 is connected to the input wait register 170, and the entries 1411 to 1413 are not connected to the input wait register 170. Compared with the wiring provided from all the entries in the reservation station 551 in the conventional data processing apparatus 500 to the arithmetic unit, the wiring in the data processing apparatus 100 is simplified.

  Since only the last entry is connected to the input waiting register 170, the newly registered instruction is not issued until the last entry 1414, 1424, 1434, 1444 is reached.

  Next, each of the entries 1414, 1424, 1434, and 1444 includes a flag indicating whether or not the two held source register numbers can be issued to the computing unit (not shown). For example, when the flag can be issued to the computing unit, the flag value is set to “1”. When it is first registered in the entries 1414, 1424, 1434, 1444, it cannot be issued to the calculator yet, so the value of each flag is set to “0”. When a predetermined condition (to be described later) is satisfied and can be issued to the computing unit, the value of each flag is set to “1”. Then, when both of the flag values of the two source register holding units belonging to the entry are “1”, it is issued to the arithmetic unit.

  Next, a condition for setting the value of the flag to “1” will be described. A tag update 196 is connected to each of the entries 1414, 1424, 1434, and 1444, and the destination register numbers of the operation result storage units 191 to 194 that store the operation result of the preceding instruction via the tag update 196. Is entered. Then, if any of the source register numbers held in the entries 1414, 1424, 1434, and 1444 is compared with the destination register numbers of the operation result storage units 191 to 194, if they match, the source register number is changed to the destination register number. This means that the operation of the preceding instruction used as the nation register number has been completed. In this case, an instruction that uses the source register number may be registered in the input wait register 170. Therefore, the value of the flag corresponding to the source register number that matches the above value is set to “1”.

  Further, even when other conditions are satisfied, the value of the flag is set to “1”, which will be described below.

  When the destination register number to which the execution result of the preceding instruction is written is used as the source register number by the subsequent instruction executed immediately after the preceding instruction, if the preceding instruction completes execution in one cycle, the preceding instruction Is input to the arithmetic unit 180 (that is, without waiting for completion of execution of the preceding instruction), when the subsequent instruction is registered in the input wait register 170, the subsequent instruction can be issued one cycle earlier.

  Therefore, the destination register numbers 171 to 174 of the instruction to be executed in the next cycle are input to each of the entries 1414, 1424, 1434, and 1444 through the tag update 196. If any of the source register numbers held by the entries 1414, 1424, 1434, and 1444 is compared with the destination register numbers 171 to 174, if they match, the source register used by the waiting instruction is determined. This means that the instruction used as the destination register is to be executed in the next cycle. In this case, an instruction that uses the source register number may be registered in the input wait register 170. Therefore, the value of the flag corresponding to the source register number that matches the above value is set to “1”.

  In order to satisfy the above condition, it is necessary to reliably execute an instruction scheduled to be executed in the next cycle in the next cycle. Therefore, it is desirable that each instruction is stored in the decode storage unit 120 in a state of being decomposed into units that are completed in one cycle. Even if the instructions are decomposed, the instruction execution order is maintained in the reorder buffer 150, so that the instruction execution order is maintained.

  Next, the queue 141 will be described in detail with reference to FIG. FIG. 3 is a schematic wiring diagram showing the configuration of the queue 141.

  As shown in FIG. 3, the queue 141 includes the source register holding units 151 to 158, the destination register holding units 159 to 162, the selectors 201 to 212, the destination register value transmission units 215 to 218, the source shown in FIG. A destination dependency checking unit 231 to 262, a source / destination dependency checking unit 271 to 274, and a new instruction registration control unit 301 to be described later. A new command registration control unit 301 to be described later is illustrated in FIG. 7, not illustrated in FIG. 3.

  Each of the source register holding units 151 to 154 holds the source register number 1211 output from the dependency checking unit 130 or the previous source register holding unit. Each of the source register holding units 155 to 158 holds the source register number 1212 output from the dependency checking unit 130 or the previous register holding unit.

  Next, each of the destination register holding units 159 to 162 holds the destination register number 1213 output from the dependency checking unit 130 or the previous destination register holding unit.

  The selectors 201 to 212 determine whether a new instruction is newly registered in the register holding unit or whether a value held in the previous register holding unit is shifted to the subsequent register holding unit. The selection is made based on the signal from the unit 301. For this purpose, the selectors 201 to 212 are connected to the output from the dependency checking unit 130 and the output from the previous register holding unit. The outputs of the selectors 201 to 212 are connected to a subsequent register holding unit. Therefore, either the output from the dependency checking unit 130 or the output from the previous register holding unit is selected and output to the subsequent register holding unit. 2, only the output is input from the dependency checking unit 130 because there is no register holding unit in the preceding stage.

  For example, the selector 204 receives the source register number of the new instruction output from the dependency relationship checking unit 130 and the source register number of the preceding instruction held in the source register holding unit 151. Then, either of them is output and input to the source register holding unit 152.

  Next, if there is a dependency between the instruction newly registered in the register holding unit and the preceding instruction registered in the register holding unit, the new instruction must be executed after executing the preceding instruction. Don't be. In this case, an instruction newly registered in the register holding unit needs to be registered in a register holding unit at a stage preceding the register holding unit in which the preceding instruction is already registered.

  Therefore, the register dependency between the new instruction and the preceding instruction is checked. For this purpose, first, the destination register value transmission unit 215 to 218 uses the destination register number already registered in the register holding unit as the 231 and 235 among the source / destination dependency checking units 231 to 262 described later. 239, 243, 247, 251, 255, 259.

  Next, the source / destination dependency checking unit 231 to 262 calculates the destination register number of the preceding instruction already registered in the register holding unit and the source register number of the instruction newly registered in the register holding unit. Check dependencies.

  For this purpose, first, the source / destination dependency checking unit 231, 235, 239, 243, 247, 255, 259 performs the source address number of the instruction A output from the dependency checking unit 130 and the destination register. The destination register number of the preceding instruction registered in the register holding unit and transmitted from the value transmission units 215 to 218 is input. Then, the dependency between the inputs is checked.

  Specifically, if the source register number and the destination register number match, a signal indicating that there is a dependency relationship (for example, a value “1”) is output. On the other hand, if they do not match, a signal indicating that there is no dependency (for example, a value “0”) is output.

  As a result, the dependency relationship between the instruction A input to the arithmetic logic unit 181 and its preceding instruction is checked.

  Further, the source / destination dependency checking units 232, 236, 240, 244, 248, 252, 256, 260 transmit signals from destination register value transmitting units 219 to 222 provided in the queue 142, which will be described later. As input. Thereby, the dependency relationship between the instruction A input to the arithmetic logic unit 181 and the preceding instruction input to the shift calculator 182 is checked.

  Similarly, the source / destination dependency checking units 233, 237, 241, 245, 249, 253, 257, and 261 are transmitted from destination register value transmitting units 223 to 226 provided in the queue 143, which will be described later. The signal is input. Thus, the dependency relationship between the instruction A input to the arithmetic logic unit 181 and the preceding instruction input to the address calculator 183 is inspected.

  Similarly, the source / destination dependency checking unit 234, 238, 242, 246, 250, 254, 258, 262 is transmitted from a destination register value transmitting unit 227 to 230 provided in the queue 144, which will be described later. The signal is input. Thereby, the dependency relationship between the instruction A input to the arithmetic logic unit 181 and the preceding instruction input to the cache 184 is checked.

  Next, it is impossible to determine whether or not a new instruction may be registered in the register holding unit only from the result of the source / destination dependency checking unit 231 to 262 independently checking whether or not there is a dependency. That is, if at least one of the two source register numbers of the instruction newly registered in the register holding unit matches one of the destination register numbers of the preceding instruction already registered in the register holding unit, There is a dependency between an instruction registered in the register holding unit and a preceding instruction already registered in the register holding unit. Therefore, it is necessary to compare the two source register numbers of the instruction newly registered in the register holding unit with all the destination register numbers of the preceding instructions already registered in the register holding unit.

  For this purpose, the source / destination dependency inspection unit 271 to 274 receives the output values of the source / destination dependency inspection units 231 to 238, 239 to 246, 247 to 254, and 255 to 262, respectively. Output logical sum.

  For example, the source / destination dependency relation inspection aggregation unit 271 will be described as an example. When at least one of the output values of the source / destination dependency checking units 231 to 238 is “1” (that is, there is a dependency), the source / destination dependency checking unit 271 outputs the value “1”. . On the other hand, when the output values of the source / destination dependency checking units 231 to 238 are all “0” (that is, there is no dependency), the source / destination dependency checking unit 271 outputs the value “0”. . Similarly, the value “1” or “0” is output also to the source / destination dependency inspection aggregation units 272 to 274.

  Then, the output values of the source / destination dependency relation inspection aggregation units 271 to 274 are input to a new instruction registration control unit 301 described later.

  As described above, the dependency between the instruction newly registered in the register holding unit and the preceding instruction registered in the register holding unit should be checked by the source / destination dependency checking / aggregating units 271 to 274. Can do. However, if there is also a dependency relationship between newly registered instructions, it is necessary to determine an appropriate register holding unit for registering a new instruction in consideration of the dependency relationship. For this purpose, a new instruction registration control unit 301 described later appropriately controls the selectors 201 to 212 to register a new instruction.

  Next, the queues 142 to 144 will be described with reference to FIGS. 4 to 6 are schematic wiring diagrams showing configurations of the queues 142 to 144. FIG.

  4 to 6, the configuration of the queues 142 to 144 includes the same members as the queue 144 illustrated in FIG. 3. However, the installation locations of the destination register value transmission units 219 to 230 are different.

  Next, input / output signals for the new instruction registration control unit 301 will be described with reference to FIG. FIG. 7 is a schematic wiring diagram showing input / output of the new command registration control unit 301.

  As shown in FIG. 7, the inputs to the new instruction registration control unit 301 include signals 311 to 314 from the source / destination dependency relation check aggregation units 271 to 274 and signals 315 from the source register holding units 151 to 158. 319, a signal 320 from the dependency checking unit 130, and a signal 330 from a new command registration control unit (not shown) provided in the queues 142 to 144 and having the same configuration as the new command registration control unit 301 Is included.

  The output of the new instruction registration control unit 301 includes signals 345 to 348 to the selectors 201 to 212 and a signal 350 to the new instruction registration control unit provided in the queues 142 to 144.

  As described above, the signals 311 to 314 from the source / destination dependency checking / aggregating units 271 to 274 are the signals of the source / destination dependency checking units 231 to 238, 239 to 246, 247 to 254, and 255 to 262, respectively. It is the logical sum of the output values.

  Signals 315 to 319 from the source register holding units 151 to 158 are signals indicating whether or not there is a vacancy in the source register holding units 151 to 158, that is, whether or not a value is registered in the source register holding units 151 to 158. .

  For example, the signal 315 indicates whether any of the source register holding units 151 and 155 is free. For example, the value is set to “1” when there is no empty space.

  The signal 320 is a signal indicating a dependency relationship between newly registered instructions, and is obtained from the dependency relationship inspecting unit 130. Specifically, it is a time interval required between instructions when a new instruction X and a new instruction Y are executed. For example, when the instruction Y may be executed one cycle after the instruction X is executed, the value of the signal 320 is “1”. For example, when it is necessary to execute the instruction Y two cycles after the execution of the instruction X, the value of the signal 320 is “2”. Note that the signal 320 can be calculated by a mechanism that the dependency checking unit 130 conventionally includes. In FIG. 7, the signal 320 is shown by a single signal line, but is composed of a plurality of signal lines as will be described later.

  The signal 330 is output by the new instruction registration control unit provided in the queues 142 to 144. The signal 330 is a signal indicating to which of the entries in the queues 142 to 144 the instructions B, C, and D are registered. Restriction when determining which entry of the queue 141 is to register the instruction A Use as information. In FIG. 7, the signal 330 is shown by one signal line, but is composed of a plurality of signal lines as will be described later.

  Signals 345 to 348 to the selectors 201 to 212 are signals for controlling each selector according to which register holding unit a new instruction is registered.

  A signal 350 is a signal to be input to the new instruction registration control unit provided in the queues 142 to 144. This signal indicates to which entry the instruction A is registered, and is used as constraint information when determining which entry the instructions B, C, and D are registered to. In FIG. 7, the signal 350 is shown by a single signal line, but is composed of a plurality of signal lines as will be described later.

  Next, the configuration of the new instruction registration control unit 301 will be described in detail with reference to FIG. FIG. 8 is a schematic wiring diagram showing the configuration of the new command registration control unit 301. As illustrated in FIG. 8, the new instruction registration control unit 301 includes registration entry determination units 401 to 404 and constraint information generation units 410, 420, and 430.

  The registered entry determination units 401 to 404 determine which of the entries 1411 to 1414 a new command is registered to control the selectors 201 to 212. For this purpose, the signals 311 to 314 from the source / destination dependency relation check aggregation units 271 to 274, the signals 331 to 342 output by the new instruction registration control unit provided in the queues 142 to 144, and the source register holding unit 151 to Signals 315 to 319 indicating 158 vacancy are input.

  Here, the signals 331 to 342 input to the registration entry determination units 401 to 404 are the details of the signal 330 shown in FIG. 7, and the new instruction registration control unit provided in the queues 142 to 144 outputs Signal. Specifically, the value of the signal 331 is “1” when the new instruction registration control unit provided in the queue 142 registers a new instruction in the entry 1421. The value of the signal 332 is “1” when the new instruction registration control unit provided in the queue 142 registers a new instruction in the entry 1422. The value of the signal 333 is “1” when the new instruction registration control unit provided in the queue 142 registers a new instruction in the entry 1423. The value of the signal 334 is “1” when the new instruction registration control unit provided in the queue 142 registers a new instruction in the entry 1424.

  Similarly, the values of the signals 335 to 338 are “1” when the new instruction registration control unit provided in the queue 143 registers new instructions in the entries 1431 to 1434, respectively. Similarly, the values of the signals 339 to 342 are “1” when the new instruction registration control unit provided in the queue 144 registers new instructions in the entries 1441 to 1444, respectively.

  Next, taking the registration entry determination unit 401 as an example, a process for determining whether or not to register an entry will be specifically described.

  The registration entry determination unit 401 receives a signal 311, a signal 331, a signal 335, a signal 339, and a signal 315. First, as described above, the presence / absence of a dependency relationship with an instruction already registered in the entry 1411 or the entry 1421 or the entry 1431 or the entry 1441 can be determined from the value of the signal 311. If there is a dependency, the value of the signal 311 is “1”.

  Further, as described above, the values of the signal 331, the signal 335, and the signal 339 can be used to determine whether another instruction to be newly registered is registered in the entry 1421, the entry 1431, and the entry 1441. When registered, the values of the signal 331, the signal 335, and the signal 339 are “1”.

  The value of the signal 315 can be used to determine whether or not the source register holding units 151 and 155 are free. If there is no space, the value is “1”.

  Therefore, if the value of the logical sum of the signal 311, the signal 331, the signal 335, the signal 339, and the signal 315 is “1”, the registration entry determination unit 401 determines that a new instruction cannot be registered in the entry 1411. To do. On the other hand, if the value of the logical sum of the signal 311, the signal 331, the signal 335, the signal 339, and the signal 315 is “0”, the registration entry determination unit 401 determines that a new instruction can be registered in the entry 1411. To do.

  The registered entry determination units 402 to 404 perform the same processing as described above. However, if there is a dependency relationship in the entry in the previous stage, the instructions B, C, and D must not be registered in the entry in the subsequent stage, and if any of the instructions B, C, and D is registered in the preceding stage, Do not register new commands after that. Therefore, all the signals input to the registration entry determination unit in the preceding stage are input to the registration entry determination unit in the subsequent stage, except for the signals 315 to 319 indicating empty. For example, the registration entry determination unit 404 receives signals 311 to 315, signals 331 to 342, and a signal 319.

  In addition, as a result of each registration entry determination unit 401-404 determining whether or not a new command can be registered, two or more registration entry determination units may determine that a new command can be registered. Here, it is desirable that the waiting period from when a new instruction is registered in the entry to when it is issued to the arithmetic unit is short. Therefore, in the above case, priority is given to the determination that the registration entry determination unit at the last stage can be registered, and the other registration entry determination units determine again that registration is impossible.

  Based on the determination, the registration entry determination units 401 to 404 output signals 345 to 348 to the selectors 201 to 212, respectively, and control the selectors. It should be noted that the registration entry determination unit that has been determined to be registerable outputs the value “1”, and the registration entry determination unit that has been determined not to register outputs the value “0”.

  Next, the constraint information generation unit 410 is provided in the queue 142 based on the dependency relationship between the instruction A registered in the entry determined by the registration entry determination units 401 to 404 and the instruction B registered in the queue 142. The constraint information is output to the new command registration control unit.

  Therefore, the constraint information generation unit 410 includes entry constraint information generation units 411 to 414. The entry constraint information generation units 411 to 414 output signals from the registered entry determination units 401 to 404 and signals 3201 to 3204 indicating dependency relationships between the command A and the command B transmitted from the dependency relationship checking unit 130. As inputs.

  Here, the signals 3201 to 3204 show a part of the signal 320 shown in FIG. 7 in detail. Specifically, if it is necessary to execute the instruction B one cycle or more after the instruction A is executed, the value of the signal 3201 is “1”; otherwise, the value of the signal 3201 is “0”. " If instruction B needs to be executed after two cycles after executing instruction A, the value of signal 3202 is “1”; otherwise, the value of signal 3202 is “0”. . In addition, if it is necessary to execute the instruction B three or more cycles after executing the instruction A, the value of the signal 3203 is “1”, otherwise, the value of the signal 3203 is “0”. . If instruction B needs to be executed four or more cycles after executing instruction A, the value of signal 3204 is “1”, otherwise the value of signal 3204 is “0”. .

  Similarly, signals 3205 to 3208 indicate that the difference between the cycles in which the instructions A and C are executed is 1 to 4, and the signals 3209 to 3212 indicate the cycles in which the instructions A and D are executed. It is a signal which shows that a difference is 1-4. Note that a signal indicating that the execution cycle difference between instructions is 5 or more is not shown.

  Next, taking the entry constraint information generation unit 414 as an example, the processing for generating constraint information will be specifically described. The entry constraint information generation unit 414 generates information indicating whether or not the instruction B may be registered in the entry 1424.

  For example, if the instruction A is registered in the entry 1414 and there is a restriction that the instruction B must be executed at least one cycle after the instruction A, the instruction B should not be registered in the entry 1424. Therefore, in this case, the entry constraint information generation unit 414 generates information indicating that the instruction B should not be registered in the entry 1424. On the other hand, in cases other than the above, the instruction B may be registered in the entry 1424. In this case, the entry constraint information generation unit 414 does not generate information indicating that the instruction B should not be registered in the entry 1424.

  For this purpose, the entry constraint information generation unit 414 receives the output signal from the registered entry determination unit 404 and the signal 321 and outputs a logical product of them. As a result, the value of the output signal from the registered entry determination unit 404 is “1” (that is, the instruction A is registered in the entry 1414), and the value of the signal 321 is “1” (that is, the instruction A is executed). The value of the output signal 3504 of the entry constraint information generation unit 414 is “1”. On the other hand, if either the value of the output signal from the registered entry determination unit 404 or the value of the signal 321 is “0”, the value of the output signal 3504 of the entry constraint information generation unit 414 is “0”.

  Subsequently, the entry constraint information generation unit 413 is taken as an example to specifically describe the processing for generating constraint information. The entry constraint information generation unit 413 generates information indicating whether or not the instruction B may be registered in the entry 1423. At this time, the entry constraint information generation unit 413 must consider both the case where the instruction A is registered in the entry 1414 and the case where the instruction A is registered in the entry 1413.

  For example, if the instruction A is registered in the entry 1414 and there is a restriction that the instruction B must be executed two or more cycles after the instruction A, the instruction B should not be registered in the entry 1423. In this case, the entry constraint information generation unit 413 generates information indicating that the instruction B should not be registered in the entry 1423. Further, if the instruction A is registered in the entry 1413 and there is a restriction that the instruction B must be executed one cycle or more after the instruction A, the instruction B should not be registered in the entry 1423. In this case, the entry constraint information generation unit 413 generates information indicating that the instruction B should not be registered in the entry 1423.

  On the other hand, in cases other than the above, the instruction B may be registered in the entry 1423. In this case, the entry constraint information generation unit 413 does not generate information indicating that the instruction B should not be registered in the entry 1423.

  For this purpose, the entry constraint information generation unit 413 receives the output signals from the registered entry determination units 403 and 404 and the signals 321 and 323. Then, a logical sum of the logical product of the signal from the registration entry determination unit 403 and the signal 321 and the logical product of the signal from the registration entry determination unit 404 and the signal 322 is output.

  As a result, the value of the output signal from the registered entry determination unit 403 is “1” (that is, the instruction A is registered in the entry 1413), and the value of the signal 321 is “1” (that is, the instruction A is executed). The instruction B may be executed after one cycle), or the value of the output signal from the registered entry determination unit 404 is “1” (that is, the instruction A is registered in the entry 1414), When the value of the signal 322 is “1” (that is, the instruction B may be executed two cycles after the execution of the instruction A), the value of the output signal 3503 of the entry constraint information generation unit 413 is “1”. Become. On the other hand, in cases other than the above, the value of the output signal 3503 of the entry constraint information generation unit 413 is “0”.

  The entry constraint information generation units 411 and 412 also output signals 3501 and 3502 with the same configuration.

  The signals 3501 to 3504 output from the entry constraint information generation units 411 to 414 are input as constraint information to the new command registration control unit provided in the queue 142 for registering the command B.

  Next, the constraint information generation unit 420 is provided in the queue 143 based on the dependency relationship between the instruction A registered in the entry determined by the registration entry determination units 401 to 404 and the instruction C registered in the queue 143. The constraint information is output to the new command registration control unit.

  Therefore, the constraint information generation unit 420 has the same configuration as that of the constraint information generation unit 410 (not shown). Then, the output signals from the registered entry determination units 401 to 404 and the signals 3205 to 3208 indicating the dependency relationship between the command A and the command C transmitted from the dependency relationship checking unit 130 are input to the queue 143. Signals 3505 to 3508 serving as constraint information for the new command registration control unit provided are output.

  Similarly, the constraint information generation unit 430 is provided in the queue 144 based on the dependency relationship between the instruction A registered in the entry determined by the registration entry determination units 401 to 404 and the instruction D registered in the queue 144. The constraint information is output to the new command registration control unit.

  For this purpose, the constraint information generation unit 430 has a configuration similar to that of the constraint information generation unit 410 (not shown), and is transmitted from the output signals from the registered entry determination units 401 to 404 and the dependency relationship inspection unit 130. The signals 3209 to 3212 indicating the dependency relationship between the instruction A and the instruction D are input, and signals 3509 to 3512 serving as constraint information for the new instruction registration control unit provided in the queue 144 are output.

  With the above configuration, when a new instruction is registered in the VLIW instruction queue 140, the instruction level parallel execution scheduling is performed using the dependency relation between the instructions.

  In the above, the new instruction registration control unit 301 receives the constraint information from the new instruction registration control unit provided in the queues 142 to 144 as input, and sends the constraint information to the new instruction registration control unit provided in the queues 142 to 144. However, the dependency checking unit 130 eliminates the register dependency between instructions, and it is guaranteed that no loop occurs in the dependency between instructions. Convergence is guaranteed.

  As described above, since the data processing apparatus 100 according to the present embodiment is configured to include the VLIW instruction queue 140, the reservation station 551 and the forwarding 590 in the conventional data processing apparatus 500 are unnecessary. Therefore, since the reservation station 551 and the forwarding 590 having a complicated configuration do not exist, power consumption can be suppressed.

  Further, in the Dispatch & Read stage 102, an instruction that can be issued is not selected from an arbitrary entry in the VLIW instruction queue 140, but an instruction is always issued only from the last entry. Therefore, the Dispatch & Read stage 102 does not need to include the associative search mechanism implemented in the Select & Read stage 507 in the conventional data processing apparatus 505. Therefore, in the Dispatch & Read stage 102, since the processing delay time is shorter than in the conventional case, the operating frequency of the data processing apparatus 100 according to the present embodiment can be improved.

  Note that instructions are issued only from the last entry of the VLIW instruction queue 140, but register renaming is performed by the dependency checking unit 130 and cache miss is detected in the cache 184. Even if a mistake is detected, the issue of the instruction is not immediately stopped. That is, when an instruction existing in the last entry of the VLIW instruction queue 140 does not use cache missed data, the instruction is issued regardless of the cache miss. When the subsequent instruction using the cache-missed data reaches the last entry in the VLIW instruction queue 140, the subsequent instruction is not issued until the cache-missed data is cached.

  In order to mitigate the occurrence of a cache miss, the cache miss occurrence management unit 198 predicts an instruction that is likely to cause a cache miss, and the instruction registration delay unit 199 displays the instruction and the operation result of the instruction. An interval for executing a command to be used is set at a predetermined interval and registered in the VLIW command queue 140. Thereby, an instruction level parallelism comparable to that of the superscalar method can be achieved.

  In the above-described embodiment, the data processing apparatus 100 is configured to include one decode storage unit 120, but is not limited to the above-described configuration, and may include a plurality of decode storage units. In this case, by further providing a plurality of program counters corresponding to the plurality of decode storage units 120, when there are a plurality of instruction streams (that is, a series of instruction groups to be executed continuously), they are mixedly executed. This will be described below.

  For example, a case where the data processing apparatus 100 is configured to further include another decode storage unit 120a in addition to the decode storage unit 120 will be described below. Further, it is assumed that the data processing apparatus 100 includes a program counter P1 corresponding to the decode storage unit 120 and a program counter P2 corresponding to the decode storage unit 120a.

  In this case, for example, the instruction stream Q1 including the instruction A1, the instruction B1, and the instruction C1 is stored in the decode storage unit 120, while the instruction stream Q2 including the instruction A2, the instruction B2, and the instruction C2 is stored in the decode storage unit 120a. Store. The instruction stored in the decode storage unit 120 is registered in the VLIW instruction queue 140 via the dependency checking unit 130 according to the program counter P1. At the same time, the instruction stored in the decode storage unit 120a is registered in the VLIW instruction queue 140 via the dependency checking unit 130 according to the program counter P2.

  Thereby, the instruction A1, the instruction B1, and the instruction C1 included in the instruction stream Q1 and the instruction A2, the instruction B2, and the instruction C2 included in the instruction stream Q2 can be registered in a mixed state in the VLIW instruction queue 140. Therefore, two different instruction streams Q1 and Q2 can be mixed and issued to the computing unit.

Note that when a plurality of instruction streams are composed of instructions conforming to different machine language instructions, they cannot be mixed in the VLIW instruction queue 140 as described above. In this case, the data processing apparatus 100 may further include a configuration for converting different machine language instructions into predetermined machine language instructions. That is, it is converted into a predetermined machine language instruction that can be registered in the VLIW instruction queue 140 and then registered in the VLIW instruction queue 140. As a result, even when there are a plurality of instruction streams composed of instructions conforming to different machine language instructions, they can be executed together.
(Additional notes)
In addition to the above, the embodiment can be expressed as follows.

[1] A data processing apparatus according to the present invention is a data processing apparatus that simultaneously interprets and executes a plurality of machine language instructions, a first storage device that stores a plurality of machine language instructions that are simultaneously interpreted and executed, and a time series A second storage device storing a plurality of machine language instructions to be executed and respective empty states, a third storage device storing a plurality of registers specified by a source operand and a destination operand, and a source operand A fourth arithmetic unit that performs an operation using the value of the register specified by the first operand, information on source operand fields belonging to a plurality of instruction words stored in the first storage device, and the second storage device A plurality of devices stored in the first storage device based on free space information stored in the storage device and destination operand information stored in the second storage device. Determining a time at which a word instruction is to be executed, and storing a plurality of machine language instructions stored in the first storage device in an empty position corresponding to the time in the second storage device, Also good.

  [2] The data processing apparatus according to the present invention further includes a READY bit indicating whether or not the source operand is in an available state for each source operand of each instruction of the second storage device, Source operands belonging to a machine language instruction when all the READY bits belonging to a set of machine language instructions with the earliest execution time among the plurality of machine language instructions stored in the storage device 2 are satisfied The source operand stored in the third storage device may be read using field information.

  [3] Furthermore, when the data processing device according to the present invention stores an instruction word from the first storage device to the second storage device, the instruction stored in the second storage device A set of machine language instructions with the earliest designated execution time among a plurality of machine language instructions stored in the second storage device by resetting the READY bit for a source operand that depends on a word destination operand When the source operand stored in the third storage device is read using the information in the source operand field belonging to, the destination operand information to be written by the instruction and the second operand are stored in the second storage device The source operand information belonging to the machine language instruction to be matched is compared, and if it matches, the READY bit of the source operand is set. May be.

  [4] Furthermore, the data processing device according to the present invention includes a destination operand information to be written by the instruction and a machine language stored in the second storage device at the completion of the operation of the fourth arithmetic device. The source operand information belonging to the instruction may be compared and, if they match, the READY bit of the source operand may be set.

  [5] Furthermore, the data processing apparatus according to the present invention may perform register renaming.

  [6] Furthermore, the data processing device according to the present invention determines a time at which a plurality of machine language instructions stored in the first storage device should be executed, and a plurality of storage units stored in the first storage device. The storage of the machine language instruction in the empty position corresponding to the time in the second storage device may be corrected using the register renaming information.

  [7] Furthermore, the data processing device according to the present invention completes the issuance of an instruction from the second storage device even when an execution delay occurs in the fourth arithmetic unit, and the execution delay is the fourth arithmetic unit. It may be retained in a vessel.

  [8] Furthermore, the data processing device according to the present invention may be configured such that when an execution delay is expected to occur in the fourth arithmetic unit, the first storage device to the second storage device. When a machine language instruction is stored, subsequent instructions depending on the delayed machine language instruction may be stored at a designated time position separated by an appropriate distance using a designated execution time difference.

  [9] Furthermore, the data processing apparatus according to the present invention, after decomposing an original machine language instruction into a simple machine language instruction set so that the machine language instruction is executed every cycle in the computing unit, A machine language instruction may be set in the storage device.

  [10] The data processing apparatus according to the present invention further includes a reorder buffer that ensures that the machine language instructions stored in the second storage device are executed in a logically correct order. Also good.

  [11] Furthermore, the data processing device according to the present invention comprises a plurality of sets of the first storage device and the program counter, and is designated by a plurality of program counters for only one second storage device. A plurality of instruction streams may be simultaneously executed by simultaneously storing instruction words belonging to a plurality of instruction streams.

  [12] Further, the data processing apparatus according to the present invention includes a plurality of mechanisms for converting different machine language instructions into a common machine language instruction suitable for the single second storage device, and having different instruction sets. A plurality of compliant instruction streams may be executed simultaneously.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be suitably used for a data processing apparatus that simultaneously executes a plurality of machine language instructions at high speed.

It is a block diagram which shows the principal part structure of the data processor which is one Embodiment of this invention. FIG. 2 is a block diagram showing a main configuration of a VLIW instruction queue in the data processing apparatus shown in FIG. 1. FIG. 3 is a block diagram showing a main configuration of a queue in the VLIW instruction queue shown in FIG. 2. FIG. 4 is a schematic wiring diagram showing a main configuration of the queue shown in FIG. 3. FIG. 4 is a schematic wiring diagram showing a main configuration of the queue shown in FIG. 3. FIG. 4 is a schematic wiring diagram showing a main configuration of the queue shown in FIG. 3. FIG. 4 is a schematic wiring diagram showing input / output of a new instruction registration control unit in the queue shown in FIG. 3. FIG. 8 is a schematic wiring diagram showing a main configuration of a new command registration control unit shown in FIG. 7. It is a block diagram which shows each stage of a general pipeline. It is a block diagram which shows the principal part structure of the conventional data processor. It is a block diagram which shows the principal part structure of the other conventional data processing apparatus.

Explanation of symbols

100 Data Processing Device 110 Decoding Unit 120 Decoding Storage Unit (First Instruction Storage Unit)
130 dependency checking unit
140 VLIW instruction queue (second instruction storage means)
150 Reorder buffer 170 Input wait register (third instruction storage means)
180 arithmetic unit (command arithmetic means)
195 Bypass 196 Tag update 198 Cache miss occurrence management unit 199 Instruction registration delay unit 215 to 230 Destination register value transmission unit 231 to 262 Source / destination dependency check unit 271 to 274 Source / destination dependency check check unit 301 New Command registration control unit (new command registration control means)
401 to 404 Registered entry determining units 410 to 430 Constraint information generating units 411 to 414 Entry constraint information generating units

Claims (13)

A plurality of machine language instructions including a source operand field for designating a source register number for storing a value used for a predetermined operation and a destination operand field for designating a destination register number for storing the result of the operation are simultaneously provided. A data processing device for interpreting and executing,
First instruction storage means for storing a pair of a source register number specified by a source operand field and a destination register number specified by a destination operand field, included in the plurality of machine language instructions;
A machine including a combination of a plurality of source register numbers and destination register numbers acquired from the first instruction storage means, a source operand field for designating the source register number, and a destination operand field for designating the destination register number Second instruction storage means for storing empty information in a storage position that stores a set of the source register number and the destination register number in a predetermined storage position corresponding to the execution order of the word instructions;
The value of the source register specified by the source operand field included in the machine language instruction with the earliest execution order stored in the second instruction storage means and the destination operand field included in the machine language instruction are specified. Third instruction storage means for storing the destination register number,
A plurality of instructions that perform a predetermined operation based on the value of the source register acquired from the third instruction storage unit and store the operation result in a register specified by the destination register number acquired from the third instruction storage unit An arithmetic means,
When the source register number acquired from the first instruction storage means depends on the destination register number stored in the second instruction storage means, the second operand storing means designates the source register number. The execution order of the machine language instruction including the field is determined to be later than the execution order of the machine language instruction including the destination operand field for specifying the destination register number, and the storage position is in accordance with the determined execution order. The destination register specified by the source operand number included in the machine language instruction including the source operand field and the source register number specified by the source operand field at the storage location where the empty information is stored With the number The data processing apparatus characterized by storing. The second instruction storage means includes, for each source register number to be stored, information indicating whether or not the value of the source register can be input to the instruction calculation means.
When all the availability information of the source register number specified by the source operand included in the machine language instruction with the earliest execution order stored in the second instruction storage means can be entered, the value of the source register is The data processing apparatus according to claim 1, wherein the data processing apparatus is obtained and stored in a third instruction storage unit. When the source register number acquired from the first instruction storage means depends on the destination register number stored in the second instruction storage means, the second instruction storage means displays whether the source register number can be entered. Set to impossible
The second instruction storage means acquires the value of the source register specified by the source operand field included in the machine language instruction that has been stored in the second instruction storage means and has the earliest execution order, and stores the third instruction. When storing in the means, the destination register number specified by the destination operand field included in the machine language instruction is compared with the source register number in which the input enable / disable information is set to input impossible, and the destination register number 2. The data processing apparatus according to claim 1, wherein when the source register number and the source register number coincide with each other, the input enable / disable information of the source register number is set to enable input.   When the instruction operation means stores the operation result in the register designated by the destination register number acquired from the third instruction storage means, the destination register number and the source register already stored in the second instruction storage means 2. The data processing apparatus according to claim 1, wherein when the destination register number and the source register number coincide with each other, the information on whether or not the source register number is input is set as input possible. . Dependency elimination means for obtaining a set of a plurality of source register numbers and destination register numbers from the first instruction storage means and eliminating the dependence relationship between the source register numbers and the destination register numbers is further provided. ,
2. The data processing apparatus according to claim 1, wherein the second instruction storage unit acquires a set of a plurality of source register numbers and destination register numbers from which the dependency relationship has been canceled from the dependency relationship canceling unit. .   When the second instruction storage means stores a set of a plurality of source register numbers and destination register numbers acquired from the first instruction storage means, the source register number and destination register acquired from the dependency relationship cancellation means The execution order of machine language instructions including the source operand field that specifies the source register number and the destination operand number that specifies the destination register number included in the multiple sets is determined based on the dependency relationship between the numbers. A new instruction registration control means for storing a set of the plurality of source register numbers and destination register numbers in a storage position corresponding to the determined execution order and storing the empty information. The data according to claim 5, further comprising: Management apparatus.   Even when the operation result in the instruction operation means cannot be stored in the register in one cycle, it is specified by the source operand included in the machine language instruction stored in the second instruction storage means and having the earliest execution order. All of the source register number input availability information can be entered, and when any of the source register numbers does not depend on the destination register number that could not store the operation result, the value of the source register, 2. The data processing apparatus according to claim 1, wherein a destination register number designated by a destination operand field included in the machine language instruction is stored in a third instruction storage means. The source register number of the set of the source register number and the destination register number acquired by the second instruction storage means from the first instruction storage means cannot store the operation result in the instruction operation means in one cycle. When depending on the expected destination register number, the execution order of the machine language instruction including the source operand field for specifying the source register number and the destination operand field for specifying the destination register number is set to 1 as the result of the operation. The order is determined to be slower by a predetermined order than the execution order of machine language instructions including the destination operand field that specifies the destination register number that is expected to be unable to be stored in the cycle,
2. The set of the source register number and the destination register number is stored in a storage position corresponding to the determined execution order and a storage position where empty information is stored. Data processing equipment.   The first instruction storing means stores a set of a source register number specified by a source operand field included in a machine language instruction executable in one cycle and a destination register number specified by a destination operand field. The data processing apparatus according to claim 1.   The pair of the source register number specified by the source operand field included in the machine language instruction and the destination register number specified by the destination operand field is managed according to the execution order of the machine language instruction, and the execution is completed. 2. A reorder buffer for managing a set of a source register number specified by a source operand field included in a machine language instruction and a destination register number specified by a destination operand field. The data processing apparatus described in 1. A plurality of first instruction storage means;
2. The second instruction storing means stores a set of a plurality of source register numbers and destination register numbers acquired from the plurality of first instruction storing means in a mixed state. Data processing equipment.   When a set of a plurality of source register numbers and destination register numbers stored in the plurality of first instruction storage means is not in a format that can be stored in the second instruction storage means, the second instruction storage means 2. The set of a plurality of source register numbers and destination register numbers acquired from a plurality of first instruction storage means is converted into a format that can be stored in the second instruction storage means. Data processing device. A plurality of machine language instructions including a source operand field for designating a source register number for storing a value used for a predetermined operation and a destination operand field for designating a destination register number for storing the result of the operation are simultaneously provided. A data processing method for performing interpretation,
A first instruction storing step for storing a set of a source register number specified by a source operand field and a destination register number specified by a destination operand field, included in the plurality of machine language instructions;
A set of a plurality of source register numbers and destination register numbers stored in the first instruction storing step is acquired, and a source operand field for specifying the source register number and a destination operand field for specifying the destination register number A second instruction storing step for storing empty information in a storage position that does not store the pair of the source register number and the destination register number, ,
Specified by the value of the source register specified by the source operand field included in the machine language instruction having the earliest execution order stored in the second instruction storage step, and by the destination operand field included in the machine language instruction A third instruction storing step for storing a destination register number;
Destination operand field in which the value of the source register specified by the source operand field stored in the third instruction storage step is acquired and a predetermined operation is performed, and the operation result is stored in the third instruction storage step A plurality of instruction operation steps stored in a register specified by a destination register number specified by
When the source register number specified by the source operand field acquired in the second instruction storing step depends on the destination register number specified by the destination operand field stored in the second instruction storing step, The execution order of the machine language instruction including the source operand field is determined to be slower than the execution order of the machine language instruction including the destination operand field, and the storage position according to the determined execution order is the empty The source register number specified by the source operand field at the storage location where the information is stored, and the destination specified by the destination operand field included in the machine language instruction including the source operand field Data processing method characterized by storing a set of the register number.

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