JP2008216096A - Testing system for semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of reducing consumption of electric power, at the testing of semiconductor integrated circuit devices (LSIs), in a testing system for LSI. <P>SOLUTION: In an LSI test system for testing a plurality of LSI devices to be tested DUT1 through DUT4 at one sitting, between the signal lines connecting the LSI devices to be tested DUT1 through DUT4 and the LSI tester 100, each of delay units DLY1 through DLY4 with different delay times is provided to each LSY devices DUT1 through DUT4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a test system for a semiconductor integrated circuit device, and more particularly to a technique effective when applied to the configuration of a test system for a semiconductor integrated circuit device that tests a plurality of semiconductor integrated circuit devices at once.

  As a technique studied by the present inventor, for example, in a test system for a semiconductor integrated circuit device (hereinafter simply referred to as “LSI”), the following technique can be considered.

  In recent years, application of BIST circuit addition by DFT (Design For Test) tools such as Memory BIST (Built in Self Test), Logic BIST, etc. has expanded to logic LSI (Large Scale Integrated Circuit). And application of an actual speed (at-speed) test using these functions has also begun.

For example, as a test method to which BIST is applied, there is a technique described in Non-Patent Document 1. The method of Non-Patent Document 1 is called a compression pattern test method. This method uses a pattern development circuit that expands the compressed input pattern in the chip and a test result output pattern on the chip as a countermeasure against the increase in the amount of test data and the increase in the number of external pins for testing, which are disadvantages of the scan test. The LSI chip has a feature that a pattern compression circuit for compression inside the LSI chip is provided. FIG. 3 shows a schematic configuration of the compression pattern test method.
"Embedded Deterministic Test For Low Cost Manufacturing Test", Proc. ITC, 2002, p. 301-310

  By the way, as a result of examination by the inventor of the test system technology for the semiconductor integrated circuit device as described above, the following has been clarified.

  For example, when the BIST circuit addition or the actual speed test as described above is applied to a large-scale high-speed logic LSI, there is a possibility that the test cannot be performed normally due to an increase in power during the test.

  In the compression pattern test method of Non-Patent Document 1, a test pattern generated using a test generation algorithm is compressed, applied from an LSI tester to an LSI chip, developed in the LSI chip, and sent to a scan chain (scan) By shifting, a desired test pattern is realized in the LSI chip. However, a random value is set for a portion whose value has not been determined by the algorithm. For this reason, the large-scale high-speed logic circuit has a problem that the activation rate (the rate at which the logic value changes) in the internal logic circuit increases during the scan shift operation, and the power consumption increases.

  Also, the BIST circuits of various DFTs mounted in the LSI chip have a large activation rate (ratio of change in logic value) in the internal logic circuit during the BIST operation in order to shorten the measurement time in the LSI tester. Therefore, there is a problem that the power increases.

  Then, when the LSI chip power at the time of measurement in the LSI tester is increased, there is a problem that the power supply amount on the LSI tester side for measuring the LSI chip is insufficient. This becomes a further problem when measuring a plurality of LSI chips at a time.

  In addition, the power for one LSI chip measurement also increases, which increases the damage to measurement jigs and probe cards outside the LSI chip, and the LSI chip cannot be measured correctly. In the worst case, the LSI being measured There is also a problem that the chip itself is destroyed due to the damage of the probe card.

  Accordingly, an object of the present invention is to provide a technique capable of reducing current consumption during LSI testing in a test system for a semiconductor integrated circuit device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In other words, the semiconductor integrated circuit device according to the present invention is a test system for a semiconductor integrated circuit device that tests a plurality of semiconductor integrated circuit devices at a time, between the signal lines connecting the plurality of semiconductor integrated circuit devices and a tester. A delay unit having a different delay time is provided for each semiconductor integrated circuit device.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a test system for a semiconductor integrated circuit device, current consumption during LSI testing can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a block diagram showing a configuration of a test system for a semiconductor integrated circuit device (LSI) according to an embodiment of the present invention. FIG. 2 shows a test system for a semiconductor integrated circuit device according to an embodiment of the present invention. It is a figure which shows the peak current reduction effect.

  First, an example of the configuration of the LSI test system according to the present embodiment will be described with reference to FIG. The LSI test system of this embodiment is a test system that tests, for example, an LSI chip or a packaged LSI. This test system includes, for example, an LSI tester 100 and a plurality of delay units DLY1 to DLY1. The delay units DLY 1 to 4 are inserted between signal lines connecting the LSI to be tested, that is, the device under test DUT (Device Under Test) 1 to 4, and the LSI tester 100. The delay units DLY1 to DLY4 are mounted on measurement jigs for the devices under test DUT (Device Under Test) 1 to 4. Each of the delay units DLY1 to DLY4 includes a plurality of delay elements. The number of delay elements is determined by the number of signal lines of each of the devices under test DUT1 to DUT4. The devices under test DUT1 to DUT4 are generally the same type of LSI, and the plurality of LSIs are measured at a time.

  In this embodiment, the case where there are four delay units is described as an example. However, the present invention is not limited to this, and the number of delay units is increased or decreased according to the number of devices under test (LSI) measured at one time.

  By providing a delay element corresponding to each LSI chip on a jig for testing N (N is a natural number) LSI chips at a time, the peak current on the LSI test system is reduced. By optimizing the configuration of the delay units DLY1 to DLY4, it is possible to obtain a pseudo simultaneous measurement time.

  Further, the shift operation and the capture operation during the SCAN test are simultaneously measured by these delay elements. The apparent peak current is reduced by shifting the measurement timing for each LSI chip. FIG. 2 shows a comparison of peak current reduction according to the present embodiment. In the conventional LSI test system, current flows through a plurality of LSI chips at a time, so the peak current has a waveform as indicated by 201 in FIG. In the LSI test system according to the present embodiment, the peak current is reduced because the peak current is dispersed and flows in the devices under test DUT1 to DUT4 as indicated by 202 in FIG.

  Accordingly, a signal delay element is provided between the LSI tester 100 and the devices under test DUT1 to DUT4, and the signal delay time by the delay element is arbitrarily adjusted for each DUT to be measured simultaneously, thereby measuring a large number of pseudo-simultaneously. Can be realized.

  In addition, since the delay units DLY1 to DLY4 are mounted on the measurement jig side outside the LSI chip, there is no increase in the area of the LSI chip, the addition of a peak power reduction structure, and the verification man-hours, etc. Become.

  Further, the configuration in the LSI chip is not affected by whether or not a plurality of devices under test are simultaneously measured.

  In addition, for example, assuming the number of pins of a semi-general-purpose LSI chip, an LSI tester measurement jig corresponding to the number of pins is prepared in advance, and the delay units DLY1 to DLY4 are mounted on the measurement jig. In addition, by reusing the applicable products, it contributes to the reduction of development time and cost. For example, a jig to which the present invention assuming a representative number of LSI pins such as 64, 128, 256, 512, and 1024 pins is prepared regardless of the development schedule on the LSI chip side, and the corresponding LSI chip is completed. It can be measured immediately.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the scope of the invention. Needless to say.

  The present invention is applicable to measurement of all logic LSIs, and is particularly suitable for measurement of large-scale high-speed logic LSIs.

1 is a block diagram showing a configuration of an LSI test system according to an embodiment of the present invention. It is a figure which shows the peak current reduction effect at the time of a test in the LSI test system by one embodiment of this invention. It is a figure which shows the structure of the LSI test system examined as a premise of this invention.

Explanation of symbols

100 LSI tester
DLY1-4 delay unit DUT1-4 DUT

Claims (4)

A test system for a semiconductor integrated circuit device for testing a plurality of semiconductor integrated circuit devices at a time,
A test system for a semiconductor integrated circuit device, wherein a delay unit having a different delay time is provided for each of the semiconductor integrated circuit devices between signal lines connecting the plurality of semiconductor integrated circuit devices and a tester. The test system for a semiconductor integrated circuit device according to claim 1,
The test system for a semiconductor integrated circuit device, wherein the delay unit includes a plurality of delay elements whose delay values are optimized for each of the semiconductor integrated circuit devices. The test system for a semiconductor integrated circuit device according to claim 1,
A test system for a semiconductor integrated circuit device, wherein the delay unit is mounted on a measurement jig for a tester. The semiconductor integrated circuit device test system according to claim 3,
A test system for a semiconductor integrated circuit device, wherein the tester measurement jig is a semi-general-purpose jig in which the number of pins of the semiconductor integrated circuit device is fixed.

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