JP2008211634A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver in which an appropriate code determination threshold is set, even when a signal at a level exceeding a conversion level of an A/D conversion part is input. <P>SOLUTION: The receiver includes: a detection part which detects an amplitude modulation signal; the A/D conversion part which samples a detection signal according to a clock signal to perform A/D conversion; a binarization part which compares digital data with the code determination threshold to binarize the digital data; a synchronization part which compares magnitude of two sample values obtained by sampling each symbol of the detection signal by two clock signals with different timing, respectively, by the A/D conversion part, detects shift of the clock signals to peak timing of the detection signal to output a delay control signal for controlling the clock signals so that respective signals are synchronized and a determination result signal indicating whether or not detection of the shift can be performed; and a threshold control part which controls the code determination threshold according to the determination result signal. The synchronization part, when the two sample values are equal to the maximum value of a conversion range of the A/D conversion part, determines that detection of the shift can not be performed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an amplitude modulation signal receiving apparatus.

  FIG. 17 is a block diagram showing a conventional receiving apparatus. The receiving apparatus shown in FIG. 17 is disclosed in Patent Document 1. The receiving apparatus calculates the signal strength of the received signal, uses the smoothed value of the calculated signal strength as a threshold value, and compares the signal strength with the signal strength to determine the presence or absence of an amplitude modulation tone signal.

  The receiving apparatus shown in FIG. 17 includes frequency selection means 1601, signal strength calculation means 1602, smoothing means 1603, comparison means 1604, and determination means 1605. The frequency selection means 1601 selects and passes only a predetermined frequency component from the input signal. The signal strength calculation unit 1602 calculates the signal strength of the output signal of the frequency selection unit 131. The smoothing unit 1603 smoothes the signal intensity output from the signal intensity calculating unit 1602. The comparison unit 1604 uses the output of the smoothing unit 1603 as a threshold value and compares it with the signal intensity output from the signal intensity calculation unit 1602. The determination unit 1605 determines the presence / absence of an amplitude modulation tone signal based on the output of the comparison unit 1604.

  FIG. 18 shows an internal configuration of the signal strength calculation unit 1602. As shown in FIG. 18, the signal strength calculation unit 1602 includes a multiplier 16021 and an integrator 16022. Usually, the integrator 16022 is constituted by a resistor and a capacitor.

  FIG. 19 is a block diagram showing a conventional receiving apparatus. The receiving apparatus shown in FIG. 19 is disclosed in Patent Document 2. The receiving device calculates the average values of the “0” level and the “1” level when receiving the “0101...” Signal (level detection pattern signal) for level detection, and calculates the average value of these two values. Is used as a sign determination threshold value.

  A receiving apparatus 1800 shown in FIG. 19 receives a level detection pattern signal before receiving a data string. The receiving apparatus 1800 includes a receiving unit 1801, an envelope detection unit 1802, a sample and hold circuit 1803, an A / D converter 1804, and binarization means 1805. The binarization unit 1805 includes a comparison unit 1851, a threshold value calculation unit 1852, and an average value calculation unit 1853. The reception unit 1801 receives a signal transmitted from the transmission device 1700. The envelope detection unit 1802 performs envelope detection on the received signal. The A / D converter 1804 A / D converts the envelope detection output given through the sample hold circuit 1803. The average value calculating means 1853 calculates the average values of the “0” level and the “1” level when receiving the level detection pattern signal. The threshold value calculation means 1852 sets an intermediate value between the average value of the “0” level and the average value of the “1” level calculated by the average value calculation means 1853 as the code determination threshold value. The comparison unit 1851 demodulates the amplitude modulation signal by comparing the code determination threshold value with the data string.

Japanese Patent No. 3402115 Japanese Patent No. 3518330

As described above, the signal strength calculation means 1602 provided in the receiving apparatus shown in FIG. 17 includes the integrator 16022, and the integrator 16022 includes a resistor and a capacitor. Since charging of the capacitor takes several microseconds, it is difficult for the receiving apparatus to be applied to high-speed transmission of several Gbps.
On the other hand, although the receiving apparatus shown in FIG. 19 does not include an integrator, when a signal having a level exceeding the conversion range of the A / D converter 1804 is input to the A / D converter 1804, an appropriate sign determination is performed. It is difficult to set a threshold value. When a signal having a level exceeding the conversion range is input to the A / D converter 1804, the variance of “0” level noise and the variance of “1” level noise in the output of the A / D converter 1804 are different. For this reason, it is difficult for a receiving apparatus that sets an intermediate value between an average value of “0” level and an average value of “1” level as a code determination threshold value to set an appropriate code determination threshold value.

  Even if a receiving device including an AGC (Automatic Gain Control) circuit is used in a high-speed transmission system, it takes time to detect signal power by AGC. For this reason, it is difficult to apply a receiving device including an AGC circuit to high-speed transmission.

  An object of the present invention is to provide a receiving apparatus capable of setting an appropriate code determination threshold even when a signal having a level exceeding the conversion level of an A / D converter is input.

  The present invention provides envelope detection of an amplitude-modulated received signal and outputs a detection signal; a clock generation unit that generates a clock signal; and a timing for outputting the clock signal to an A / D conversion unit. A variable delay unit for delay control and A / D conversion of a sample value obtained by sampling the detection signal according to the timing of the input delay-controlled clock signal in a predetermined conversion range, and outputs digital data An A / D conversion unit, a binarization unit that binarizes the digital data by comparing it with a code determination threshold, and the A / D conversion unit converts each symbol of the detection signal into two or more different timings. By comparing the magnitudes of two or more sample values obtained by sampling with the delay-controlled clock signal, the delay-controlled with respect to the peak timing of the detection signal A delay control signal that controls the timing of the clock signal so that the peak timing of the detection signal and the timing of the delay-controlled clock signal are synchronized can be detected by detecting a shift in the timing of the lock signal, and the detection of the shift A synchronization unit that outputs a determination result signal indicating whether or not each detection signal symbol, and a threshold control unit that controls the code determination threshold used in the binarization unit according to the determination result signal. The synchronization unit outputs a determination result signal indicating that the shift cannot be detected to the threshold control unit when the two or more sample values are equal to the maximum value of the conversion range. provide.

  In the receiving apparatus, the threshold control unit includes a first counter that counts the number of times the determination result signal indicating that the detection of the deviation has not been performed is continuously input, and the first counter When the counter value is equal to or greater than the first predetermined number, the sign determination threshold is increased to the first value.

  In the receiving apparatus, the threshold value control unit includes a second counter that counts the number of times a determination result signal indicating that the shift in the past predetermined number of symbols has not been detected can be input, and the second counter When the counter value of the counter becomes less than the second predetermined number, the sign determination threshold is lowered from the first value to the second value.

  In the receiving apparatus, when the determination result signal indicating that the deviation cannot be detected is input, the threshold control unit adds a counter value to the determination to indicate that the deviation is detected. When a result signal is input, a third counter that subtracts a predetermined value from the counter value, and a counter average value calculation unit that calculates an average value of the counter values of the third counter over a plurality of symbols of the detection signal The code determination threshold is determined according to the counter average value calculated by the counter average value calculation unit.

  In the receiving apparatus, the threshold control unit includes a memory that stores threshold setting information indicating a relationship between a counter average value and a code determination threshold, the counter average value calculated by the counter average value calculation unit, and the memory The code determination threshold value is determined based on the threshold value setting information stored in.

  In the receiving device, the threshold control unit, based on the counter average value and the threshold setting information, when the counter average value calculated by the counter average value calculation unit is greater than or equal to a first value and less than a second value. A code determination threshold value is determined, and when the counter average value calculated by the counter average value calculation unit is equal to or greater than the second value, the maximum value of the threshold setting information is set as the code determination threshold value.

  According to the receiving apparatus of the present invention, it is determined whether or not the level of the detection signal exceeds the conversion range of the A / D converter based on the determination result signal output from the synchronization unit, and based on the determination result. Since the code determination threshold value of the binarization unit is controlled, an appropriate code determination threshold value can be set even when a detection signal having a level exceeding the conversion level of the A / D conversion unit is input. As a result, the bit error of the code “0” can be reduced and the bit error rate can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram illustrating a receiving apparatus according to the first embodiment. As illustrated in FIG. 1, the receiving apparatus 100 according to the first embodiment includes an antenna 101, a detection unit 102, a clock generation unit 103, a variable delay unit 104, an A / D conversion unit 105, and a synchronization unit 106. And a binarization unit 107 and a threshold control unit 108. The threshold control unit 108 includes a counter 1080, an M-stage shift register 1081, an adder 1082, and a determination unit 1083.

  The detection unit 102 includes a diode and a low-pass filter. In the detection unit 102, only the positive part of the reception signal input via the antenna 101 is extracted by the diode, and then the carrier wave component is removed by the low-pass filter. In this way, the detection unit 102 detects the envelope of the received signal and outputs the detection signal 151 to the A / D conversion unit 105.

  The clock generation unit 103 generates a clock signal 153 having the same period as the symbol period of the received signal and outputs it to the variable delay unit 104. The variable delay unit 104 delays the clock signal 153 according to the delay control signal 155 input from the synchronization unit 106 and outputs the delayed signal to the A / D conversion unit 105. The A / D conversion unit 105 samples the detection signal 151 at the timing of the rising edge (or falling edge) of the clock signal 153 input via the variable delay unit 104, and uses the obtained sample value as a predetermined conversion range. The A / D converted digital data 157 is output to the synchronization unit 106 and the binarization unit 107.

  FIG. 2 is a block diagram showing the A / D conversion unit 105. As shown in FIG. 2, the A / D converter 105 is a flash type. The flash A / D converter compares the analog input signal and the reference voltage at the same time using a plurality of comparators. As the number of quantization bits is increased, the number of comparators increases. However, analog values can be converted into digital values by one comparison, and therefore A / D conversion can be performed at high speed. The range from Max to Min shown in FIG. 2 is a range that can be converted into a digital value (hereinafter referred to as “conversion range”).

  FIG. 3 is a diagram illustrating how the analog detection signal 151 input to the A / D conversion unit 105 is converted into digital data 157. As shown in FIG. 3A, when the level of the detection signal 151 is within the conversion range (Max to Min), although the quantization error is included, the waveform indicated by the digital data 157 is the detection signal 151. Close to the waveform. On the other hand, as shown in FIG. 3B, when the level of the detection signal 151 exceeds the Max value of the conversion range, all of the digital data 157 in the portion exceeding the Max value is the Max value. Similarly, all of the digital data 157 below the Min value is the Min value.

The detection signal 151 at a level within the conversion range of the A / D conversion unit 105 is quantized according to the number of quantization bits and output. Therefore, as shown in FIG. 3B, when the level of the detection signal 151 exceeds the Max value of the conversion range, the waveform indicated by the digital data 157 becomes a waveform in which the upper portion is cut out flatly and detected. This is completely different from the original waveform shown by the signal 151.
In the present embodiment, the A / D conversion unit 105 samples only one point for each symbol (for example, sampling at timings T1, T2, T3, and T4 in FIG. 3), and converts the sample value to a digital value. The digital data 157 is output after conversion.

  Based on the digital data 157 output from the A / D conversion unit 105, the synchronization unit 106 determines the rising edge (or falling edge) of the clock signal 153 with respect to the timing (peak timing) at which the amplitude of the detection signal 151 peaks. Detects timing shifts (whether they are advanced or delayed). The synchronization unit 106 delays the clock signal 153 according to the detection result, and outputs a delay control signal 155 for aligning the timings of both to the variable delay unit 104.

The early / late determination shown in FIG. 4 is used to detect the timing shift performed by the synchronization unit 106. In the Early / Late method, the A / D conversion unit 105 uses two sample values obtained by sampling each symbol of the detection signal 151 with two clock signals having different timings (“A” and “A” shown in FIG. 4). The size of B ″) is compared.
Although only one A / D conversion unit 105 is provided in FIG. 1, when the Early / Late method is determined, the detection signal 151 is sampled with two clock signals. Two / D conversion units 105 are provided. One of the two clock signals having different timings is supplied to one A / D converter 105, and the other clock signal is supplied to the other A / D converter 105.

  As shown in FIG. 4A, the synchronization unit 106 that determines the Early / Late method determines “Early” because the clock signal is advanced with respect to the detection signal 151 when “A <B”. . Conversely, when “A> B”, it is determined as “Late”. As shown in FIG. 4B, when “A = B”, the synchronization unit 106 determines that the clock signal and the detection signal 151 are synchronized. Based on these determination results, the synchronization unit 106 outputs the delay control signal 155 to the variable delay unit 104 so that the two sample values are equal (“A = B”).

  Further, the synchronization unit 106 outputs a determination result signal 159 indicating whether or not Early / Late determination has been performed to the threshold control unit 108. In FIG. 5, since the level of the detection signal 151 exceeds the conversion range of the A / D conversion unit 105, the early / late determination is performed even though the detection signal 151 and the clock signal 153 are actually out of timing. It is a figure which shows the example which cannot be performed. In the detection signal 151 before A / D conversion indicated by a broken line, since there is a level difference between the sample value A and the sample value B, Early / Late determination is possible.

  However, in the digital data 157 after A / D conversion indicated by the solid line, all the portions of the conversion level that are larger than the Max value are converted to the Max value, so “A = B”, and Early / Late determination Is not done. However, since “A = B” even in actual synchronization, both must be distinguished. Therefore, for example, when “A = B = Max value”, the synchronization unit 106 determines that the Early / Late determination cannot be performed. In this way, it is possible to distinguish between the case of actual synchronization and the case where the level of the detection signal 151 exceeds the conversion range of the A / D conversion unit 105. As the determination result signal 159, the synchronization unit 106 indicates a signal indicating “0” when the Early / Late determination is performed, and a signal indicating “1” when the Early / Late determination cannot be performed. The detected signal 151 is output for each symbol.

  The counter 1080 included in the threshold control unit 108 counts the number of times “1” is continuously input as the determination result signal 159. Assuming that the counter value of the counter 1080 is “Cnt”, the counter 1080 sets “Cnt = Cnt + 1” when the determination result signal 159 = “1”, and sets “Cnt = 0” when the determination result signal 159 = “0”. Reset the value of. The counter value Cnt is output to the determination unit 1083 included in the threshold control unit 108. When the counter value Cnt is greater than or equal to N (N is a predetermined positive integer) (Cnt ≧ N), the determination unit 1083 determines that the level of the detection signal 151 indicating the code “1” is the value of the A / D conversion unit 105. It is determined that the Max value of the conversion range is exceeded. At this time, the determination unit 1083 outputs a threshold control signal 161 for instructing to increase the code determination threshold used in the binarization unit 107 to the binarization unit 107.

Hereinafter, the reason why the code determination threshold used in the binarization unit 107 is increased will be described. Here, it is assumed that there is no intersymbol interference. The detection signal 151 that is an input signal to the A / D conversion unit 105 is affected by noise. FIG. 6 is a diagram illustrating the relationship between the noise variance of the detection signal 151 input to the A / D conversion unit 105 and the conversion range. Assuming that the noise variance is σ ² , the “0” level and the “1” level of the detection signal 151 fluctuate on the average within a range of ± σ as indicated by arrows in FIG. Accordingly, as shown in FIG. 6 (a), the level of the detection signal 151 when the conversion range, "0" level noise variance and of the "1" level noise variance are both sigma ^2.

However, as shown in FIG. 6B, when the level of the detection signal 151 exceeds the conversion range, the variance of the “0” level noise remains σ ² , but the variance of the “1” level noise is It is smaller than σ ^2. This is because when the detection signal 151 indicated by the dotted line in FIG. 6B is input to the A / D conversion unit 105, all portions exceeding the Max value of the conversion range are cut off. For this reason, even if the “1” level fluctuates in the direction smaller than the Max value (the portion indicated by the downward arrow in FIG. 6), it does not fluctuate in the direction larger than the Max value.

  Further, when the “1” level of the detection signal 151 is sufficiently larger than the Max value of the conversion range, the detection signal indicating the “1” level is uniformly converted into digital data indicating the Max value. It becomes almost zero. In this case, even if the code determination threshold is made as close as possible to the Max value, the binarization unit 107 hardly makes a determination error for the code “1”. Further, since the distance between the “0” level and the code determination threshold is increased, the determination error of the code “0” can be reduced. Thus, when the level of the detection signal 151 exceeds the conversion range, the code determination threshold used in the binarization unit 107 can be increased.

  On the other hand, since control to restore the threshold value is also necessary, for example, when the synchronization unit 106 can accurately determine Early / Late for L symbols or more of the past M symbols (determination result signal 159 = “0”). Lower the sign determination threshold. Therefore, the threshold control unit 108 includes an M-stage shift register 1081, an adder 1082, and a determination unit 1083 as shown in FIG.

  The threshold control unit 108, when N is the added value of the number of times of being unable to determine, indicates the number of times that MN has been determined, so that the Early / Late determination is accurately performed for L symbols or more of the past M symbols. The conditional expression indicating the completed state is MN ≧ L. When the addition value N is solved for the addition value N, the threshold value control signal 161 for lowering the sign determination threshold value is binarized. It outputs to 107.

  Here, the determination result signal is input to the M-stage shift register 1081, and “0” or “1” is sequentially shifted. The adder 1082 sequentially calculates the sum of the M-stage shift register 1081 and outputs it as N. The determination unit 1083 determines whether or not to lower the precode determination threshold value using the input addition value N, the number of stages of the shift register, and the target value L of the predetermined number of determinations. When the addition value N is less than ML, the detection signal 151 can be determined to be in the state of FIG. 3A, and thus the threshold control signal 161 for instructing to lower the code determination threshold is binarized. Output to the unit 107. On the other hand, when the added value N is greater than or equal to ML, it can be determined that the detection signal 151 is in the state of FIG. To the conversion unit 107.

  FIG. 8 is a block diagram showing an internal configuration of the binarization unit 107. As illustrated in FIG. 8, in the binarization unit 107, the reference voltage supplied to the comparator 1072 is changed by switching the switch 1071 in accordance with the threshold control signal 161 supplied from the threshold control unit 108. Note that the resistance value of the resistor R1 and the resistance value of the resistor R2 shown in FIG. 8 are not equal (R1 ≠ R2). Different sign determination thresholds can be supplied to the comparator 107 depending on the difference in resistance value.

  As described above, the binarization unit 107 changes the code determination threshold by switching the switch 1071 according to the threshold control signal 161, and binarizes the digital data 157 by comparing with the code determination threshold. As a result of comparing the digital data 157 with the code determination threshold, the binarization unit 107 outputs “1” when the digital data 157 is larger than the code determination threshold, and outputs “0” when the digital data 157 is smaller. The data “1” and “0” output from the binarization unit 107 is demodulated data 163.

  FIG. 9 is a flowchart illustrating a procedure in which the receiving apparatus 100 increases the code determination threshold. In step S401, the detection unit 102 performs envelope detection on the received signal. In step S402, the A / D conversion unit 105 samples the detection signal 151, and A / D converts the detection signal 151. In step S <b> 403, the synchronization unit 106 performs Early / Late determination based on the digital data 157. In step S <b> 404, it is determined whether the synchronization unit 106 has performed Early / Late determination, and a determination result signal (“0” or “1”) 159 is output to the threshold control unit 108. If the Early / Late determination can be performed (“Yes” in Step S404), the process proceeds to Step S405. If the Early / Late determination cannot be performed (“No” in Step S404), the process proceeds to Step S406. .

  In step S405, after the threshold value control unit 108 resets the counter 1080 (Cnt = 0), the process returns to step S403, and the synchronization unit 106 performs Early / Late determination using the digital data 157 of the next symbol. In step S406, the threshold control unit 108 increments the counter 1080 (Cnt = Cnt + 1), that is, increases the counter value.

  In step S407, the threshold control unit 108 determines whether or not the counter value Cnt is equal to or greater than N (Cnt ≧ N). If Cnt ≧ N (“Yes” in step S407), the process proceeds to step S408. If Cnt <N (“No” in step S407), the process returns to step S403, and the synchronization unit 106 determines whether the next symbol The Early / Late determination is performed using the digital data 157.

  In step S408, the threshold control unit 108 outputs to the binarization unit 107 a threshold control signal 161 that instructs to increase the code determination threshold. The binarization unit 107 switches the sign determination threshold to a value based on the reference voltage determined by either the resistor R1 or R2 according to the threshold control signal 161.

  FIG. 10 is a flowchart illustrating a procedure in which the receiving apparatus 100 decreases the code determination threshold. In step S501, the detection unit 102 performs envelope detection on the received signal. In step S502, the A / D conversion unit 105 samples the detection signal 151 and A / D converts the detection signal 151. In step S <b> 503, the synchronization unit 106 performs Early / Late determination based on the digital data 157. In step S 504, it is determined whether or not the synchronization unit 106 has performed Early / Late determination, and a determination result signal (“0” or “1”) 159 is output to the threshold control unit 108. If the Early / Late determination can be performed (“Yes” in step S504), the process proceeds to step S505. If the Early / Late determination cannot be performed (“No” in step S504), the process proceeds to step S506. .

  In step S505, the synchronization unit 106 outputs “determination result signal 159 = 1”. On the other hand, in step S506, the synchronization unit 106 outputs “determination result signal 159 = 0”. In step S507, the determination unit 1083 determines whether or not the addition value N (the number of times of determination cannot be determined) of the adder 1082 illustrated in FIG. 7 is smaller than ML. If “addition value N <ML” (“Yes” in step S507), the process proceeds to step S508. If “addition value N ≧ ML” (“No” in step S507), the process proceeds to step S508. Returning to S503, the synchronization unit 106 performs Early / Late determination using the digital data 157 of the next symbol.

  In step S508, the threshold control unit 108 outputs to the binarization unit 107 a threshold control signal 161 that instructs to lower the code determination threshold. In accordance with the threshold control signal 161, the binarization unit 107 switches the sign determination threshold to a value based on the reference voltage determined by either the resistor R2 or R1.

  As described above, in the present embodiment, when the level of the detection signal 151 exceeds the conversion range of the A / D conversion unit 105, the threshold control unit 108 outputs the determination result signal 159 output from the synchronization unit 106. Based on this, control is performed so that the sign determination threshold used in the binarization unit 107 is raised above the intermediate value between the “0” level average value and the “1” level average value. For this reason, the determination error of the code “0” can be reduced, and as a result, the overall bit error rate can be improved. In addition, when the level of the detection signal 151 returns to within the conversion range, the code determination threshold can be lowered.

(Second Embodiment)
In the first embodiment, the sign determination threshold is increased when the level of the detection signal 151 exceeds the conversion range of the A / D conversion unit 105, and the sign determination threshold is decreased when returning to the conversion range. In the second embodiment, the sign determination threshold value is more flexibly controlled to various values according to the level of the detection signal 151.

  FIG. 11 is a block diagram illustrating a receiving apparatus according to the second embodiment. The difference between the receiving apparatus 200 of the second embodiment and the receiving apparatus 100 of the first embodiment is the internal configuration and operation of the threshold control unit. Except for this point, the second embodiment is the same as the first embodiment, and in FIG. 11, the same reference numerals are given to the components common to FIG. 1.

  The threshold control unit 208 of the present embodiment detects the synchronization position of the sampling timing that changes depending on the level of the detection signal 151. As shown in FIG. 11, the threshold control unit 208 of this embodiment includes a counter 2080, a counter average value calculation unit 2081, and a memory 2082. The counter 2080 increases or decreases the counter value Cnt according to the determination result signal 159 input from the synchronization unit 106. Specifically, the counter 2080 increments the counter value Cnt (increases the count value) when “1” is input as the determination result signal 159, and counters when “0” is input as the determination result signal 159. A predetermined value is subtracted from the value Cnt. The counter average value calculation unit 2081 calculates an average value of counter values Cnt (hereinafter referred to as “counter average value”) over a plurality of symbols of the detection signal 151. The memory 2082 stores a relationship between a counter average value, which will be described later, and a code determination threshold value.

  Hereinafter, the operation of the receiving apparatus of this embodiment will be described. In actual communication, there is a difference between the clock frequency of the transmission device and the clock frequency of the reception device. Therefore, if the state in which the synchronization unit 106 cannot perform Early / Late determination continues for a while, the sampling timing of the clock signal 153 supplied to the A / D conversion unit 105 gradually shifts. For example, the frequency of the reception signal is Frx, and the frequency of the clock signal 153 of the reception device is Fclk. Assuming that “Frx> Fclk”, the sampling timing of the A / D conversion unit 105 is gradually delayed with respect to the detection signal 151. When the detection signal 151 reaches the vicinity of the falling edge, a level difference occurs, so that Early / Late determination can be performed. Therefore, the sampling timing is finally synchronized near the falling edge of the detection signal 151.

  When the level of the detection signal 151 exceeds the conversion range, as shown in FIG. 12, the width of the “1” level in which the digital data 157 indicates the Max value of the conversion range changes according to the level of the detection signal 151. Therefore, the position of the falling edge of the waveform indicated by the digital data 157 also changes. For example, when the detection signal 151 changes from the broken line shown in FIG. 12 to the solid line, the position of the falling edge of the waveform indicated by the digital data 157 changes from P1 to P2, so the sampling timing changes from P1 to P2.

  FIG. 13 is a diagram showing in detail the change in the sampling timing shown in FIG. Since the synchronization unit 106 follows the synchronization and adjusts the sampling timing, the sampling timing first fluctuates around P1, then moves to P2, and fluctuates around P2. If it is assumed that there is no intersymbol interference, the waveform of the received signal is known in advance, and therefore the level of the detection signal 151 can be known if the position where the sampling timing is synchronized can be known. For this reason, the threshold control unit 208 determines the amount of change in the code determination threshold according to the level of the detection signal 151.

  Hereinafter, the control of the code determination threshold according to the level of the detection signal 151 in the present embodiment will be described. First, as a premise, in this embodiment, the level of the detection signal 151 is within the conversion range of the A / D conversion unit 105 as an initial state, and the sampling timing of the clock signal 153 supplied to the A / D conversion unit 105 is Assume that the signal is synchronized with the center of the symbol by using a synchronization signal sequence such as a preamble signal. Further, the width of the “1” level of the detection signal 151 before A / D conversion is set to “W”. Further, there is a difference (frequency shift) between the frequency Frx of the received signal and the frequency Fclk of the clock signal 153, and they are in a relationship of Frx> Fclk. Control of the code determination threshold is started from such an initial state.

  FIG. 14 is a diagram illustrating an example of sampling timing for different levels of the detection signal 151. FIG. 14A is a diagram showing sampling timing when the level of the detection signal 151 is within the conversion range. The sampling timing P0 in the initial state is located at the center of the symbol. Since the Early / Late determination cannot be performed during the width W of the “1” level, the sampling timing gradually shifts due to the influence of the frequency shift, and synchronizes at the sampling timing P1. The width from the sampling timing P0 to the sampling timing P1 is W / 2.

  FIG. 14B is a diagram illustrating the sampling timing when the “1” level of the detection signal 151 becomes equal to the Max value of the conversion range. Since the width of the “1” level in this state remains W, the final sampling timing synchronization position P3 is equal to the sampling timing P1 shown in FIG. FIG. 14C is a diagram showing sampling timing when the “1” level of the detection signal 151 is 2σ larger than the Max value of the conversion range. “Σ” is the standard deviation of noise. As shown in FIG. 14C, the width of the “1” level extends to W ′ (> W), and the synchronization position of the final sampling timing is the sampling timing P1 shown in FIG. The position P4 (≠ P1 = P3) is further away from the center than the sampling timing P3 shown in FIG. In the state of FIG. 14C, the “1” level hardly falls below the Max value, so that the code determination threshold can be made as close as possible to the Max value.

  Hereinafter, the case where the level of the detection signal 151 changes as shown in FIG. 12 will be described with reference to FIGS. The sampling timing deviates from the symbol center P0 which is the initial position to the vicinity of the position P1 of the falling edge of the detection signal 151. Thereafter, when the “1” level of the detection signal 151 exceeds the conversion range, the sampling timing is shifted to a position near the position P2 further away from the symbol center P0. Note that the position of the sampling timing P2 is the falling edge indicated by the waveform of the digital data 157.

  FIG. 15 is a diagram illustrating the counter value Cnt when the sampling timing shifts from P0 to P1 and further to P2. The counter value Cnt starts from the initial value “0”, and the counter value Cnt increases while the synchronization unit 106 cannot determine Early / Late. When the sampling timing exceeds P1, Early / Late determination is possible, and therefore, a predetermined value is subtracted from the counter value Cnt as shown in FIG. In order to synchronize with the position of the sampling timing P1 for a while, the counter value Cnt varies around the counter value C1 shown in FIG. Note that the counter value C1 shown in FIG. 15 is an average value of counters over a plurality of symbols during synchronization at the position of the sampling timing P1.

  Thereafter, when the level of the detection signal 151 is increased, the synchronization unit 106 cannot determine the Early / Late again, so that the sampling timing is shifted to P2. While the sampling timing deviates from P1 to P2, the counter value Cnt increases as shown in FIG. When the sampling timing exceeds P2, the Early / Late determination can be performed again, so that a predetermined value is subtracted from the counter value Cnt as shown in FIG. At this time, the counter value Cnt fluctuates around the counter value C2 shown in FIG. 15 in order to synchronize with the position of the sampling timing P2 for a while. Note that the counter value C2 shown in FIG. 15 is an average value of counters over a plurality of symbols during synchronization at the position of the sampling timing P2. The counter average values C1 and C2 correspond to the sampling timings P1 and P2 shown in FIG.

  The counter average value C1 corresponds to the width of W / 2 shown in FIG. For this reason, for example, if the equation C1: Cn = W / 2: X / 2 (Cn is the counter average value at that time) is solved for X, a width X of “1” level is derived. Since the waveform of the received signal and the conversion range of the A / D converter 105 are known, if the width X of the “1” level is known, the level of the detection signal 151 at that time can be derived. As described above, the counter value Cnt, the width X of the “1” level, and the level of the detection signal 151 are proportional to each other.

  FIG. 16 is a diagram illustrating the relationship between the counter average value and an appropriate code determination threshold value. Since the level of the detection signal 151 is within the conversion range in the range where the counter average value is less than C1, the threshold value control unit 208 calculates the average value of the “0” level and the average value of the “1” level of the detection signal 151. The intermediate value is set as the sign determination threshold.

  At this time, the receiving apparatus includes the average value calculating unit 1853 and the threshold value calculating unit 1852 shown in FIG. 19, and the threshold value control unit 208 acquires the intermediate value. In FIG. 8, the binarization unit 107 includes only two resistors, but includes two or more resistors. Since the reference voltage and each resistance value supplied to the binarization unit 107 are known, the threshold control unit 208 calculates which resistor can be supplied to the comparator 1072 with a sign determination threshold value close to the intermediate value. Can do. The control signal is output to the binarization unit 107 so as to select the resistance as described above.

  On the other hand, in the range where the counter average value is C1 or more and less than C4 (C4 is the counter value corresponding to the sampling timing P4 in FIG. 14C), the code determination threshold value calculated in advance from the noise variance and the width of “1” level. Is stored in the memory 2082 of the threshold control unit 208, the threshold control unit 208 refers to the threshold setting information stored in the memory 2082 and sets the counter average value. Accordingly, an appropriate code determination threshold value is selected. In the range where the counter average value is C4 or more, the threshold control unit 208 sets the maximum value indicated by the threshold setting information as the code determination threshold.

  In the range where the counter average value is C1 or more and less than C4, the code determination threshold is selected with reference to the threshold setting information stored in the memory 2082, but the code determination threshold is calculated based on the counter average value and the calculation formula. You may do it.

  As described above, in the present embodiment, the threshold control unit 208 can control the code determination threshold used by the binarization unit 107 to be a desired value according to the counter average value.

  The receiving apparatus according to the present invention is useful as a communication device that performs high-speed communication.

The block diagram which shows the receiver of 1st Embodiment Block diagram showing the A / D converter The figure which shows a mode that the analog detection signal input into the A / D conversion part is converted into digital data. The figure which shows two sample values obtained by the sampling by Early / Late system The figure which shows the example which cannot make Early / Late determination when the level of a detection signal exceeds the conversion range of an A / D conversion part The figure which shows the relationship between the dispersion | distribution of the noise of the detection signal input into an A / D conversion part, and a conversion range Block diagram showing an M-stage shift register and an adder included in the threshold control unit Block diagram showing the internal structure of the binarization unit The flowchart which shows the procedure in which the receiver increases the code determination threshold The flowchart which showed the procedure which a receiver reduces a code | symbol determination threshold value The block diagram which shows the receiver of 2nd Embodiment Diagram showing how the detection signal level exceeds the conversion range The figure which shows the change of the sampling timing shown in FIG. 12 in detail The figure which shows the example of the sampling timing for the different level of the detection signal The figure which shows counter value Cnt when a sampling timing shifts from P0 to P1, and further shifts to P2. The figure which shows the relationship between counter value Cnt and a suitable code | symbol determination threshold value Block diagram showing a conventional receiver Block diagram showing the internal configuration of the signal strength calculation means Block diagram showing a conventional receiver

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Receiver 101 Antenna 102 Detection part 103 Clock generation part 104 Variable delay part 105 A / D conversion part 106 Synchronization part 107 Binarization part 108,208 Threshold control part 1080 Counter 1081 M stage shift register 1082 Adder 2080 Counter 2081 Counter Average value calculation unit 2082 Memory

Claims (6)

A detection unit that detects an envelope of the amplitude-modulated received signal and outputs a detection signal;
A clock generator for generating a clock signal;
A variable delay unit that delay-controls the timing of outputting the clock signal to the A / D converter;
An A / D converter that performs A / D conversion on a sample value obtained by sampling the detection signal in accordance with a timing of an input delay-controlled clock signal and outputs digital data; and
A binarization unit that binarizes the digital data by comparing with a code determination threshold;
The A / D converter compares the magnitudes of two or more sample values obtained by sampling each symbol of the detection signal with two or more delay-controlled clock signals having different timings, A shift in the timing of the delay-controlled clock signal with respect to the peak timing of the detection signal is detected, and the timing of the clock signal is controlled so that the peak timing of the detection signal and the timing of the delay-controlled clock signal are synchronized. A synchronization unit that outputs a delay control signal and a determination result signal indicating whether or not the shift has been detected, for each symbol of the detection signal;
A threshold control unit that controls the code determination threshold used in the binarization unit according to the determination result signal,
The receiver is configured to output a determination result signal indicating that the shift cannot be detected to the threshold controller when the two or more sample values are equal to the maximum value of the conversion range. The receiving device according to claim 1,
The threshold control unit includes:
A first counter that counts the number of times that a determination result signal indicating that the deviation could not be detected is continuously input;
A receiving apparatus that raises the code determination threshold to a first value when a counter value of the first counter is equal to or greater than a first predetermined number. The receiving device according to claim 1,
The threshold control unit includes:
A second counter that counts the number of times a determination result signal indicating that the detection of the deviation in the past predetermined number of symbols could not be detected;
A receiving device that lowers the sign determination threshold value from the first value to a second value when a counter value of the second counter becomes less than a second predetermined number. The receiving device according to claim 1,
The threshold control unit includes:
When a determination result signal indicating that the deviation could not be detected is input, the counter value is added,
A third counter that subtracts a predetermined value from the counter value when a determination result signal indicating that the deviation has been detected is input;
A counter average value calculation unit that calculates an average value of the counter values of the third counter over a plurality of symbols of the detection signal;
A receiving device that determines the code determination threshold according to a counter average value calculated by the counter average value calculation unit. The receiving device according to claim 4,
The threshold control unit includes:
A memory for storing threshold setting information indicating a relationship between the counter average value and the code determination threshold;
A receiving device that determines the code determination threshold based on a counter average value calculated by the counter average value calculation unit and the threshold setting information stored in the memory. The receiving device according to claim 5,
The threshold control unit includes:
When the counter average value calculated by the counter average value calculation unit is greater than or equal to the first value and less than the second value, the code determination threshold is determined based on the counter average value and the threshold setting information,
A receiving device that sets the maximum value of the threshold setting information as the code determination threshold when the counter average calculated by the counter average value calculator is equal to or greater than the second value.

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