JP2008211090A - Method and apparatus for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, where reliability and productivity are improved in a metal cap layer, and to provide an apparatus for manufacturing the semiconductor device. <P>SOLUTION: A second interlayer insulating film and first wiring, or a second wiring layer and a hard mask are formed on the surface of a silicon substrate 2, the silicon substrate 2 is conveyed to a reaction chamber S, and N<SB>2</SB>gas excited by microwaves is introduced to the reaction chamber S. Ar gas allows Zr(BH<SB>4</SB>)<SB>4</SB>stored in a supply tank T to bubble, and the Ar gas containing Zr(BH<SB>4</SB>)<SB>4</SB>is introduced to the reaction chamber S as Zr(BH<SB>4</SB>)<SB>4</SB>gas. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus.

  In semiconductor devices, with the progress of miniaturization and multilayering, electromigration (EM) due to an increase in current density becomes serious. The multilayer wiring technology of copper (Cu) having high EM resistance is indispensable for highly integrating semiconductor devices.

  In the manufacturing process of the Cu wiring, a so-called damascene method is used in which a trench corresponding to the wiring shape is formed in an insulating layer in advance and the wiring is formed by filling the trench with Cu. Furthermore, in the manufacturing process of Cu wiring, a via hole (Via-Hole) is formed in a wiring trench in advance, and both the trench and the via hole are filled with Cu to form a wiring and a via contact at the same time. Dual-Damascene) method is used.

  In the Cu wiring after the damascene process, a cap layer such as SiC or SiN is laminated between the Cu wiring and an insulating layer (for example, a bottom dielectric film: Low-k film) on the Cu wiring. The cap layer functions as an antioxidant film on the surface of the Cu wiring, a Cu diffusion preventing film, and an etch stop film for the via hole. On the other hand, since the cap layer made of an insulating film such as SiC or SiN has low adhesion to the Cu wiring, the reliability of the Cu wiring is lowered. In addition, the etching process when forming the via hole is complicated, and the productivity of the semiconductor device is impaired.

  Therefore, in the Cu multilayer wiring technology, in order to solve the above-described problem, proposals have conventionally been made to apply a metal material to the cap layer on the Cu wiring. A cap layer made of a metal material (hereinafter simply referred to as a metal cap layer) has high adhesion to the Cu wiring, low specific resistance, and high barrier properties (moisture from the low-k film). And a high barrier property against Cu atoms from the Cu wiring) and a selectivity to be formed only on the Cu wiring.

  Patent Document 1 uses an electroless plating method to selectively deposit cobalt tungsten phosphorus (CoWP) on the surface of a Cu wiring, and further salicide the surface of the CoWP layer to form a metal cap layer. Thereby, the adhesiveness, conductivity, barrier property, and film formation selectivity as the metal cap layer can be satisfied, and the oxidation resistance of the metal cap layer can be improved.

On the other hand, Patent Document 2 uses zirconium nitride or a zirconium nitride compound as a material for the metal cap layer, and forms a metal cap layer on the entire surface of the substrate including the Cu wiring, so that the metal cap layer is selectively conductive only on the Cu wiring. give. According to this, the function as a metal cap layer can be achieved without requiring the film formation selectivity described above.
JP 2002-43315 A JP 2003-17496 A

  However, Patent Document 1 uses an electroless plating method in order to obtain film formation selectivity. In the electroless plating method, the shape and film thickness of the CoWP layer are greatly affected by the concentration of the chemical solution and the oxidation-reduction atmosphere. As a result, the deposition state of CoWP greatly fluctuated depending on the density, surface area, shape, etc. of the Cu wiring, resulting in a short circuit between adjacent CoWP layers and defective coating of the Cu wiring.

  In addition, in order to realize film formation selectivity, the electroless plating method requires that the surfaces immersed in the chemical solution, such as the surface of the Cu wiring after the damascene process and the surface of the low-k film, be in an extremely clean state. . For this reason, an increase in the surface treatment process accompanying the cleaning is caused, and the productivity of the semiconductor device is impaired.

  On the other hand, Patent Document 2 discloses only a production method relating to zirconium nitride (ZrN) using tetrakisdiethylaminozirconium (TDEAZ), and does not disclose any production method relating to a zirconium nitride compound with respect to its raw materials and conditions. . Moreover, according to experiments by the inventors of the present application, the ZrN film forming method using TDEMA generates a sufficient amount of powdery ZrN and by-products at the same time to produce a sufficient particle level for manufacturing a semiconductor device. It was hard to get. In addition, powdery ZrN and by-products are deposited in the raw material gas supply system and the exhaust system, making stable operation of the manufacturing apparatus impossible.

  The present invention has been made to solve the above-described problem, and relates to a semiconductor device and a method for manufacturing the semiconductor device in which the reliability and productivity of a metal cap layer are improved.

In the study of ZrN as one of the metal barrier materials, the inventors of the present invention used a ZrB _x N _y film containing boron (B), as with the ZrN film, having good adhesion to metal wiring and a high barrier. And has been found to have a high base dependency on the conductivity.

That is, the present inventor has found that the ZrB _x N _y film has good adhesion, high conductivity, and high barrier properties as a metal cap layer, and has high conductivity on the metal film (for example, on Cu wiring). It has been found that it has a high insulating property on an insulating film (for example, on a low-k film or a hard mask). By using Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas) as the source gas for this ZrB _x N _y film, generation of particles can be avoided and a stable reaction system is constructed. I found out that I can do it.

In order to achieve the above object, according to the first aspect of the present invention, an insulating layer step of stacking an insulating layer on a semiconductor substrate having an element region, a concave step of forming a concave portion in the insulating layer, and a metal layer in the concave portion A metal layer step of embedding, a planarization step of planarizing the surface of the insulating layer and the surface of the metal layer in substantially the same plane, and excitation with Zr (BH ₄ ) _{4 in} the reaction chamber having the semiconductor substrate. And a metal cap layer step of forming a metal cap layer containing at least zirconium element and nitrogen element on the planarized surface of the insulating layer and the surface of the metal layer by supplying the nitrogen gas This is the gist.

According to this configuration, a metal cap layer made of ZrB _x N _y (x includes 0) is generated in a reaction system using Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas). Can do. Therefore, regardless of the density, surface area, shape, etc. of the metal layer, the metal cap layer exhibits conductivity only in the region corresponding to the metal layer, and avoids a short circuit between adjacent metal layers. In addition, a complicated cleaning process can be omitted because the metal cap layer does not require film formation selectivity. And the reaction system which made the metal cap layer avoid the production | generation of a particle can be constructed | assembled. As a result, the reliability and productivity of the metal cap layer can be improved.

  The gist of the invention according to claim 2 is that the metal cap layer step irradiates the nitrogen gas with microwaves outside the reaction chamber and introduces the excited nitrogen gas into the reaction chamber. .

According to this structure, compared with the case where nitrogen gas is excited in the reaction chamber, the excited nitrogen gas can be supplied in an amount required for the reaction. Therefore, the reaction system using Zr (BH ₄ ) ₄ and the excited nitrogen gas can be further stabilized. In addition, damage to the semiconductor substrate can be avoided when the nitrogen gas is excited.

The gist of the invention according to claim 3 is that the metal cap layer step forms the metal cap layer by a CVD method using the Zr (BH ₄ ) ₄ and the excited nitrogen gas. .

According to a fourth aspect of the present invention, in the semiconductor device manufacturing method according to the first or second aspect, the metal cap layer process uses the Zr (BH ₄ ) ₄ and the excited nitrogen gas. The gist is to form the metal cap layer by an atomic layer deposition method.

According to this configuration, since the metal cap layers made of ZrB _x N _y (x includes 0) are stacked on a monoatomic layer basis, the metal cap layer has information on the foundation (that is, whether the foundation is a conductive film). No) can be taken over with certainty. As a result, the base dependency can be more reliably given to the conductivity of the metal cap layer.

  According to a fifth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the first to fourth aspects, the metal cap layer step is performed at a temperature of less than 260 ° C., preferably 210 ° C., on the semiconductor substrate. The gist is to form the metal cap layer by heating to ˜250 ° C.

According to this configuration, the conductivity of the metal cap layer can be more reliably provided with base dependency, and a more thermally stable metal cap layer can be provided.
In order to achieve the above object, according to the invention described in claim 6, Zr (BH ₄ ) ₄ is supplied to the chamber body, a stage provided in the reaction chamber of the chamber body for mounting the semiconductor substrate, and the reaction chamber. A first supply means for performing the above operation, a second supply means for supplying the excited nitrogen gas to the reaction chamber, and a control means for drivingly controlling the first supply means and the second supply means. Drives and controls the first supply means and the second supply means to supply the Zr (BH ₄ ) ₄ and the excited nitrogen gas to the reaction chamber, and at least zirconium on the surface of the semiconductor substrate. The gist is to form a metal cap layer containing an element and a nitrogen element.

According to this configuration, a metal cap layer made of ZrB _x N _y (x includes 0) is generated in a reaction system using Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas). Can do. Therefore, regardless of the density, surface area, shape, etc. of the metal layer, the metal cap layer exhibits conductivity only in the region corresponding to the metal layer, and avoids a short circuit between adjacent metal layers. In addition, a complicated cleaning process can be omitted because the metal cap layer does not require film formation selectivity. And the reaction system which made the metal cap layer avoid the production | generation of a particle can be constructed | assembled. As a result, the reliability and productivity of the metal cap layer can be improved.

According to a seventh aspect of the present invention, in the semiconductor device manufacturing apparatus according to the sixth aspect, the control means drives and controls the first supply means and the second supply means, so that the Zr (BH ₄ ) ₄ and the excited nitrogen gas are both supplied to the reaction chamber, and a metal cap layer containing at least zirconium element and nitrogen element is formed on the surface of the semiconductor substrate.

According to an eighth aspect of the present invention, in the semiconductor device manufacturing apparatus according to the sixth aspect, the control means drives and controls the first supply means and the second supply means, so that the Zr (BH ₄ ) ₄ and the excited nitrogen gas are alternately supplied to the reaction chamber to adsorb Zr (BH ₄ ) ₄ on the surface of the semiconductor substrate, and then adsorbed by the excited nitrogen gas. (BH
₄ ) The gist is to modify ₄ to a metal cap layer containing at least a zirconium element and a nitrogen element.

According to this configuration, since the metal cap layers made of ZrB _x N _y (x includes 0) are stacked on a monoatomic layer basis, the metal cap layer has information on the foundation (that is, whether the foundation is a conductive film). No) can be taken over with certainty. As a result, the base dependency can be more reliably given to the conductivity of the metal cap layer. In addition, the uniformity of the film thickness and electrical characteristics of the ZrB _x N _y film can be improved by the amount of alternately performing the adsorption reaction and the reforming reaction of Zr (BH ₄ ) ₄ .

  As described above, according to the present invention, it is possible to provide a semiconductor device and a semiconductor device manufacturing method in which the reliability and productivity of the metal cap layer are improved.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. First, a semiconductor device manufactured using the present invention will be described. The semiconductor device is, for example, a memory including various RAMs and various ROMs, a logic including an MPU and general-purpose logic. FIG. 1 is a cross-sectional view of a main part illustrating a semiconductor device.

(Semiconductor device 1)
In FIG. 1, a semiconductor device 1 includes a silicon substrate 2 constituting a semiconductor substrate. The silicon substrate 2 has an element isolation region 2a and an element region 2b surrounded by the element isolation region 2a on the surface (that is, the upper surface shown in FIG. 1). For example, an insulating film such as a silicon oxide film having an STI (Shallow Trench Isolation) structure is buried in the element isolation region 2a. A MOS transistor 3 is formed in the element region 2b. The MOS transistor 3 includes, for example, a gate insulating film 4 formed in the element region 2b, source / drain regions 5 formed on both sides of the gate insulating film 4, a gate electrode 6 stacked on the gate insulating film 4, And a sidewall 7 that covers the outer surface of the gate electrode 6.

  A first interlayer insulating film 8 covering the MOS transistor 3 is laminated on the surface of the silicon substrate 2. The first interlayer insulating film 8 can be constituted by, for example, a silicon oxide film (PSG) to which phosphorus is added or a silicon oxide film (BPSG) to which phosphorus and boron are added. In the first interlayer insulating film 8, recesses (hereinafter simply referred to as contact holes 9) penetrating to the source / drain regions 5 are formed. Contact plugs 10 are respectively formed inside the contact holes 9. The contact plug 10 can be configured by a laminated structure including a contact layer / barrier layer / plug layer (for example, titanium silicide / titanium nitride / tungsten).

  A second interlayer insulating film 11 is stacked on the surface of the first interlayer insulating film 8. As the second interlayer insulating film 11, for example, a silicon oxide film, a silicon oxide film added with phosphorus, or the like can be used. In the second interlayer insulating film 11, a recess (hereinafter simply referred to as the first trench 12) penetrating to the contact hole 9 (or the contact plug 10) is formed. A first wiring 13 is formed inside the first trench 12. The first wiring 13 can be configured by a laminated structure composed of a first barrier layer 14 / first wiring layer 15 (for example, tantalum nitride or titanium nitride / copper).

A first metal cap layer 16 common to the second interlayer insulating film 11 and the first wiring 13 (that is, the first barrier layer 14 and the first wiring layer 15) is laminated on the surface of the second interlayer insulating film 11. ing. The first metal cap layer 16 is a layer mainly composed of zirconium nitride (ZrN) or zirconium nitride boride (ZrB _x N _y ) having high oxidation resistance, and has conductivity according to the conductivity of the base. To express. For example, the first metal cap layer 16 has a specific resistance value of several to several tens [μΩ · cm] in a region corresponding to the surface of the first wiring 13 (a region indicated by a dark dot in FIG. 1). Further, the first metal cap layer 16 has an infinite specific resistance value in a region corresponding to the surface of the second interlayer insulating film 11 (a region indicated by thin dots in FIG. 1).

  Here, a region of the first metal cap layer 16 corresponding to the surface of the first wiring 13 is referred to as a first conductive region 16a. A region of the first metal cap layer 16 corresponding to the surface of the second interlayer insulating film 11 is referred to as a first insulating region 16b.

  The first metal cap layer 16 has a high barrier property against moisture. The first metal cap layer 16 surrounds the first wiring layer 15 by the first conductive region 16 a and the first barrier layer 14 and prevents oxidation of the first wiring layer 15. The first metal cap layer 16 covers the surface of the second interlayer insulating film 11 and prevents the second interlayer insulating film 11 from absorbing moisture. The first metal cap layer 16 prevents metal diffusion of the first wiring 13 and migration of the first wiring 13 due to high adhesion to the first wiring 13 and high barrier properties.

  The first metal cap layer 16 has high conductivity in the first conductive region 16a and high insulation in the first insulating region 16b. Therefore, the first metal cap layer 16 exhibits conductivity only in the first conductive region 16a corresponding to the first wiring 13 regardless of the density, surface area, shape, etc. of the first wiring 13, and the second The first insulating region 16b corresponding to the interlayer insulating film 11 exhibits insulation.

  Thereby, the first metal cap layer 16 reliably avoids a short circuit between the adjacent first wirings 13. Further, since the first metal cap layer 16 is formed on the entire surface of the silicon substrate 2 (that is, the surface of the second interlayer insulating film 11 and the surface of the first wiring 13), the film thickness difference for each first wiring 13. Can be suppressed, and the coating failure of the first wiring 13 due to the variation in film thickness can be avoided.

  A third interlayer insulating film 21 and a trench etch stopper 22 are stacked on the surface of the first metal cap layer 16. The third interlayer insulating film 21 can be composed of a low dielectric constant film (hereinafter simply referred to as a low-k film) such as organic silica glass or porous silica glass. The trench etch stopper 22 is a film having an etching selection ratio with respect to the third interlayer insulating film 21, and can be formed of, for example, a silicon nitride film or a silicon carbide film. The third interlayer insulating film 21 and the trench etch stopper 22 are formed with a common recess (hereinafter simply referred to as a via hole 23) penetrating to the first conductive region 16a of the first metal cap layer 16.

  A fourth interlayer insulating film 31 and a hard mask 32 are stacked on the surface of the trench etch stopper 22. As with the third interlayer insulating film 21, the fourth interlayer insulating film 31 can be composed of various low-k films, for example. The hard mask 32 is a film having an etching selectivity with respect to the fourth interlayer insulating film 31, and can be composed of, for example, a silicon nitride film or a silicon carbide film. The fourth interlayer insulating film 31 and the hard mask 32 are formed with a common recess connected to the via hole 23 (hereinafter simply referred to as a second trench 33).

A second wiring 34 is formed inside the via hole 23 and the second trench 33. The second wiring 34 has a via contact 34 a corresponding to the via hole 23 and a second wiring portion 34 b corresponding to the second trench 33. The second wiring 34 includes a second barrier layer 35 / second wiring layer 36.
(For example, it can be comprised by the laminated structure which consists of tantalum nitride or titanium nitride / copper).

  The second wiring 34 is connected to the first wiring 13 through the first conductive region 16 a of the first metal cap layer 16. The first metal cap layer 16 prevents oxidation of the first conductive region 16 a due to its high oxidation resistance, and enables electrical connection between the first wiring 13 and the second wiring 34.

A second metal cap layer 37 common to the hard mask 32 and the second wiring 34 (that is, the second barrier layer 35 and the second wiring layer 36) is laminated on the surface of the hard mask 32. Similar to the first metal cap layer 16, the second metal cap layer 37 is a layer mainly composed of ZrB _x N _y (x includes 0), and has conductivity according to the conductivity of the base. For example, the second metal cap layer 37 has a specific resistance value of several to several tens [μΩ · cm] in a region corresponding to the surface of the second wiring 34 (a region indicated by a dark dot in FIG. 1). The second metal cap layer 37 has an infinite specific resistance value in a region corresponding to the surface of the hard mask 32 (a region indicated by thin dots in FIG. 1).

  Here, the region of the second metal cap layer 37 corresponding to the surface of the second wiring 34 is referred to as a second conductive region 37a. A region of the second metal cap layer 37 corresponding to the surface of the hard mask 32 is referred to as a second insulating region 37b.

  The second metal cap layer 37 has a high barrier property against moisture. The second metal cap layer 37 surrounds the second wiring layer 36 by the second conductive region 37a and the second barrier layer 35 and prevents oxidation of the second wiring layer 36. The second metal cap layer 37 covers the surface of the hard mask 32, prevents moisture absorption of the fourth interlayer insulating film 31, and stabilizes the dielectric constant of the low-k film. The second metal cap layer 37 prevents metal diffusion from the second wiring 34 and migration of the second wiring 34 due to high adhesion to the second wiring 34 and high barrier properties.

  The second metal cap layer 37 has high conductivity in the second conductive region 37a and high insulation in the second insulating region 37b. Therefore, the second metal cap layer 37 exhibits conductivity only in the second conductive region 37a corresponding to the second wiring 34 regardless of the density, surface area, shape, etc. of the second wiring 34, and is a hard mask. The second insulating region 37b corresponding to 32 exhibits insulation.

  Thereby, the second metal cap layer 37 reliably avoids a short circuit between the adjacent second wirings 34. In addition, since the second metal cap layer 37 is formed on the entire surface of the silicon substrate 2 (that is, the surface of the hard mask 32 and the surface of the second wiring 34), the difference in film thickness for each second wiring 34 is suppressed. Therefore, it is possible to avoid the coating failure of the second wiring 34 due to the variation in film thickness.

(Semiconductor device manufacturing equipment)
Next, the film forming apparatus 40 as the semiconductor device manufacturing apparatus will be described.
In FIG. 2, the film forming apparatus 40 includes a load lock chamber 40L, a core chamber 40C connected to the load lock chamber 40L, and four film forming chambers 40D connected to the core chamber 40C. Yes. The load lock chamber 40L, the core chamber 40C, and the film forming chambers 40D communicate with each other in a releasable manner to form a common vacuum system.

The load lock chamber 40L accommodates the plurality of silicon substrates 2 in the decompression space, and carries the plurality of silicon substrates 2 into the film forming apparatus 40 when starting the film forming process of the silicon substrate 2, respectively. When the film formation process of the silicon substrate 2 is completed, the load lock chamber 40L accommodates the silicon substrate 2 after the film formation process, releases it to the atmosphere, and carries it out of the film formation apparatus 40.

  When starting the film forming process of the silicon substrate 2, the core chamber 40C carries the silicon substrate 2 before the film forming process from the load lock chamber 40L and transfers it to each film forming chamber 40D. When the film forming process of the silicon substrate 2 is finished, the core chamber 40C carries the silicon substrate 2 after the film forming process from each film forming chamber 40D and transports it to the load lock chamber 40L.

Each film formation chamber 40D is a chamber for forming a ZrB _x N _y film using a CVD method or an atomic layer deposition (ALD) method. When each film forming chamber 40D performs the film forming process of the silicon substrate 2, the silicon substrate 2 is loaded from the core chamber 40C, and a ZrB _x N _y film, that is, the first and second films are formed on the surface of the silicon substrate 2. Metal cap layers 16 and 37 are formed.

  In FIG. 3, the film forming chamber 40 </ b> D includes a chamber main body 41 having an upper opening, and a chamber lid 42 disposed on the upper portion of the chamber main body 41 so that the upper opening can be opened and closed. The film forming chamber 40D has an internal space (hereinafter simply referred to as a reaction chamber S) surrounded by the chamber body 41 and the chamber lid 42.

  The chamber body 41 is provided with a substrate stage 43 on which the silicon substrate 2 is placed. The substrate stage 43 is a stage on which a resistance heater is mounted. When placing the silicon substrate 2, the substrate stage 43 raises the temperature of the silicon substrate 2 to a predetermined temperature (for example, 200 [° C.] to 240 [° C.]). An elevating mechanism 44 is connected to the lower side of the substrate stage 43. The elevating mechanism 44 moves the substrate stage 43 up and down to allow the silicon substrate 2 to be carried in and out.

  An exhaust pump 45 is connected to one side of the chamber body 41 through an exhaust port PD. The exhaust pump 45 includes various pumps such as a turbo molecular pump and a dry pump, and reduces the pressure in the reaction chamber S to a predetermined pressure (for example, 1 [Pa] to 1000 [Pa]).

A shower head 46 for introducing gas into the reaction chamber S is disposed below the chamber lid 42. The shower head 46 includes a plurality of first gas supply holes H1 and a plurality of second gas supply holes H2 that are independent from the first gas supply holes H1. The shower head 46 introduces Zr (BH ₄ ) ₄ gas from the first gas supply holes H 1 toward the reaction chamber S. Further, the shower head 46 introduces nitrogen gas into the reaction chamber S from each second gas supply hole H2.

A first gas port P <b> 1 is provided on the upper side of the chamber lid 42. The first gas port P <b> 1 communicates with each first gas supply hole H <b> 1 of the shower head 46 through the inside of the chamber lid 42. The first gas port P <b> 1 is connected to the supply tank T via a supply pipe and a supply valve outside the chamber lid 42. The supply tank T is a tank that stores Zr (BH ₄ ) ₄ while keeping the temperature at 0 ° C., and is connected to the mass flow controller MC1.

The mass flow controller MC1 is connected to a carrier gas (for example, argon (Ar)) supply system, and supplies Ar at a predetermined flow rate into the supply tank T. The mass flow controller MC1 controls the supply amount of Ar in a flow rate range of 10 [sccm] to 500 [sccm], for example. When mass flow controller MC1 supplies the carrier gas, supply tank T is bubbling Zr _{(BH 4) 4} which houses, Zr _{(BH 4) 4} carrier gas (hereinafter simply containing, Zr _{(BH 4) 4} gas Is supplied to the first gas port P1. Zr (BH ₄ ) ₄ gas is introduced into the reaction chamber S from each first gas supply hole H1 through the first gas port P1.

  A second gas port P <b> 2 is provided at the upper end portion of the chamber lid 42. The second gas port P <b> 2 communicates with each second gas supply hole H <b> 2 of the shower head 46 through the inside of the chamber lid 42. The second gas port P2 is connected to the mass flow controller MC2, the mass flow controller MC3, and the mass flow controller MC4 via a supply pipe and a supply valve outside the chamber lid 42.

Each mass flow controller MC2, MC3, MC4 is connected to a supply system of hydrogen (H ₂ ) gas, ammonia (NH ₃ ) gas, and nitrogen (N ₂ ) gas, respectively, and has a predetermined flow rate of H _{2 at} the second gas port P2. , NH ₃ and N ₂ are supplied. The mass flow controllers MC2, MC3, and MC4 control the supply amounts of H ₂ , NH ₃ , and N _{2 in} a flow rate range of 10 [sccm] to 500 [sccm], for example. Mass flow controllers MC2, MC3, when MC4 supplies the _{H 2,} NH _{3, N} 2, _{respectively,} H _2, NH _{3, N 2,} the reaction chamber from the second gas supply holes H2 through the second gas port P2, respectively S is introduced and reaches the surface of the silicon substrate 2 placed on the substrate stage 43.

  An irradiation tube 47 is provided in the upper part of the chamber lid 42 and between the second gas port P2 and the second gas supply hole H2. The irradiation tube 47 is a heat-resistant cylindrical tube made of a quartz tube or an alumina tube, and guides the gas supplied to the second gas port P2 toward the second gas supply holes H2.

  Outside the irradiation tube 47 and in the middle of the irradiation tube 47 in the longitudinal direction, a microwave source 48 driven by a microwave power source FG and a waveguide connected to the microwave source 48 and extending toward the irradiation tube 47. 49 are arranged.

  The microwave source 48 is a microwave oscillator (that is, a magnetron) that generates a microwave of 2.45 GHz, for example, and receives a driving power of the microwave power source FG to have a predetermined output range (for example, 0.1 to 3.. 0 [kW]) microwaves are intermittently output. The waveguide 49 propagates the microwave oscillated by the microwave source 48 into the waveguide 49 and introduces it into the irradiation tube 47. When the microwave source 48 oscillates the microwave, the waveguide 49 is excited by irradiating the gas passing through the irradiation tube 47 with the microwave and activated (that is, converted into plasma).

The gas introduced into the irradiation tube 47 from the second gas port P2 is introduced into the reaction chamber S from each second gas supply hole H2, and is introduced in an excited state when the microwave source 48 oscillates microwaves. . Zr (BH ₄ ) ₄ staying in the reaction chamber S reacts with the excited N ₂ gas to form a ZrB _x N _y film on the surface of the silicon substrate 2.

Next, the electrical configuration of the film forming apparatus 40 will be described.
In FIG. 4, the control unit 51 causes the film forming apparatus 40 to execute various processing operations, such as a transfer processing operation of the silicon substrate 2 and a film forming processing operation of the silicon substrate 2. The control unit 51 includes a CPU that executes various arithmetic processes, a storage unit 51A that stores various data and various control programs, and a timer 51B that measures a process time for each of various processing steps. For example, the control unit 51 reads the film formation processing program stored in the storage unit 51A, and causes the film formation processing operation to be executed according to the process time measured by the timer 51B and the read film formation processing program.

An input / output unit 52 is connected to the control unit 51. The input / output unit 52 includes various operation switches such as a start switch and a stop switch, and various display devices such as a liquid crystal display. The input / output unit 52 inputs data used for each processing operation to the control unit 51 and outputs data regarding the processing status of the film forming apparatus 40. The input / output unit 52 includes, for example, data related to various parameters (process time, gas flow rate, output value of the microwave power source FG, etc.) during film formation (hereinafter simply referred to as film formation condition data Id) to the control unit 51. input. The control unit 51 receives the film formation condition data Id input from the input / output unit 52, generates various drive control signals corresponding to the film formation condition data Id, and forms film formation conditions corresponding to the film formation condition data Id. The film forming operation is performed under

  An exhaust system drive circuit 53 for driving and controlling the exhaust system is connected to the control unit 51. The control unit 51 outputs a drive control signal corresponding to the exhaust system drive circuit 53 to the exhaust system drive circuit 53. In response to a drive control signal from the control unit 51, the exhaust system drive circuit 53 drives an exhaust system (for example, the exhaust pump 45) for reducing the pressure in the chamber (for example, the reaction chamber S) to a predetermined pressure. .

  A transport system drive circuit 54 is connected to the control unit 51. The control unit 51 outputs a drive control signal corresponding to the transport system drive circuit 54 to the transport system drive circuit 54. In response to the drive control signal from the control unit 51, the transport system drive circuit 54 drives a transport system (for example, the lifting mechanism 44) for transporting the silicon substrate 2. Further, the transfer system drive circuit 54 drives a heater of the substrate stage 43 for raising the temperature of the silicon substrate 2 in response to a drive control signal from the control unit 51.

  A mass flow controller drive circuit 55 is connected to the control unit 51. The control unit 51 outputs a drive control signal corresponding to the mass flow controller drive circuit 55 to the mass flow controller drive circuit 55. In response to the drive control signal from the control unit 51, the mass flow controller drive circuit 55 drives each mass flow controller MC1 to MC4 for supplying each gas.

  A microwave power source driving circuit 56 is connected to the control unit 51. The control unit 51 outputs a drive control signal corresponding to the microwave power supply driving circuit 56 to the microwave power supply driving circuit 56. The microwave power supply driving circuit 56 drives the microwave power supply FG for oscillating microwaves in response to the drive control signal from the control unit 51.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing the semiconductor device 1 using the film forming apparatus 40 will be described.
First, as shown in FIG. 1, an element isolation region 2 a and an element region 2 b are partitioned on the surface of the silicon substrate 2. For example, a silicon oxide film is embedded in the element isolation region 2a using a known STI process. Further, a gate insulating film 4, a source / drain region 5, a gate electrode 6, sidewalls 7 and the like are formed using a known MOS process, and a MOS transistor 3 is formed in the element region 2b.

  When the MOS transistor 3 is formed, a first interlayer insulating film 8 is stacked on the surface of the silicon substrate 2 to form a contact plug 10. For example, the first interlayer insulating film 8 is formed by laminating a silicon oxide film covering the MOS transistor 3 on the surface of the silicon substrate 2 using the CVD technique, and the first interlayer insulating film using the photolithography technique and the etching technique. Contact holes 9 are formed in the film 8. Next, titanium silicide / titanium nitride / tungsten is buried in the contact hole 9 using a sputtering technique or a CVD technique, and planarized using a CMP (Chemical Mechanical Polishing) technique or an etch back technique to form the contact plug 10.

When the contact plug 10 is formed, a second interlayer insulating film 11 is stacked on the surface of the first interlayer insulating film 8, and a first trench 12 is formed in the second interlayer insulating film 11. That is, an insulating layer process is performed, and then a recess process is performed. For example, the insulating layer process uses a CVD technique to form a second interlayer insulating film 11 by laminating a silicon oxide film on the surface of the first interlayer insulating film 8, and the recess process uses a photolithography technique and an etching technique. In this way, the first trench 12 is formed.

  When the first trench 12 is formed, the first wiring 13 is stacked on the surface of the second interlayer insulating film 11 including the inside of the first trench 12, and the surface of the second interlayer insulating film 11 and the surface of the first wiring 13 are planarized. Let That is, a metal layer process is performed, and then a planarization process is performed. For example, in the metal layer process, the first barrier layer 14 is formed by stacking titanium nitride on the entire silicon substrate 2 including the inner surface of the first trench 12 by using a sputtering technique. Next, a copper plating seed layer is formed on the surface of the first barrier layer 14 using an electroless plating technique or a CVD technique, and the entire silicon substrate 2 including the inside of the first trench 12 is formed using an electrolytic plating technique. Copper is deposited on the first wiring layer 15 to form the first wiring layer 15. In the planarization step, the first barrier layer 14 and the first wiring layer 15 are polished using CMP technology, and the surfaces of the first barrier layer 14 and the first wiring layer 15 are substantially the same as the surface of the second interlayer insulating film 11. The first wiring 13 is formed so as to be flush with each other.

  When the first wiring 13 is formed, the silicon substrate 2 having the second interlayer insulating film 11 and the first wiring 13 on the surface is set in the load lock chamber 40L of the film forming apparatus 40, and the metal cap layer process is performed.

  That is, the control unit 51 of the film forming apparatus 40 receives the film forming condition data Id from the input / output unit 52, drives the exhaust pump 45 via the exhaust system drive circuit 53, and reacts to accommodate the silicon substrate 2. The chamber S is depressurized in advance to a predetermined ultimate pressure (for example, 1 [Pa]). When the pressure in the reaction chamber S is reduced, the control unit 51 drives the transfer system via the transfer system drive circuit 54 to transfer the silicon substrate 2 in the load lock chamber 40L to the film forming chamber 40D.

The control unit 51 drives the elevating mechanism 44 via the transfer system drive circuit 54 to place the silicon substrate 2 on the substrate stage 43, starts a process time counting operation using the timer 51B, The temperature is raised to a predetermined temperature (for example, 240 [° C.]). At this time, as shown in FIG. 5, the controller 51 drives the mass flow controller MC < _b > 2 via the mass flow controller drive circuit 55 to supply the reaction chamber S with H ₂ gas having a predetermined flow rate. Further, the control unit 51 drives the exhaust system via the exhaust system drive circuit 53 to maintain the pressure in the reaction chamber S at a predetermined pressure value. Thereby, the temperature rise of the silicon substrate 2 can be promoted, and if the temperature of the silicon substrate 2 is 250 [° C.] or higher, the surface of the copper film (first wiring 13) is reduced. In addition, when hydrogen (H ₂ ) excited by microwaves is used, if the temperature of the silicon substrate 2 is 130 ° C. or higher, a reduction effect on the copper film surface can be obtained.

  When the process time counted by the timer 51B reaches a predetermined time, the control unit 51 passes through the exhaust system drive circuit 53, the mass flow controller drive circuit 55, and the microwave power supply drive circuit 56, and sets each process according to the film formation condition data Id. A processing step is executed.

That is, the control unit 51 causes the mass flow controller MC2 to stop supplying the H ₂ gas via the mass flow controller drive circuit 55. Next, the control unit 51 drives the exhaust system via the exhaust system drive circuit 53 and sets the exhaust capacity of the exhaust system in advance so that the pressure of the reaction chamber S under the film forming conditions becomes a predetermined pressure value. .

When the exhaust system is set, the control unit 51 drives the mass flow controller MC4 via the mass flow controller drive circuit 55 to supply the reaction chamber S with N ₂ gas having a predetermined flow rate. In addition, the control unit 51 drives the microwave power source FG via the microwave power source driving circuit 56 to supply the excited N ₂ gas to the reaction chamber S.

When the controller 51 starts supplying the excited N ₂ gas, the controller 51 drives the mass flow controller MC1 via the mass flow controller drive circuit 55 to supply the reaction chamber S with a predetermined flow rate of Zr (BH ₄ ) ₄ gas. Let As a result, the control unit 51 starts a gas phase reaction between Zr (BH ₄ ) ₄ and the excited N ₂ gas, and the first metal whose main component is the ZrB _x N _y film on the entire surface of the silicon substrate 2. A cap layer 16 is deposited.

The deposited ZrB _x N _y film exhibits conductivity only in the region on the first wiring 13 regardless of the density, surface area, shape, and the like of the first wiring 13, and avoids a short circuit between adjacent wirings. In addition, since the ZrB _x N _y film has high oxidation resistance and high barrier properties, oxidation of the ZrB _x N _y film itself, oxidation of the first wiring 13, moisture absorption of the second interlayer insulating film 11, etc. in the manufacturing process are performed. Stop. In addition, since the ZrB _x N _y film has high adhesion with the first wiring 13, mechanical damage such as film peeling of the first metal cap layer 16 is avoided. Moreover, this ZrB _x N _y film is formed on the entire silicon substrate 2 by the film forming chamber 40D. Therefore, compared to the case where a metal cap layer is formed for each first wiring 13, this ZrB _x N _y film suppresses a difference in film thickness between the first wirings 13, and the first wiring 13 due to film thickness variation. To avoid poor coating.

A stable reaction system can be provided by using Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas) as a source gas for the ZrB _x N _y film, and the inside of the reaction chamber S The generation of particles can be suppressed throughout the reaction system such as the supply pipe and the exhaust pipe. Moreover, as compared with the thermal decomposition reaction of Zr (BH ₄ ) ₄ in an N ₂ gas atmosphere, more nitrogen element is contained in the ZrB _x N _y film as much as the excited N ₂ gas is used. Can do. In addition, the life of the excited N ₂ gas can be extended by the amount of nitrogen-based gas (N ₂ gas) not containing hydrogen element, and the generation of Zr—N bonds can be promoted. As a result, the substrate selectivity of the resistivity of the ZrB _x N _y film can be expressed more reliably.

When the process time counted by the timer 51B reaches a predetermined time, the control unit 51 causes the mass flow controller MC1 to stop supplying the Zr (BH ₄ ) ₄ gas via the mass flow controller drive circuit 55. Next, the control unit 51 stops the microwave oscillation and stops the supply of N ₂ gas via the microwave power source driving circuit 56 and the mass flow controller driving circuit 55. Then, the control unit 51 drives the transport system via the transport system drive circuit 54, transports the silicon substrate 2 having the first metal cap layer 16 to the load lock chamber 40 </ b> L, and unloads it from the film forming apparatus 40.

  When the first metal cap layer 16 is formed, a third interlayer insulating film 21, a trench etch stopper 22, a fourth interlayer insulating film 31, and a hard mask 32 are sequentially stacked on the surface of the first metal cap layer 16. That is, an insulating layer process is performed.

  For example, in the insulating layer process, the third interlayer insulating film 21 is formed by laminating an organic silica glass on the surface of the first metal cap layer 16 using the CVD technique or the spin coat technique, and the first interlayer cap film 21 is formed using the CVD technique. A trench etching stopper 22 is formed by laminating a silicon carbide film on the surface of the three interlayer insulating film 21. Further, the fourth interlayer insulating film 31 is formed by laminating organic silica glass on the surface of the trench etch stopper 22 using the CVD technique or the spin coat technique, and the surface of the fourth interlayer insulating film 31 is formed using the CVD technique. A hard mask 32 is formed by laminating a silicon carbide film.

When the hard mask 32 is formed, the via hole 23 and the second trench 33 are formed in the third interlayer insulating film 21, the trench etch stopper 22, the fourth interlayer insulating film 31, and the hard mask 32. That is, the concave step is executed. For example, in the recess process, the via hole 23 and the second trench 33 are formed using a via first method in which the via hole 23 is formed in advance.

  When the via hole 23 and the second trench 33 are formed, the second wiring 34 is stacked on the surface of the fourth interlayer insulating film 31 including the inside of the via hole 23 and the second trench 33, and the surface of the fourth interlayer insulating film 31 and the second The surface of the wiring 34 is flattened. That is, a metal layer process is performed, and then a planarization process is performed. For example, in the metal layer process, the second barrier layer 35 is formed by stacking titanium nitride on the entire silicon substrate 2 including the inner surface of the via hole 23 and the second trench 33 by using a sputtering technique. Next, a copper plating seed layer is formed on the surface of the second barrier layer 35 using the electroless plating technique or the CVD technique, and the silicon substrate including the via hole 23 and the inside of the second trench 33 is used using the electrolytic plating technique. Then, copper is deposited on the entire surface 2 to form the second wiring layer 36. In the planarization step, the second barrier layer 35 and the second wiring layer 36 are polished using CMP technology so that the surfaces of the second barrier layer 35 and the second wiring layer 36 are substantially flush with the surface of the hard mask 32. Thus, the second wiring 34 is formed.

When the second wiring 34 is formed, the silicon substrate 2 is transferred to the film forming apparatus 40, and a second metal cap layer 37 is formed on the surfaces of the hard mask 32 and the second wiring 34. That is, similar to the first metal cap layer 16, a common ZrB _x N _y film is laminated on the entire surface of the silicon substrate 2 (the surface of the hard mask 32 and the surface of the second wiring 34) to form the second metal cap layer 37. (A metal cap layer process is performed).

Like the first metal cap layer 16, the second metal cap layer 37 has high oxidation resistance and high barrier properties. Therefore, the oxidation of the ZrB _x N _y film itself, the oxidation of the second wiring 34, the fourth, The moisture absorption of the interlayer insulating film 31 is prevented. In addition, since the ZrB _x N _y film has high adhesion with the second wiring 34, mechanical damage such as film peeling of the second metal cap layer 37 is avoided. Moreover, this ZrB _x N _y film is formed on the entire silicon substrate 2 by the film forming chamber 40D. Therefore, compared with the case of forming a metal cap layer for each second wire 34, the ZrB _x N _y film, the second wiring to suppress the film thickness difference between the second wire 34, due to variation in the film thickness 34 To avoid poor coating.

A stable reaction system can be provided by using Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas) as the source gas of the second metal cap layer 37, and It is possible to suppress the generation of particles throughout the reaction system such as the inside, supply piping, and exhaust piping. Moreover, as compared with the thermal decomposition reaction of Zr (BH ₄ ) ₄ in an N ₂ gas atmosphere, more nitrogen element is contained in the ZrB _x N _y film as much as the excited N ₂ gas is used. Can do. In addition, the life of the excited N ₂ gas can be extended by the amount of nitrogen-based gas (N ₂ gas) not containing hydrogen element, and the generation of Zr—N bonds can be promoted. As a result, the substrate selectivity of the resistivity of the ZrB _x N _y film can be expressed more reliably.

(Example)
Next, the effects of the present invention will be described with reference to examples. Tables 1 to 4 show the conductivity of the ZrB _x N _y film formed under various conditions using the film forming apparatus 40, respectively. 6 to 9 show the element concentrations of Examples and Comparative Examples in Tables 1 to 4, respectively. The film thickness data in the examples are values measured using a scanning electron microscope (SEM) by cleaving the vicinity of the center of the silicon substrate.

In Table 1, a silicon substrate having a copper film on the surface was used, Zr (BH ₄ ) ₄ gas was 100 [sccm], N ₂ gas was 100 [sccm], and the film formation time was 2 [min]. Film formation was performed under the conditions of a temperature of 240 [° C.], a film forming pressure of 700 [Pa], and a microwave output of 500 [W], and the ZrB _x N _y film of Example 1 was obtained. In addition, using a silicon substrate having a silicon oxide film on the surface, film formation was performed under the same conditions as in Example 1 to obtain a ZrB _x N _y film in Example 2. At this time, the number of particles in and on the ZrB _x N _y film was measured, and it was confirmed that the number of particles increased was several. Further, the inner wall of the reaction chamber S, the inside of the supply pipe, and the inside of the exhaust pipe were visually confirmed to confirm that no powdery by-product was generated.

Further, in Table 1, the ZrB _x N _y film of Comparative Example 1 was obtained by changing the N ₂ gas of Example 2 to NH ₃ gas and using the same conditions. Moreover, the N ₂ gas of Example 2 was changed to a mixed gas of N ₂ gas and H ₂ gas, and the ZrB _x N _y film of Comparative Example 2 was obtained under the same conditions. At this time, the number of particles in and on the ZrB _x N _y film was measured, and it was confirmed that the number of particles increased was several. Further, the inner wall of the reaction chamber S, the inside of the supply pipe, and the inside of the exhaust pipe were visually confirmed to confirm that no powdery by-product was generated.

And the film thickness and the sheet resistance value were measured for the ZrB _x N _y films of Example 1, Example 2, Comparative Example 1, and Comparative Example 2, respectively. In addition, the element concentrations in the films were measured for the ZrB _x N _y films of Example 2, Comparative Example 1, and Comparative Example 2 using Auger Electron Spectroscopy (AES). The results of the film thickness and the sheet resistance value are shown in Table 1, and the measurement results of the element concentrations of Example 2, Comparative Example 1, and Comparative Example 2 are shown in FIGS. 6, 7, and 8, respectively. 6 to 9, the horizontal axis indicates the sputtering time of the sample (ZrB _x N _y film / silicon oxide film), that is, the film thickness of the ZrB _x N _y film, and the vertical axis indicates the concentration of the target element, That is, elemental concentrations of boron (B), carbon (C), nitrogen (N), oxygen (O), silicon (Si), and zirconium (Zr) are shown.

表１において、“∞”は、対応するＺｒＢ_ｘＮ_ｙ膜のシート抵抗値が計測した４９点の全てにおいて検出限界を超えた値（５×１０^６［Ω／□］以上）であることを示す。

In Table 1, “∞” indicates that the sheet resistance value of the corresponding ZrB _x N _y film exceeded the detection limit at all 49 points measured (5 × 10 ⁶ [Ω / □] or more). Show.

In Table 1, the ZrB _x N _y film of Example 1 has a sheet resistance value of about 6 [Ω / □], and exhibits high conductivity when laminated on a copper film (conductive film). I understand. It can be seen that the ZrB _x N _y film of Example 2 has a sheet resistance value of “∞” and exhibits high insulating properties when laminated on the silicon oxide film (insulating film). That is, it can be seen that the ZrB _x N _y films obtained by the film forming conditions of Example 1 and Example 2 have a large base selectivity with respect to the resistivity.

  On the other hand, although Comparative Example 1 and Comparative Example 2 were formed on the silicon oxide film, each showed a sheet resistance value lower than that of Example 2, and were laminated on the silicon oxide film (insulating film). It turns out that perfect insulation is not expressed in the state.

In FIG. 6, Example 2 contains nitrogen element (N) at a concentration higher than that of boron element (B) in the ZrB _x N _y film, and contains more than 40% nitrogen element in its bulk. I understand that. On the other hand, in FIGS. 7 and 8, Comparative Example 1 and Comparative Example 2 each contain nitrogen element (N) at a concentration clearly lower than the concentration of boron element (B), and the concentration is less than 20%. I understand that.

As a result, the NH ₃ gas of Comparative Example 1 and the H ₂ gas of Comparative Example 2, that is, the hydrogen element in the process gas decreases the concentration of the nitrogen element taken into the ZrB _x N _y film, and ZrB _x N _y It becomes a factor that inhibits the expression of the insulating properties of the film. Therefore, a nitrogen-added gas that does not contain a hydrogen element, that is, a gas phase reaction system of excited N ₂ gas and Zr (BH ₄ ) ₄ , provides more reliable substrate selectivity for the resistivity of the ZrB _x N _y film. Can make things. Further, the gas phase reaction system of Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas) is sufficiently stable as a reaction system of the ZrB _x N _y film because no increase factor of the particles is observed. A system can be provided.

In Table 2, the ZrB _x N _y films of Comparative Example 3 and Comparative Example 4 were obtained under the same conditions except for extending the film formation time of Example 2. In Table 3, the ZrB _x N _y films of Comparative Example 5, Comparative Example 6, and Comparative Example 7 were obtained under the same conditions except that the film formation temperature of Example 2 was changed. In Table 4, the ZrB _x N _y films of Comparative Example 8, Comparative Example 9, and Comparative Example 10 were obtained under the same conditions except that the film formation pressure and microwave output of Example 2 were changed. At this time, the number of particles in and on each ZrB _x N _y film was measured, and it was confirmed that the number of particles increased was several. Further, the inner wall of the reaction chamber S, the inside of the supply pipe, and the inside of the exhaust pipe were visually confirmed to confirm that no powdery by-product was generated.

Then, the film thickness and the sheet resistance value were measured for each of the ZrB _x N _y films of Comparative Examples 3 to 10, and the element concentration in the film was measured using AES for the ZrB _x N _y film of Comparative Example 7 Was measured. The film thickness and sheet resistance values of Comparative Examples 3 to 10 are shown in Tables 2 to 4, respectively, and the element concentration measurement results of Comparative Example 7 are shown in FIG.

表２において、比較例３と比較例４は、実施例２と同じく、ＺｒＢ_ｘＮ_ｙ膜のシート抵抗値が“∞”を示し、シリコン酸化膜（絶縁膜）に積層された状態で、高い絶縁性を示すことが分かる。したがって、Ｚｒ（ＢＨ_４）_４と励起された窒素ガス（Ｎ_２ガス）の反応系は、その成膜時間に大きく依存することなく、ＺｒＢ_ｘＮ_ｙ膜の抵抗率の下地選択性を発現させることができ、その成膜条件の範囲を拡張させることができる。

In Table 2, Comparative Example 3 and Comparative Example 4 have the same sheet resistance value of ZrB _x N _y film as “∞” as in Example 2, and are high in a state where the film resistance is laminated on the silicon oxide film (insulating film). It can be seen that insulation is exhibited. Therefore, the reaction system of Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas) exhibits the substrate selectivity of the resistivity of the ZrB _x N _y film without greatly depending on the film formation time. And the range of film forming conditions can be expanded.

In Table 3, Comparative Example 5 and Comparative Example 6 have the same sheet resistance value of ZrB _x N _y film as “∞” as in Example 2, and are high in a state where the film resistance is laminated on the silicon oxide film (insulating film). It can be seen that insulation is exhibited. On the other hand, Comparative Example 7 shows a sheet resistance value lower than that of Example 2 despite being formed on the silicon oxide film, and is completely insulated in a state of being laminated on the silicon oxide film (insulating film). It turns out that sex is not expressed.

Also, in FIG. 9, it can be seen that Comparative Example 7 contains nitrogen element (N) at a concentration lower than the concentration of boron element (B), and the concentration is less than 30%. That is, excess deposition of conditions was raised lowers the concentration of nitrogen element taking the ZrB _x N _y film, and is a cause of inhibiting the ZrB _x N _y expression of an insulating film.

Therefore, the temperature at which the ZrB _x N _y film takes in a sufficient amount of nitrogen element and the various bonds contained in the ZrB _x N _y film are stabilized by thermal energy, that is, less than 260 ° C. The temperature range, preferably 180 ° C. to 250 ° C., makes the substrate selectivity of the resistivity of the ZrB _x N _y film more reliable and ensures the thermal stability of the ZrB _x N _y film. Can be made.

In Table 4, Comparative Example 8, like Example 2, has a sheet resistance value of “∞” for the ZrB _x N _y film, and exhibits high insulation properties when laminated on the silicon oxide film (insulating film). I understand that. That is, the ZrB _x N _y film obtained by the film formation conditions of Example 1 and Example 2 exhibits the resistivity base selectivity even when the film formation pressure is low.

Therefore, the reaction system of Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas) can ensure a wide pressure range when forming a ZrB _x N _y film having base selectivity. The range of the film forming conditions can be expanded.

In Table 4, Comparative Example 9, like Example 2, has a sheet resistance value of “∞” for the ZrB _x N _y film, and exhibits high insulation when stacked on the silicon oxide film (insulating film). I understand that. On the other hand, although Comparative Example 10 is formed on the silicon oxide film, the sheet resistance value is lower than that of Example 2 and is completely insulated in a state where it is laminated on the silicon oxide film (insulating film). It turns out that sex is not expressed.

Therefore, by using the excited nitrogen gas (N ₂ gas), the concentration of nitrogen element taken into the ZrB _x N _y film is increased, and the ZrB _x N _y film is induced to exhibit its insulating properties. Can do.

According to the said embodiment, there exist the following effects.
(1) In the above embodiment, the second interlayer insulating film 11 and the first wiring 13, or the second wiring layer 36 and the hard mask 32 are formed on the surface of the silicon substrate 2, and the silicon substrate 2 is placed in the reaction chamber S. The N ₂ gas excited by the microwave is introduced into the reaction chamber S. Then, a Zr _{(BH 4)} 4 which is accommodated in the supply tank T bubbled with Ar gas, is introduced into the reaction chamber S and Ar gas containing Zr _{(BH 4)} 4 as Zr _{(BH 4) 4} gas.

Therefore, the first and second metal cap layers 16 and 37 made of ZrB _x N _y (x includes 0) are made to react with Zr (BH ₄ ) ₄ and excited nitrogen gas (N ₂ gas). Can be generated. As a result, the first and second metal cap layers 16 and 37 develop conductivity only in the region corresponding to the metal layer regardless of the density, surface area, shape, etc. of the underlying metal layer, and between the adjacent metal layers. Avoid short circuit. Further, since the first and second metal cap layers 16 and 37 do not require film formation selectivity, a complicated cleaning process can be omitted. A reaction system that avoids the generation of particles can be constructed for the first and second metal cap layers 16 and 37. Therefore, the reliability and productivity of the first and second metal cap layers 16 and 37 can be improved.

(2) In the above embodiment, the N ₂ gas is irradiated with microwaves outside the reaction chamber S, and the excited N ₂ gas is introduced into the reaction chamber S. Therefore, compared with the case where the N ₂ gas is excited in the reaction chamber S, the excited N ₂ gas can be supplied in an amount required for the reaction. As a result, the reaction system using Zr (BH ₄ ) ₄ and the excited N ₂ gas can be further stabilized. In addition, damage to the silicon substrate 2 can be avoided when the N ₂ gas is excited.

(3) In the above embodiment, the silicon substrate 2 is heated to 210 ° C. to 240 ° C. when the ZrB _x N _y film is formed. Therefore, it is possible to more reliably exhibit the base dependency with respect to the conductivity of the first and second metal cap layers 16 and 37 and to form a thermally stable ZrB _x N _y film. .

(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the film formation condition of the ZrB _x N _y film in the first embodiment is changed from the CVD method to the ALD method. Therefore, hereinafter, the deposition conditions for the ZrB _x N _y film will be described.

  The control unit 51 of the film forming apparatus 40 receives the film forming condition data Id from the input / output unit 52 as in the first embodiment. The control unit 51 drives the exhaust pump 45 via the exhaust system drive circuit 53 to reduce the reaction chamber S to a predetermined ultimate pressure (for example, 1 [Pa]). When the pressure in the reaction chamber S is reduced, the control unit 51 drives the transfer system via the transfer system drive circuit 54 to transfer the silicon substrate 2 in the load lock chamber 40L to the film forming chamber 40D.

  When the temperature of the silicon substrate 2 is raised to a predetermined temperature, the control unit 51 performs each process according to the film formation condition data Id via the exhaust system drive circuit 53, the mass flow controller drive circuit 55, and the microwave power supply drive circuit 56. The process is executed.

That is, in FIG. 10, when the film forming process is started, the control unit 51 drives the mass flow controller MC1 via the mass flow controller drive circuit 55, and supplies Zr (BH ₄ ) ₄ gas at a predetermined flow rate to the reaction chamber S. Introduce and start the adsorption process. For example, the control unit 51 causes the mass flow controller MC1 to supply 100 [sccm] of Ar and Zr (B
Ar gas containing H ₄ ) ₄ , that is, Zr (BH ₄ ) ₄ gas is introduced into the reaction chamber S.

Here, a period during which Zr (BH ₄ ) ₄ gas is introduced into the reaction chamber S is referred to as an adsorption period Ta. The adsorption period Ta is set in advance based on a test or the like, and a period during which Zr (BH ₄ ) ₄ (adsorbed molecule MA) forms a monomolecular layer over the entire surface of the silicon substrate 2 (for example, 1 to 5 seconds). Is set to

In FIG. 11, Zr (BH ₄ ) ₄ (adsorption molecule MA) introduced into the reaction chamber S is adsorbed on the same surface by a strong interaction with the surface of the silicon substrate 2. That is, Zr (BH ₄ ) ₄ functions as an adsorbed molecule MA that is physically or chemically adsorbed to the surface of the silicon substrate 2 and forms a monomolecular layer over the entire surface.

In FIG. 10, the control unit 51 causes the mass flow controller MC1 to stop supplying the Zr (BH ₄ ) ₄ gas via the mass flow controller drive circuit 55 when the process time has elapsed for the adsorption period Ta after introducing the adsorbed molecules MA. The adsorption process is terminated.

When the controller 51 ends the adsorption process, the controller 51 drives the mass flow controller MC4 via the mass flow controller drive circuit 55 to supply the reaction chamber S with N ₂ gas having a predetermined flow rate. Further, the control unit 51 drives the microwave power source FG via the microwave power source driving circuit 56 to supply the excited N ₂ gas to the reaction chamber S and start the reforming process.

Here, the period during which the microwave source 48 oscillates the microwave is referred to as a reforming period Tr. The modification period Tr is set in advance based on a test or the like, and is set to a period (for example, 1 second to 10 seconds) in which the monomolecular layer of the adsorbed molecule MA is nitrided to generate a monomolecular film of ZrB _x N _y. ing.

In FIG. 12, the excited N ₂ gas (reformed gas R) promotes the decomposition reaction of Zr (BH ₄ ) ₄ (adsorbed molecule MA) and uses all the adsorbed molecules MA adsorbed on the surface of the silicon substrate 2. Thus, a decomposition product and a by-product BP (for example, borohydride) are generated, and a nitridation reaction of the decomposition product is promoted to generate a nitride MP. That is, the excited N ₂ gas (reformed gas R) generates a monomolecular film of ZrB _x N _y over the entire surface of the silicon substrate 2.

In FIG. 10, the control unit 51 oscillates the microwave and stops the supply of N ₂ gas to the mass flow controller MC 4 via the mass flow controller drive circuit 55 when the process time has passed for the reforming period Tr. The control unit 51 stops the microwave oscillation via the microwave power supply driving circuit 56. That is, the reforming process is terminated.

  When the reforming step is completed, the controller 51 drives the mass flow controller MC1 again via the mass flow controller drive circuit 55 to introduce the adsorbed molecules MA having a predetermined flow rate into the reaction chamber S. That is, the adsorption process is started again. Thereafter, similarly, the control unit 51 alternately repeats the adsorption step and the modification step, and sequentially deposits the monomolecular layer ML made of the nitride MP.

Thus, the film forming apparatus 40 can form the metal cap layers 16 and 37 mainly composed of ZrB _x N _y by stacking monoatomic layers. Therefore, the metal cap layers 16 and 37 can reliably inherit the information on the base (that is, whether the base is a conductive film).

According to the said embodiment, there exist the following effects.
(1) In the above embodiment, Zr (BH ₄ ) ₄ gas is introduced into the reaction chamber S only during the adsorption period Ta, and the surface of the second interlayer insulating film 11 and the surface of the first wiring 13 or the hard mask 32 Zr (BH ₄ ) ₄ is adsorbed on the surface and the surface of the second wiring 34 to form a monomolecular layer made of adsorbed molecules MA. Then, after the adsorption period Ta has elapsed, only during the reforming period Tr, N2 gas excited in the reaction chamber S is introduced, and a monomolecular film of ZrB _x N _y is generated using the adsorbed molecules MA.

Therefore, the metal cap layers 16 and 37 mainly composed of ZrB _x N _y can be stacked in monoatomic layers, and each metal cap layer 16 and 37 has information on the corresponding base, that is, the base is a conductive film. It is possible to reliably take over whether or not. As a result, each of the metal cap layers 16 and 37 has conductivity only in a region corresponding to the first wiring 13 and the second wiring 34, and between the adjacent first wirings 13 and between the adjacent second wirings 34. Short circuit can be avoided more reliably.

In addition, you may implement the said embodiment in the following aspects.
In the second embodiment, the excited N2 gas is introduced only during the reforming step. For example, as shown in FIG. 13, an excited N 2 gas may be introduced in both the reforming process and the adsorption process. In other words, when introducing the adsorbed molecule MA, an excited N ₂ gas may be introduced. According to this configuration, the gas phase reaction of Zr (BH ₄ ) ₄ gas and excited N ₂ gas and the adsorption reaction of Zr (BH ₄ ) ₄ can be performed simultaneously. As a result, Zr (BH ₄ ) ₄ equivalent to the unreacted portion of the adsorbed molecule MA or Zr (BH ₄ ) ₄ conceived to the unreacted portion of the gas phase reaction is more reliably set to ZrB _x N _y. And a more uniform Zr—N bond can be formed.

  In the above embodiment, the metal layer is embodied in the first wiring 13 and the second wiring 34. For example, the metal layer may be embodied as an electrode of a capacitive element or an inductive element.

FIG. 3 is a cross-sectional view of a main part showing a semiconductor device of the present invention. The top view which shows the film-forming apparatus. FIG. 1 is a block circuit diagram showing an electrical configuration of a film forming apparatus. The time chart which shows the manufacturing process of 1st embodiment. The figure which shows the elemental-analysis result of Example 2. FIG. The figure which shows the elemental-analysis result of the comparative example 1. The figure which shows the elemental-analysis result of the comparative example 2. The figure which shows the elemental-analysis result of the comparative example 7. The time chart which shows the manufacturing process of 2nd embodiment. Process drawing explaining the adsorption | suction process of 2nd embodiment. Process drawing explaining the modification | reformation process of 2nd embodiment. The time chart which shows the manufacturing process of the semiconductor device in the example of a change.

Explanation of symbols

  MC1 ... mass flow controller constituting the first supply means, MC4 ... mass flow controller constituting the second supply means, S ... reaction chamber, T ... supply tank constituting the first supply means, 1 ... semiconductor device, 2 ... semiconductor substrate 2b ... element region, 11 ... second interlayer insulating film constituting the insulating layer, 12 ... first trench constituting the recess, 13 ... first wiring constituting the metal layer, 15 ... first wiring layer , 16 ... 1st metal cap layer, 21 ... 3rd interlayer insulation film which comprises an insulating layer, 23 ... Via hole which comprises a recessed part, 33 ... 2nd trench which comprises a recessed part, 31 ... 4th interlayer which comprises an insulating layer Insulating film, 34 ... second wiring constituting metal layer, 36 ... second wiring layer, 37 ... second metal cap layer, 40 ... deposition apparatus as a semiconductor device manufacturing apparatus, 41 ... chamber body, 51 ... Control portion constituting the control means.

Claims (8)

An insulating layer step of laminating an insulating layer on a semiconductor substrate having an element region;
A recess step for forming a recess in the insulating layer;
A metal layer step of embedding a metal layer in the recess;
A planarization step of planarizing the surface of the insulating layer and the surface of the metal layer in substantially the same plane;
Zr (BH ₄ ) ₄ and excited nitrogen gas are supplied to the reaction chamber having the semiconductor substrate, and at least a zirconium element and a nitrogen element are provided on the planarized surface of the insulating layer and the surface of the metal layer. A metal cap layer step of forming a metal cap layer containing
A method for manufacturing a semiconductor device, comprising: A method of manufacturing a semiconductor device according to claim 1,
The metal cap layer process includes
Irradiating the nitrogen gas with microwaves outside the reaction chamber and introducing the excited nitrogen gas into the reaction chamber;
A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1 or 2,
The metal cap layer process includes
Forming the metal cap layer by a CVD method using the Zr (BH ₄ ) ₄ and the excited nitrogen gas;
A method of manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1 or 2,
The metal cap layer process includes
Forming the metal cap layer by an atomic layer deposition method using the Zr (BH ₄ ) ₄ and the excited nitrogen gas;
A method of manufacturing a semiconductor device. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 4,
The metal cap layer process includes
Heating the semiconductor substrate to less than 260 ° C. to form the metal cap layer;
A method of manufacturing a semiconductor device. A chamber body;
A stage that is provided in the reaction chamber of the chamber body and on which a semiconductor substrate is placed;
First supply means for supplying Zr (BH ₄ ) ₄ to the reaction chamber;
Second supply means for supplying excited nitrogen gas to the reaction chamber;
Control means for driving and controlling the first supply means and the second supply means;
With
The control means includes
The first supply unit and the second supply unit are driven and controlled to supply the Zr (BH ₄ ) ₄ and the excited nitrogen gas to the reaction chamber, and at least zirconium element is formed on the surface of the semiconductor substrate. Forming a metal cap layer containing nitrogen element;
An apparatus for manufacturing a semiconductor device, comprising: An apparatus for manufacturing a semiconductor device according to claim 6,
The control means includes
The first supply means and the second supply means are driven and controlled to supply both the Zr (BH ₄ ) ₄ and the excited nitrogen gas to the reaction chamber, and at least zirconium element and nitrogen are formed on the surface of the semiconductor substrate. Forming a metal cap layer containing an element;
An apparatus for manufacturing a semiconductor device, comprising: An apparatus for manufacturing a semiconductor device according to claim 6,
The control means includes
The first supply means and the second supply means are driven and controlled to supply the Zr (BH ₄ ) ₄ and the excited nitrogen gas alternately to the reaction chamber, and to the surface of the semiconductor substrate with Zr (BH _{4) 4} after adsorption and by the excited said nitrogen gas, be reformed to the metal cap layer containing at least zirconium element and nitrogen element the Zr (BH _{4) 4} adsorbed,
An apparatus for manufacturing a semiconductor device.

Images