JP2008211088A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress concentration of electric field at a drain end of a field effect transistor. <P>SOLUTION: LDD regions 7a and 7b of relatively low impurity concentration are formed in a semiconductor substrate 3 on both sides of a gate electrode 5, with a silicide block film 9 formed on one LDD region 7b away from a side wall 6 of the gate electrode 5. A source region 8a and a drain region 8b of relatively high impurity concentration are formed in the semiconductor substrate 3 on an element isolation region 2 side of the silicide block film 9 and in the semiconductor substrate 3 on the LDD region 7a side, respectively. No heavily doped region such as the drain region 8b is formed in the region between the side wall 6 and the silicide block film 9, to suppress concentration of electric field at the end of the LDD region 7b. Further, a silicide layer 10c is formed on the surface of the region, for lower resistance. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a transistor having a relatively high operating voltage and a manufacturing method thereof.

  A transistor included in a semiconductor device is required to satisfy desired performance and have high reliability. In the case of a semiconductor device in which a logic circuit and an analog circuit are mixedly mounted, a high performance is particularly required for a transistor (logic transistor) of the logic circuit. High reliability is required.

  An analog transistor is required to have high reliability and suppress the generation of hot carriers by sufficiently relaxing the electric field at the drain end near the gate electrode so that a large output voltage amplitude can be obtained. For this purpose, there is a method in which the impurity distribution is inclined by sufficient annealing, thereby relaxing the electric field at the drain end. However, when analog transistors are mixed with logic transistors, it is actually difficult to perform such annealing sufficiently in order not to deteriorate the performance of the logic transistors.

Conventionally, an attempt has been made to reduce the electric field at the drain end by configuring a transistor having a so-called silicide block region (see, for example, Patent Documents 1 and 2).
JP 2003-133433 A JP 2004-111746 A

A transistor having a silicide block region can be formed, for example, as follows.
First, a gate electrode is formed on a semiconductor substrate in an element region defined by an element isolation region via a gate insulating film, and then an LDD (Lightly Doped Drain) region is formed in the semiconductor substrate on both sides thereof. Thereafter, an insulating film is formed on the entire surface, and etched to form a sidewall on the gate electrode. In that case, the insulating film is left as a silicide block film in parallel with the gate electrode on one LDD region slightly away from the sidewall (toward the drain side). In this state, ion implantation is performed to form source / drain regions, and then the surfaces of the gate electrode and the source / drain regions are silicided.

  The ion implantation for forming the source / drain regions is performed on the drain side with respect to the semiconductor substrate on both sides of the silicide block film, that is, on the element isolation region side and the sidewall side by the silicide block film left on the LDD region. And then those regions are silicided. Under the silicide block film, ion implantation for forming a source / drain region is not performed, and no subsequent silicidation is performed, that is, a silicide block region is formed. As a result, on the drain side, regions having a relatively high impurity concentration are formed on both sides of the silicide block region having a relatively low impurity concentration.

  In the transistor formed in this manner, due to its structure, when a large voltage is applied to the high concentration impurity region (drain region) on the element isolation region side, the silicide block region acts as a parasitic resistance, and the voltage drops. It is expected that the electric field at the drain end near the gate electrode is relaxed. In addition, in order to form such a transistor, it is not necessary to add a new annealing as compared with a normal process, and even when a logic transistor is mixedly mounted, there is no fear of causing performance deterioration due to the annealing.

  However, even when a transistor having a silicide block region as described above is formed, if a high voltage is applied to the high concentration impurity region on the element isolation region side, a voltage is actually applied to the parasitic resistance of the silicide block region. In other words, it has been found that there is a problem that the electric field at the drain end near the gate electrode may not be alleviated.

  Therefore, even when such a transistor is applied to an analog transistor, it is difficult to suppress the generation of hot carriers depending on the applied voltage.As a result, the analog transistor, and further, the semiconductor device in which it is mounted together with the logic transistor, It is also difficult to ensure a certain level of performance and reliability.

  The present invention has been made in view of these points, and an object thereof is to provide a high-performance and highly reliable semiconductor device and a method for manufacturing the same.

  In the present invention, in order to solve the above problems, in a semiconductor device including a field effect transistor, a gate electrode formed on a semiconductor substrate via an insulating film, a sidewall formed on the gate electrode, A first impurity region formed in the semiconductor substrate on both sides of the gate electrode; a silicide block film formed on the first impurity region of the first impurity region and spaced apart from the sidewall; and the one The side where the first impurity region is formed, the side of the silicide block film opposite to the side wall side in the semiconductor substrate, and the side of the first impurity region where the other first impurity region is formed A second impurity region formed in each of the semiconductor substrates, a surface of the gate electrode, a surface of the second impurity region, and the silicide bromide. The semiconductor device is provided which is characterized in that it has a, a silicide layer formed on each of said first impurity region surface between the click film and the sidewalls.

  According to such a semiconductor device, the first impurity region is formed in the semiconductor substrate on both sides of the gate electrode, and the silicide block film is formed on one of the first impurity regions so as to be separated from the side wall of the gate electrode. The A second impurity region is formed in the semiconductor substrate on the side opposite to the sidewall side of the silicide block film and in the semiconductor substrate on the other first impurity region side. A first impurity region is formed on the sidewall side of the silicide block film, that is, between the silicide block film and the sidewall, no second impurity region is formed, and a silicide layer is formed on the surface thereof. The

  According to the present invention, in order to solve the above problems, in a method of manufacturing a semiconductor device including a field effect transistor, a step of forming a gate electrode on a semiconductor substrate via an insulating film, and the formed gate electrode Forming a first impurity region by introducing an impurity into the semiconductor substrate on both sides; forming a sidewall on the gate electrode; and forming a sidewall on one of the first impurity regions in the first impurity region. Forming a silicide block film spaced apart from the sidewall, forming a mask covering the first impurity region between the silicide block film and the sidewall, and using the formed mask Impurities are introduced, and the half of the silicide block film on the side opposite to the sidewall side is formed on the side where the first impurity region is formed. Forming a second impurity region in the body substrate and in the semiconductor substrate on the side where the other first impurity region of the first impurity regions is formed; removing the mask; Forming a silicide layer on the surface of the gate electrode, the surface of the second impurity region, and the surface of the first impurity region between the silicide block film and the sidewall from which the mask has been removed, respectively. A method for manufacturing a semiconductor device is provided.

  According to such a manufacturing method of a semiconductor device, the first impurity region is formed between the silicide block film and the sidewall, the second impurity region is not formed, and the silicide layer is formed on the surface thereof. A semiconductor device in which is formed is obtained.

  In the present invention, on one side of the gate electrode formed on the semiconductor substrate, a silicide block film is formed on the first impurity region formed in the semiconductor substrate so as to be separated from the sidewall of the gate electrode. Then, a second impurity region is formed in the semiconductor substrate opposite to the sidewall side of the silicide block film. Then, a silicide layer is formed on the surface of the first impurity region on the side of the sidewall sandwiching the silicide block film and the surface of the second impurity region formed on the opposite side. Thereby, when a voltage is applied to the second impurity region, electric field concentration in the vicinity of the gate electrode can be effectively suppressed, and furthermore, the resistance of the region between the silicide block region and the gate electrode can be suppressed low. it can. Therefore, a semiconductor device having high reliability and excellent performance can be realized.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
First, the first embodiment will be described.
FIG. 1 is a diagram illustrating a configuration example of the semiconductor device according to the first embodiment.

  In the semiconductor device 1 of the first embodiment shown in FIG. 1, a well region 12 is formed in an element region of a semiconductor substrate 3 defined by an element isolation region 2, and a gate electrode 5 is formed via a gate insulating film 4. The gate electrode 5 has a configuration in which a sidewall 6 is formed. In the semiconductor substrate 3 on both sides of the gate electrode 5, LDD regions 7a and 7b, a source region 8a and a drain region 8b into which a predetermined impurity is introduced at a predetermined concentration are formed.

  The LDD regions 7 a and 7 b are formed so as to partially extend to a region below the gate electrode 5 in the semiconductor substrate 3. The source region 8a and the drain region 8b are deeper than the LDD regions 7a and 7b and are formed at a higher concentration. The source region 8a is formed so as to partially extend to a region immediately below the sidewall 6, whereas the drain region 8b is formed in a region separated from the sidewall 6 by a predetermined distance.

  In the semiconductor device 1, a silicide block film 9 is formed on the LDD region 7 b on the drain region 8 b side so as to be separated from the sidewall 6 and extend in parallel with the gate electrode 5. Then, the semiconductor surface excluding the element isolation region 2, the silicide block film 9 and the sidewall 6, that is, each surface of the gate electrode 5, the source region 8 a and the drain region 8 b, and between the sidewall 6 and the silicide block film 9. Silicide layers 10, 10a, 10b, and 10c are formed on the surface of the LDD region 7b, respectively. A region immediately below the silicide block film 9 is a silicide block region 11 that is not silicided.

  As described above, in the semiconductor device 1, the drain region 8 b is formed only in the semiconductor substrate 3 on the side opposite to the sidewall 6 side of the silicide block film 9, and the semiconductor substrate between the sidewall 6 and the silicide block film 9 is formed. 3 is not formed. With such a configuration, even when a high voltage is applied to the drain region 8b, electric field concentration at the end of the LDD region 7b near the gate electrode 5 can be effectively suppressed.

  Here, the potential distribution in the semiconductor device 1 in which a relatively high concentration impurity region such as the drain region 8b is not formed in the semiconductor substrate 3 between the sidewall 6 and the silicide block film 9 is examined. We will describe the results.

  2 and 3 are diagrams for explaining the potential distribution in the semiconductor device. FIG. 2A shows an example of the configuration of the semiconductor device, and FIG. 3B shows an example of the potential distribution of the main part thereof. 2 and 3, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  For the examination of the potential distribution, the drain region 8b having a higher impurity concentration than the LDD region 7b is formed only in the semiconductor substrate 3 on the side opposite to the sidewall 6 side of the silicide block film 9 as shown in FIG. The formed semiconductor device 1 was used. For comparison, a relatively high-concentration impurity region 101 similar to the drain region 8b is also formed in the semiconductor substrate 3 between the sidewall 6 and the silicide block film 9 as shown in FIG. The formed semiconductor device 100 was used. FIG. 2 shows an example of the potential distribution of the main part of the semiconductor device 1100 when the gate electrode 5 and the source region 8a of the semiconductor device 1100 are set to 0V and a voltage of 10V is applied to the drain region 8b. (B) and FIG.

  First, in the semiconductor device 100 in which the impurity region 101 having a relatively high concentration is formed between the sidewall 6 and the silicide block film 9 as shown in FIG. 3A, a voltage of 10 V is applied to the drain region 8b. Then, as shown in FIG. 3B, the electric field was concentrated in the vicinity of the gate electrode 5. On the other hand, in the semiconductor device 1 in which only a relatively low concentration LDD region 7b is formed as an impurity region between the sidewall 6 and the silicide block film 9 as shown in FIG. 2 was applied, the electric field concentration in the vicinity of the gate electrode 5 as seen in the semiconductor device 100 was suppressed as shown in FIG. Thus, the semiconductor device 1 can effectively suppress the electric field concentration even when a high voltage is applied to the drain region 8b.

  In addition, the semiconductor device 1 includes the silicide layers 10, 10 a, and 10 b formed on the surfaces of the gate electrode 5, the source region 8 a, and the drain region 8 b, and the LDD between the sidewall 6 and the silicide block film 9. A silicide layer 10c is also formed on the surface of the region 7b. Thereby, in addition to the effect of relaxing the electric field at the end of the LDD region 7b in the vicinity of the gate electrode 5, the effect of reducing the parasitic resistance between the drain region 8b and the gate electrode 5 can also be obtained.

  4A and 4B are diagrams for explaining the effect of reducing the parasitic resistance by the silicide layer between the sidewall and the silicide block film, wherein FIG. 4A is a semiconductor device having no silicide layer between the sidewall and the silicide block film, and FIG. A semiconductor device having a silicide layer between a sidewall and a silicide block film. In FIG. 4, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The semiconductor device 200 shown in FIG. 4A is different from the semiconductor device 1 shown in FIG. 4B in that the silicide layer 10 c is not formed on the surface of the LDD region 7 b between the sidewall 6 and the silicide block film 9. Is different.

  In the semiconductor devices 200 and 1 shown in FIGS. 4A and 4B, the width of the sidewall 6 is 80 nm, the distance between the sidewall 6 and the silicide block film 9 is 80 nm, and the width of the silicide block film 9 is 240 nm. Assume a certain case.

  First, in the semiconductor device 200 shown in FIG. 4A, assuming that the sheet resistance of the LDD region 7b is 400Ω / □, the parasitic in the surface region of the semiconductor substrate 3 between the drain region 8b and the gate electrode 5 is obtained. The resistance can be roughly estimated as follows.

400Ω / □ × (0.08 μm + 0.08 μm + 0.24 μm) = 160Ω · μm
On the other hand, in the semiconductor device 1 shown in FIG. 4B, if the sheet resistance of the silicide layer 10c is 20Ω / □, the parasitic in the surface region of the semiconductor substrate 3 between the drain region 8b and the gate electrode 5 is obtained. The resistance can be roughly estimated as follows.

400Ω / □ × (0.08μm + 0.24μm) + 20Ω / □ × 0.08μm ≒ 130Ω ・ μm
Thus, by forming the silicide layer 10 c on the surface of the LDD region 7 b between the sidewall 6 and the silicide block film 9, the parasitic region between the drain region 8 b and the gate electrode 5 is compared with the case where it is not formed. Resistance can be reduced by 19%.

Next, a method for forming the semiconductor device 1 having the above configuration will be described.
FIG. 5 is a schematic cross-sectional view of the main part of the LDD region forming process of the first embodiment, FIG. 6 is a schematic cross-sectional view of the main part of the insulating film / resist forming process of the first embodiment, and FIG. FIG. 8 is a schematic cross-sectional view of the relevant part of the resist formation / ion implantation process of the first embodiment.

  First, as shown in FIG. 5, an element isolation region 2 is formed on a semiconductor substrate 3 by using an STI (Shallow Trench Isolation) method or the like, and then a well region 12 is formed. An insulating film, a polycrystal is formed on the semiconductor substrate 3. Conductive materials such as silicon are sequentially formed and processed to form the gate insulating film 4 and the gate electrode 5. In that case, the gate electrode 5 is formed such that the distance from the gate electrode 5 to the element isolation region 2 is longer on the drain side than on the source side. Thereafter, predetermined impurities are ion-implanted under predetermined conditions to form LDD regions 7a and 7b as shown in FIG.

  After the formation of the LDD regions 7a and 7b, an insulating film 13 is formed on the entire surface as shown in FIG. Further, as shown in FIG. 6, a resist 14 is formed in a predetermined region on the insulating film 13, that is, a region corresponding to a region where the silicide block film 9 is finally formed.

  After the resist 14 is formed, the insulating film 13 is anisotropically etched using the resist 14 as a mask to form a silicide block film 9 on the LDD region 7b as shown in FIG. Further, by the anisotropic etching of the insulating film 13, side walls 6 are formed on the gate electrode 5 as shown in FIG. 7 simultaneously with the silicide block film 9.

  Next, as shown in FIG. 8, a resist 15 for ion implantation is formed. The resist 15 is formed such that a region between the silicide block film 9 and the element isolation region 2 is opened in the LDD region 7a exposed on the source side and the LDD region 7b exposed on the drain side. To form. Then, using this resist 15 as a mask, a predetermined impurity is ion-implanted under a predetermined condition to form a source region 8a and a drain region 8b as shown in FIG.

  Finally, silicidation is performed with the resist 15 removed, and on the surfaces of the gate electrode 5, the source region 8a and the drain region 8b, and the surface of the LDD region 7b between the sidewall 6 and the silicide block film 9, By forming the silicide layers 10, 10a, 10b, and 10c, the semiconductor device 1 as shown in FIG. 1 can be obtained.

In the above formation flow, the impurities after ion implantation are activated by performing predetermined annealing at an appropriate stage.
As described above, in the semiconductor device 1, a relatively high concentration impurity region such as the drain region 8 b is not formed in the region in the semiconductor substrate 3 between the sidewall 6 and the silicide block film 9. The silicide layer 10c is formed on the surface of the region. Thereby, the electric field concentration at the end of the LDD region 7b near the gate electrode 5 can be suppressed, and the resistance of the surface region of the semiconductor substrate 3 between the silicide block film 9 and the sidewall 6 can be suppressed low.

  Next, an example (first application example) in which the principle configuration of the semiconductor device 1 according to the first embodiment is applied to a semiconductor device in which a plurality of types of transistors are mounted will be described. Here, a semiconductor device including an internal transistor, an input / output transistor, and an analog transistor will be described as an example with reference to FIGS. 9 to 20 below. In the following FIGS. 9 to 20, only the n-channel type portion is shown, and the p-channel type portion is not shown.

FIG. 9 is a schematic cross-sectional view of the relevant part in the element isolation region forming step.
First, as shown in FIG. 9, an element isolation region 21 is formed on a semiconductor substrate 20 by using the STI method, a region 30 in which an internal transistor is formed (internal transistor portion), and a region in which an input / output transistor is formed (input). An output transistor portion) 40 and a region (analog transistor portion) 50 in which an analog transistor is formed are defined.

FIG. 10 is a schematic sectional view showing an important part of a first well region forming / threshold adjusting ion implantation step.
After the formation of the element isolation region 21, as shown in FIG. 10, a resist 60 having a pattern in which the internal transistor portion 30 is opened is formed, and this is used as a mask for ion implantation (well implantation). ) And ion implantation (channel implantation) for threshold adjustment. Well implantation is performed by, for example, boron (B) using an acceleration voltage of about 100 keV to 150 keV, a dose amount of about 2 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² , and an angle (an angle with respect to the normal direction of the semiconductor substrate 3). It is performed under the condition of injecting at 0 degree. The channel implantation is performed, for example, under the condition that B is implanted at an acceleration voltage of about 10 keV to 30 keV, a dose amount of about 3 × 10 ¹² cm ^{−2 to} 1.5 × 10 ¹³ cm ⁻² , and an angle of 0 degrees.

FIG. 11 is a schematic sectional view showing an important part of a second well region forming / threshold adjusting ion implantation step.
After predetermined ion implantation into the internal transistor section 30, as shown in FIG. 11, a resist 61 having a pattern in which the input / output transistor section 40 and the analog transistor section 50 are opened is formed, and well regions 48 and 58 are formed using the resist 61 as a mask. Well injection and channel injection are sequentially performed. Well implantation is performed, for example, under the condition that B is implanted at an acceleration voltage of about 100 keV to 150 keV, a dose of about 2 × 10 ¹³ cm ^{−2 to} 3 × 10 ¹³ cm ⁻² , and an angle of 0 °. The channel implantation is performed, for example, under the condition that B is implanted at an acceleration voltage of about 10 keV to 30 keV, a dose amount of about 3 × 10 ¹² cm ^{−2 to} 9 × 10 ¹³ cm ⁻² , and an angle of 0 degrees.

FIG. 12 is a schematic cross-sectional view of the relevant part in the insulating film forming step.
After predetermined ion implantation for the input / output transistor section 40 and the analog transistor section 50, as shown in FIG. 12, first, an insulating film 62 having a film thickness of about 5 nm to 7 nm is formed on the entire surface by using a thermal oxidation method or the like.

  Then, a resist 63 having a pattern in which the internal transistor portion 30 is opened is formed, and the insulating film 62 formed in the internal transistor portion 30 is removed by wet etching. After this wet etching, the resist 63 is removed.

FIG. 13 is a schematic cross-sectional view of the relevant part in the insulating film / polysilicon forming step.
After removing the resist 63, as shown in FIG. 13, an insulating film 64 having a film thickness of about 1 nm to 2 nm is formed in the internal transistor portion 30 by using a thermal oxidation method or the like. As a result, insulating films 64 and 62 having different thicknesses are formed in the internal transistor portion 30, the input / output transistor portion 40, and the analog transistor portion 50. When the insulating film 64 of the internal transistor unit 30 is formed by a thermal oxidation method, the thickness of the insulating film 62 of the input / output transistor unit 40 and the analog transistor unit 50 formed previously is increased.

After the formation of the insulating film 64, a polysilicon layer 65 having a film thickness of about 100 nm to 150 nm is formed on the entire surface by using a CVD method or the like.
FIG. 14 is a schematic sectional view showing an important part of a gate processing step.

  The insulating films 62 and 64 and the polysilicon layer 65 shown in FIG. 13 are processed into a predetermined pattern by anisotropic etching, and the gate insulating film 31 is formed in the internal transistor unit 30, the input / output transistor unit 40, and the analog transistor unit 50, respectively. , 41, 51 and gate electrodes 32, 42, 52 are formed. In this gate processing, for example, the gate electrode 32 having a gate length direction width of about 30 nm to 50 nm is formed in the internal transistor portion 30, and the input / output transistor portion 40 and the analog transistor portion 50 have a gate length direction width. Gate electrodes 42 and 52 of about 180 nm to 350 nm are formed.

FIG. 15 is a schematic cross-sectional view of an essential part of an ion implantation process for forming extension regions and pocket regions.
After the gate processing, as shown in FIG. 15, a resist 66 having a pattern in which the internal transistor portion 30 is opened is formed, and predetermined ion implantation is performed, so that a pocket region (not shown) and the internal transistor portion 30 are formed. Extension regions 33a and 33b are formed. In the ion implantation for forming the pocket region, for example, B is accelerated in an acceleration voltage of about 10 keV to 30 keV, a dose amount of about 3 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ⁻² and an angle of 20 ° to 40 ° in four directions. The conditions are as follows. The ion implantation for forming the extension regions 33a and 33b is performed by implanting, for example, arsenic (As) with an acceleration voltage of about 1 keV to ² keV and a dose amount of about 0.5 × 10 ¹⁵ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² . It is performed under the condition of injecting at 0 degree.

FIG. 16 is a schematic sectional view showing an important part of an ion implantation process for forming an LDD region.
After predetermined ion implantation for the internal transistor section 30, as shown in FIG. 16, a resist 67 having a pattern in which the input / output transistor section 40 and the analog transistor section 50 are opened is formed, and predetermined ion implantation is performed using the resist 67 as a mask. Then, LDD regions 43a and 43b are formed in the input / output transistor portion 40, and LDD regions 53a and 53b are formed in the analog transistor portion 50. The ion implantation at this time is performed, for example, under the condition that phosphorus (P) is implanted at an acceleration voltage of about 10 keV to 20 keV, a dose of about 1 × 10 ¹³ cm ⁻² to 4 × 10 ¹³ cm ⁻² and an angle of 0 °. .

FIG. 17 is a schematic cross-sectional view of the relevant part in the step of forming the sidewall / silicide block film.
An insulating film having a thickness of about 80 nm to 120 nm, for example, an insulating film such as silicon oxide or silicon nitride is formed on the entire surface, a resist is formed on a part of the insulating film, and anisotropic etching is performed (FIG. 6). (See FIG. 7). As a result, as shown in FIG. 17, sidewalls 34 are formed in the internal transistor portion 30, and insulating film patterns 45 and 55 are formed in part of the input / output transistor portion 40 and the analog transistor portion 50, respectively. Is done. The patterns 45 and 55 are referred to as silicide block films in this specification. In this step, sidewalls 44 and 54 are also formed.

FIG. 18 is a schematic sectional view showing an important part of an ion implantation process for forming a source region and a drain region.
As shown in FIG. 18, a resist in which all regions of the internal transistor unit 30 and the input / output transistor unit 40 are opened and a region excluding a region between the sidewall 54 and the silicide block film 55 of the analog transistor unit 50 is opened. 68 is formed, and predetermined ion implantation is performed using this as a mask (see FIG. 8). For example, this ion implantation is performed under the condition that As is implanted at an acceleration voltage of about 30 keV to 60 keV, a dose of about 1 × 10 ¹⁵ cm ⁻² to 4 × 10 ¹⁵ cm ⁻² , and an angle of 0 °. Also, for example, P is implanted under the conditions of an acceleration voltage of about 10 keV to 20 keV, a dose of about 1 × 10 ¹⁵ cm ⁻² to 4 × 10 ¹⁵ cm ⁻² and an angle of 0 °.

  By this ion implantation, a source region 36 a and a drain region 36 b are formed in the internal transistor portion 30. In the input / output transistor section 40, a source region 46a and a drain region 46b are formed, and a similar impurity region 46c is formed in a region between the sidewall 44 and the silicide block film 45. In the analog transistor portion 50, a source region 56a and a drain region 56b are formed. In the analog transistor unit 50, since the resist 68 covering the region between the sidewall 54 and the silicide block film 55 is formed, no impurity region such as the drain region 56b is formed in that region.

After the ion implantation, the resist 68 is removed, and activation annealing under predetermined conditions, for example, spike annealing at a temperature of about 1000 ° C. to 1050 ° C. is performed to activate the implanted impurities.
FIG. 19 is a schematic sectional view showing an important part of the silicide layer forming step.

  After activation annealing, silicidation is performed using cobalt (Co) or nickel (Ni). By this silicidation, silicide layers 37, 37a, and 37b are formed on the surfaces of the gate electrode 32, the exposed source region 36a, and the drain region 36b in the internal transistor portion 30, respectively. In the input / output transistor section 40, silicide layers 47, 47a, 47b, 47c are formed on the surfaces of the gate electrode 42, the exposed source region 46a, drain region 46b, and impurity region 46c. In the analog transistor portion 50, silicide layers 57, 57a, 57b, and 57c are formed on the surfaces of the gate electrode 52, the exposed source region 56a, the drain region 56b, and the LDD region 53b.

  Through the steps so far, the internal transistor, the input / output transistor, and the analog transistor are formed in each region of the internal transistor unit 30, the input / output transistor unit 40, and the analog transistor unit 50, respectively.

FIG. 20 is a schematic sectional view showing an important part of the plug forming process.
Finally, an interlayer insulating film 69 is formed, and plugs 70 connected to the source regions 36a, 46a, 56a and the drain regions 36b, 46b, 56b of the internal transistor unit 30, the input / output transistor unit 40, and the analog transistor unit 50, respectively. Form.

  As described above, the internal transistor capable of high-speed operation with a relatively low voltage, the input / output transistor and the analog transistor corresponding to a higher operating voltage are formed by the steps shown in FIGS.

  In particular, in the analog transistor, a high-concentration impurity region is not formed in the semiconductor substrate 20 in a region between the sidewall 54 and the silicide block film 55, and a silicide layer 57c is formed in that region. Therefore, even when a high voltage is applied to the drain region 56b via the plug 70, the analog transistor suppresses electric field concentration at the end of the LDD region 53b near the gate electrode 52 and obtains an output with a large voltage amplitude. It is possible.

  Further, by configuring the analog transistor in such a manner, even when the operating voltages of the analog transistor and the input / output transistor are different, the gate insulating films 41 and 51 of both are kept the same in thickness and can handle different operating voltages. can do.

  As with the analog transistor, the input / output transistor may be configured not to form the impurity region 46c depending on the magnitude of the voltage applied during its operation.

  In the description of the steps shown in FIGS. 9 to 20, only the n-channel type portion has been described. However, the p-channel type portion is an n-channel type portion under a predetermined condition according to a conventional method. Should be formed in parallel.

Although the first embodiment has been described above, the following forms (second and third embodiments) can be used in order to suppress the electric field concentration at the drain end.
Next, a second embodiment will be described.

  FIG. 21 is a diagram illustrating a configuration example of the semiconductor device according to the second embodiment. In FIG. 21, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the semiconductor device 80 of the second embodiment shown in FIG. 21, the silicide block film 9 is not formed, and a continuous silicide layer 81 is formed on the exposed surfaces of the LDD region 7b and the drain region 8b. This is different from the semiconductor device 1 of the first embodiment. According to such a semiconductor device 80, it is possible to reduce the resistance between the drain region 8b and the gate electrode 5 while suppressing electric field concentration at the end of the LDD region 7b.

  Here, in this semiconductor device 80, the width of the sidewall 6 is 80 nm, the distance from the sidewall 6 to the drain region 8b is 320 nm (the interval between the sidewall 6 and the silicide block film 9 shown in FIG. 4 is 80 nm, If the sheet resistance of the LDD region 7b is 400Ω / □ and the sheet resistance of the silicide layer 81 is 20Ω / □, the drain region 8b and the gate electrode The parasitic resistance of the surface region of the semiconductor substrate 3 between 5 and 5 can be roughly estimated as follows.

400Ω / □ × 0.08μm + 20Ω / □ × 0.32μm ≒ 38Ω ・ μm
Thus, by forming the silicide layer 81, the parasitic resistance between the drain region 8b and the gate electrode 5 can be greatly reduced to 76% compared to the case where the silicide layer 81 is not formed (FIG. 4A). Can do. In addition, the parasitic resistance can be reduced as compared with the semiconductor device 1 (FIG. 4B) of the first embodiment.

Next, a method for forming the semiconductor device 80 having the above configuration will be described.
The formation of the semiconductor device 80 is the same up to the LDD region forming step of FIG. 5 described for the formation of the semiconductor device 1, and the subsequent steps will be described here.

FIG. 22 is a schematic cross-sectional view of an essential part of an etching process according to the second embodiment, and FIG. 23 is a schematic cross-sectional view of an essential part of a resist formation / ion implantation process according to the second embodiment.
After the LDD regions 7a and 7b are formed as shown in FIG. 5, an insulating film is formed on the entire surface, and anisotropic etching is performed on the entire surface. As shown in FIG. Form.

  Thereafter, as shown in FIG. 23, the resist is so covered as to cover the region other than the element region and the sidewall 6 to a predetermined region in the LDD region 7b exposed to the drain side in the element region. 82 is formed. Then, using this resist 82 as a mask, a predetermined impurity is ion-implanted under a predetermined condition to form a source region 8a and a drain region 8b as shown in FIG.

  Finally, silicidation is performed to form silicide layers 10, 10a, 81 on the surfaces of the gate electrode 5 and the source region 8a, and the surfaces of the LDD region 7b and the drain region 8b, respectively, as shown in FIG. Such a semiconductor device 80 can be obtained.

In the above formation flow, the impurities after ion implantation are activated by performing predetermined annealing at an appropriate stage.
Next, an example (second application example) in which the principle configuration of the semiconductor device 80 of the second embodiment is applied to a semiconductor device in which an internal transistor, an input / output transistor, and an analog transistor are mixedly mounted will be described. The formation flow is the same for the steps of FIGS. 9 to 16 used in the description of the first application example, and the subsequent steps will be described with reference to FIGS. 24 to 27 below. To go. In FIGS. 24 to 27 used for the description of the second application example, the same elements as those of FIGS. 9 to 20 used for the description of the first application example are denoted by the same reference numerals. Details of the description are omitted. Similarly to FIGS. 9 to 20, also in FIGS. 24 to 27, only the n-channel type portion is illustrated, and the p-channel type portion is not illustrated.

FIG. 24 is a schematic cross-sectional view of an essential part of the sidewall / silicide block film forming step of the second application example.
After forming the LDD regions 43a, 43b, 53a, 53b of the input / output transistor unit 40 and the analog transistor unit 50 shown in FIG. 16, an insulating film having a thickness of about 80 nm to 120 nm is formed on the entire surface, and the insulating film is formed on the insulating film. A resist is formed on a part (on the region corresponding to the formation region of the silicide block film 45), and anisotropic etching is performed (see FIGS. 6, 7, and 22). Thus, as shown in FIG. 24, sidewalls 34 and 54 are formed in the internal transistor portion 30 and the analog transistor portion 50, respectively, and a silicide block film 45 is formed in the input / output transistor portion 40 together with the sidewalls 44. Is done.

FIG. 25 is a schematic cross-sectional view of an essential part of an ion implantation step for forming a source region and a drain region according to a second application example.
As shown in FIG. 25, the internal transistor portion 30 and the input / output transistor portion 40 are opened, and a resist 68 is formed in which the region except for a part on the LDD region 53b of the analog transistor portion 50 is opened, and this is used as a mask. Predetermined ion implantation is performed (see FIG. 23). By this ion implantation, source regions 36a, 46a, 56a, drain regions 36b, 46b, 56b and an impurity region 46c are formed.

After the ion implantation, the resist 68 is removed and, for example, spike annealing is performed at a temperature of about 1000 ° C. to 1050 ° C. to activate the implanted impurities.
FIG. 26 is a schematic cross-sectional view of the relevant part in the silicide layer forming step of the second application example.

  After activation annealing, silicidation is performed to form silicide layers 37, 37 a and 37 b in the internal transistor portion 30, and silicide layers 47, 47 a, 47 b and 47 c are formed in the input / output transistor portion 40. Further, by this silicidation, silicide layers 57 and 57a are formed in the analog transistor portion 50, and a silicide layer 57d is formed on the LDD region 53b and the drain region 56b exposed after the removal of the resist 68.

FIG. 27 is a schematic cross-sectional view of the relevant part in the plug forming step of the second application example.
Finally, an interlayer insulating film 69 is formed, and plugs 70 connected to the source regions 36a, 46a, 56a and the drain regions 36b, 46b, 56b are formed.

  As a result, a semiconductor device including an internal transistor, an input / output transistor, and an analog transistor is obtained. As described above, in the analog transistor of this semiconductor device, the silicide layer 57d that is continuous on the LDD region 53b and the drain region 56b is formed on the drain side. Therefore, although the voltage drop applied to the drain region 56b in the LDD region 53b can be suppressed, the resistance between the drain region 56b and the gate electrode 52 can be lowered.

Next, a third embodiment will be described.
FIG. 28 is a diagram illustrating a configuration example of the semiconductor device according to the third embodiment. In FIG. 28, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The semiconductor device 90 of the third embodiment shown in FIG. 28 is the same as that of the first embodiment in that a silicide block film 91 integral with the sidewall 6 is formed on the LDD region 7b on the drain side. This is different from the semiconductor device 1 of FIG. Since such a silicide block film 91 is formed, a silicide layer is not formed on the surface of the LDD region 7b.

Next, a method for forming the semiconductor device 90 having the above configuration will be described.
The formation of the semiconductor device 90 is the same up to the LDD region forming step of FIG. 5 described for the formation of the semiconductor device 1, and the subsequent steps will be described here.

  29 is a schematic cross-sectional view of an essential part of an insulating film / resist forming process of the third embodiment, FIG. 30 is a schematic cross-sectional view of an essential part of an etching process of the third embodiment, and FIG. It is a principal part cross-sectional schematic diagram of the resist formation and ion implantation process of a form.

  After the LDD regions 7a and 7b are formed as shown in FIG. 5, an insulating film 92 is formed on the entire surface as shown in FIG. Further, as shown in FIG. 29, a resist 93 is formed in a predetermined region on the insulating film 92, that is, a region corresponding to the silicide block film 91 to be finally formed.

  After the resist 93 is formed, the insulating film 92 is anisotropically etched using the resist 93 as a mask to form the sidewall 6 and the silicide block film 91 on the gate electrode 5 as shown in FIG.

  Thereafter, as shown in FIG. 31, a resist 94 is formed in a region other than the element region, and a predetermined impurity is ion-implanted under a predetermined condition using the resist 94 as a mask, and the source region 8a and the drain as shown in FIG. Region 8b is formed.

  Finally, silicidation is performed, and silicide layers 10, 10a, and 10b are formed on the surfaces of the gate electrode 5, the source region 8a, and the drain region 8b, respectively, thereby obtaining the semiconductor device 90 as shown in FIG. It becomes like this.

In the above formation flow, the impurities after ion implantation are activated by performing predetermined annealing at an appropriate stage.
According to such a formation flow, the silicide block film 91 is integrally formed simultaneously with the sidewall 6, and the drain region 8 b and the silicide layer 10 b are separated from the gate electrode 5 by a certain distance using the silicide block film 91. Form. Therefore, a structure capable of suppressing electric field concentration at the end of the LDD region 7b can be efficiently formed.

  Here, the total width of the sidewall 6 and the silicide block film 91 of this semiconductor device 90 is 400 nm (the width of the sidewall 6 shown in FIG. 4 is 80 nm, the distance between the sidewall 6 and the silicide block film 9 is 80 nm, and If the sheet resistance of the LDD region 7b is 400Ω / □, the parasitic resistance of the surface region of the semiconductor substrate 3 between the drain region 8b and the gate electrode 5 is assumed. The resistance can be roughly estimated as follows.

400Ω / □ × 0.4μm = 160Ω ・ μm
Although the resistivity of the semiconductor device 90 increases as compared with the semiconductor devices 1 and 80 of the first and second embodiments, it is possible to effectively suppress the electric field concentration at the end of the LDD region 7b. is there.

  Subsequently, an example (third application example) in which the principle configuration of the semiconductor device 90 of the third embodiment is applied to a semiconductor device in which an internal transistor, an input / output transistor, and an analog transistor are mixedly mounted will be described. The formation flow is the same for the steps of FIGS. 9 to 16 used in the description of the first application example, and the subsequent steps will be described with reference to FIGS. 32 to 35 below. To go. 32 to 35 used in the description of the second application example, the same reference numerals are given to the same elements as those in FIGS. 9 to 20 used in the description of the first application example. Details of the description are omitted. Similarly to FIGS. 9 to 20, also in FIGS. 32 to 35, only the n-channel type portion is illustrated, and the p-channel type portion is not illustrated.

FIG. 32 is a schematic cross-sectional view of the relevant part in the side wall / silicide block film forming step of the third application example.
After the process of FIG. 16, an insulating film having a thickness of about 80 nm to 120 nm is formed on the entire surface, and a resist is formed on a part of the insulating film (on the region corresponding to the formation region of the silicide block films 45 and 55a). Then, anisotropic etching is performed (see FIGS. 29 and 30). As a result, silicide block films 45 and 55a are formed along with the sidewalls 34, 44 and 54 as shown in FIG.

FIG. 33 is a schematic cross-sectional view of the relevant part showing an ion implantation step for forming a source region and a drain region in the third application example.
As shown in FIG. 33, a resist 68 in which the internal transistor portion 30, the input / output transistor portion 40, and the analog transistor portion 50 are opened is formed, and predetermined ion implantation is performed using the resist 68 as a mask (see FIG. 31). Thereby, source regions 36a, 46a, 56a, drain regions 36b, 46b, 56b and impurity region 46c are formed.

After the ion implantation, the resist 68 is removed and, for example, spike annealing is performed at a temperature of about 1000 ° C. to 1050 ° C. to activate the implanted impurities.
FIG. 34 is a schematic cross-sectional view of the relevant part in the silicide layer forming step of the third application example.

  After activation annealing, silicidation is performed, silicide layers 37, 37a, 37b are formed in the internal transistor portion 30, silicide layers 47, 47a, 47b, 47c are formed in the input / output transistor portion 40, and the analog transistor portion 50 is formed. Silicide layers 57, 57a and 57c are formed.

FIG. 35 is a schematic cross-sectional view of the relevant part in the plug forming step of the third application example.
Finally, an interlayer insulating film 69 is formed, and plugs 70 connected to the source regions 36a, 46a, 56a and the drain regions 36b, 46b, 56b are formed.

  As a result, a semiconductor device including an internal transistor, an input / output transistor, and an analog transistor is obtained. As described above, in the analog transistor of this semiconductor device, the silicide block film 55a integrated with the sidewall 54 is formed on the drain side. Therefore, the voltage applied to the drain region 56b can be effectively lowered in the LDD region 53b, and the electric field concentration at the end of the LDD region 53b in the vicinity of the gate electrode 52 can be effectively suppressed.

(Supplementary Note 1) In a semiconductor device including a field effect transistor,
A gate electrode formed on a semiconductor substrate via an insulating film;
A sidewall formed on the gate electrode;
A first impurity region formed in the semiconductor substrate on both sides of the gate electrode;
A silicide block film formed on one first impurity region of the first impurity regions and spaced apart from the sidewall;
In the semiconductor substrate on the side opposite to the sidewall side of the silicide block film on the side where the one first impurity region is formed, and on the other side of the first impurity region, the other first impurity region is formed. A second impurity region formed in each of the semiconductor substrates on the other side,
A silicide layer formed on each of the gate electrode surface, the second impurity region surface, and the first impurity region surface between the silicide block film and the sidewall;
A semiconductor device comprising:

  (Supplementary note 2) The semiconductor according to supplementary note 1, wherein the first and second impurity regions have the same conductivity type, and the first impurity region has a lower concentration than the second impurity region. apparatus.

(Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the first impurity region is formed in a shallower region in the semiconductor substrate than the second impurity region.
(Supplementary Note 4) The first impurity region is formed to reach a region under the gate electrode,
The second impurity region is formed so as to reach a region immediately below the silicide block film on the side where the one first impurity region is formed, and on the side where the other first impurity region is formed. 4. The semiconductor device according to any one of appendices 1 to 3, wherein the semiconductor device is formed so as to reach a region directly under a sidewall.

(Additional remark 5) The said side wall and the said silicide block film are comprised by the insulating film of the same composition, The semiconductor device in any one of Additional remark 1 to 4 characterized by the above-mentioned.
(Additional remark 6) In the manufacturing method of a semiconductor device provided with a field effect transistor,
Forming a gate electrode on the semiconductor substrate via an insulating film;
Introducing an impurity into the semiconductor substrate on both sides of the formed gate electrode to form a first impurity region;
Forming a sidewall on the gate electrode, and forming a silicide block film on a part of one of the first impurity regions apart from the sidewall;
Forming a mask covering the first impurity region between the silicide block film and the sidewall;
Impurities are introduced using the formed mask, and the first impurity is formed in the semiconductor substrate on the side opposite to the sidewall side of the silicide block film on the side where the first impurity region is formed. Forming a second impurity region in each of the semiconductor substrates on the side where the other first impurity region is formed,
Removing the mask;
Forming a silicide layer on each of the gate electrode surface, the second impurity region surface, and the first impurity region surface between the silicide block film and the sidewall from which the mask has been removed;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary Note 7) When forming the first and second impurity regions, the first and second impurity regions are formed with the same conductivity type, and the first impurity region is formed more than the second impurity region. The method for manufacturing a semiconductor device according to appendix 6, wherein the semiconductor device is formed at a low concentration.

  (Supplementary Note 8) When forming the first and second impurity regions, the first impurity region is formed in a shallower region in the semiconductor substrate than the second impurity region. A method for manufacturing a semiconductor device according to 6 or 7.

  (Additional remark 9) When forming the first impurity region, the first impurity region is formed so as to reach a region under the gate electrode. A method for manufacturing a semiconductor device.

  (Supplementary Note 10) The step of forming the silicide block film includes depositing an insulating film on the semiconductor substrate and performing anisotropic etching on the gate electrode after the step of forming the first impurity region. The method for manufacturing a semiconductor device according to any one of appendices 6 to 9, further comprising: forming a sidewall and leaving the insulating film in a part on the one first impurity region.

(Additional remark 11) In the manufacturing method of a semiconductor device provided with a field effect transistor,
Forming a gate electrode on the semiconductor substrate via an insulating film;
Introducing an impurity into the semiconductor substrate on both sides of the formed gate electrode to form a first impurity region;
Forming a sidewall on the gate electrode;
Forming a mask covering from a part of the sidewall to a part of one first impurity region of the first impurity regions;
Impurities are introduced using the formed mask, and the first impurity region is formed in the semiconductor substrate on the side where the first impurity region is formed and on the other side of the first impurity region. Forming a second impurity region in each of the semiconductor substrates on the other side,
Removing the mask;
Forming a silicide layer on each of the gate electrode surface, the second impurity region surface, and the first impurity region surface from which the mask has been removed;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary Note 12) When forming the first and second impurity regions, the first and second impurity regions are formed with the same conductivity type, and the first impurity region is formed more than the second impurity region. The method for manufacturing a semiconductor device according to appendix 11, wherein the semiconductor device is formed at a low concentration.

  (Supplementary note 13) When forming the first and second impurity regions, the first impurity region is formed in a shallower region in the semiconductor substrate than the second impurity region. A method for manufacturing a semiconductor device according to 11 or 12.

  (Additional remark 14) When forming the first impurity region, the first impurity region is formed so as to reach a region under the gate electrode. A method for manufacturing a semiconductor device.

(Additional remark 15) In the manufacturing method of a semiconductor device provided with a field effect transistor,
Forming a gate electrode on the semiconductor substrate via an insulating film;
Introducing an impurity into the semiconductor substrate on both sides of the formed gate electrode to form a first impurity region;
Forming a sidewall on the gate electrode, and forming a silicide block film integrally with the sidewall from the sidewall to a part of the first impurity region on one of the first impurity regions;
Impurities are introduced using the silicide block film, and the other first impurity region of the first impurity region is formed in the semiconductor substrate on the side where the first impurity region is formed. Forming a second impurity region in each of the semiconductor substrates on the side,
Forming a silicide layer on each of the gate electrode surface and the second impurity region surface;
A method for manufacturing a semiconductor device, comprising:

  (Supplementary Note 16) When the first and second impurity regions are formed, the first and second impurity regions are formed with the same conductivity type, and the first impurity region is formed more than the second impurity region. The method for manufacturing a semiconductor device according to appendix 15, wherein the semiconductor device is formed at a low concentration.

  (Supplementary Note 17) When forming the first and second impurity regions, the first impurity region is formed in a shallower region in the semiconductor substrate than the second impurity region. A method for manufacturing a semiconductor device according to 15 or 16.

  (Supplementary note 18) When the first impurity region is formed, the first impurity region is formed so as to reach a region under the gate electrode. A method for manufacturing a semiconductor device.

  (Supplementary Note 19) The step of forming the silicide block film includes depositing an insulating film on the semiconductor substrate and performing anisotropic etching on the gate electrode after the step of forming the first impurity region. The method for manufacturing a semiconductor device according to any one of appendices 15 to 18, further comprising: forming a sidewall and leaving the insulating film in a part on the first impurity region.

It is a figure which shows the structural example of the semiconductor device of 1st Embodiment. FIGS. 2A and 2B are diagrams illustrating a potential distribution in a semiconductor device (part 1), where FIG. 1A is an example of a semiconductor device configuration, and FIG. FIGS. 2A and 2B are diagrams illustrating a potential distribution in a semiconductor device (part 2), where FIG. 2A is an example of a semiconductor device configuration, and FIG. FIGS. 4A and 4B are diagrams for explaining a parasitic resistance reduction effect by a silicide layer between a sidewall and a silicide block film, where FIG. 5A is a semiconductor device having no silicide layer between the sidewall and the silicide block film, and FIG. A semiconductor device having a silicide layer between silicide block films. It is a principal part cross-sectional schematic diagram of the LDD area | region formation process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the insulating film and resist formation process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of the resist formation and ion implantation process of 1st Embodiment. It is a principal part cross-sectional schematic diagram of an element isolation region formation process. It is a principal part cross-sectional schematic diagram of the ion implantation process for 1st well area | region formation and threshold value adjustment. It is a principal part cross-sectional schematic diagram of the ion implantation process for 2nd well region formation and threshold value adjustment. It is a principal part cross-sectional schematic diagram of an insulating film formation process. It is a principal part cross-sectional schematic diagram of an insulating film and polysilicon formation process. It is a principal part cross-sectional schematic diagram of a gate processing process. It is a principal part cross-sectional schematic diagram of the ion implantation process for extension area | region and pocket area | region formation. It is a principal part cross-sectional schematic diagram of the ion implantation process for LDD area | region formation. It is a principal part cross-sectional schematic diagram of a sidewall silicide block film formation process. It is a principal part cross-sectional schematic diagram of the ion implantation process for source region / drain region formation. It is a principal part cross-sectional schematic diagram of a silicide layer formation process. It is a principal part cross-sectional schematic diagram of a plug formation process. It is a figure which shows the structural example of the semiconductor device of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the resist formation and ion implantation process of 2nd Embodiment. It is a principal part cross-sectional schematic diagram of the side wall silicide block film formation process of the 2nd application example. It is a principal part cross-sectional schematic diagram of the ion implantation process for source region / drain region formation of the 2nd application example. It is a principal part cross-sectional schematic diagram of the silicide layer formation process of the 2nd application example. It is a principal part cross-sectional schematic diagram of the plug formation process of the 2nd application example. It is a figure which shows the structural example of the semiconductor device of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the insulating film and resist formation process of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the etching process of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the resist formation and ion implantation process of 3rd Embodiment. It is a principal part cross-sectional schematic diagram of the sidewall silicide block film formation process of the 3rd application example. It is a principal part cross-sectional schematic diagram of the ion implantation process for source region / drain region formation of the 3rd application example. It is a principal part cross-sectional schematic diagram of the silicide layer formation process of the 3rd application example. It is a principal part cross-sectional schematic diagram of the plug formation process of the 3rd application example.

Explanation of symbols

1, 80, 90, 100, 200 Semiconductor device 2, 21 Element isolation region 3, 20 Semiconductor substrate 4, 31, 41, 51 Gate insulating film 5, 32, 42, 52 Gate electrode 6, 34, 44, 54 Side wall 7a, 7b, 43a, 43b, 53a, 53b LDD regions 8a, 36a, 46a, 56a Source regions 8b, 36b, 46b, 56b Drain regions 9, 45, 55, 55a, 91 Silicide block films 10, 10a, 10b, 10c , 37, 37a, 37b, 47, 47a, 47b, 47c, 57, 57a, 57b, 57c, 57d, 81 Silicide layer 11 Silicide block region 12, 38, 48, 58 Well region 13, 62, 64, 92 Insulating film 14, 15, 60, 61, 63, 66, 67, 68, 82, 93, 94 resist 0 internal transistor section 33a, 33b extension regions 40 output transistor section 46c, 101 impurity region 50 analog transistor 65 polysilicon layer 69 interlayer insulating film 70 plugs

Claims (10)

In a semiconductor device including a field effect transistor,
A gate electrode formed on a semiconductor substrate via an insulating film;
A sidewall formed on the gate electrode;
A first impurity region formed in the semiconductor substrate on both sides of the gate electrode;
A silicide block film formed on one first impurity region of the first impurity regions and spaced apart from the sidewall;
In the semiconductor substrate on the side opposite to the sidewall side of the silicide block film on the side where the one first impurity region is formed, and on the other side of the first impurity region, the other first impurity region is formed. A second impurity region formed in each of the semiconductor substrates on the other side,
A silicide layer formed on each of the gate electrode surface, the second impurity region surface, and the first impurity region surface between the silicide block film and the sidewall;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the first and second impurity regions have the same conductivity type, and the first impurity region has a lower concentration than the second impurity region.   The semiconductor device according to claim 1, wherein the first impurity region is formed in a shallower region in the semiconductor substrate than the second impurity region. The first impurity region is formed to reach a region under the gate electrode;
The second impurity region is formed so as to reach a region immediately below the silicide block film on the side where the one first impurity region is formed, and on the side where the other first impurity region is formed. 4. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to reach a region immediately below the sidewall.   5. The semiconductor device according to claim 1, wherein the sidewall and the silicide block film are made of an insulating film having the same composition. In a method for manufacturing a semiconductor device including a field effect transistor,
Forming a gate electrode on the semiconductor substrate via an insulating film;
Introducing an impurity into the semiconductor substrate on both sides of the formed gate electrode to form a first impurity region;
Forming a sidewall on the gate electrode, and forming a silicide block film on a part of one of the first impurity regions apart from the sidewall;
Forming a mask covering the first impurity region between the silicide block film and the sidewall;
Impurities are introduced using the formed mask, and the first impurity is formed in the semiconductor substrate on the side opposite to the sidewall side of the silicide block film on the side where the first impurity region is formed. Forming a second impurity region in each of the semiconductor substrates on the side where the other first impurity region is formed,
Removing the mask;
Forming a silicide layer on each of the gate electrode surface, the second impurity region surface, and the first impurity region surface between the silicide block film and the sidewall from which the mask has been removed;
A method for manufacturing a semiconductor device, comprising:   When forming the first and second impurity regions, the first and second impurity regions are formed with the same conductivity type, and the first impurity region is formed at a lower concentration than the second impurity region. The method of manufacturing a semiconductor device according to claim 6.   8. The first and second impurity regions are formed in a shallower region in the semiconductor substrate than the second impurity region when forming the first and second impurity regions. The manufacturing method of the semiconductor device as described in 2.   9. The semiconductor device according to claim 6, wherein when forming the first impurity region, the first impurity region is formed so as to reach a region under the gate electrode. Production method.   In the step of forming the silicide block film, after the step of forming the first impurity region, an insulating film is deposited on the semiconductor substrate, and anisotropic etching is performed to form the sidewalls on the gate electrode. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of leaving the insulating film in a part on the one first impurity region.

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