JP2008210436A - Semiconductor memory device equipped with internal clock generating circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a command fetch in a command decoder is delayed because arrangement position of an input pad of an external clock and arrangement positions of an input pad of a command signal and the command decoder, are sometimes separated by the user's demand, with respect to the semiconductor memory device. <P>SOLUTION: A clock to be input to the command decoder is generated by the internal clock generating circuit provided with a DLL circuit. The command decoder to which the internal clock is input from the internal clock generating circuit, can output an internal command signal in timing of highest speed synchronized with the external clock. Further by preparing a DCC decision circuit, a duty can also be adjusted. The high speed accessible semiconductor memory device is obtained by preparing the internal clock generating circuit for the command decoder. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including an internal clock generation circuit that generates an internal clock synchronized with an external clock.

  In recent years, semiconductor memory devices have been increasing in storage capacity and access speed. In order to realize this high-speed access, the semiconductor memory device employs a clock synchronization method synchronized with an external clock. For example, in a dynamic random access memory (hereinafter referred to as DRAM) which is a typical semiconductor memory device, a synchronous DRAM (hereinafter referred to as SDRAM) or a double data rate DRAM (hereinafter referred to as DDR-DRAM) system is adopted.

  In SDRAM and DDR-DRAM, an internal circuit of a semiconductor memory device is operated in synchronization with an input external clock. For example, it takes in command signals and address signals from outside and controls the timing of data input / output. In particular, for data, both input of write data and output of read data are controlled by an external system clock. Further, high-speed operation is required so that one data is input / output to the SDRAM and two data is input / output to the DDR-DRAM per cycle of the external clock. For these reasons, an internal clock synchronized with an external clock generated by an internal clock generation circuit is used for timing adjustment of data input / output.

  On the other hand, the external clock is used as it is for taking in the command signal and address signal. The command signal and address signal should be input every one to several cycles of the external clock. Further, after being once taken in, the external clock is used as it is because it is used only inside the semiconductor memory device. However, the semiconductor memory device may be required to strictly limit the position of the signal input pad as the storage capacity is increased and the access speed is increased, and the user is further customized. That is, the input pad position of the external clock may be arranged apart from other command signal input pad positions according to a user request. Since the input pad position is different, the wiring delay difference inside the semiconductor memory circuit becomes remarkable, and synchronization with an external clock and high-speed access become difficult. As a result, the risk of malfunction of the clock synchronous DRAM has increased.

  These problems in the conventional synchronous DRAM will be described with reference to FIGS. FIG. 11 shows a schematic chip layout of a conventional semiconductor memory device, and FIG. 12 shows a timing chart thereof. In particular, when the position of the input pad for various command signals and the input pad for the external clock CK are separated due to a request from the user, this problem becomes significant. The input pad includes an external connection pad and an input first stage circuit.

  In the chip layout shown in FIG. 11, the position of the input pad 12 for the external clock CK is distant from the position of the input pad 12 for various command signals COM (WEB, CASB, RASB, CSB, CKE). Therefore, the command decoder 10 is arranged in the vicinity of the input pad 12 for various command signals COM. As a result, the wiring from the input pad 12 of the external clock CK to the command decoder 10 becomes long, and the wiring delay time becomes long. In order to synchronize with the external clock CK having a large delay time, it is necessary to delay the other command signal COM and adjust the timing. Thus, extra delay adjustment is required for various internal signals, and DRAM access is delayed.

  FIG. 12 shows a timing chart of the external clock CK (@ input pad), the command signal COM (@ input pad), the external clock CK (@ command decoder), and the internal command signal INTCOM. Since the position of the input pad for the external clock CK is far from the position of the command decoder 10, the timing input to the command decoder 10 is delayed. In the following description, a signal having a large delay time is identified as, for example, an external clock CK (@input pad) for an external clock at an input pad, and an external clock CK (@command decoder) for an external clock at a command decoder. And

  The external clock CK (@ input pad) and the command signal COM (@ input pad) are input to the input pad 12 almost simultaneously. However, since the external clock CK (@command decoder) is delayed, the command signal COM in the command decoder 10 is delayed. Therefore, the internal command signal INTCOM from the command decoder 10 is generated with a delay. As a result, DRAM access is delayed. Thus, the delay time differs depending on the location of the external clock CK in the DRAM chip, and there is a problem that delay adjustment with other command signals COM is required and the DRAM access is delayed.

  The following patent documents are related to the internal clock generation circuit. In Patent Document 1 (Japanese Patent Laid-Open No. 2005-332548), the DLL circuit includes a phase detector, a delay line controller, a delay line, and a replication delay model whose delay time can be controlled by a control signal. A technique for generating an internal clock using this DLL circuit is disclosed. Patent Document 2 (Japanese Patent Laid-Open No. 2002-1000098) discloses a technique for generating an internal clock by a DLL circuit including a phase comparator that detects an edge of a feedback clock with respect to a reference clock.

  Japanese Patent Laid-Open No. 2005-318520 discloses a duty cycle calibration (Duty Cycle Correction, hereinafter referred to as DCC) circuit that calibrates a duty cycle from a clock and its inverted clock. Patent Document 4 (Japanese Patent Laid-Open No. 8-21385) discloses a technique for generating an internal clock having the same cycle as that of a reference clock but having a different duty cycle.

JP 2005-332548 A Japanese Patent Laid-Open No. 2002-10072 JP 2005-318520 A JP-A-8-213885

  As described above, the delay time to the command decoder differs depending on the input pad position of the external clock and the command signal. For this reason, it is necessary to adjust the timing of the external clock and the command signal, which makes it difficult to access the SDRAM at high speed. In view of these problems, an object of the present invention is to provide a semiconductor memory device including a clock generation circuit that generates an internal clock optimal for taking in a command signal.

  In order to solve the above-described problems, the present application basically employs the techniques described below. Needless to say, application techniques that can be variously changed without departing from the technical scope of the present invention are also included in the present application.

  The semiconductor memory device of the present invention includes an internal clock generation circuit that generates a clock input to a command decoder, and the internal clock generation circuit generates an internal clock in synchronization with an external clock in the command decoder, and The command decoder to which the internal clock from the clock generation circuit is input outputs an internal command signal synchronized with the external clock.

  The internal clock generation circuit of the semiconductor memory device of the present invention has an external clock and a feedback clock as input, a phase detection circuit for comparing the phases of the two clocks, and a delay circuit whose delay time is controlled by a delay control circuit And a replica circuit having a delay time from the internal clock generation circuit to the command decoder, the delay control circuit determines a delay amount based on a phase comparison result from the phase detection circuit, and the delay circuit is input The external clock is an internal clock delayed by a desired time by a control signal from the delay control circuit, and is output to the command decoder and the replication circuit, and the replication circuit outputs a feedback clock to the phase detection circuit. It is characterized by.

  In the semiconductor memory device of the present invention, the internal clock output from the internal clock generation circuit is branched and further output to the data control circuit, and the delay time from the internal clock generation circuit to the data control circuit is The delay time is equal to the delay time from the internal clock generation circuit to the command decoder.

  The internal clock generation circuit of the semiconductor memory device of the present invention further includes a duty cycle calibration determination circuit, and calibrates the duty cycle of the internal clock.

  The duty cycle calibration determination circuit of the semiconductor memory device according to the present invention is characterized in that the feedback clock is input and a control signal for calibrating the duty cycle is output to the delay control circuit.

  The phase detection circuit of the semiconductor memory device of the present invention compares the phase of one of the rising side or the falling side of the input external clock and the feedback clock, and outputs the phase comparison result to the delay control circuit. The control circuit sets a delay amount so that one of the rise side and the fall side is in phase according to the phase comparison result, and the remaining one of the fall side or rise side sets the delay amount by a control signal from the duty cycle calibration determination circuit. The duty cycle is calibrated by setting.

  The internal clock generation circuit according to the present invention includes a DLL circuit and generates an internal clock input to the command decoder. An internal clock is generated by an internal clock generation circuit having a DLL circuit so as to be synchronized with an external clock. With this internal clock, the internal command signal from the command decoder can be synchronized with the external clock and output at the fastest timing. The internal clock generation circuit of the present invention has the advantage that the fastest internal command signal synchronized with the external clock can be obtained and a semiconductor memory device capable of high speed access can be obtained.

  A semiconductor memory device having an internal clock generation circuit according to the present invention will be described in detail with reference to the drawings.

  A first embodiment of a semiconductor memory device having an internal clock generation circuit according to the present invention will be described with reference to FIGS. FIG. 1 shows an overall configuration block of an internal clock generation circuit. FIG. 2 shows a chip layout of the semiconductor memory device. FIG. 3 shows a timing chart of signals.

  In the chip layout of the semiconductor memory device shown in FIG. 2, the arrangement position of the input pad 12 for the external clock CK is separated from the arrangement position of the input pad 12 and the command decoder for various command signals COM. An internal clock generation circuit 11 is arranged between the input pad 12 for the external clock CK and the command decoder 10. The external clock CK is input to the input first stage circuit 1 and output to the internal clock generation circuit 11. The internal clock generation circuit 11 generates an internal clock INTCK that is synchronized with the external clock CK in the command decoder 10 and outputs it to the command decoder 10. The command decoder 10 takes in the input command signal COM in synchronization with the internal clock INTCK, and outputs it as an internal command signal INTCOM to various circuits in the chip.

  The internal clock generation circuit 11 shown in FIG. 1 includes a DLL (Delayed Locked Loop) circuit including a phase detection circuit 3, a delay control circuit 4, a delay circuit 5, and a replication circuit 6. Here, the replica circuit 6 is a replica circuit of the path A from the internal clock generation output circuit 11 to the command decoder 10 as shown in the chip layout of FIG. This duplication circuit 6 is called a path A duplication circuit 6 because it is a duplication of the path A and has the same delay time as the path A. The path A duplicating circuit 6 outputs a feedback clock FBCK having the same phase as the internal clock INTCK input to the command decoder 10.

  The phase detection circuit 3 receives the feedback clock FBCK and the external clock CK from the input first stage circuit 1 and compares the phases. The delay amount of the delay circuit 5 is determined by the delay control circuit 4 so that the two clock phases match. The phase detection circuit 3 detects both the rising edge and the falling edge of the phases of the feedback clock FBCK and the external clock CK. Further, the delay control circuit 4 also sets the delay amounts on the rise side and the fall side so that both the phases on the rise side and the fall side are matched.

  The external clock input by the delay circuit 5 is delayed by a desired amount to generate the internal clock INTCK. The internal clock INTCK is output to the command decoder 10 and the path A replication circuit 6. The path A replication circuit 6 outputs a feedback clock obtained by delaying the delay time to the command decoder 10 to the phase detection circuit 3. The DLL circuit synchronizes the phases of the input external clock CK and the feedback clock FBCK. By doing so, the internal clock INTCK input to the command decoder 10 is synchronized with the external clock CK. The external clock serving as a reference to be synchronized is an external clock (@ input pad) input to the input pad of the semiconductor memory device. The reference external clock (@input pad) may be simply referred to as an external clock.

  Next, the operation of the first embodiment will be described with reference to the timing chart of FIG. FIG. 3 shows an external clock CK (@ input pad), a command signal COM (@ input pad), an internal clock INTCK (@ command decoder), and an internal command signal INTCOM. The internal clock INTCK input to the command decoder 10 is synchronized with the external clock CK (@input pad). For this reason, the internal command signal INTCOM is also synchronized with the external clock CK (@ input pad) and is output at the fastest timing without delay.

  As described above, even when the positions of the input pads for the external clock CK and the other command signal COM are separated, the internal clock INTCK input to the command decoder 10 is synchronized with the external clock CK (@ input pad). The internal command signal INTCOM can be output at the fastest timing. Since the internal command signal INTCOM is output at the fastest timing, a semiconductor memory device capable of high-speed access can be obtained.

  In the present embodiment, an internal clock generation circuit composed of a DLL circuit is provided, and an internal clock synchronized with an external clock is generated. By inputting this internal clock to the command decoder, the internal command signal is output at the fastest timing synchronized with the external clock. According to this embodiment, an internal command signal is output at the fastest timing, and a semiconductor memory device that can be accessed at high speed is obtained.

  A second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing the overall configuration of the internal clock generation circuit. FIG. 5 shows a timing chart of the signal waveform, and FIG. 6 shows a timing chart in the conventional example. This embodiment is an improvement of the first embodiment, and is an embodiment in which a DCC determination circuit is added to the internal clock generation circuit of the first embodiment and the clock duty is adjusted.

  The chip layout of the semiconductor memory device in the second embodiment is the same as that in the first embodiment (FIG. 2). The position of the input pad 12 for the external clock CK and the position where the input pad 12 and the command decoder 10 for the various command signals COM are arranged are separated. An internal clock generation circuit having a DCC determination circuit is inserted between the input pad 12 of the external clock CK and the command decoder 10. The external clock CK input here has a duty deviation.

  Referring to FIG. 6, the problem when there is no internal clock generation circuit and the external clock has a duty deviation will be described. FIG. 6 shows a timing chart of the external clock CK (@ input pad), the command signal COM (@ input pad), the external clock CK (@ command decoder), and the internal command signal INTCOM. The position of the input pad for the external clock CK is far from the position of the command decoder 10. Therefore, the external clock CK (@command decoder) input to the command decoder 10 is delayed.

  Further, the external clock CK (@ input pad) has a duty shift. As described above, when the frequency of the external clock increases as the access speed increases, the duty shift of the external clock CK increases. When the command signal COM is taken in by the command decoder 10 using this external clock CK (@command decoder), the internal command signal INTCOM has a large delay time and its pulse width depends on the duty of the input clock. Have changed.

  When the duty is shifted as described above, the margin of the latch timing becomes strict in the internal circuit. In contrast to FIG. 6, when the duty is shifted in the direction in which the high level disappears, there is a risk that the high level disappears and the clock is lost in the worst case. Thus, when there is a duty shift at a high frequency, it becomes more difficult to synchronize with an external clock, and the semiconductor memory device malfunctions. In order to solve these problems, an internal clock generation circuit including a DCC determination circuit shown in FIG. 4 can be employed.

  FIG. 4 shows a block diagram of the overall configuration of the internal clock generation circuit. Here, in addition to the configuration of the internal clock generation circuit of FIG. 1, a DCC determination circuit 7 is newly added. The DCC determination circuit 7 receives the feedback clock FBCK and outputs a delay control signal to the delay control circuit 4. The basic operation of the internal clock generation circuit is the same as that of the first embodiment, and the added DCC determination circuit 7 will be described.

  The phase detection circuit 3 receives the external clock CK and the feedback clock FBCK, and compares the phases of one of the rising side and the falling side of the two clock waveforms. The phase comparison result is output to the delay control circuit 4. The delay control circuit 4 sets the delay amount so that one of the phases on the rise side or the fall side is matched according to the phase comparison result from the phase detection circuit 3. The delay amount on the other fall side or rise side is controlled by the delay control signal from the DCC determination circuit 7 so that the clock duty matches. As a result, the command decoder 10 is supplied with the internal clock INTCK which is synchronized with the external clock CK and whose duty is adjusted.

  Next, the operation waveform of the second embodiment will be described with reference to the timing chart of FIG. FIG. 5 shows waveforms of the external clock CK (@ input pad), the command signal COM (@ input pad), the internal clock INTCK (@ command decoder), and the internal command signal INTCOM. The external clock CK (@ input pad) is input with the duty shifted. However, the internal clock INTCK has a waveform in which the duty is adjusted in synchronization with the external clock. Therefore, the internal command signal INTCOM is also output as a waveform with a fixed duty at the fastest timing. Unlike the waveform of the conventional example of FIG. 6, the internal clock is output with the duty adjusted by the DCC determination circuit, so there is no possibility of causing the malfunction of the semiconductor memory device as described above.

  In this embodiment, an internal clock generation circuit composed of a DLL circuit having a DCC determination circuit is provided, and an internal clock having a duty adjusted in synchronization with an external clock is generated. By inputting this internal clock to the command decoder, the internal command signal is output at the fastest timing. According to this embodiment, an internal command signal is output at the fastest timing, and a semiconductor memory device that can be accessed at high speed is obtained.

  A third embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a chip layout of the semiconductor memory device in this embodiment. FIG. 8 shows a block diagram showing the overall configuration of the internal clock generation circuit. For comparison, FIGS. 9 and 10 show a semiconductor memory circuit having an internal clock generation circuit for data strobe signal DQS as a conventional example. FIG. 9 shows a chip layout of the semiconductor memory device, and FIG. 10 shows an overall configuration block of an internal clock generation circuit for the data strobe signal DQS. In this embodiment, the internal clock generation circuit for the command decoder and the data control circuit is shared.

  First, a conventional internal clock generation circuit for a data control circuit will be described with reference to FIGS. As shown in FIG. 9, the position of the input pad 12 for the external clock CK is distant from the position of the input pad 12 and the command decoder for the various command signals COM (WEB, CASB, RASB, CSB, CKE). The external clock CK is input to the command decoder 10 as it is. The internal clock INTCK from the internal clock generation circuit 11 is input to the data control circuit 2.

  The internal clock generation circuit 11 includes a phase detection circuit 3, a delay control circuit 4, a delay circuit 5, a duplication circuit 6, and a DCC determination circuit 7 for duty correction. The internal clock INTCK generated by the internal clock generation circuit 11 needs to be synchronized with the external clock CK in the data control circuit 2. Therefore, the replica circuit 6 of the path B having the delay time of the path B from the internal clock generation circuit 11 to the data control circuit 2 is employed. By using the internal clock generation circuit 11, the data control circuit 2 can obtain the data strobe signal DQS synchronized with the external clock CK and can be accessed at high speed. On the other hand, the command system uses the external clock CK as it is, so that the command is fetched at a timing delayed by the delay time from the input pad 12 of the external clock CK to the command decoder 10. Therefore, there is a problem that high-speed access cannot be performed.

  A solution to this problem is shown in FIGS. As shown in FIG. 7, the external clock CK is input to the internal clock generation circuit 11, and the internal clock INTCK is output. The internal clock INTCK is output to the command decoder 10 and the data control circuit 2. At this time, the internal clock INTCK is commonly routed from the internal clock generation circuit 11 via the path C, and then branched to the data control circuit 2 via the path D and the command decoder 10 via the path D '. Here, equal-length wiring is performed so that the delay times in the path D and the path D 'are equal. That is, the delay time from the internal clock generation circuit 11 to the data control circuit 2 and the delay time from the internal clock generation circuit 11 to the command decoder 10 are set to be equal in length.

  The internal clock generation circuit 11 shown in FIG. 8 includes a phase detection circuit 3, a delay control circuit 4, a delay circuit 5, a duplication circuit 6, and a DCC determination circuit 7 for duty correction. The delay time of the duplication circuit 6 is the sum of the delay times of the path C and the path D (= path D ′). That is, the internal clocks arriving at the data control circuit 2 and the command decoder 10 have the same timing and can be synchronized with the external clock CK (@input pad). Since the operation of the internal clock generation circuit 11 is the same as that of the second embodiment, its detailed description is omitted.

  In this way, by setting the delay time of the replication circuit as the sum of the delay times of the path C and the path D (= path D ′), an internal clock generation circuit that can be shared by the data control circuit 2 and the command decoder 10 is configured. be able to. Both the data control circuit 2 and the command decoder 10 supplied with the internal clock INTCK generated by the internal clock generation circuit 11 can operate at the fastest timing in synchronization with the external clock CK (@input pad). Therefore, a semiconductor memory device that can be accessed at high speed can be obtained.

  In addition to the embodiments described above, there are application examples. For example, during a period in which the semiconductor memory device is in a standby state and no auto-refresh operation is performed, the operation of the internal clock generation circuit can also be in a standby state. In this case, the lock signal is generated when the delay adjustment of the DLL circuit is completed. By logically processing the lock signal, the auto-refresh period signal, and the like, the operation of the internal clock generation circuit is also set in the standby state, and the generation of the internal clock can be stopped for a short period. In this standby state, the previous state is maintained, and an internal clock can be generated immediately after returning. By setting the standby state in this way, the power consumption of the semiconductor memory device can be reduced.

  The semiconductor memory device of the present invention includes an internal clock generation circuit using a DLL circuit. The internal clock generated in the internal clock generation circuit is supplied to the command decoder. The command decoder to which the internal clock from the internal clock generation circuit is input can output the internal command signal at the fastest timing synchronized with the external clock. Therefore, a semiconductor memory device that can be accessed at high speed is obtained. These internal clock generation circuits can be commonly used for the command decoder and the data control circuit, and can be supplied from one internal clock generation circuit to the command decoder and the data control circuit. Further, by providing a DCC determination circuit in the internal clock generation circuit and adjusting the duty of the clock, an operation margin such as a command latch margin can be secured, and a semiconductor memory device capable of high-speed access can be obtained.

  Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention. Needless to say, this is also included in the present application.

  As a field of application of the present invention, it can be suitably used in synchronous dynamic random access memories such as SDRAM and DDR-DRAM.

1 is an overall configuration block diagram of an internal clock generation circuit in Embodiment 1. FIG. 1 is a diagram showing a chip layout in Example 1. FIG. 3 is a timing chart in the first embodiment. FIG. 6 is a block diagram of an overall configuration of an internal clock generation circuit according to a second embodiment. 6 is a timing chart in the second embodiment. It is a timing chart in case there exists a delay and duty shift in a conventional example. FIG. 6 is a diagram showing a chip layout in Example 3. FIG. 9 is a block diagram of an overall configuration of an internal clock generation circuit according to a third embodiment. It is the figure which showed the chip layout provided with the internal clock generation circuit for DQS in a prior art example. It is a whole block diagram of the internal clock generation circuit for DQS in a prior art example. It is the figure which showed the chip layout for demonstrating the subject in a prior art example. It is a timing chart for demonstrating the subject in a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Input first stage circuit 2 Data control circuit 3 Phase detection circuit 4 Delay control circuit 5 Delay circuit 6 Duplicate circuit 7 DCC determination circuit 10 Command decoder 11 Internal clock generation circuit 12 Input pad

Claims (6)

  An internal clock generation circuit for generating a clock input to a command decoder; the internal clock generation circuit generates an internal clock in synchronization with an external clock in the command decoder; and an internal clock from the internal clock generation circuit The input command decoder outputs an internal command signal in synchronization with an external clock.   The internal clock generation circuit receives an external clock and a feedback clock, compares a phase of the two clocks, a delay circuit whose delay time is controlled by a delay control circuit, and the internal clock generation circuit The delay control circuit determines a delay amount based on the phase comparison result from the phase detection circuit, and the delay circuit controls the input external clock to the delay control. 2. An internal clock delayed by a desired time by a control signal from a circuit and output to the command decoder and the duplicating circuit, and the duplicating circuit outputs a feedback clock to the phase detection circuit. The semiconductor memory device described in 1.   The internal clock output from the internal clock generation circuit is branched and further output to the data control circuit. The delay time from the internal clock generation circuit to the data control circuit is from the internal clock generation circuit to the command decoder. The semiconductor memory device according to claim 2, wherein the delay time is equal to a delay time of   The semiconductor memory device according to claim 2, wherein the internal clock generation circuit further includes a duty cycle calibration determination circuit to calibrate the duty cycle of the internal clock.   5. The semiconductor memory device according to claim 4, wherein the duty cycle calibration determination circuit receives the feedback clock and outputs a control signal for calibrating a duty cycle to the delay control circuit.   The phase detection circuit compares the phase of one of the input external clock and the rising or falling side of the feedback clock, and outputs the phase comparison result to the delay control circuit. The delay amount is set so that one of the phases on the rise side or the fall side is in phase, and the duty cycle is calibrated by setting the delay amount on the other fall side or rise side by the control signal from the duty cycle calibration judgment circuit. The semiconductor memory device according to claim 5.

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