JP2008210432A - Optical disk device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control a mark space of a 13T part of a synchronous code for DSV suppression and running OPC in order to deal with high-speed recording. <P>SOLUTION: A code modulation system for converting a 2-bit data word into a 3n-bit code word includes a byte counter for counting the number of data words, a synchronous frame counter for counting a byte counter value, a DSV processing circuit for establishing a DSV control bit, a 13T mark detection part for detecting that 13T polarity is a mark, and a 13T part polarity selection table for deciding which of a mark and a space the synchronous polarity part information of an odd frame is set to. In an odd synchronous frame, a DSV control bit is controlled by using the 13T part polarity selection table. In an even synchronous frame, a DSV control bit is controlled, a 13T mark detection signal is output to a sample holding circuit, recording laser power or the like is adjusted, and running OPC is carried out. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a modulation circuit used when digital data is recorded on an optical disc and an optical disc apparatus including the modulation circuit.

  Patent Document 1 discloses 8-12 modulation in which an 8-bit data word is converted into a 12-bit code word (also referred to as “modulation code”). Since the 8-12 modulation has a high coding rate of 2/3, it is suitable for high-density recording than the coding rate of 1/2 of the 8-16 modulation adopted in the DVD standard. Also, 8-12 modulation has a feature that there are few direct current components.

  In the 8-12 modulation of Patent Document 1, the correspondence between the data word and the code word is held in advance in order to satisfy RLL (1, 10) which limits the number of 0 between 1 and 1 to 10 at most. Modulation processing is performed using the modulation table. The modulation table defines three types of code words corresponding to each data word and next state information (Next State) for each code word. Three types of codewords corresponding to one data word are called a State0 codeword, a State1 codeword, and a State2 codeword. During the modulation process, a code word corresponding to the data word 8 bits and the state information (State0, State1, State2) is selected and output from the modulation table, and the next state information (Next State) is also output.

  The channel bit string generated by the 8-12 modulation is further converted into a pulse corresponding to a mark to be recorded by NRZI processing. NRZI is a process of inverting the polarity of a pulse every time 1 appears in a channel bit string. The pulse width is an integral multiple of the time width T for one channel bit. Since there is a portion having a 13T width in the sync code, the longest mark is a 13T mark.

  Patent Document 2 discloses a 4-6 modulation method for converting a 4-bit data word into a 6-bit code word. The 4-6 modulation also has a high coding rate of 2/3, and further has a feature that the conversion process can be simplified. In the modulation process of Patent Document 2, in order to satisfy RLL (1, 10) as in the 8-12 modulation of Patent Document 1, data words are converted into code words using a modulation table. In the modulation process of Patent Document 2, a code word corresponding to the data word 4 bits and the state information (State0, State1) is selected from the modulation table. The next state information (Next State) is also output.

The HD DVD standard employs 8-12 modulation and 4-6 modulation as modulation schemes. The 8-12 modulation system and 4-6 modulation system in the HD DVD standard have the following three characteristics.
(1) Modulation is performed so that a pattern “1010101010101” in which run length 1 continues six times in a code word does not appear. When such a pattern occurs when normal modulation is performed, control is performed so that “1010101010101” is not generated by replacing the code word based on a predetermined replacement rule (hereinafter, “concatenation rule”).
(2) The code word has a DSV control bit “#” that can be selected from “0” or “1” in accordance with DSV (Digital Sum Value).
(3) When codewords are combined, it is possible to select either “0” or “1” according to the first bit of the immediately following codeword so that the bit “1” does not continue at the boundary. The concatenation bit “*” is included at the end (LSB) of each code word.

  As described above, in 8-16 modulation, an 8-bit data word is converted into a 16-bit code word. Since one recording clock is required to output 1-bit NRZI, 16 recording clocks are required to output NRZI of one code word (16 bits). Therefore, if the modulation time of one data word (8 bits) is not suppressed within 16 recording clocks, which is the output time of one code word, the data word to be modulated accumulates in the previous stage of the modulation circuit and the recording system fails. There is a problem.

  In the optical disk device, user data is input from the ATAPI interface, user data modulated by the modulation circuit is output to the laser drive circuit as NRZI, and information is recorded on the optical disk with laser light emitted from the laser. The data input speed from the ATAPI interface and the NRZI output speed (recording speed) are defined in the standard.

  Data processing such as scrambling for input data input from the ATAPI interface is performed using a master clock. The writing of NRZI to the optical disc is performed in synchronization with a recording clock extracted from wobble provided on the recording surface of the optical disc. Either the master clock or the recording clock may be used for the operation of the modulation circuit that modulates the input data to NRZI. However, in the case of 8-16 modulation, it is necessary to perform modulation processing within the time of 16 recording clocks.

  The 8-16 modulation circuit for DVD disclosed in Patent Document 3 has an even or odd number of DSV modulation tables and code “1” included in the modulation code in order to speed up the DSV modulation time. An odd / even discrimination table indicating information indicating the above is provided. In paragraph 0025 of Patent Document 3, “If a processing time of 1 byte clock or more is required to modulate 1 byte information, more time is required to record a large amount of information. The problem is that the data transfer speed is substantially reduced. "

  The DSV calculation means of Patent Document 3 uses the odd / even discrimination table to speed up the DSV calculation of the modulation codeword. The polarity of the DSV value obtained from the odd / even discrimination table depends on whether the head of the codeword is a space or a mark. For example, even if an odd number of “1” bits are included in a certain modulation code, the polarity of the DSV value is different when the head of the modulation code is a space and when it is a mark. Similarly, when an even number of “1” bits are included in a certain modulation code, the polarity of the DSV value differs depending on whether the modulation code starts with a space or a mark. In other words, the polarity of the DSV value cannot be known even if the odd / even discrimination table is used unless the head of the code word is known in advance.

  Japanese Patent Application Laid-Open No. 2004-228688 discloses control of a synchronization code of an HD DVD that performs synchronization code control different from that of a DVD. As shown in FIG. 4A, there are four types of synchronization codes of HD DVD, SY0 to SY3, and each synchronization code has a pattern of State 0 and a pattern of State 1 and 2. As shown here, each synchronization code is 2 bytes (1 byte of codeword = 12 bits), and includes 13T (part of “10000000000001”) in which 12 consecutive 0s are arranged between 1 and 1. Since 13T is not included in the data portion, the synchronization code and the data portion can be distinguished by the presence or absence of 13T.

  Hereinafter, the front byte of each synchronization code is referred to as a front synchronization code (Front Sync Code), and the rear byte is referred to as a rear synchronization code (Rear Sync Code). As shown in FIG. 4A, the backward synchronization codes are all the same code (000000_001001). The forward synchronization code includes a DSV control bit #.

  In the HD DVD, one sector is composed of 26 synchronization frames as in the DVD. The arrangement of the synchronization code in each sector is shown in FIG. In Patent Document 4, the polarity (mark, space) of the 13T portion is switched once every two times by controlling the DSV control bit # included in each synchronization code. In an even frame, DSV control in the synchronization code (hereinafter referred to as “DC control: DC component suppression control”) is performed, and # is selected so that the DSV value becomes small. In the odd frame next to the even frame subjected to DC control, the DSV control bit # is set so that the 13T portion in the synchronization code of the preceding even frame is a space if it is a mark, and so that it is a mark if it is a space. Control. It is described that 13T polarity control (13T part polarity control) of the synchronization code is performed in this way, and R-OPC (Running Optimum Power Control) is executed at the timing of the 13T mark.

JP 2004-213863A (FIGS. 1 to 5a, b) JP 2004-213767 A (FIG. 1) Japanese Patent Laid-Open No. 10-233690 (paragraphs of FIGS. 3, 4, 5, and 0025) JP 2005-149640 A (2 pages, 3 pages)

  Normally, signal processing including modulation processing uses a master clock (MCLK), and recording processing such as laser driver control uses a recording clock (WCK) extracted from wobble. Since a 12-bit code word synchronized with the recording clock is converted into NRZI and output to the laser driver, a master clock having a cycle longer than 1/12 of the recording clock cannot be used.

FIG. 15 shows the relationship between the HD DVD recording clock (WCK) and the master clock (MCLK). Here, for the sake of simplicity, only a 1 × speed example and a 10 × speed example are shown.
In the case of 8-12 modulation, in order to perform the recording operation normally,
Time required for one modulation cycle <Time required for one modulation codeword output (12WCK) (Equation 1)
It is necessary to satisfy. The “modulation 1 cycle” is a time for converting one data word (8 bits) to one code word (12 bits) and determining the connection bit * and the DSV control bit #.
When MCK is used to express the time required for one modulation cycle,
1 / MCK × N (Formula 2)
It becomes. N is a positive integer.

  When the master clock is constant, it is necessary to decrease the number of clocks as the speed becomes higher. For example, in the case of 1 × speed, the modulation process may be completed within 16 cycles of the master clock (time required for one modulation cycle). In the case of 10 × speed, modulation is performed within one cycle of the master clock (time required for 1 modulation cycle). Processing needs to end. ○ in the right column indicates that (Expression 1) is satisfied, and x indicates that (Expression 1) is not satisfied.

  Patent Documents 1 and 2 show a simplified configuration of the modulation circuit, but modulation taking into account the DSV control bit # in the synchronization code and the concatenated bit * when the code word and the synchronization code are concatenated. The configuration of the circuit is not disclosed. Of course, the determination method of # and * is not taken into consideration. The configurations of Patent Documents 1 and 2 cannot support a modulation method that takes into account the DSV control bit # in the synchronization code defined by the HD DVD standard and the concatenated bit * when the code word and the synchronization code are concatenated. There is a problem that the relationship of (Equation 1) cannot be satisfied when the speed is doubled.

  Patent Document 3 discloses a DSV table used in 8-16 modulation that does not include the DSV control bit # and the concatenated bit *. However, the modulation includes the DSV control bit # and the concatenated bit * defined by the HD DVD standard. It is not clarified what DSV table can be used to complete the DSV calculation within the processing time required by the system when using the method. That is, 6 recordings of a modulation scheme of 4-6 modulation including a DSV table, DSV control bit #, and concatenated bit * that suppress modulation processing of 8-12 modulation including DSV control bit # and concatenated bit * within 12 recording clocks. A DSV table that is kept within a clock is not disclosed. For this reason, the configuration of Patent Document 3 cannot satisfy the modulation method including the DSV control bit # and the concatenated bit * defined by the HD DVD standard, and therefore satisfies the relationship of (Equation 1) when high speed is achieved. There is a problem that can not be.

  Patent Document 4 does not disclose a specific method for detecting and outputting the timing of which is the 13T mark among the 13T portions of the continuous 2-sync frame sync code. In addition, a specific circuit configuration on how to adjust the laser power using the 13T mark portion is not disclosed.

  Further, in any patent document, a specific circuit configuration corresponding to a modulation scheme of 8-12 modulation or 4-6 modulation including a DSV control bit # and a concatenated bit *, a running OPC (R-) using a 13T mark No specific circuit configuration of OPC), in particular, a circuit configuration realizing reduction in the number of elements and low power consumption is not disclosed.

  An object of the present invention is to solve the above problems.

  The above problems are solved by the invention described in the claims.

  According to the present invention, it is possible to improve the user's perceived speed during recording processing on an optical disc. Further, by performing polarity control of the synchronization code 13T portion using the conversion table, the position of the 13T mark can be known appropriately, and the running OPC can be easily performed.

  The present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of the optical disk apparatus according to the first embodiment. In FIG. 1, 1 is an optical disc such as an HD DVD-R / RW having an information recording layer, 2 is a spindle motor, 3 is an optical head (PU), 4 is an I / V conversion circuit (photodetector), 5 is Sample hold circuit, 51 A / D conversion circuit, 6 laser drive circuit, 8 RAM controller, 11 modulation circuit, 13 memory such as DRAM, 14 CPU, 111 flip-flop (FF), 112 code Word conversion circuits 1 and 113 are code word conversion circuits 2 and 114 are concatenation processing circuits that output a code word of # = 0, 115 is a DSV processing circuit, 116 is an NRZI conversion circuit, 120 is a 13T polarity control circuit, and 121 is synchronous It is a # selection table 121 for selecting # in the code.

As shown in FIG. 1, the optical disk apparatus is connected to a host computer (hereinafter referred to as “host 15”) such as a personal computer or a workstation. Commands and information data from the host 15 are input to the CPU 14, and under the control of the CPU 14, an information recording operation, a reproducing operation, and a seek operation for moving the optical head 3 to a target track are executed.
<Playback operation>
First, the reproduction operation of the optical disc apparatus will be described. The optical disk 1 is rotationally driven by a spindle motor 2. The semiconductor laser in the optical head 3 emits laser light for reproducing information. The optical system in the optical head 3 forms light emitted from the semiconductor laser as a light spot on the optical disk surface. Further, the photodetector in the optical head 3 converts the reflected light from the optical disk 1 into an electrical signal. Light spot control such as focus control and tracking control and information reproduction are performed using the converted electrical signal.
<Recording operation>
Next, the recording operation of the optical disc apparatus will be described in detail. First, a recording start instruction is input from the host 15 to the CPU 14. Next, the above-described reproduction operation is executed, and an electric signal based on the reflected light of the optical disk is output from the optical head 3. This electric signal is converted from current to voltage by the I / V conversion circuit 4 and input to a wobble processing circuit (not shown). The wobble processing circuit extracts a wobble signal corresponding to the wobble provided on the recording surface of the optical disc 1. Then, the binarized signal synchronized with the wobble signal is output to the NRZI conversion circuit 116 in the modulation circuit 11 as a recording clock. The wobble processing circuit also outputs a wobble signal to an address decoder (not shown). When the address decoder detects a recording target address on the optical disc, it outputs a gate signal indicating a recording position to a recording clock synchronization processing circuit (not shown) in the modulation circuit 11.

  The DRAM 13 stores data subjected to processing such as ID addition processing, scramble processing, and correction code addition processing. The RAM controller 8 outputs the data in the DRAM 13 to the modulation circuit 11 as a data word every 8 bits. The data word is input to the code word conversion circuit 1 (112) via the flip-flop 111. The codeword conversion circuit 1 (112) performs 8-12 modulation for converting the data word 8 bits (dat1) into the codeword 12 bits (mod1). The data word is input to the codeword conversion circuit 2 (113) without going through the flip-flop. The codeword conversion circuit 2 (113) also performs 8-12 modulation for converting the data word 8 bits (dat2) into the codeword 12 bits (mod2).

  Since the data word dat1 supplied to the codeword conversion circuit 1 (112) passes through the flip-flop 111, the data word dat2 supplied to the codeword conversion circuit 2 (113) is delayed by the flip-flop 111. Become. The relationship between the data word input (dat) and the code word output (mod) will be described with reference to FIG. For example, assume that data words input from the RAM controller 8 are Da, Db, Dc, Dd, De, Df, and Dg. At time 1, dat1 is Da and dat2 is Db. The code word conversion circuit 1 (112) converts the data word Da and outputs a code word Ca, and the code word conversion circuit 2 (113) converts the data word Db and outputs a code word Cb. That is, continuous code words Ca and Cb are output from the code word conversion circuit 1 (112) and the code word conversion circuit 2 (113).

  The concatenation processing circuit 114 performs processing for determining the bit connector * included in mod1. If the modulation circuit 11 shown in FIG. 1 is used, since the first bit of the code word Cb input as mod2 is fixed, the code word Ca input as mod1 includes a bit connector *. In addition, the connection processing circuit 114 can determine the Ca bit connector *. That is, if the first bit of the code word Cb is 0, the concatenated bit * of the Ca is set to 1, and if the first bit of the code word Cb is 1, the concatenated bit * of the Ca is set to 0. By performing the same processing after time 2, the concatenated bit * included in mod1 can be set appropriately.

  The 13T polarity control circuit 120 outputs a 2-byte synchronization code once per code word (91 bytes). This synchronization code is input to the concatenation processing circuit 114. As shown in FIG. 9 (time 7), at the timing when the synchronization code (SY) is input, the concatenated bit * included in mod1 is set using the synchronization code (SY) instead of mod2.

  The concatenation processing circuit 114 also performs processing (concatenation rule processing) for reducing “01” in the code word five times or less continuously based on a predetermined replacement rule.

The 12-bit code word subjected to DSV processing by the DSV processing circuit 115 is converted into NRZI by the NRZI conversion circuit 116 in accordance with the timing of the recording position detection signal supplied from the address decoder, and the laser driving circuit 6 together with the recording clock WCK. Is output. The laser drive circuit 6 supplies a drive current to the laser in the pickup 3. Digital data is recorded on the optical disk 1 by the laser light emitted from the laser. The laser drive circuit 6 may be provided in the pickup 3.
<R-OPC at 13T mark>
Next, the 13T polarity control in the synchronization code for executing R-OPC will be described with reference to FIG. As shown here, DC control (DC component suppression control) is performed for even-numbered synchronization frames, and 13T control (13T part polarity control) is performed for odd-numbered synchronization frames.

  The 13T polarity control circuit 120 switches between DC control and 13T control. In the case of 13T control, the synchronization code is determined and output to the DSV processing circuit 115. In the case of DC control, a synchronization code in which the DSV control bit # in the synchronization code is temporarily replaced with 0 is output to the DSV processing circuit 115. A method for determining the DSV control bit # of the synchronization code will be described later.

  As shown in Patent Document 4, the 13T portion whose polarity is a mark appears once in two synchronization frames. The 13T polarity control circuit 120 outputs the position information of the 13T portion of which the mark is a mark to the sample and hold circuit 5. The sample hold circuit outputs a laser control pulse (hold pulse) for laser light control to the laser drive circuit 6. In addition, the sample hold circuit outputs position information of the 13T unit for voltage value measurement to the A / D converter 51. The position information of the 13T portion is almost the same timing as the laser control pulse output when recording the 13T portion, but delay is taken into consideration. When the 13T portion is a mark, the output of the photodetector 4 for detecting the laser beam is measured by the A / D converter 51 and output to the CPU 14. The CPU 14 calculates based on the value obtained from the A / D converter 51 at this timing, and calculates appropriate laser power adjustment information. By controlling the laser power based on this power adjustment information, it is possible to realize R-OPC in which the 13T mark is recorded in an appropriate shape.

  In R-OPC, it is considered that the recording film sensitivity of the optical disc is not necessarily uniform in the plane. That is, when recording data with the optimum recording power determined by OPC, the return light amount (reproduction signal voltage) at the time of data recording is monitored, and the laser recording power is feedback-controlled so that this return light amount becomes a constant value. To do.

    Details of this control will be described with reference to FIG. 14A is an NRZI representing a 13T mark, FIG. 4B is a laser control pulse for controlling the laser drive current, FIG. 4C is a recording light power applied to the optical disc 1, and FIG. ) Is a recording mark formed on the information recording layer of the optical disc 1, and FIG. 4E shows a reproduced signal waveform of the recording mark from the photodetector 4. A broken line indicates when the recording light power of the laser is large. The solid line indicates when the recording light power of the laser is small. (E) The amplitude value of the reproduction signal varies depending on the recording light power. When a long mark such as a 13T mark is recorded on the disk, the laser controls the laser control pulse to record a mark having an appropriate length on the disk.

The reproduction signal (FIG. 4 (e)) voltage at the 13T recording mark position is detected by the A / D converter 51, and taken into the CPU 14, and the parameters (pulse width, power, etc.) relating to the laser are calculated. The laser light is controlled by the laser control pulse (b) so that the desired recording light power (c) is obtained. The voltage value obtained by the A / D converter 51 is calculated by the CPU by calculating the timing of the laser control pulse, the pulse width, the laser power, etc. so that the optimum mark can be recorded by the CPU, and the adjustment information is supplied to the laser drive circuit. 6 is output. When adjusting the pulse width of the laser control pulse, adjustment information is output to the sample hold circuit 5.
<8-12 modulation processing and synchronization code 13T polarity control>
The 8-12 modulation processing and 13T polarity control performed in the modulation circuit 11 will be described in more detail using the flowchart of FIG.

  When the modulation is started (400), the State state information is initialized to 2 and the DSV value is initialized to 0 (401). Next, it is determined whether or not it is a synchronization code position (402).

  As shown in FIG. 16, the code word corresponding to the data word includes * and #. The 13T polarity control circuit 120 outputs a code word in which * and # are temporarily set to 0 and Next State (403). In addition, a code word in which the bit connector * and the DSV control bit # are temporarily set to 0 and the Next State are output (403). The bit connector * and the DSV control bit # temporarily set to “0” in 403 are fixed to “1” or “0” in processing 405, 406, and 410 described later.

  Next, processing of concatenated bits * 404, 405, and 406 is performed in the concatenation processing circuit 114. If there is a concatenated bit *, the immediately preceding code word head bit is identified (404). If the immediately following code word leading bit is 1, the concatenated bit * is fixed to 0 (405), and the immediately following code word If the first bit is 0, the concatenated bit * is determined to be 1 (406).

  Next, connection rule processings 407 and 408 are performed in the connection processing circuit 114. First, it is checked whether a pattern prohibited by the concatenation rule such as “1010101010101” is generated as a result of the concatenation bit processing (407). If a prohibited pattern is included, the code word is replaced according to a predetermined rule (408).

  Next, DSV processing of 409 and 410 is performed in the DSV processing circuit 115. First, it is determined whether the DSV control bit # is present in the code word (409). When the DSV control bit # is present, the DSV value when # = 1 is compared with the DSV value when # = 0. Then, the DSV control bit # having a smaller DSV value is selected to determine the DSV control bit # (410). Then, the DSV value of the confirmed code word is added to the previous DSV value (419).

  If the determination at 402 is the synchronization code position, the synchronization code and Next State are output (412). At this time, the DSV control bit # included in the synchronization code is temporarily set to 0 and the synchronization code is output. Note that the DSV control bit # provisionally set to “0” in 412 is fixed to “1” or “0” in processing 410 described later.

  Thereafter, the concatenation processing circuit 114 performs concatenation processing of synchronization codes 414, 415, and 416. First, it is determined whether the tail pattern of the code word immediately before the synchronization code SY3 matches 000000 # (hereinafter referred to as “S pattern”). If it matches the S pattern, connection rule S pattern processing is performed to change # to 1 (415). If it does not match the S pattern, the synchronization code (any one of SY0, SY1, SY2, SY3) is output as it is (416). Thereafter, it is determined whether or not the 13T polarity processing is performed (417).

  When the 13T polarity process is not performed, the DSV process (409, 410) is performed. When R-OPC is not executed, the 13T polarity control process is not performed.

  When performing 13T polarity processing, if the synchronization frame number is an odd number (411), if the previous 13T is a mark, the DSV control bit # is set so that the next 13T becomes a space, and the previous 13T is a space. Is set with a DSV control bit # such that the next 13T becomes a mark (418). Thereafter, the determined codeword DSV value is added to the previous DSV value (419).

Then, it is determined whether or not the end of the modulation data has been reached (420). When the end of the modulation data has been reached, the modulation process is terminated (421), and if not, the next data is modulated (402 to 410, 412). 420).
<Detailed description of modulation circuit>
Next, the internal configuration of the modulation circuit 11, in particular, the 13T polarity control circuit 120 will be described in detail with reference to FIG. First, the codeword conversion circuit 1 (112) converts an 8-bit data word (Dat1) into a 12-bit codeword (mod1), and outputs Next State state information using a modulation table. The modulation table is configured as shown in FIG. 16, and one Next State state information can be selected from among three types of Next State state information of State 0, State 1, and State 2 based on the data word and the current State state information. it can. Reference numeral 119 denotes a switch (SW) for switching between a synchronization code and a modulated code word. The DSV processing circuit 115 includes a DSV calculator 1152 for performing DSV calculation. The DSV processing circuit 115 performs NRZI conversion on the concatenated concatenated codeword (codeword) and performs DSV calculation.
<DSV control>
FIG. 12 shows the NRZI conversion method and the DSV calculation method. Here, a 12-bit code word is represented by CW [11: 0], and a 12-bit code word is represented by NRZI [11: 0]. The NRZI value at time 0 is NRZI [0] (LSB: 0th bit). In this example, the initial value of NRZI is set to zero. When the 11th bit (CW [11]), which is the MSB (Most Significant Bit) of the current codeword, is 1, an exclusive OR of NRZI [0] and CW [11] = 1 is obtained as NRZI [1]. Output. On the other hand, if the current code word CW [11] is 0, the value of NRZI [0] is output as it is as NRZI [1]. The NRZI of the current codeword can be obtained by repeating this in order up to CSB [0], which is the LSB. By performing this processing, it is possible to know that the polarity of the code word starts, for example, if NRZI [0] is 1, it is a mark, and if 0, it is a space. Note that the same processing can be performed for the next codeword by setting NRZI [12] to a new NRZI [0].

  Next, a DSV calculation method will be described. Basically, if the value of NRZI is 1, 1 is added to the previous DSV value, and if the value of NRZI is 0, -1 is added to the previous DSV value. A specific calculation method will be described by taking the case where the code word CW [11: 0] is 100100_000010 as an example. First, DSV calculation example 1 (when the DSV value of Time 0 is 0) will be described. Since NRZI [1] is 1 for the DSV value at time 1, +1 is added to the previous DSV value 0. By performing this calculation in order, 6 can be obtained as the DSV in the LSB. DSV calculation example 2 (when the DSV value at Time 0 is 10) is calculated in the same manner, whereby 16 can be obtained as the DSV in the LSB.

    The DSV processing circuit 115 determines the DSV control bit # to 1 or 0. When the DSV control bit # is fixed to 1, position information indicating the position of # (for example, position information 0000_0000_0001 indicating that # = 1 is in the LSB) is output to the OR circuit 118. The SW 119 switches a synchronization code or a connected code word in accordance with a counter value of a counter 123 described later.

The OR circuit 118 ORs the # = 0 code word or synchronization code that is the output of the concatenation processing circuit 114 and the position information of # = 1, thereby determining the bit concatenation * and the DSV control bit #. Output a word. For example, the OR output of the code word 0100_0010_0000 and the position information 0000_0000_0001 is converted from 0 to 1 in the LSB and becomes 0100_0010_0001.
<Code word and synchronous code switching counter>
The counter 123 includes a byte counter that counts the number of 1 byte of data words and a synchronization frame counter that counts synchronization frames. Since there are 26 sync frames in one sector, the sync frame counter counts 0-25.

FIG. 18 shows an HD DVD physical sector. A 2-byte synchronization code (SY0 to SY3) and 91-byte data (RD) are called a synchronization frame. One physical sector is composed of 26 synchronization frames. FIG. 5 shows counter values of the data portion and the synchronization portion. As shown here, from the frame counter value and the byte counter value, it is possible to know what frame the current position is, whether it is a synchronization part, a data part, or what byte. That is, when the byte counter is 1-2, it can be known that it is a synchronization code, and when it is 3-93, it is a data portion. Therefore, by controlling the switch (SW) 119 based on the byte counter value, the synchronization code and the modulated code word can be switched and output.
<Synchronous code 13T polarity control>
The 13T polarity control circuit 120 includes a synchronization code selection table 124. This table is a table in which the DSV control bit # in each synchronization code shown in FIG. 4 (1) is set to 0, and has a code as shown in FIG. 4 (2).

The 13T polarity control circuit 120 also includes a # selection table 121 for performing 13T mark space control of the synchronization code. The # selection table 121 is a table for selecting the DSV control bit # value of the synchronization code from 0 or 1 during 13T polarity control, and the following input is required.
(A) Synchronization code information (any of SY0, SY1, SY2, and SY3)
(B) Next State status information of 93rd byte data (c) Mark space information of 13T part of immediately preceding synchronization frame (d) Mark space polarity information of synchronization code start (c) Note that (c) is a synchronization frame for performing 13T polarity control 13T mark space information at the time of DC control performed on the previous synchronization frame is shown. Further, (d) is mark space polarity information at the end position (93rd byte) of the frame.
<Synchronous code 13T polarity control flowchart>
FIG. 19 shows a flowchart of a method for determining # in the synchronization code. Details of 418 in <synchronization code 13T polarity control> and <DC control> 410 shown in FIG. 3 are shown.

  First, it is set whether to perform R-OPC (417). Whether or not R-OPC is executed is performed from the host 15 via the CPU 14. If No, DC control is performed. If Yes, it is determined whether the frame counter value is even or odd (411). If the frame counter value is an even number, DC control of 409 and 410 is performed. If the frame counter value is an odd number, 13T polarity control is performed (418).

Also, (a) synchronization code information (SY0 to SY3) is output from the frame counter value (1907).
<DC control>
If the byte counter value is 93, the next byte is the sync code position. Next state information on the 93rd byte is obtained (1901). Synchronization code information is selected from the 93rd byte Next State state information (1901) and (a) synchronization code number output (1907).

When the byte counter value is 1 (corresponding to the forward synchronization code position), the value of the DSV control bit # is determined so that the DSV value becomes small, and the synchronization code is determined (1902). At the same time, (c) polarity information indicating whether the 13T portion in the synchronization code is a mark space is obtained (1906). This value is stored in the register until 13T polarity control.
<13T polarity control>
When R-OPC is executed (417), if the frame counter value is an odd number (411), 13T polarity control (418) is performed.

  When 13T polarity control is performed, when the byte counter value is 93 (1904), Next State state information and (d) polarity information at the beginning of the synchronization code are obtained (1905).

  Using (a) to (d) stored in the register as an input, using the 13T polarity # selection table (1909), when the forward sync code part (byte counter value is 1), # is determined and the sync code # Can be confirmed (1908).

  Next, FIG. 7 shows the sync frame number, sync code # control method, and 13T portion recording mark position. At the time of DC control, # is selected so that the DSV up to the DSV control bit # of the synchronization code of the even frame is small, and the mark (M) or space (S) of the 13T portion is determined. In the next synchronous claim, # is set by 13T polarity control so that a space is formed if the front 13T portion is a mark, and a mark is formed if the front 13T portion is a space.

Examples of the recording mark position of the synchronous code 13T portion are shown in (1), (2) and (3) of FIG. As shown in the drawing, a 13T mark appears in either the even-numbered synchronization frame or the odd-numbered synchronization frame.
<Synchronization code 13T polarity mark position information>
When the code word CW shown in FIG. 12 is a forward synchronization code, the NRZI [12] value (LSB) indicates the position of the 13T part of the synchronization code. The position of the 13T portion is also shown in FIG. If the NRZI [12] value is 1, the synchronization code 13T part is a mark. By knowing this information, it is possible to output the position information of the mark having the synchronization code 13T polarity to the sample and hold circuit. The forward synchronization code position can be known from the byte counter value.
<13T polarity control synchronization code # selection table>
FIG. 8 shows a 13T control # selection table for realizing 13T polarity control.

  FIG. 8A shows the # selection value in state 0 and the # selection value in states 1 and 2. FIG. 8A will be described. For example, if (a) the synchronization code SY0, (b) State0, (c) the previous 13T part is a mark, the 13T part in 13T polarity control needs to be a space. (D) If the start of the synchronization code is a space, the 13T part is set as a space by setting # to 0. Similarly, the value of # can be determined for the inputs (a) to (d).

FIG. 8 (2) is a table of the contents of (1) and is a # selection table (excerpt). The first line will be described as an example. If (a) the synchronization code is SY0, (b) the State state information is 0, (c) the previous 13T polarity information is a mark, and (d) the polarity information at the beginning of the synchronization code is a space, then # = 0 It shows that 13T can be a space. By using this 13T polarity control table, it is possible to realize the 13T polarity control of the synchronization code under an arbitrary condition.
<Switching between DC control and 13T polarity control>
Next, output switching between DC control and 13T polarity control will be described. The output switching here is switching of an input signal from the 13T polarity control circuit 120 to the DSV processing circuit 115.

  In either control method, the synchronization code and the # position are input from the 13T polarity control circuit 120 to the DSV processing circuit 115.

  At the time of DC control, a synchronization code in which # of the synchronization code corresponding to the value of the sync frame counter is 0 and # position information indicating the # position are output. Since the backward synchronization code has a fixed value as shown in FIG. 4, the forward synchronization code will be described. For example, the forward synchronization code (1000 # 0_010000) of the synchronization code SY0 of State0 is set to 0 (100000_010000). Also, (000010_000000) is output as # position information. The DSV processing circuit 115 calculates the DSV of # = 1 and the DSV of # = 0, and obtains # where the DSV is small. When # at which the DSV becomes small is 1, the # position information and the synchronization code obtained by converting # into 0 can be processed by the OR circuit 118, and a synchronization code with 1 in # can be obtained. When # at which DSV becomes small is 0, the # position information (000000_000000) and the synchronization code obtained by converting # to 0 are processed by the OR circuit 118 to obtain a synchronization code in which 0 is entered in #. it can.

  At the time of 13T polarity control, since # is determined based on the above-described # selection table 121, there is no undefined # in the synchronization code. For this reason, the 13T polarity control circuit outputs #position information = 0 indicating that # does not exist in the code word. For example, when # = 1 is selected by the # selection table 121, the forward synchronization code (1000 # 0_010000) of the synchronization code SY0 of State0 is set to 1 (100010_010000). On the other hand, when # = 0 is selected by the # selection table, (1000 # 0_010000) in which # is set to 0 is output (100000_010000). The # position information (000000_000000) and the synchronization code obtained by 13T polarity control are processed by the OR circuit 118, and the synchronization code obtained by 13T polarity control can be output to the NRZI conversion circuit 116.

  As described above, by using the 13T polarity # selection table, it is possible to switch between the 13T polarity control and the DC control of the synchronization code, and to realize R-OPC while suppressing the DSV fluctuation.

  In the method according to the first embodiment in which the code word is converted into NRZI and the DSV calculation is performed, the delay time increases because of the large number of additions and the circuit scale. As shown in the first embodiment, in order to perform normal processing, it is necessary to satisfy the relationship of (Equation 1). For example, when a master clock of 90 MHz is used, in the case of 10 times speed, within one cycle of the master clock It is necessary to finish the modulation. However, in a configuration with many additions as in the configuration of the first embodiment, it is difficult to design a circuit that satisfies (Equation 1).

  The DSV calculation range is probabilistically within ± 4095 when using 13T polarity control, and is described in the HD DVD standard. If the number of bits to be added is set within this range, 2 12 is required. When obtaining the DSV value of one codeword, since there are 12 bits for one codeword, it is necessary to add 12 bits 12 times. If the master clock is made faster, there is room for the delay time. However, if the master clock is raised, the power consumption increases, so the master clock cannot be speeded up easily.

Therefore, in the second embodiment, the DSV value of # = 0 and the DSV value of # = 1 are stored in the table in advance, and the DSV calculation up to the previous code word is performed without performing the DSV value of 1 code word 12 bits. And the DSV value correction associated with the concatenation rule are added only twice so that high-speed recording can be handled without raising the master clock. Further, the second embodiment has a configuration in which the circuit scale is reduced and the delay is reduced in addition to the effects of the first embodiment.
<Configuration of Example 2>
The configuration of Example 2 is shown in FIG. The 13T polarity control circuit 120 determines whether the # selection table 121 described in the first embodiment, the synchronization code selection table 124, the synchronization code DSV table 122, and the number of 1s in the synchronization code are odd numbers. It has odd / even even number, # position information table 125, 13T polarity control and DC control switching circuit 126.

  The synchronization code DSV table 122 has two types of DSV tables 1221 and 1222. Reference numeral 1221 denotes a DSV value storage table of 1 code word 12 bits. 1222 is a DSV value storage table from MSB to ## when there is # in one codeword.

Since a DSV calculation of one synchronization code is performed in advance, addition (12-bit addition 12 times) can be reduced.
<Multiple synchronization code tables>
FIG. 17A shows the synchronization code DSV table 1221 at state 0. FIG. 1221 has # = 1 o'clock DSV value, # = 0 o'clock DSV value, and # position. According to the DSV calculation method shown in FIG. 12, 0 (space) is given to NRZI [0] as an initial value. 1 (mark) may be given as an initial value. In addition to this, there are also tables of state 1 and 2, but the description is omitted because they have the same format. FIG. 17B shows a synchronization code DSV table 1222 at state 0. In addition, it also has tables of state 1 and 2. A synchronization code DSV table 1222 is different from 1221 and has a table indicating DSV values from MSB to #. In addition to this, there are also tables of state 1 and 2, but the description is omitted because they have the same format. FIG. 17C shows the number information of 1 and the # position information table (in the case of State 0) for the synchronization code.

The plurality of synchronous code table outputs are used by the DSV processing circuit 115.
<DSV processing circuit, mark space control circuit>
As in the first embodiment, the DSV processing circuit 115 is a circuit that calculates the DSV value when # = 0 and # = 1 and selects the one with the smaller DSV.

  The mark space control circuit 1141 calculates the next codeword from the 1-number odd / even information in the code of the codeword conversion circuit 1 output and the 1-number odd / even information in the synchronization code of the 13T polarity control circuit 120 output. This is a circuit for determining the leading mark space polarity.

  As shown in FIG. 13, the NRZI mark space polarity at the end of the code word is determined by the NRZI mark space polarity at the beginning of the code word and the number of 1 in the code word (odd / even information). The NRZI mark space polarity at the end of the code word indicates the mark space polarity of the NRZI at the beginning of the next code word. FIG. 13 shows two examples of codewords 00010_000010 (2 in the codeword: even number: even) and 000000_010000 (1 in the codeword: odd number). When there are two 1s (even numbers) in the codeword, if the space starts, the next code starts is a space, and the DSV value is +2. On the other hand, when the mark starts, the next code start is a mark and the DSV value is −2. Thus, the polarity of the next code can be known by knowing the number information of 1 in the code, the current mark, and the beginning of the space. Further, addition and subtraction in DSV calculation can be controlled.

  In the DSV calculation, the mark space polarity at the beginning of the code word is used to control the addition or subtraction of the DSV value of the current code word. DSV values at the beginning of a space are stored in the DSV tables 1221 and 1222. Therefore, when the mark space polarity at the beginning of the code word is a space, the DSV value of the code word is added, and when it is a mark, the DSV value of the code word is subtracted.

When # = 1 is selected in the DSV processing circuit 115, the mark space control circuit 1141 sets the odd / even information value (odd number) indicating whether the number of “1” in the synchronization code is odd or even. Invert 1 if 0 and 0 if even. When # = 0 is selected, the odd / even information value is used without being inverted. Similarly, when 01 is converted into 00 according to the code word connection rule, if the number of 1 converted before and after the application of the connection rule is an odd number, a process of inverting the value of odd / even information is performed (not shown). )
<Synchronization code 13T polarity mark position information>
The byte counter knows the position of the front synchronization code, and the mark space control circuit outputs the polarity information of the head of the next rear synchronization code at that position. With this polarity information, the position information of the 13T polarity mark can be output to the sample and hold circuit. If the output of the mark space control circuit is 1, it is possible to know the start of the mark, and if it is 0, the start of the space can be known.
<Input from 13T polarity control circuit to DSV processing circuit>
Next, input from the 13T polarity control circuit 120 to the DSV processing circuit 115 will be described.

As shown in FIG. 11, an input signal from the 13T polarity control circuit to the DSV processing circuit is output from the 13T polarity control circuit to the DSV processing circuit from the synchronization code, # position information, and a plurality of DSV values. Further, since the output is different between the DC control and the 13T polarity control, the output is switched by the 13T / DC control switching unit 126.
<13T polarity control and DC control switching>
First, in the case of DC control, the DSV value of the synchronization code corresponding to the value of the sync frame counter is output. The values of the synchronization code DSV table indicated by 1221 in FIG. 10 and the DSV table up to the synchronization code # indicated by 1222 are output to the DSV processing circuit 115. The DSV processing circuit 115 compares the DSV values up to the previous code word with the DSV values of # = 1 and # = 0 using the DSV table 1222 up to the synchronization code #, and selects # with the smaller DSV value. After # selection, when the value shown in the synchronization code DSV table 1221 is changed to the DSV value up to the previous code word by the DSV calculator 1151, and the mark space information output from the mark space control circuit 1141 is a space. , And when the mark space information is a mark, an arithmetic process is performed to subtract. In this way, in the DC processing, since the DSV value described in the DSV table is used without calculating one synchronization code 12 bits, the DSV calculation processing for one code word can be eliminated. Also, the circuit scale is reduced.

  On the other hand, at the time of 13T polarity control, the value shown in the synchronization code DSV table shown in FIG. Since # is determined based on the above-described # selection table 121, a DSV value corresponding to the determined # value is output. When # is fixed to 1, the value of odd / even information is inverted and output. When # is fixed to 0, odd / even information indicating whether the number of 1s in one codeword when # is replaced with 0 is an even number or an odd number is output.

When the sync frame counter value is an even number, DC control is performed, and when the value is an odd number, 13T polarity control is performed. Further, in accordance with an instruction from the CPU 14, when the 13T polarity control is not used and the R-OPC is not used, only the DC control may be selected. Since the DC control is always performed with the synchronization code as compared with the case where the 13T polarity control is performed, the maximum value of the DSV fluctuation is stochastically reduced to ± 2047. (Described in HD DVD specifications)
In this way, since the DSV table of the synchronization code is created in advance, twelve addition processes using NRZI can be eliminated. Therefore, when the master clock is the same (the master clock is not accelerated), the first embodiment is used. Since the number of operations is smaller than the DSV processing by NRZI shown, high-speed processing is possible, so that high-speed recording can be supported.

  As described above, a specific method for causing a mark to appear in the 13T portion once every two consecutive sync frames has been shown.

  Also, a specific method for detecting which one of the 13T portions of the synchronization code of two consecutive sync frames is a mark and outputting the 13T mark position to the sample hold circuit is shown. By switching between 13T polarity control and DC control using the DSV selection table and 13T polarity control # selection table in this way, running OPC is possible during high-speed recording without increasing the master clock speed. In addition to the effects obtained in the first embodiment, the circuit scale is reduced and the delay is reduced.

Schematic which shows a 1st Example. The figure which shows the 2nd Example of the 8-12 modulation circuit and 13T polarity control circuit of this invention. The figure which shows the flowchart of 8-12 modulation processing. The figure which shows a synchronous code and a synchronous code order. The figure which shows a frame counter, a byte counter, and 13T polarity control processing. The figure which shows the # control method in a synchronous code. The figure which shows a synchronous frame number, a synchronous code # control method, and a 13T part recording mark position. The figure which shows a 13T polarity control table. The figure which shows a data word and a code word. The figure which shows the 3rd Example of the 8-12 modulation circuit and 13T polarity control circuit of this invention. The figure which shows the output from a 13T polarity control circuit to a DSV processing circuit. The figure which shows the conversion processing method from codeword to NRZI. The figure which shows the number of 1 in a code word, and a NRZI waveform. The figure which shows a recording mark and reflected light. The figure which shows the relationship between the recording clock of HD DVD, and a master clock. The figure which shows an 8-12 modulation | alteration encoding table (extract). The figure which shows the DSV table of a synchronous code. The figure which shows a physical sector. The figure which shows the flowchart of the synchronous code # determination method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Optical disk, 2 ... Spindle motor, 3 ... Optical head (PU), 4 ... I / V conversion circuit (light detector), 5 ... Sample hold circuit, 51 ... A / D conversion circuit, 6 ... Laser drive circuit, DESCRIPTION OF SYMBOLS 8 ... RAM controller, 11 ... Modulation circuit, 12 ... RAM controller interface (RAMCON I / F), 13 ... DRAM, 14 ... CPU, 15 ... Host, 111 ... Flip-flop (FF), 111 is flip-flop (FF), DESCRIPTION OF SYMBOLS 112 ... Code word (code word) conversion circuit 1, 113 ... Code word (code word) conversion circuit 2, 114 ... Connection processing circuit, 115 ... DSV processing circuit, 116 ... NRZI conversion circuit, 1141 ... Mark space control circuit, 118 ... OR circuit, 119... Synchronous code changeover switch, 120... 13T polarity control circuit, 121. Bull, 122 ... sync DSV selection table 123 ... counter.

Claims (11)

A code word obtained by modulating an input data word of 2n bits (n is a positive integer) into 3n bits, a 13T part not included in the code word, and a DSV control bit # for controlling a DSV (Digital Sum Value) value An optical disk device for recording data on an optical disk in a synchronization frame unit composed of a synchronization code including
A spindle motor for rotating the optical disc;
A laser for irradiating the optical disc with laser light;
A laser driving circuit for supplying a driving current to the laser;
When the DSV control bit # included in the synchronization code of the odd-numbered synchronization frame is set, the mark space polarity of the 13T portion included in the synchronization code of the preceding even-numbered synchronization frame and the synchronization code of the odd-numbered synchronization frame are set. A 13T polarity control circuit that selects a DSV control bit # that changes the mark space polarity of the included 13T portion and outputs 13T mark position information indicating the position at which the polarity of the 13T portion becomes a mark;
A modulation circuit including the 13T polarity control circuit and a code error conversion circuit that modulates a data word into a code word;
An optical disc apparatus comprising: The optical disc apparatus according to claim 1, further comprising:
A photodetector for converting return light from the optical disc into an electrical signal;
An A / D converter that converts an electrical signal from the photodetector into a digital value;
A sample hold circuit for outputting a laser control pulse to the laser driving circuit, delay-adjusting the 13T mark position information, and outputting it to the A / D converter;
A CPU for controlling the laser drive circuit so that a laser drive current becomes an optimum value based on a voltage value observed by the A / D converter according to the 13T mark position information;
An optical disc apparatus comprising: The optical disk apparatus according to claim 2, wherein
The optical disk apparatus, wherein the CPU controls a laser driving pulse of the sample and hold circuit based on a digital value which is an output of the A / D converter. The optical disc apparatus according to claim 1, further comprising:
A synchronization frame counter for counting the synchronization frames;
The optical disk apparatus according to claim 13, wherein the 13T polarity control circuit selects a DSV control bit # that decreases DSV when setting a DSV control bit # included in a synchronization code of an even-numbered synchronization frame. A state in which a 2n-bit (n is a positive integer) data word is modulated into a 3n-bit code word including a DSV control bit for controlling a DSV (Digital Sum Value) value, and indicated by the current data word and the previous data word An optical disk apparatus using a modulation method that records a data on an optical disk by determining a DSV control bit after provisionally determining a code word by information, inserting the synchronization code once for each synchronization frame,
A synchronization polarity control circuit for outputting position information of the mark of the synchronization polarity part;
A photodetector for converting return light from the optical disc into an electrical signal;
During the period of position information of the sync polarity mark output from the sync polarity control circuit, the electric signal obtained by the photodetector is held in a period in which the intensity level is greater than a certain value in synchronization with the intensity timing of the laser beam. A sample and hold circuit for performing a sample in a period other than that, or holding in a period in which the intensity level is smaller than a certain value and performing a sample in a period other than that,
An A / D converter that converts the electrical signal obtained by the sample and hold circuit into a digital value;
An arithmetic circuit for optimally adjusting laser power and the like from the digital value obtained by the A / D converter;
A laser drive circuit controlled based on laser power adjustment information obtained from the arithmetic circuit and an output of the codeword conversion circuit;
A sync frame counter for counting sync frames;
The even sync frame has a DSV processing circuit that controls the mark and space so that the DSV value is minimized, and selects the DSV control bit.
The synchronization polarity control circuit selects a mark and space different from the synchronization polarity part of the previous even frame in the odd synchronization frame, and the synchronization polarity part becomes a mark in at least one of the even synchronization frame and the odd synchronization frame. An optical disc apparatus characterized by performing polarity control. In claim 5,
A code word conversion circuit that modulates the input data word in accordance with the modulation method and outputs a code word in which the DSV control bit is replaced with 0;
The codeword conversion circuit includes a codeword corresponding to a data word and an encoding table that records state information indicating the next state;
A byte counter that counts the number of codewords in a synchronization frame;
The DSV processing circuit is
A DSV operation unit for comparing the DSV value when the DSV control bit is 0 with the DSV value when the DSV control bit is 1, and selecting the DSV control bit of the smaller DSV value;
A mark space detection circuit that indicates whether the synchronization code, or codeword, starts with a mark or starts with a space;
The synchronous polarity control circuit is
A synchronization code selection table indicating which one of a plurality of synchronization codes is selected from the state information output from the encoding table and the decoded value of the synchronization frame counter;
The synchronization code selection table includes a synchronization code in which the DSV control bit part is set to 0,
A synchronization code with the DSV control bit part set to 1,
Synchronization polarity part information of the even synchronization frame obtained from the mark space detection circuit;
The timing obtained from the decode values of the mark space detection circuit, the synchronization frame counter and the byte counter, and the polarity information indicating whether the start of the synchronization code of the odd synchronization frame is the mark or the space obtained from the code word immediately before the synchronization code ,
From the synchronization code obtained from the synchronization code selection table,
The synchronization code obtained from the synchronization code selection table has a synchronization polarity selection table for deciding whether to mark or space the synchronization polarity part information in an odd frame,
An optical disc apparatus, wherein a DSV control bit of a synchronization code of an odd frame is selected to be 1 or 0 by the synchronization polarity selection table. In claim 6,
Perform sync polarity control to select DSV control bit using sync polarity selection table in odd sync frame,
In the even synchronization frame, a first DSV control bit selection method capable of performing DSV control for selecting a DSV control bit so that the DSV becomes small in the calculation result of the DSV processing circuit;
A selection switch capable of switching between a second DSV control bit selection method capable of performing DSV control for selecting a DSV control bit so that the DSV becomes small in the calculation result of the DSV processing circuit in all synchronization frames. An optical disc apparatus comprising: In claim 7,
A flip-flop that performs a delay process on the input data word;
A first modulation circuit for performing a modulation process on a data word supplied via a flip-flop and outputting a first code word;
A second modulation circuit that performs a modulation process on a data word supplied without going through a flip-flop and outputs a second code word;
When the DSV control bit is 1, the DSV processing circuit outputs DSV control position data indicating in which position of the codeword the DSV control bit is present;
A synchronization code-concatenated codeword switching switch for switching the synchronization code output from the synchronization processing circuit and the concatenated codeword of the concatenation processing circuit according to the decode value of the byte counter;
An optical disk apparatus characterized by ORing the DSV control position data and the output of the changeover switch and outputting a code word determined by DSV control. In claim 8,
The synchronous polarity control circuit is
In the DSV control, position data indicating whether the DSV control bit of the synchronization code exists is output to the DSV processing circuit,
In the synchronization polarity control, 0 is output to the DSV processing circuit as position data indicating that there is no DSV control bit of the synchronization code,
In the DSV control, the synchronization code selected from the synchronization selection table and having the DSV control bit replaced with 0 is output to the synchronization code-concatenated codeword changeover switch.
In the synchronization polarity control, according to the synchronization polarity selection table,
When the DSV control bit 1 is selected, the synchronization code selected from the synchronization selection table and having the DSV control bit replaced with 1 is output to the synchronization code-concatenated codeword changeover switch.
When the DSV control bit 0 is selected, the synchronization code selected from the synchronization selection table and having the DSV control bit replaced with 0 is output to the synchronization code-concatenated codeword changeover switch.
An optical disk apparatus characterized by ORing the DSV control position data and the output of the synchronous code-concatenated codeword changeover switch and outputting a code word determined by synchronous polarity control or DSV control. In claim 9,
The synchronous polarity control circuit is
The DSV value of the first synchronization code when the DSV control bit is 0;
A DSV value of the second synchronization code when the DSV control bit is 1, and a third DSV value from the MSB to the DSV control bit of the synchronization code when the DSV control bit is 0;
An optical disc apparatus having a DSV table having a fourth DSV value from an MSB of a synchronization code to a DSV control bit when the DSV control bit is 1. In claim 9,
The synchronous polarity control circuit is
In the synchronization polarity control, according to the synchronization polarity selection table,
When the DSV control bit 1 is selected, instead of the first DSV value from the DSV table, the DSV value of the second synchronization code when the DSV control bit is 1 is output to the DSV processing circuit,
When the DSV control bit 0 is selected, instead of the second DSV value from the DSV table, the DSV value of the first synchronization code when the DSV control bit is 0 is output to the DSV processing circuit,
In the DSV control,
An optical disc apparatus that outputs first to fourth DSV values to the DSV processing circuit.

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