JP2008199827A - Battery pack - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a battery pack capable of executing highly accurate charging/discharging control even when five or more secondary battery cells are connected in series, and reducing power consumption of a circuit. <P>SOLUTION: The battery pack has a combined battery group 1 in which combined batteries 1-1, 1-2 consisting of battery cells BAT1-BAT4 and BAT5-BAT8 are connected in series; and a power supply terminal unit and a signal terminal unit 2 to be detachably attached on a charger or a load body. The battery pack is provided with a power supply activating circuit 8 and power supplying circuits 9-1, 9-2 to be activated based on an activation signal to be supplied from the charger or the load body when the charger or the load body is attached, and the power activation circuit 8 and the power supply circuits 9-1, 9-2 are activated, thereby battery voltage is supplied from each of the combined batteries 1-1, 1-2 to each of charging control signal conversion circuits 4-1, 4-2, a charging control signal logical OR circuit 6, discharging control signal conversion circuits 5-1, 5-2 and a discharging control signal logical OR circuit 7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a battery pack for a secondary battery used in an electronic device.

  In recent years, in consideration of portability and workability, a battery pack of a secondary battery is mounted on the power source of the electric tool. As the secondary battery, a nickel cadmium battery or a nickel metal hydride battery has been generally used, but recently, a lithium ion battery having a high energy density has attracted attention from the viewpoint of weight reduction. However, since this lithium ion battery is vulnerable to overcharge and overdischarge, a protection IC that monitors each cell voltage is provided from the viewpoint of reliability and safety, and charge / discharge control by the cell voltage is generally performed. .

By the way, in an electric tool, there exists a use used by making a battery pack voltage high for high output, and what connected the secondary battery 5 cells or more in series is needed. However, as the protection IC for monitoring each cell voltage, one corresponding to a series of four cells is generally used, and one corresponding to a series of five cells or more is hardly commercialized. Therefore, in a battery pack in which five or more secondary batteries are connected in series, as disclosed in Patent Document 1, for example, a protection IC that supports up to four cells is connected in multiple stages. In this conventional example, each cell voltage is analog-output from the protection IC, the voltage level difference between the protection ICs is level-converted by an operational amplifier, and the voltage reference is made uniform, and then input to the control microcomputer for charge / discharge control. I am doing so.
JP 2003-111294 A

  However, the conventional example has a problem that the circuit becomes complicated and the circuit current consumption increases. Further, since the cell voltage is input to the microcomputer after conversion, there is a problem that the voltage detection accuracy is deteriorated.

  The present invention has been made in view of the above points, and it is possible to perform charge / discharge control with high accuracy even when five or more secondary batteries are connected in series, and to reduce circuit current consumption. An object of the present invention is to provide a battery pack that can be used.

  In order to achieve the above object, the invention of claim 1 is detachably attached to an assembled battery group in which an assembled battery comprising a plurality of secondary batteries connected in series is connected in series and a charger or a load body. A battery pack having a terminal portion electrically connected to the charger or the load body, wherein the voltage value of at least one secondary battery connected to each assembled battery is a first predetermined value. When higher, a plurality of charge control voltage detection circuits that output a charge control signal that instructs the charger to control charging of the assembled battery group, and a charge control signal that is connected to each of the charge control voltage detection circuits, respectively, A plurality of charge control signal conversion circuits that convert and output signals, and the logical sum of the outputs of each charge control signal conversion circuit and the voltage of the activation signal applied from the charger via the terminal when the charger is mounted Signal converted according to logical sum Charge control signal logical sum circuit that outputs to the charger, a power supply start circuit that is started by the start signal, and each charge control signal conversion circuit and charge control signal logic that are connected to the power supply start circuit and start the power start circuit And a plurality of first power supply circuits for supplying the voltage of each assembled battery to the sum circuit.

  According to a second aspect of the present invention, in the first aspect of the present invention, the charge control signal is an active high of an open drain output or a C-MOS output, and each charge control signal conversion circuit has a charge control signal applied to the gate. The open drain output P-channel MOS transistor or the open collector output PNP transistor to which the charge control signal is applied to the base is provided, and the voltage of each assembled battery is output when the charge control signal is active high.

  The invention of claim 3 is the invention of claim 1 or 2, further comprising a charge control signal delay circuit provided between the charge control signal logical sum circuit and the terminal portion for delaying the input signal, the charge control signal delay The circuit is operated by the start signal supplied via the terminal when the charger is mounted, and the detection delay time for detecting the charge control signal is made longer than the frequency cycle of the commercial power source and the charge control signal is released. The delay time is shorter than a half cycle of the frequency of the commercial power supply.

  According to a fourth aspect of the present invention, in the first aspect of the invention, when the voltage value of at least one secondary battery connected to each assembled battery is lower than a second predetermined value lower than the first predetermined value. A plurality of discharge control voltage detection circuits for outputting a discharge control signal for instructing the load main body to stop the operation, and each discharge control voltage detection circuit connected to each discharge control voltage detection circuit for converting the discharge control signal into a predetermined signal for output Takes the logical sum of the outputs of multiple discharge control signal conversion circuits and each discharge control signal conversion circuit, converts the voltage to the start signal applied from the load body via the terminal when the load body is mounted, and outputs it to the load body A discharge control signal logical sum circuit that is connected to each of the power supply start circuit and a plurality of second power supplies that supply the voltage of each assembled battery to each discharge control signal conversion circuit and the discharge control signal logical sum circuit when the power start circuit is started Power supply Characterized in that a feed circuit.

  According to a fifth aspect of the present invention, in the fourth aspect of the present invention, the discharge control signal is an active high of an open drain output or a C-MOS output, and each discharge control signal conversion circuit has a discharge control signal applied to the gate. A PNP MOS transistor having an open drain output or a PNP transistor having an open collector output to which a discharge control signal is applied to the base, and outputs the voltage of each assembled battery when the discharge control signal is active high.

  According to a sixth aspect of the present invention, there is provided a discharge control signal delay circuit provided between the discharge control signal logical sum circuit and the terminal portion for delaying an input signal in the invention of the fourth or fifth aspect, wherein the discharge control signal delay is provided. The circuit is operated by a start signal supplied via the terminal portion when the load body is mounted, and the release delay time for releasing the discharge control signal is shortened from the detection delay time for detecting the discharge control signal. .

  According to a seventh aspect of the present invention, in the power supply activation circuit according to any one of the first to sixth aspects, the open-drain output N-channel MOS transistor in which the activation signal is applied to the gate or the activation signal is applied to the base. The first power supply circuit and the second power supply circuit include an open drain output PPN channel in which the output of the power supply start circuit is applied to the gate via a rectifier diode and a resistor. It is characterized by comprising an open collector PNP transistor in which the output of the MOS transistor or the power supply starting circuit is applied to the base via a rectifier diode and a resistor.

  The invention of claim 8 is characterized in that, in the invention of any one of claims 1 to 7, the circuit constants are set so that the current consumption in each assembled battery is substantially the same.

  The invention of claim 9 is the invention of any one of claims 1 to 8, wherein a resistance is connected in parallel with every other secondary battery among the secondary batteries connected in series of the assembled battery group. It is characterized by that.

  According to the first aspect of the present invention, since the charge control voltage detection circuit and the charge control signal conversion circuit are provided for each assembled battery, the charge voltage can be detected with high accuracy, and from the charger when the charger is mounted. A power start circuit that is activated by the voltage of the start signal applied through the terminal section, and a first power supply that supplies the voltage of each assembled battery to the charge control signal conversion circuit and the charge control signal logical sum circuit when the power start circuit is activated. Since the power supply circuit is provided, the current consumption in each circuit when the charger is not attached can be reduced.

  According to the invention of claim 3, the detection delay time for detecting the charge control signal is made longer than the frequency cycle of the commercial power supply, and the release delay time for releasing the charge control signal is made shorter than the half cycle of the commercial power supply frequency. Therefore, constant voltage charging can be performed efficiently while gradually reducing the charging current, and malfunction due to single noise can be prevented.

  According to the invention of claim 4, since the discharge control voltage detection circuit and the discharge control signal conversion circuit are provided for each assembled battery, it is possible to detect the discharge voltage with high accuracy, and from the load body when the load body is mounted. Since the second power supply circuit for supplying the voltage of each assembled battery to the discharge control signal conversion circuit and the discharge control signal OR circuit when the power supply start circuit is started by the voltage of the start signal applied via the terminal portion is provided. The current consumption in each circuit when the load main body is not attached can be reduced.

  According to the sixth aspect of the present invention, the release delay time for releasing the discharge control signal is made shorter than the detection delay time for detecting the discharge control signal, so that it is possible to prevent malfunction caused by noise generated when the load main body is driven by pulses. it can.

  According to the eighth aspect of the present invention, by setting the circuit constant so that the current consumption in each assembled battery is substantially the same, the variation in the current consumption between the assembled batteries can be eliminated.

  According to the invention of claim 9, since the resistor is connected in parallel with every other secondary battery, the short circuit in the secondary battery, the secondary battery and the charge / discharge control voltage detection circuit and the overcharge voltage detection circuit In the case of disconnection of the connection line between them, the detected battery voltage shows an abnormal value, so that the charging control can be stopped or the electric circuit can be interrupted by the protection element, and overcharging can be prevented.

  Hereinafter, embodiments of a battery pack according to the present invention will be described with reference to the drawings. In addition, although this embodiment is an 8-cell series battery pack in which two assembled batteries in which four secondary battery cells are connected in series are connected in series, an assembled battery in which a plurality of secondary batteries are connected in series. As long as they are connected in a plurality of stages in series, the configuration is not limited to the above.

  In this embodiment, as shown in FIG. 1, an assembled battery 1-1 in which battery cells BAT1 to BAT4 are connected in series and an assembled battery 1-2 in which battery cells BAT5 to BAT8 are connected in series is connected. A terminal S1 connected to the group 1, the positive electrode of the assembled battery group 1, a terminal S2 connected to the negative electrode of the assembled battery group 1, and a terminal connected to the positive electrode of the assembled battery group 1 via the protective element 10 A power source terminal portion that is detachably mounted on a load main body (not shown) such as an electric tool or a terminal portion (not shown) provided on a charger (not shown), and the load main body or charging. And a signal terminal portion 2 that is detachably attached to the terminal portion of the battery charger and inputs and outputs signals to and from the load main body or the charger. Here, the protective element 10 is a non-returning element that cuts off the electric circuit by cutting a fuse by passing a current through the heater resistor. The terminal S2 is connected to a power supply ground.

  Terminals V1 to V4 connected to the positive electrodes of the battery cells BAT1 to BAT4 are connected to the charge / discharge control voltage detection circuit 3-1 and the overcharge voltage detection circuit 11-1, respectively. The charge / discharge control voltage detection circuit 3-1 is a general-purpose IC for four cells for detecting the voltage of each battery cell BAT1 to BAT4, and at least one of the cell voltages of the battery cells BAT1 to BAT4 is the first. When the voltage becomes higher than a predetermined value (4.2 V in this embodiment), a charge control signal (open drain output active high) is output to a charge control signal conversion circuit 4-1, which will be described later, and the cell voltages of the battery cells BAT1 to BAT4 are output. When at least one of them becomes lower than a second predetermined value (2 V in the present embodiment) lower than the first predetermined value, a discharge control signal (active high of C-MOS output) will be described later. Output to 1. The charge / discharge control voltage detection control circuit 3-1 is supplied with power from the assembled battery 1-1 by connecting the power supply side terminal VDD to the terminal V4 and connecting the ground side terminal VSS to the terminal S2. It has become. Capacitors C1 and C2 for setting delay times of the charge control signal and the discharge control signal are provided between the charge / discharge control voltage detection circuit 3-1 and the terminal S2, respectively.

  The overcharge voltage detection circuit 11-1 is a four-cell general-purpose IC for detecting an overcharge voltage, and at least one of the cell voltages of the battery cells BAT1 to BAT4 is higher than a first predetermined value. Overcharge control signal (C-MOS output active high) is output to the voltage conversion circuit 13 to be described later. The overcharge voltage detection circuit 11-1 is supplied with power from the assembled battery 1-1 by connecting the power supply side terminal VDD to the terminal V4 and connecting the ground side terminal VSS to the terminal S2. ing. A capacitor C5 for setting the delay time of the overcharge control signal is provided between the overcharge voltage detection circuit 11-1 and the terminal S2.

  The terminals V5 to V7 and VB connected to the positive electrodes of the battery cells BAT5 to BAT8 are connected to the charge / discharge control voltage detection circuit 3-2 and the overcharge voltage detection circuit 11-2, respectively. The charge / discharge control voltage detection circuit 3-2 is a general-purpose IC for four cells for detecting the voltage of each of the battery cells BAT5 to BAT8, and at least one of the cell voltages of the battery cells BAT5 to BAT8 is the first. When it becomes higher than a predetermined value, a charge control signal is outputted to a charge control signal conversion circuit 4-2 described later, and when at least one of the cell voltages of the battery cells BAT5 to BAT8 becomes lower than a second predetermined value, the discharge control signal is output later. To the discharge control signal conversion circuit 5-1. The charge / discharge control voltage detection control circuit 3-2 is configured such that power is supplied from the assembled battery 1-2 by connecting the power supply side terminal VDD to the terminal VB and connecting the ground side terminal VSS to the terminal V4. It has become. Capacitors C3 and C4 for setting delay times of the charge control signal and the discharge control signal are provided between the charge / discharge control voltage detection circuit 3-2 and the terminal V4, respectively.

  The overcharge voltage detection circuit 11-2 is a 4-cell general-purpose IC for detecting an overcharge voltage. When at least one of the cell voltages of the battery cells BAT5 to BAT8 becomes higher than a third predetermined value, the overcharge voltage detection circuit 11-2 is overcharged. The charge control signal is output to the drive circuit 12 described later. The overcharge voltage detection circuit 11-2 is supplied with power from the assembled battery 1-2 when the power supply side terminal VDD is connected to the terminal VB and the ground side terminal VSS is connected to the terminal V4. ing. Further, a capacitor C6 for setting a delay time of the overcharge control signal is provided between the overcharge voltage detection circuit 11-2 and the terminal V4.

  Resistors Ra to Rd (for example, 1 MΩ or more) are connected in parallel to the battery cells BAT1, BAT3, BAT5, and BAT7, respectively. Therefore, a short circuit in the battery cells BAT1 to BAT8, and connection lines between the battery cells BAT1 to BAT8 and the charge / discharge control voltage detection circuits 3-1 and 3-2 and the overcharge voltage detection circuits 11-1 and 11-2. In the case of disconnection or the like, when the detected cell voltage shows an abnormal value, the charging control can be stopped or the electric circuit can be interrupted by the protective element 10, and overcharging can be prevented.

  The charge control signal conversion circuits 4-1 and 4-2 are connected to the charge / discharge control voltage detection circuits 3-1 and 3-2, respectively. As shown in FIG. 2, the charge control signal is supplied to the gate via a resistor R1. A supplied P-channel MOS transistor Q1, NPN transistors Q2 and Q3, and an open collector output PNP transistor Q4 are provided. Further, between the drain of the MOS transistor Q1 and the base of the transistor Q2, between the collector of the transistor Q2 and the output of power supply circuits 9-1 and 9-2 described later, between the collector of the transistor Q3 and the base of the transistor Q4. Between them, resistors R2, R3 and R4 are provided, respectively. Thus, when the input charge control signal is at a high level, the MOS transistor Q1 and the transistor Q2 are turned off, and the transistor Q3 and the transistor Q4 are turned on, so that the output signal is at a high level, that is, the power supply circuit 9- Signal conversion is performed so that the output voltage is 1, 9-2.

  Discharge control signal conversion circuits 5-1 and 5-2 are connected to charge / discharge control voltage detection circuits 3-1 and 3-2, respectively, and as shown in FIG. 3, the discharge control signal is supplied to the gate via resistor R5. A supplied P-channel MOS transistor Q5, NPN transistors Q6 and Q7, and an open collector output PNP transistor Q8 are provided. Further, between the drain of the MOS transistor Q5 and the base of the transistor Q6, between the collector of the transistor Q6 and the output of power supply circuits 9-1 and 9-2 described later, between the collector of the transistor Q7 and the base of the transistor Q8. Between them, resistors R6, R7, and R8 are provided, respectively. Thus, when the input discharge control signal is at a high level, the MOS transistor Q5 and the transistor Q6 are turned off and the transistor Q7 and the transistor Q8 are turned on, so that the output signal is at a high level, that is, the power supply circuit 9- Signal conversion is performed so that the output voltage is 1, 9-2.

  The charge control signal OR circuit 6 includes an NPN transistor Q9 whose emitter is connected to the terminal S2, and the output signals of the charge control signal conversion circuits 4-1 and 4-2 are connected to resistors R9-1 and 9-, respectively, at the base. 2 is input. A start signal VT, which will be described later, is input to the collector of the transistor Q9 via a resistor R10, and the collector output is input to a charge control signal delay circuit 14, which will be described later. The charge control signal delay circuit 14 delays the input signal from the charge control signal logical sum circuit 6, and the activation signal VT is supplied to the power supply side terminal. The output is connected to a terminal 2g of the signal terminal unit 2 described later. Thus, if the output signals of the charge control signal conversion circuits 4-1 and 4-2 are both at a low level, the transistor Q9 is turned off and the start signal VT is input to the charge control signal delay circuit 14, and the charge control signal When at least one of the output signals of the conversion circuits 4-1 and 4-2 becomes high level, the transistor Q 9 is turned on and a low level signal is input to the charge control signal delay circuit 14.

  The discharge control signal OR circuit 7 includes an NPN transistor Q10 having an emitter connected to the terminal S2, and the output signals of the discharge control signal conversion circuits 5-1 and 5-2 are connected to resistors R11-1 and 11-, respectively, at the bases. 2 is input. The start signal VT is input to the collector of the transistor Q10 via the resistor R12, and the collector output is input to a discharge control signal delay circuit 15 described later. The discharge control signal delay circuit 15 delays the input signal from the discharge control signal logical sum circuit 7, and the start signal VT is supplied to the power supply side terminal. The output is connected to a terminal 2c of the signal terminal unit 2 described later. Thus, if the output signals of the discharge control signal conversion circuits 5-1 and 5-2 are both at a low level, the transistor Q10 is turned off and the start signal VT is input to the discharge control signal delay circuit 15, and the discharge control signal When at least one of the output signals of the conversion circuits 5-1 and 5-2 becomes high level, the transistor Q 10 is turned on and a low level signal is input to the discharge control signal delay circuit 14.

  The power supply circuit 9-1 has a PNP transistor Q12- whose emitter is connected to the terminal V4 and whose collector is connected to the power supply side terminals of the charge control signal conversion circuit 4-1 and the discharge control signal conversion circuit 5-1. 1 and the base of the transistor Q12-1 is connected to a power supply starting circuit 8 to be described later via a resistor R14-1 and a diode D1-1. The power supply circuit 9-2 has a PNP transistor Q12- whose emitter is connected to the terminal VB and whose collector is connected to the power supply side terminals of the charge control signal conversion circuit 4-2 and the discharge control signal conversion circuit 5-2. 2 and the base of the transistor Q12-2 is connected to the power supply starting circuit 8 via a resistor R14-2 and a diode D1-2.

  The power supply starting circuit 8 includes an NPN transistor Q11 having an emitter connected to a terminal 2h of the signal terminal unit 2 described later, and a base connected to the terminal 2b of the signal terminal unit 2 via a resistor R13. And a start signal VT generated by the charger. Further, the collector of the transistor Q11 is connected to the power supply circuits 9-1 and 9-2 as described above. Thus, when the start signal VT is supplied to the base of the transistor Q11 of the power supply start circuit 8, the transistors Q11, Q12-1, and Q12-2 are turned on, and the charge control signal conversion is performed from the power supply circuit 9-1. The battery voltage of the assembled battery 1-1 is supplied to the circuit 4-1 and the discharge control signal conversion circuit 5-1, and the charge control signal conversion circuit 4-2 and the discharge control signal conversion circuit 5 are supplied from the power supply circuit 9-2. -2 is supplied with the battery voltage of the assembled battery 1-2.

  The voltage conversion circuit 13 includes an N-channel MOS transistor Q14 whose source is connected to the terminal S2, and a P-channel MOS transistor Q15 whose source is connected to the terminal VB. The drain of the MOS transistor Q14, the gate of the MOS transistor Q15, Are connected via a resistor 17. The gate of the MOS transistor Q14 is connected to the output of the overcharge voltage detection circuit 11-1 via the resistor R16, and the drain of the MOS transistor Q15 is connected to the terminal V4 and connected to the input of the drive circuit 12 described later. It is connected.

  The drive circuit 12 includes N-channel MOS transistors Q13-1 and Q13-2 whose sources are connected to the terminal V4, and each drain is connected to the protection element 10. The gate of the MOS transistor Q13-1 is connected to the drain of the MOS transistor Q15 of the voltage conversion circuit 13 through the resistor R15-1, and the gate of the MOS transistor Q13-2 is overcharged through the resistor R15-2. It is connected to the output of the voltage detection circuit 11-2.

  Thus, when the overcharge control signal of the overcharge voltage detection circuit 11-1 becomes high level, the MOS transistors Q14 and Q15 of the voltage conversion circuit 13 are turned on, and the MOS transistor Q13-1 of the drive circuit 12 is turned on. Then, the battery voltage of the assembled battery 1-2 or the charging voltage is applied to the heater resistance of the protective element 10 via the terminal S3 when the charger is mounted, and the fuse is instantaneously blown by the generated heat. The electric circuit between the plus electrode of the assembled battery group 1 is cut off. Similarly, when the overcharge control signal of the overcharge voltage detection circuit 11-2 becomes high level, the MOS transistor Q13-2 of the drive circuit 12 is turned on, and the battery voltage or charge voltage of the assembled battery 1-2 is applied to the protection element 10. Is applied to cut off the electric circuit between the terminal S3 and the plus electrode of the assembled battery group 1.

  The signal terminal unit 2 includes eight terminals 2a to 2h connected to a terminal unit provided on the load main body or the charger, and the terminal 2h is connected to a signal ground. An identification resistor 16 having a resistance value corresponding to information (number of cells, configuration, voltage, capacity, etc.) of the assembled battery group 1 is connected between the terminal 2a and the terminal 2h. The terminal 2b is connected to the charge control signal logical sum circuit 6, the discharge control signal logical sum circuit 7, the power supply starting circuit 8, the charge control signal delay circuit 14, and the discharge control signal delay circuit 15, and is loaded when the load body or the charger is mounted. The activation signal VT generated by the main body or the charger is supplied to each circuit. The output signal of the discharge control signal delay circuit 15 and the output signal of the charge control signal delay circuit 14 are input to the terminals 2c and 2g, respectively. A temperature sensor (thermistor) 18 for detecting the temperature of the assembled battery group 1 is connected between the terminals 2d and 2h. Between the terminal 2e and the terminal 2f, a storage unit 17 composed of a non-volatile memory for recording a control history from the load main body or the charger is connected, and activated by an activation signal VT supplied from the terminal 2b. To do.

  Note that the terminal S2 and the terminal 2h connected to the negative electrode of the assembled battery group 1 are not directly connected but separated from each other. For this reason, when terminal S2 becomes poor in conduction, it is possible to prevent a large charge / discharge current from flowing through terminal 2h and causing problems such as ignition.

  Thus, when a charger is attached, charge control is performed via the terminals S3 and S2 of the power supply terminal section and the signal terminal section 2. Further, when the load main body is mounted, the load is controlled via the terminals S1 and S2 of the power terminal portion and the signal terminal portion 2 by operating a trigger switch (not shown) provided on the load main body. . When the load main body and the charger are mounted, the terminal S2 and the terminal 2h are internally connected, and the power supply ground and the signal ground are a common ground.

  Hereinafter, an operation when the present embodiment is mounted on a charger will be described. When the charger is attached, the information of the temperature sensor 18 and the identification resistor 16 is detected via the terminals 2a and 2d to automatically detect that the present embodiment is attached, and the charging operation is started. . First, a start signal VT is applied to the terminal 2b, and the temperature of the assembled battery group 1 detected by the terminal 2d is within a predetermined temperature range (70 ° C. or less in the present embodiment), and the signal input to the terminal 2g Is at the high level, that is, when the battery voltages of the battery cells BAT1 to BAT8 are all equal to or lower than the first predetermined value (4.2V), constant current charging is started via the terminals S3 and S2. When the signal input to the terminal 2g is at a low level, that is, when the battery voltage of at least one of the battery cells BAT1 to BAT8 becomes equal to or higher than the first predetermined value (4.2V), the charging current is sequentially decreased. When voltage charging is started and charging current becomes below a certain level, charging is completed and current consumption is suppressed by stopping application of the start signal VT at the terminal 2b. Whether the charger has been removed is determined by detecting the voltages at the terminals 2a and 2b.

  Here, when the temperature of the assembled battery group 1 detected by the temperature sensor 18 exceeds a predetermined temperature (70 ° C.), the charging voltage applied to the terminals S3 and S2 is a predetermined value (in this embodiment, 35V). ) Will stop charging. Furthermore, in the overcharge voltage detection circuits 11-1 and 11-2, when at least one battery voltage of each of the battery cells BAT1 to BAT8 exceeds a third predetermined value (4.5V), the drive circuit 12 is activated. Thus, the protection element 10 is melted to prevent charging. For this reason, the high safety | security at the time of charge is securable.

  Next, an operation when the present embodiment is mounted on the load body will be described. When the load main body is mounted and the trigger switch for activation is operated, the control circuit of the load main body is activated, the activation signal VT is applied to the terminal 2b, and the assembled battery group 1 is connected via the terminals 2d and 2c. When the temperature is normal and information on whether or not it is overdischarged, if normal, the load body is activated via the terminals S1 and S2. When the trigger switch is released or when an abnormality is detected at the terminals 2d and 2c, the discharge is stopped and the application of the start signal to the signal terminal VT is stopped to suppress the current consumption.

  In general, the lithium ion battery is over-discharged to reduce the reliability and shorten the life. Specifically, when the deposition voltage is lower than the Fe deposition voltage (1.0 V) and Cu deposition voltage (0.5 V), the capacity is reduced. Therefore, the voltage between the terminals S1 and S2 is monitored by the control circuit of the load main body, and when it becomes a predetermined voltage (20 V in this embodiment) or less, the load is stopped and the discharge is stopped. In addition, the load is stopped when the signal input to the terminal 2c is at a low level, that is, when the battery voltage of at least one of the battery cells BAT1 to BAT8 falls below the second predetermined value (2.0V). Yes. Furthermore, when the temperature of the assembled battery group 1 detected by the temperature sensor 18 exceeds a predetermined value (70 ° C.), the load is stopped and the discharge is stopped. For this reason, the fall of the reliability by discharge can be prevented.

  Next, an operation when the present embodiment is left without being mounted on either the load body or the charger will be described. The charge / discharge control voltage detection circuits 3-1 and 3-2 and the overcharge voltage detection circuits 11-1 and 11-2 are all driven by being supplied with power from the assembled batteries 1-1 and 1-2 even when left unattended. to continue. Therefore, it is necessary to use a circuit with extremely low current consumption, and the charge / discharge control voltage detection circuits 3-1 and 3-2 do not require a detection operation when left unattended, and therefore when the start signal VT is not input from the terminal 2b. Is in a standby mode so that output signals to the charge control signal conversion circuits 4-1 and 4-2 and the discharge control signal conversion circuits 5-1 and 5-2 are at a high level. Further, when at least one battery voltage of the battery cells BAT1 to BAT8 becomes equal to or lower than the second predetermined value (2.0V), the mode automatically shifts to the low power consumption mode. In this mode, the output signals to the charge control signal conversion circuits 4-1 and 4-2 and the discharge control signal conversion circuits 5-1 and 5-2 are at a high level, and the circuit is stopped (consumption current is 0.1 μA or less). Become.

  By the way, the circuits after the charge control signal conversion circuits 4-1 and 4-2 and the discharge control signal conversion circuits 5-1 and 5-2 consume a considerable current (about 1 mA) even if they are designed to have a low current consumption. The Therefore, a power start circuit 8 and power supply circuits 9-1 and 9-2 that are started by a start signal VT from the terminal 2b are provided, and when the start signal VT is not input from the terminal 2b and when left unattended, the power supply circuit 9-1 is provided. , 9-2 is stopped to stop the circuit and suppress current consumption. At this time, the charge / discharge control voltage detection circuits 3-1 and 3-2 are in a standby mode or a low power consumption mode, and both of the terminals are at a high level. In addition, the transistors in the input stage of the discharge control signal conversion circuits 5-1 and 5-2 are turned off so that no current flows. Thus, since the current consumption can be suppressed to an extremely low value (about 3 μA), deterioration due to overdischarge can be prevented even when left for a long period of time.

  Hereinafter, the operation of the circuit of this embodiment will be described in detail. First, the case where the load main body or the charger is attached and the activation signal VT is applied from the terminal 2b will be described. Here, when the battery voltages of all the battery cells BAT1 to BAT8 of the assembled battery group 1 are equal to or lower than the first predetermined value (4.2V), the output is performed from the charge / discharge control voltage detection circuits 3-1 and 3-2, respectively. Any charge control signal to be performed is at a low level. For this reason, in the charge control signal conversion circuits 4-1 and 4-2, the MOS transistors Q 1 and Q 2 are turned on and the transistors Q 3 and Q 4 are turned off. All the signals output from are at a low level. Therefore, the transistor Q9 of the charge control signal OR circuit 6 is turned off, the activation signal VT (for example, 5V) is input to the charge control signal delay circuit 14, and the activation signal VT delayed by the charge control signal delay circuit 14 is received. Input to the terminal 2g.

  When at least one battery voltage of each of the battery cells BAT1 to BAT8 of the assembled battery group 1 exceeds the first predetermined value (4.2V), if the battery cell is BAT1 to BAT4, the charge / discharge control voltage detection circuit 3 If the charge control signal of −1 is the battery cells BAT5 to BAT8, the charge control signal of the charge / discharge control voltage detection circuit 3-2 becomes high level. When the charge control signal becomes high level, in the charge control signal conversion circuits 4-1 and 4-2, the MOS transistors Q 1 and Q 2 are turned off and the transistors Q 3 and Q 4 are turned on. The signals output from the charge control signal conversion circuits 4-1 and 4-2 to which the signal is input are at a high level. Therefore, the transistor Q9 of the charge control signal OR circuit 6 is turned on, a low level signal is input to the charge control signal delay circuit 14, and the low level signal delayed by the charge control signal delay circuit 14 is applied to the terminal 2g. Entered.

  Here, the delay time of the charge control signal will be described with reference to FIG. The charging current by the charger varies depending on the frequency of the commercial power supply, and voltage ripples are generated in the battery voltages of the battery cells BAT1 to BAT8 due to the internal resistance of the battery cells BAT1 to BAT8 (FIG. 4 (a), ( b) shows the voltage signal at the terminal V1). For example, if the release delay time of the charge control signal, that is, the delay time of the high level signal input to the charge control signal delay circuit 14 is longer than a half cycle of the frequency of the commercial power supply, as shown in FIG. Even if the charging current is lowered, the charging control signal does not become high level, and the charging current is continuously lowered in the charger. The upper end of the ripple of the voltage signal falls below the charging control voltage level (4.2V). It becomes high level for the first time, and charging is performed by the charging current when it becomes high level. For this reason, when the change width of the charging current becomes rough, the charging efficiency is deteriorated and the charging time is increased. If the detection delay time of the charge control signal, that is, the delay time of the low level signal input to the charge control signal delay circuit is shorter than the cycle of the commercial power supply, the charge control signal becomes high in synchronization with the commercial power supply ripple. Since the level and the low level can be switched alternately, a malfunction occurs when a single noise occurs.

  FIG. 4A shows a case where the detection delay time of the charging control signal is made longer than the frequency cycle of the commercial power source and the release delay time of the charging control signal is made shorter than the half cycle of the commercial power source frequency as delay characteristics. Show. In the case of such delay characteristics, when the ripple lower end of the voltage signal exceeds the charge control level longer than the frequency cycle of the commercial power supply, a low level signal is input to the terminal 2g. In response to this, the charger lowers the charging current to decrease the voltage signal (current control in FIG. 4A). When the charging control voltage level falls below, a high level signal is input to the terminal 2g and the voltage is again applied. The signal rises. In this way, constant voltage charging can be performed efficiently while gradually reducing the charging current, and malfunction due to single noise can be prevented. In addition, the delay characteristic in charge control can be set in two places of the capacitors C1 and C3 of the charge / discharge voltage detection circuits 3-1 and 3-2 and the charge control signal delay circuit 14.

  Next, when the battery voltages of all the battery cells BAT1 to BAT8 of the assembled battery group 1 are equal to or higher than the second predetermined value (2V), the discharge control signals of the charge / discharge control voltage detection circuits 3-1 and 3-2 are Low level. For this reason, in the discharge control signal conversion circuits 5-1 and 5-2, the MOS transistors Q 5 and Q 6 are turned on and the transistors Q 7 and Q 8 are turned off. Therefore, the discharge control signal conversion circuits 5-1 and 5-2. All the signals output from are at a low level. Therefore, the transistor Q10 of the discharge control signal logical sum circuit 7 is turned off, the start signal VT is input to the discharge control signal delay circuit 14, and the start signal VT delayed by the discharge control signal delay circuit 15 is input to the terminal 2c. The

  Thereafter, the load main body is driven, and when at least one battery voltage of the battery cells BAT1 to BAT8 of the assembled battery group 1 becomes equal to or lower than the second predetermined value (2.0 V), the battery cells BAT1 to BAT4 If so, the discharge control signal of the charge / discharge control voltage detection circuit 3-1 becomes high level, and if the battery cells BAT5 to BAT8, the discharge control signal of the charge / discharge control voltage detection circuit 3-2 becomes high level. When the discharge control signal becomes high level, in the discharge control signal conversion circuits 5-1 and 5-2, the MOS transistor Q5 and the transistor Q6 are turned off and the transistors Q7 and Q8 are turned on. The signals output from the discharge control signal conversion circuits 5-1 and 5-2, to which is input, become high level. Therefore, the transistor Q10 of the discharge control signal logical sum circuit 7 is turned on, a low level signal is input to the discharge control signal delay circuit 15, and the low level signal delayed by the discharge control signal delay circuit 15 is applied to the terminal 2c. Entered. Since it is necessary to prevent malfunction due to noise generated when the load main body is driven by a pulse, it is effective that the delay characteristic of the discharge control signal is to make the detection delay time (about 1 second) longer than the release delay time. .

  Next, when all the battery cells BAT1 to BAT8 of the assembled battery group 1 are equal to or lower than the third predetermined value (4.5V), the overcharge control signals of the overcharge voltage detection circuits 11-1 and 11-2 are low. Is a level. Therefore, in response to the overcharge control signal from the overcharge voltage detection circuit 11-1, the MOS transistors Q14 and Q15 of the voltage conversion circuit 13 are turned off, and the battery voltage of the assembled battery 1-1 is output to the drive circuit 12. On the other hand, the overcharge voltage detection circuit 11-2 outputs the battery voltage of the assembled battery 1-1 to the drive circuit 12. In this case, both the MOS transistors Q13-1 and Q13-2 of the drive circuit 12 remain off, and the protection element 10 is not blown. Therefore, the charging current is supplied to the assembled battery group 1 via the terminals S3 and S2. To be supplied.

  Thereafter, when the battery voltage of the battery cells BAT1 to BAT8 rises due to charging or the like and at least one of the battery voltages of the battery cells BAT1 to 4 exceeds a third predetermined value (4.5V), an overcharge voltage detection circuit The overcharge control signal 11-1 is at a high level. Therefore, the MOS transistors Q14 and Q15 of the voltage conversion circuit 13 are turned on, and the battery voltage of the assembled battery group 1 is output to the drive circuit 12. In response to the output of the voltage conversion circuit 13, the MOS transistor Q13-1 of the drive circuit 12 is turned on, the battery voltage of the assembled battery 1-2 is applied to the heater resistance of the protection element 10, and the protection element 10 is blown by this heat generation. As a result, the power supply from the terminal S3 is interrupted to prevent overcharging. Similarly, when the battery voltage of at least one of the battery cells BAT5 to BAT8 exceeds the third predetermined value (4.5V), the overcharge control signal output of the overcharge voltage detection circuit 11-2 becomes high level. Then, the battery voltage of the assembled battery group 1 is output to the drive circuit 12. In response to the output of the overcharge voltage detection circuit 11-2, the MOS transistor Q13-2 of the drive circuit 12 is turned on, and the applied voltage of the assembled battery 1-2 is supplied to the heater resistance of the protection element 10, and the heat generation protects it. When the element 10 is melted, the power supply from the terminal S3 is cut off to prevent overcharging.

  Here, the battery voltage of the assembled battery 1-2 is applied to the protection element 10 when any of the overcharge voltage detection circuits 11-1 and 11-2 is activated. The protective element 10 can be used, and a stable operation can be realized even when any of the battery cells BAT1 to BAT8 exceeds the overcharge voltage.

  Although the delay characteristic of the overcharge control signal can be set by the capacitors C5 and C6 of the overcharge voltage detection circuits 11-1 and 11-2, it does not require a fast operation, thereby preventing malfunction due to noise or voltage fluctuation. Therefore, it is desirable to set a longer delay time (about 1 second or more). Even when the internal resistance of the battery cell increases due to a decrease in room temperature or deterioration of the battery cell and exceeds the third predetermined value (4.5 V) at the initial charging current, the delay time is set to the above-described charging control signal. By setting the detection time longer than the detection delay time, the protection element 10 is not melted and charging control is performed first to lower the charging current. Therefore, it is possible to prevent malfunctions that cause the protection element 10 to melt without meaning.

  Next, the case where the load body and the charger are connected and the activation signal VT is not supplied, or the case where the present embodiment is left unattached to either the load body or the charger will be described. First, in the normal state (2.0 to 4.2 V), both the charge control signal and the discharge control signal of the charge / discharge voltage detection circuits 3-1 and 3-2 are at a high level. In this case, the input of the charge control signal conversion circuits 4-1 and 4-2 is open, and no power is supplied from the power supply circuits 9-1 and 9-2, so that no current is consumed in the circuit. Since the input of the charge control signal logical sum circuit 6 is also open and the activation signal VT from the terminal 2b is not supplied, no current is consumed in the circuit. Even in a circuit driven by the activation signal VT from the terminal 2b such as the charge control signal delay circuit 14, current is not consumed. Further, the inputs of the discharge control signal conversion circuits 5-1 and 5-2 become the potentials of the terminals V4 and VB, respectively, the MOS transistor Q5 is turned off, and no power is supplied from the power supply circuits 9-1 and 9-2. No current is consumed in the circuit. Further, since the overcharge control signals of the overcharge voltage detection circuits 11-1 and 11-2 are at a low level, all the transistors of the voltage conversion circuit 13 and the drive circuit 12 are off, and current is consumed in the circuit. There is no. Therefore, the current consumption is only the current consumption of the charge / discharge voltage detection circuits 3-1 and 3-2 (about 10 μA) and the current consumption of the overcharge voltage detection circuits 11-1 and 11-2 (about 1 μA). In the overdischarge state (2.0 V or less), the charge / discharge control voltage detection circuits 3-1 and 3-2 are in the low power consumption mode (0.1 μA or less), and the current consumption is further reduced.

  By the way, in this embodiment, voltage conversion is performed by the charge control signal logical sum circuit 6, the discharge control signal logical sum circuit 7, and the power supply circuits 9-1 and 9-2. Variations in current consumption occur between 1 and 1-2. For this reason, in the present embodiment, the following device has been devised to eliminate variations in current consumption between the assembled batteries 1-1 and 1-2.

  As an example, the charge control signal will be described. The resistance values of the resistors R9-1 and R9-2 of the charge control signal OR circuit 6 are set so that the same current flows in order to stabilize the driving of the transistor Q9. . Specifically, voltage is supplied from the assembled battery 1-1 to the resistor R9-1, and voltage is supplied from the assembled batteries 1-1 and 1-2 to the resistor R9-2. The resistance value is set to twice the resistance value of the resistor R9-1. At this time, in the charge control signal logical sum circuit 6, the assembled battery 1-1 consumes twice as much current as the assembled battery 1-2 (that is, the assembled battery 1-1 is only V4 / R9-1. A lot)

  Therefore, it is necessary to flow a large amount of this difference in a circuit driven by the assembled battery 1-2. For example, the resistance value of the resistor R2 (hereinafter referred to as “resistor R2-1”) of the charge control signal conversion circuit 4-1 is referred to as the resistance R2 (hereinafter referred to as “resistor R2-2”) of the charge control signal conversion circuit 4-2. So that a large amount of consumption current flows in the charge control signal conversion circuit 4-2. Specifically, the resistance R2-1 of the charging control signal conversion circuit 4-1 is set to the same resistance value as the resistance R9-1, and the resistance R2-2 of the charging control signal conversion circuit 4-2 is set to the charging control signal conversion circuit 4- If the resistance value of the resistor R2 of 1 is half, the consumption current of the charge control signal conversion circuit 4-2 is larger than that of the charge control signal conversion circuit 4-1, by the resistor R9-1 of the charge control signal OR circuit 6. Therefore, the current consumption between the assembled batteries 1-1 and 1-2 as a whole can be made substantially equal.

  Specifically, each resistance value is R9-1 = (R9-2) / 2 = r, R2-1 = 2 · (R2-2) = r, and the battery voltage of each battery cell BAT1 to BAT8 is v. Then, the consumption current in the assembled battery 1-1 is 4v / r + 8v / 2r + 4v / r = 12v / r, and the consumption current in the assembled battery 1-2 is 8v / 2r + 4v / (r / 2) = 12v / r. Therefore, the current consumption of each of the assembled batteries 1-1 and 1-2 is the same. For other circuits, the current consumption between the assembled batteries 1-1 and 1-2 can be made substantially equal by adjusting the resistance value in the same manner as described above.

  In this way, when the current is adjusted only by the resistance value, the battery capacity and voltage vary due to other factors (initial battery capacity, battery capacity deterioration, etc.) between the assembled batteries 1-1 and 1-2. However, an assembled battery having a high capacity and voltage will cause a larger amount of current to flow than the others, and can work to reduce variations in current consumption. In addition, although the normal state (2.0 to 4.2 V) has been described here, the variation in the consumption current can be eliminated in the same way in the charge control state (4.2 V or more) (in this case, the resistance R3 and R4 are adjusted.) In addition, the variation in current consumption can be eliminated with the same concept for the overdischarge state (2.0 V or less).

  Furthermore, compared to the current consumption in the normal state (2.0 to 4.2 V), the current consumption in the charge control state (4.2 V or higher) (mainly in the charge control signal conversion circuits 4-1 and 4-2). Current consumption in the overdischarged state (2.0 V or less) (mainly current consumption in the discharge control signal conversion circuits 5-1 and 5-2) is reduced between the assembled batteries. Can be used to level out battery capacity and voltage variations. In other words, the battery pack that has reached the charge control state earlier has a larger capacity voltage than the other batteries, so if it is set to consume more current, it is automatically adjusted in the same way as other battery packs. It will be. In addition, battery packs that have reached the discharge control state sooner are automatically adjusted in the same way as other battery packs if they are set to consume less current because the capacity voltage of the batteries is lower than others. Will be.

It is a circuit diagram which shows the battery pack of embodiment of this invention. It is a circuit diagram of a charge control signal conversion circuit same as the above. It is a circuit diagram of the same discharge control signal conversion circuit. The waveform diagram of the voltage signal and the charging control signal at the terminal V1 is the same as (a), in which the detection delay time is made longer than the frequency cycle of the commercial power supply and the release delay time for canceling the charging control signal is set to It is a figure which shows the case where it makes shorter than a half cycle, (b) is a figure which shows the case where release delay time is made longer than the half period of the frequency of a commercial power source.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 assembled battery group 1-1, 1-2 assembled battery 2 signal terminal part 3-1, 3-2 charge / discharge control voltage detection circuit 4-1, 4-2 charge control signal conversion circuit 6 charge control signal OR circuit BAT1 ~ BAT8 battery cell (secondary battery)
S1-S3 Power supply terminal

Claims (9)

  An assembled battery group in which a plurality of secondary batteries are connected in series, and a terminal that is detachably attached to the charger or load body and electrically connected to the charger or load body The battery pack is connected to each assembled battery, and the charger controls the charging of the assembled battery group when the voltage value of at least one secondary battery is higher than a first predetermined value. A plurality of charge control voltage detection circuits for outputting a charge control signal instructing to the plurality of charge control signals, and a plurality of charge control signal conversion circuits connected to the respective charge control voltage detection circuits for converting the charge control signal into a predetermined signal and outputting the predetermined signal Charging that outputs a logical sum of the outputs of the respective charge control signal conversion circuits and outputs a signal obtained by converting the voltage of the activation signal applied from the charger through the terminal unit according to the logical sum when the charger is mounted to the charger. Control signal OR circuit A power start circuit that is activated by a start signal, and a plurality of second power supplies that supply the voltage of each assembled battery to each charge control signal conversion circuit and the charge control signal OR circuit when the power start circuit is connected to the power start circuit and starts. A battery pack comprising a power supply circuit.   The charge control signal is an active high of an open drain output or a C-MOS output, and each charge control signal converter circuit is an open drain output P-channel MOS transistor or a charge control signal to which the charge control signal is applied to the gate. 2. The battery pack according to claim 1, further comprising an open collector output PNP transistor applied to a base, wherein the voltage of each assembled battery is output when the charge control signal is active high.   A charge control signal delay circuit is provided between the charge control signal logical sum circuit and the terminal portion and delays an input signal, and the charge control signal delay circuit is supplied via the terminal portion when the charger is mounted. It operates with the start signal, and the detection delay time for detecting the charge control signal is made longer than the frequency cycle of the commercial power supply, and the release delay time for releasing the charge control signal is made shorter than the half cycle of the commercial power supply frequency. The battery pack according to claim 1 or 2.   A discharge control signal for instructing the load body to stop operating when the voltage value of at least one secondary battery connected to each assembled battery is lower than a second predetermined value lower than the first predetermined value. A plurality of discharge control voltage detection circuits, a plurality of discharge control signal conversion circuits each connected to each discharge control voltage detection circuit for converting a discharge control signal into a predetermined signal, and each discharge control signal conversion A discharge control signal logical sum circuit that takes the logical sum of the output of the circuit and converts it to the voltage of the start signal applied from the load main body via the terminal when the load main body is mounted, and outputs it to the load main body, and the power start circuit A plurality of second power supply circuits that supply voltages of each assembled battery to each discharge control signal conversion circuit and discharge control signal logical sum circuit when the power supply start circuit is connected and activated. 1 The battery pack of the mounting.   The discharge control signal is an active high of an open drain output or a C-MOS output, and each discharge control signal conversion circuit is an open drain output P-channel MOS transistor or a discharge control signal to which the discharge control signal is applied to the gate. 5. The battery pack according to claim 4, further comprising an open collector output PNP transistor to be applied to a base, and outputting a voltage of each assembled battery when the discharge control signal is active high.   A discharge control signal delay circuit is provided between the discharge control signal logical sum circuit and the terminal unit and delays an input signal, and the discharge control signal delay circuit is supplied via the terminal unit when the load body is mounted. 6. The battery pack according to claim 4, wherein the battery pack operates according to the start signal, and the release delay time for releasing the discharge control signal is shorter than the detection delay time for detecting the discharge control signal.   The power start circuit includes an open drain output N-channel MOS transistor to which a start signal is applied to a gate or an open collector output NPN transistor to which a start signal is applied to a base, and includes a first power supply circuit and a second power supply circuit In this power supply circuit, the output of the power start circuit is applied to the gate via a rectifier diode and a resistor, or an open drain output P-channel MOS transistor or the output of the power start circuit is applied to the base via a rectifier diode and a resistor. The battery pack according to claim 1, further comprising an open collector PNP transistor.   The battery pack according to any one of claims 1 to 7, wherein the circuit constants are set so that current consumption in the assembled batteries is substantially the same.   The battery pack according to any one of claims 1 to 8, wherein a resistance is connected in parallel with every other secondary battery among the secondary batteries connected in series of the assembled battery group. .

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