JP2008192692A - Resist pattern forming method and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resist pattern forming method capable of forming a satisfactory minute pattern, and to provide a manufacturing method of a semiconductor device that employs the same. <P>SOLUTION: The resist pattern forming method comprises a step of forming a first resist pattern 101a, capable of supplying an acid on a semiconductor substrate 103; a step of forming a second resist 102 on the first resist pattern; a step of forming a bridging layer 104 on an interface portion of the second resist, contacting the first resist pattern; and a step of removing a non-bridging portion of the second resist to form a second resist pattern. The step of forming the second resist pattern 102a includes a first developing step for developing using water, a second developing step of developing with a solution having higher solderbility with respect to the second resist than that of the water, after the first developing step, and a step of rinsing with water after the second developing step. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a resist pattern forming method and a semiconductor device manufacturing method.

  In recent years, with the increase in the degree of integration of semiconductor devices, the dimensions of individual elements have been miniaturized, and the widths of wirings and gates constituting each element have also been miniaturized. In general, a fine pattern is formed by forming a desired resist pattern using a photolithography technique and then etching various underlying thin films using the resist pattern as a mask. Therefore, photolithography technology is very important in forming a fine pattern.

  The photolithographic technique includes steps of resist application, mask alignment, exposure, and development. However, in recent advanced devices, the pattern dimensions are approaching the limit resolution of light exposure, so the development of higher resolution exposure technology has become an urgent task.

  By the way, in general, when the sensitivity of the resist material is shifted to the short wavelength side, the etching resistance of the resist is lowered. For example, in the case of a resist having an aromatic ring in the molecule, the etching resistance is good, but it has sensitivity at a long wavelength of 300 nm or more. On the other hand, a resist having no aromatic ring in the molecule has sensitivity at a lower wavelength, but the etching resistance is lowered. For this reason, a problem arises that the resist film is etched and the pattern accuracy of the finally formed thin film is lowered.

  On the other hand, a method for forming a fine resist pattern by forming a so-called organic frame on the resist side surface using a water-soluble resin having a property of cross-linking by reacting with an acid catalyst is disclosed (for example, (See Patent Documents 1 and 2.) According to this method, it is possible to form a fine pattern exceeding the limit of the exposure wavelength.

  Further, along with the miniaturization of device circuits, not only the pattern size but also the pattern pitch itself has been miniaturized. For example, in the contact hole process, it is necessary to miniaturize the hole size, but the interval is also miniaturized. In such a case, the distance between adjacent holes is close to the resolution limit, and the width of the organic frame formed on the resist side surface is reduced from 30 nm to 60 nm from the conventional 60 nm to 100 nm. Improvement is required.

Japanese Patent No. 3071401 Japanese Patent No. 3189773

  In the method using a water-soluble resin having a property of cross-linking by reacting with an acid catalyst, first, a first resist pattern capable of supplying an acid is formed, and then the presence of an acid is formed on the first resist pattern. To form a second resist that causes a crosslinking reaction. Next, after causing a crosslinking reaction at the interface between the first resist pattern and the second resist, the non-crosslinked portion of the second resist is removed to form a resist pattern. Thereby, a finer pattern than the first resist pattern can be formed.

  In the conventional formation of the second resist pattern, a method using water alone (Japanese Patent No. 3071401) as a developing solution or a solution treatment in which a water-soluble organic solvent such as alcohol is mixed with water is rinsed with water. The method (Japanese Patent No. 3189773) was used. However, in the vicinity of the interface between the second resist and the first resist, as shown in FIG. 4, the reactivity with the acid, that is, the crosslink density gradually changes. There was a problem that the halfway low crosslink density layer dissolved in the water of the process was dissolved, and the dissolved material was reprecipitated at the time of spin drying and adhered to the resist pattern to cause a pattern defect. In addition, in the method of rinsing with water after solution treatment in which water-soluble organic solvent such as alcohol is mixed in water, the pattern due to swelling due to solvent penetration for the high permeability of the organic solvent into the second and first resists. There was a problem that a thread-like residue defect was generated in the meantime, and a crack (crack) defect was generated in the pattern due to the contraction stress in the process in which the second and first resist films contracted when the permeated solvent was dried.

  Further, in the above method, by forming the second resist pattern, for example, the inner diameter of the hole pattern provided in the first resist pattern can be reduced. However, in the method of developing with water or rinsing with water after solution processing in which water-soluble organic solvents such as alcohols are mixed in water, the inner diameter of the hole pattern becomes too small and the holes are blocked. there were. This can be dealt with by increasing the inner diameter of the hole provided in the first resist pattern in advance, but this is adjacent to the hole in the contact hole process, for example, for the purpose of miniaturizing the pattern pitch as described above. In some cases, the distance between the holes was close to the resolution limit and was impossible. Further, when used in the vicinity of the limit, stricter dimensional control is required for the first resist pattern.

  The present invention has been made in view of these problems. That is, an object of the present invention is to provide a resist pattern forming method capable of forming a good fine pattern and a semiconductor device manufacturing method using the resist pattern forming method.

  Other objects and advantages of the present invention will become apparent from the following description.

  According to one embodiment of the present invention, a step of forming a first resist pattern capable of supplying an acid on a substrate, a step of forming a second resist on the first resist pattern, A step of forming a crosslinked layer at an interface portion of the second resist in contact with the first resist pattern by supplying an acid from the first resist pattern; and removing the non-crosslinked portion of the second resist to form the second resist A method of forming a resist pattern is provided. The second resist includes any one of a water-soluble resin, a water-soluble cross-linking agent, and a mixture thereof that does not dissolve the first resist pattern and causes a cross-linking reaction in the presence of an acid. The step of forming the second resist pattern includes a first development step of developing with water, and a second development step of developing with a solution having a higher solubility in the second resist than water after the first development step. And a step of rinsing with water after the second development step.

  The role of the first development step of developing with water is to prevent the formation of thread-like residue defects and crack defects between patterns caused by the penetration of the developing solution, so that the first penetration step is highly penetrable with water having low permeability. 4 is to dissolve and peel a portion having a low crosslink density formed in the vicinity of the interface between the non-crosslinked portion of the resist 2 and the first resist whose degree of reactivity gradually changes as shown in FIG.

  The role of the second development step of developing with a solution having a higher solubility in the second resist than water is to dissolve the low crosslink density layer into the rinse with water later, and the dissolved matter is reprecipitated during spin drying. An object of the present invention is to eliminate the problem of pattern defects caused by adhering to a resist pattern, and to reduce the width of an organic frame formed on the side surface of the resist so as to satisfy the needs for miniaturization of device circuits. In addition, the width of the swollen layer in this step can be reduced because the non-swelled layer is removed in the first developing step that has been performed previously.

  In the final rinsing step with water, the low cross-linking density layer that has already dissolved in water is dissolved and peeled, and there is no concern of reprecipitation due to redissolution. In addition, as described above, the rinsing process includes a spin drying process after washing with water, and the solvent that permeates at this stage volatilizes, so that film contraction occurs and cracks occur in the pattern. is there. In the present invention, when TMAH (tetramethylammonium hydroxide) is used as a solution having a higher solubility in the second resist than water, TMAH has no volatility and therefore provides a process that does not cause this crack. I can do it.

  According to this embodiment, a good fine pattern can be formed.

  FIGS. 1A to 1C show examples of mask patterns for forming a finely separated resist pattern as an object of the present invention. FIG. 1A shows a fine hole mask pattern 100, FIG. 1B shows a fine space mask pattern 200, and FIG. 1C shows an isolated pattern 300. 2 and 3 are process flow diagrams for explaining a resist pattern forming method.

  First, an example of a resist pattern forming method will be described with reference to FIGS.

  As shown in FIG. 2A, a first resist 101 capable of supplying an acid is applied on a semiconductor substrate (semiconductor wafer) 103 as a base material. The thickness of the first resist 101 can be, for example, about 0.7 μm to 1.0 μm. The first resist 101 may be either a positive type or a negative type.

  As the first resist 101, for example, a resist in which an acidic component is generated inside the resist by heat treatment and / or irradiation with light or the like is used. Specifically, the first resist 101 can be composed of a novolak resin and a naphthoquinonediazide-based photosensitizer. Further, as the first resist 101, a chemically amplified resist that generates an acid upon exposure can be used. Further, the first resist 101 may contain an acidic substance such as a carboxylic acid, and the acidic substance may be configured to diffuse by heating. However, when both the reactivity of the first resist pattern and the second resist described later are low, when the required thickness of the cross-linked layer is relatively thick, or when the cross-linking reaction is made uniform, light, etc. It is desirable to generate an acid by irradiating with.

  The first resist 101 can be applied using a spin coating method or the like. After application, pre-baking (heat treatment at 70 to 110 ° C. for about 1 minute) is performed as necessary to evaporate the solvent contained in the first resist 101.

  Next, in order to form the first resist pattern 101a, the first resist 101 is selectively exposed through a mask including a pattern as shown in any of FIGS. Do. The light source used for the exposure only needs to correspond to the sensitivity wavelength of the first resist 101. For example, the first resist 101 is irradiated with g-line, i-line, deep ultraviolet light, KrF excimer laser light (248 nm), ArF excimer laser light (193 nm), EB (electron beam), or X-ray.

  After the exposure, PEB treatment (post-exposure heat treatment) is performed as necessary. Thereby, the resolution of the first resist 101 can be improved. The PEB treatment is performed by performing a heat treatment at 50 ° C. to 130 ° C., for example.

  Next, development processing is performed using an appropriate developer, and the first resist 101 is patterned. As a developing solution, about 0.05 to 3.0 weight% alkaline aqueous solution, such as TMAH (tetramethylammonium hydroxide), can be used, for example. FIG. 2B shows the first resist pattern 101a formed in this way.

  After development processing, post-development baking may be performed as necessary. Since this heat treatment affects the subsequent crosslinking reaction, it is desirable to set the temperature appropriately depending on the material constituting the first resist or the second resist to be used. For example, it can be heated at 60 ° C. to 120 ° C. for about 60 seconds using a hot plate.

  Next, as shown in FIG. 2C, a second resist 102 is applied on the semiconductor substrate 103 so as to cover the first resist pattern 101a. The method for applying the second resist 102 is not particularly limited as long as it can be applied uniformly on the first resist pattern 101a. For example, it can apply | coat using a spray method, a spin coat method, or a dip method.

  The second resist 102 includes one of a water-soluble resin, a water-soluble cross-linking agent, and a mixture thereof that cause a cross-linking reaction in the presence of an acid without dissolving the first resist pattern 101a. These are coated on the semiconductor substrate 103 in a state of being dissolved in water, a water-soluble organic solvent such as N-methylpyrrolidone, or a water-soluble solvent such as isopropyl alcohol or N-methylpyrrolidone mixed in water. be able to. In addition, the solvent mixed with water is not particularly limited as long as it is water-soluble, and in addition to the above, other alcohols such as ethanol and methanol, γ-butyrolactone, acetone and the like can be mentioned. In the solvent of the second resist 102, it is necessary not to dissolve the first resist pattern 101a and to sufficiently dissolve the above water-soluble material. There is no limitation. In the case of using a mixed solvent, the first resist pattern 101a may be mixed within a range that does not dissolve in accordance with the solubility of the material used for the second resist 102.

  Examples of water-soluble resins applicable to the second resist 102 include polyacrylic acid, polyvinyl acetal, polyvinyl pyrrolidone, polyvinyl alcohol, polyethyleneimine, styrene-maleic anhydride copolymer, polyvinylamine, polyallylamine, and oxazoline. Examples include at least one selected from the group consisting of a group-containing water-soluble resin, water-soluble urethane, water-soluble phenol, water-soluble epoxy, water-soluble melamine resin, water-soluble urea resin, alkyd resin, sulfonamide, and salts thereof. it can.

  Examples of water-soluble crosslinking agents applicable to the second resist 102 include melamine-based crosslinking agents such as melamine derivatives and methylol melamine derivatives, urea derivatives, methylol urea derivatives, ethylene urea carboxylic acid, and methylol ethylene urea derivatives. Mention may be made of at least one selected from the group consisting of urea-based crosslinking agents and amino-based crosslinking agents such as benzoguanamine, glycoluril and isocyanate.

  Note that the second resist 102 may contain other components as additives in addition to components such as a water-soluble resin, a water-soluble crosslinking agent, or a mixture thereof. For example, the second resist 102 can include at least one plasticizer. Examples of the plasticizer include ethylene glycol, glycerin, triethylene glycol, and the like. In addition, at least one surfactant can be added to the second resist 102 for the purpose of improving coating properties. Examples of the surfactant in this case include water-soluble surfactants such as 3M Fluorard or Sanyo Kasei nonipol.

  After applying the second resist 102, a pre-bake treatment is performed as necessary to evaporate the solvent. The pre-baking process is performed, for example, by performing a heat treatment at about 85 ° C. for about 1 minute using a hot plate.

  When the first resist 101 generates an acid by heat treatment, next, the first resist pattern 101a formed on the semiconductor substrate 103 and the second resist 102 formed on the first resist pattern 101 Then, heat treatment (mixing bake treatment; hereinafter, abbreviated as “MB treatment” if necessary) is performed. Thereby, the diffusion of the acid in the first resist pattern 101a is promoted, and the acid is supplied from the first resist pattern 101a to the second resist 102. Then, as shown in FIG. 2D, a crosslinking reaction occurs in the second resist 102, and a crosslinked layer 104 is formed in the vicinity of the interface with the first resist pattern 101a. The MB treatment is performed, for example, by heating at 70 ° C. to 150 ° C. for 60 seconds to 120 seconds using a hot plate. It is preferable to set optimum MB processing conditions according to the type of resist material used and the required thickness of the reaction layer.

  In the case where acid is generated by exposure instead of heat treatment or prior to heat treatment, exposure is performed after the second resist layer 102 is formed. As a result, an acid is generated in the first resist pattern 101 a to form a cross-linked layer 104 at the interface between the first resist pattern 101 a and the second resist 102. As a light source used for exposure at this time, an Hg lamp, a KrF excimer laser beam, an ArF excimer laser beam, or the like can be used depending on the photosensitive wavelength of the first resist 101. However, there is no particular limitation as long as acid can be generated by exposure, and exposure may be performed with a light source and an exposure amount corresponding to the photosensitive wavelength of the first resist 101.

  When acid is generated by exposure, the first resist pattern 101a is exposed in a state covered with the second resist 102. Therefore, the amount of acid generated in the first resist pattern 101a is determined by the exposure amount. It can be controlled accurately in a wide range by adjusting. Therefore, the thickness of the crosslinked layer 104 can be controlled with high accuracy.

  If necessary, MB processing can be performed after exposure. Thereby, since the diffusion of the acid from the first resist pattern 101a is promoted, the crosslinking reaction at the interface between the second resist 102 and the first resist pattern 101a can be promoted. It is desirable to set optimum conditions for the MB treatment temperature and time depending on the type of resist material used and the required thickness of the crosslinked layer 104. As an example, using a hot plate, heating can be performed at 60 ° C. to 130 ° C. for 60 seconds to 120 seconds.

  Control of the cross-linking reaction between the first resist pattern 101 a and the second resist 102 includes a method by adjusting process conditions and a method by adjusting the composition of the material constituting the second resist 102.

  Examples of the method by adjusting the process conditions include adjusting the exposure amount of the first resist pattern 101a and adjusting the temperature and time of MB processing. In particular, according to the method of adjusting the crosslinking time depending on the MB treatment conditions, the thickness of the crosslinked layer 104 can be accurately controlled.

  As a method for adjusting the composition of the second resist 102, for example, two or more appropriate water-soluble resins are mixed and the mixing ratio is adjusted to control the reaction amount with the first resist pattern 101a. For example, an appropriate water-soluble crosslinking agent may be mixed with the water-soluble resin, and the mixing ratio may be adjusted to control the amount of reaction with the first resist pattern 101a. Specifically, the amount of reaction with the first resist pattern 101a can be controlled by using a polyvinyl acetal resin as the second resist 102 and adjusting the degree of acetalization of the polyvinyl acetal resin. Further, for example, the second resist 102 is a mixture of the water-soluble resin and the water-soluble crosslinking agent, and the first resist pattern 101a is adjusted by adjusting the mixing amount of the water-soluble crosslinking agent. The reaction amount of can also be controlled.

  However, the control of the crosslinking reaction is not determined in a centralized manner. (1) Reactivity of each material applied to the first resist pattern 101a and the second resist 102, (2) shape and film thickness of the first resist pattern 101a, and (3) required film of the crosslinked layer 104 It is necessary to determine the thickness, (4) usable exposure conditions or MB processing conditions, and (5) coating conditions. In particular, it has been found that the reactivity between the first resist pattern 101a and the second resist 102 is influenced by the composition of the material constituting the first resist pattern 101a. Therefore, the present invention is actually applied. In this case, it is desirable to optimize the composition of the material constituting the second resist 102 in consideration of the above points.

  Further, in this embodiment mode, a material for supplying an acid to the first resist 101 is not necessarily used. For example, a method of performing surface treatment on the first resist pattern 101a with an acidic liquid or an acidic gas may be used. In this method, the acid soaks into the first resist pattern 101a, whereby a thin layer containing acid is formed on the surface of the first resist pattern 101a. Therefore, it is possible to supply acid to the second resist 102 without using a material that supplies acid to the first resist 101.

  After the MB treatment, the non-crosslinked portion of the second resist 102 is removed to form a second resist pattern 102a. This step includes a first development step of developing with water, a second development step of developing with a solution having a higher solubility in the second resist 102 after the first development step, and a second development step. And a step of rinsing with water after the step.

  The formation process of the second resist pattern 102a will be described with reference to FIGS. In FIGS. 3B to 3I, each pattern provided on the semiconductor substrate 103 is omitted.

  First, as shown in FIG.3 (b), it rinses using water. Specifically, water 105 is supplied onto the semiconductor substrate 103 on which the second resist 102 is formed while rotating the semiconductor substrate 103. Next, the supply of water 105 is stopped, and the first development is performed after a predetermined time with the rotation stopped (FIG. 3C).

  Again, rinsing is performed by supplying water 106 while rotating the semiconductor substrate 103 (FIG. 3D). Next, the rotation of the semiconductor substrate 103 is continued in a state where the supply of the water 106 is stopped, and the remaining water 106 is shaken off (hereinafter referred to as “shake-off treatment” as necessary) to dry the surface of the semiconductor substrate 103. (FIG. 3E).

  Thereafter, water 107 is supplied again while rotating the semiconductor substrate 103 to perform rinsing (FIG. 3F). Next, an aqueous solution 108 in which TMAH (tetramethylammonium hydroxide) is dissolved in water at a concentration of 2.38 wt% is supplied instead of the water 107, and the semiconductor substrate 103 is stopped rotating for a predetermined time. Second development is performed (FIG. 3G).

  Again, rinsing is performed by supplying water 109 while rotating the semiconductor substrate 103 (FIG. 3H). Next, the rotation is continued with the supply of water 109 stopped, and the remaining water 109 is shaken off to dry the surface of the semiconductor substrate 103 (FIG. 3I).

  Through the above process, a second resist pattern 102a as shown in FIG. According to the present invention, it is possible to obtain a resist pattern in which the hole inner diameter or line pattern separation width of the first resist pattern 101a is reduced, or the area of the isolated remaining pattern is enlarged. This pattern is a fine pattern having a better shape than a pattern formed by a conventional method. This point will be described in detail.

  In the conventional formation of the second resist pattern 102a, water is used as a developer. However, when developed with water, there is a problem that the second resist 102 dissolved in water re-deposits and adheres to the second resist pattern 102a, causing a pattern defect. This pattern defect is observed as a circular residue. However, as a result of intensive studies, the present inventors have found that the development of such circular residues can be suppressed by developing using TMAH. This mechanism will be described with reference to FIG.

  FIG. 4 shows the distance from the edge of the first resist pattern 101a in the second resist 102 on the horizontal axis, and the reactivity between the second resist 102 and the acid on the vertical axis. Since the reactivity with the acid decreases as the distance from the first resist pattern 101a increases, the crosslinked layer 104 is formed near the interface between the first resist pattern 101a and the second resist 102.

  In FIG. 4, the dotted line indicates the solubility limit of water, and the broken line indicates the solubility limit of the TMAH aqueous solution. As can be seen from these, water and the TMAH aqueous solution are common in that the non-crosslinked portion of the second resist 102 is dissolved, but there is a difference in solubility in the crosslinked layer 104. That is, the TMAH aqueous solution exhibits higher solubility than water in the second resist having a high reactivity with acid.

  Generally, water is used for rinsing after development. Therefore, when development is performed using water, a part of the crosslinked layer 104 that could not be dissolved in the development process is dissolved in the rinse process. In other words, since the second resist 102 is dissolved in both the development and rinsing steps, the second resist 102 dissolved in water easily re-deposits and adheres to the second resist pattern, resulting in a pattern defect. It is easy for problems to occur. On the other hand, when development is performed using a TMAH aqueous solution, a part of the cross-linked layer 104 is hardly dissolved in water in the subsequent rinsing step. This is because the cross-linked layer 104 remaining after development with an aqueous TMAH solution has a high reactivity with an acid and has low solubility in water. Therefore, if development is performed using the TMAH aqueous solution, it is possible to suppress the dissolution of the second resist 102 in the rinsing step, and thus it is possible to suppress the occurrence of pattern defects due to the deposition of the second resist 102.

  By the way, when development is performed using a TMAH aqueous solution, a problem of development residue occurs. This defect is observed in a state where the second resist 102 swollen by the TMAH aqueous solution is attached to the second resist pattern 102a so as to pull the yarn. However, the present inventor has found that this problem can be solved by performing development with water before development with an aqueous TMAH solution. That is, a first development step in which development is performed with water, a second development step in which development is performed with a solution having higher solubility in water than water after the first development step, and a second development step. In the subsequent rinsing with water, the second resist 102 dissolved in water re-deposits and adheres to the second resist pattern 102a, and the second resist 102 becomes the second resist 102. It is possible to simultaneously solve the problem of stringing that is adhered to the resist pattern 102a in a state where the string is pulled. Note that the threading problem can be improved by this method because the swelling of the second resist 102 due to the TMAH aqueous solution can be suppressed as much as possible by developing with a TMAH aqueous solution after removing what is previously dissolved in water. It is done.

  Below, the difference in the occurrence of circular residue and stringing due to the difference in process will be described.

  Table 1 shows Examples 1 to 3 having a first developing process performed using water and a second developing process performed using TMAH, and Comparative Example 1 performing only a developing process using water. And Comparative Example 2 in which only the developing process using TMAH is performed. In these examples, the steps from the formation of the second resist to the MB processing were performed as follows.

  First, a coating material (trade name: SWK-EX3) manufactured by Tokyo Ohka Kogyo Co., Ltd. was applied as an antireflection film (BARC: Bottom Anti-Reflection Coating) on a semiconductor wafer. Subsequently, it heated at 230 degreeC for 90 second using the hotplate, and formed the film | membrane with a thickness of 130 nm. Next, a chemically amplified resist (trade name: KrF-M211Y) manufactured by JSR was applied as a first resist on the film. Thereafter, pre-baking was performed at 120 ° C. for 60 seconds using a hot plate to form a film having a thickness of 585 nm. Next, a coating material (trade name: TSP-10A) manufactured by Tokyo Ohka Kogyo Co., Ltd. was formed in a thickness of 44 nm as an antireflection film (TARC: Top Anti-Reflection Coating) on the first resist. . Then, after exposing through a mask, PEB processing was performed. The PEB treatment was performed using a hot plate at 130 ° C. for 60 seconds. Next, the 2.38 wt% TMAH aqueous solution was discharged for 3 seconds to develop the first resist, and then rinsed by discharging water for 75 seconds while rotating at a rotation speed of 300 rpm to 1800 rpm. In the development process, all TARC was dissolved in the developer, and a first resist pattern was obtained later.

  Next, a resist (trade name: R200) manufactured by AZ Electronic Materials was applied as a second resist on the first resist pattern to form a film having a thickness of 350 nm. Next, MB treatment was performed by heating at 110 ° C. for 70 seconds using a hot plate.

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Table 1.

* Use pure water for rinsing and dry by shaking off.
* ○: Level at which almost no defects are observed.

  In Table 1, the conditions of the rinse treatment performed first are all that the discharge time is 20 seconds and the rotation speed is 1000 rpm. The conditions of water development in Examples 1 to 3 and Comparative Example 1 are a discharge time of 45 seconds in a stationary state. The conditions of the rinsing process after water development in Examples 1 and 2 and Comparative Example 1 are that water is discharged for 20 seconds while rotating at a rotation speed of 2000 rpm, and then water is discharged for 15 seconds at a rotation speed of 600 rpm. It is. The conditions for the rinse treatment before TMAH development in Example 1 and Comparative Example 2 are a discharge time of 20 seconds and a rotation speed of 1000 rpm. The conditions of TMAH development in Examples 1 to 3 and Comparative Example 2 are such that a 2.38 wt% TMAH aqueous solution is discharged for 45 seconds in a stationary state. The conditions of the rinse treatment after TMAH development in Examples 1 to 3 and Comparative Example 2 are that water is discharged for 20 seconds while rotating at a rotational speed of 2000 rpm, and then water is discharged for 15 seconds at a rotational speed of 600 rpm. It is.

  As can be seen from Table 1, in Comparative Example 1, a circular residue is generated, and in Comparative Example 2, stringing is generated. On the other hand, in Examples 1-3, a circular residue is hardly seen. In addition, there is almost no stringing, or even if it is seen, there is no practical problem. Therefore, by the first development process performed using water, the second development process performed using TMAH after the first development process, and the rinse process performed using water after the second development process, It turns out that generation | occurrence | production of a circular residue and stringing can be suppressed.

  In Example 1, stringing is hardly observed, and a good pattern can be formed even when compared with Examples 2 and 3. This is probably because the surface of the substrate is dried by performing a process of shaking off the water remaining on the substrate between the first development step and the second development step. Therefore, in the present invention, it is preferable to perform the second development step after performing the first development step and then performing the process of shaking off water.

  Next, the relationship between development time and defects in the second development step will be considered.

  Table 2 shows an example of the results of examining the relationship between the development time by TMAH and the occurrence of circular residues and stringing. In this example, the process from the formation of the second resist to the MB processing was performed as follows.

  First, a coating material (trade name: DUV112) manufactured by Nissan Chemical Co., Ltd. was applied as an antireflection film (BARC: Bottom Anti-Reflection Coating) on a semiconductor wafer. Subsequently, it heated at 180 degreeC for 90 second using the hotplate, and the film | membrane with a thickness of 62 nm was formed. Next, a chemically amplified resist (trade name: KrF-M211Y) manufactured by JSR was applied as a first resist on the film. Thereafter, pre-baking was performed at 120 ° C. for 60 seconds using a hot plate to form a film having a thickness of 480 nm. Next, a coating material (trade name: TSP-10A) manufactured by Tokyo Ohka Kogyo Co., Ltd. was formed in a thickness of 44 nm as an antireflection film (TARC: Top Anti-Reflection Coating) on the first resist. . Then, after exposing through a mask, PEB processing was performed. The PEB treatment was performed using a hot plate at 180 ° C. for 90 seconds. Next, the 2.38 wt% TMAH aqueous solution was discharged for 3 seconds to develop the first resist, and then rinsed by discharging water for 75 seconds while rotating at a rotation speed of 300 rpm to 1800 rpm. In the development process, all TARC was dissolved in the developer, and a first resist pattern was obtained later.

  Next, a resist (trade name: R200) manufactured by AZ Electronic Materials was applied as a second resist on the first resist pattern to form a film having a thickness of 350 nm. Next, MB treatment was performed by heating at 110 ° C. for 70 seconds using a hot plate.

  The second resist pattern was formed in the same manner as in Example 1 in Table 1. Specifically, first, a rinsing process using water was performed with a discharge time of 20 seconds and a rotation speed of 1000 rpm. Next, the first development process was performed by discharging water for 45 seconds in a stationary state. Subsequently, water was discharged for 20 seconds while rotating at a rotation speed of 2000 rpm, and then the water was discharged for 15 seconds at a rotation speed of 600 rpm to perform a rinsing process. Thereafter, the supply of water was stopped, a swing-off process was performed, and drying was performed. Then, a rinse process using water was performed at a discharge time of 20 seconds and a rotation speed of 1000 rpm. Next, a 2.38 wt% TMAH aqueous solution was discharged at each time shown in Table 2 in a stationary state, and a second development process was performed. Thereafter, water was discharged for 20 seconds while rotating at a rotational speed of 2000 rpm, and then the water was discharged at a rotational speed of 600 rpm for 15 seconds to perform a rinsing process. Finally, the supply of water was stopped, and a shake-off process was performed for drying.

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Table 2.

* ○: Level at which almost no defects are observed.

  From Table 2, it can be seen that stringing occurs as the development time increases. On the other hand, for the circular residue, no difference due to the development time is observed in the range of Table 2. Therefore, in order to suppress stringing and circular residues, it is preferable to shorten the development time.

  Note that the developer used in the second development step is not limited to the TMAH aqueous solution as long as it has a higher solubility in the second resist than water. For example, the second development process can be performed using IPA (isopropyl alcohol). However, if the internal stress generated on the surface of the second resist when the developer evaporates is large, there is a risk that cracks will occur in the second resist. Therefore, when using IPA, it is preferable to slow down the evaporation rate by adjusting the concentration in an aqueous solution. On the other hand, in development with an aqueous TMAH solution, there is little concern about the occurrence of cracks. Therefore, in the present invention, it is more preferable to use TMAH.

  The concentration of IPA relative to water can be set, for example, in the range of about 1% to 30% by weight. Of these, depending on the type of the second resist, a solution in which IPA is diluted with water to a concentration of 7% by weight can effectively suppress the occurrence of cracks compared to a solution diluted to a concentration of 10% by weight. There is a case. Therefore, it is important to adjust the IPA concentration according to the type of the second resist. However, it goes without saying that the concentration of IPA is in a range in which the first resist is not dissolved, and in which the uncrosslinked portion of the second resist is sufficiently dissolved. This also applies to the case of mixing other water-soluble organic solvents mixed with water.

  Through the above processing, a second resist pattern 2a as shown in FIG. 2E can be obtained. The second resist pattern 2a can be a pattern that reduces the hole inner diameter or separation width with the first resist pattern 1a, or a pattern that increases the area of the isolated remaining pattern.

  In addition, according to the present invention, the pattern provided on the first resist pattern 1a can be set to a desired size, so that strict dimensional control is not performed on the first resist pattern 1a. However, a good fine pattern can be obtained. This will be further described with reference to Table 3.

  Table 3 shows the relationship between the type of the developing solution and the dimension capable of reducing the inner diameter of the hole provided in the first resist pattern. Further, the hole inner diameter of the second resist pattern formed after the development and rinsing is also shown.

Table 3.

  As can be seen from Table 3, when IPA or TMAH is used, the size for reducing the inner diameter of the hole can be reduced as compared with the case of developing with water. Therefore, by using IPA or TMAH, it is possible to solve the problem that the inner diameter of the hole provided in the first resist pattern becomes too small and the hole is blocked. In particular, in TMAH, a high effect can be obtained in this respect. The same applies to the case where the separation width provided in the first resist pattern is reduced. In addition, when the first resist pattern is an isolated remaining pattern and this area is enlarged, by using IPA or TMAH, it is avoided that the patterns are enlarged and the patterns are connected to each other. Can do.

  Note that in this embodiment mode, the second resist pattern 102 a can be formed over the entire surface of the semiconductor substrate 103, or can be selectively formed only in a desired region of the semiconductor substrate 103. In the latter case, after the second resist 102 is formed, a part of the semiconductor substrate 103 is exposed in a light-shielded state to generate an acid in the first resist pattern 101a. Thereby, the crosslinked layer 104 can be formed only at the interface between the first resist pattern 101a and the second resist 102 in the exposed portion. Therefore, on the same semiconductor substrate 103, it is possible to form a fine pattern having hole inner diameters and separation widths having different dimensions, or isolated remaining patterns having different areas.

  The resist pattern forming method of the present invention can be applied not only to a resist pattern formed on a semiconductor substrate, but also to each step in a method of manufacturing a semiconductor device as necessary. For example, the present invention can be applied to a resist pattern formed on an insulating layer such as a silicon oxide film or a resist pattern formed on a conductive layer such as a polysilicon film. That is, the resist pattern forming method of the present invention is not limited to the base film, and can be applied to any substrate as long as it is on a substrate capable of forming a resist pattern. In other words, the resist pattern formed according to the present invention is formed on a base material as required, and in the present application, these base materials are collectively referred to as a semiconductor base material.

  In the present invention, various underlying thin films are etched using the resist pattern formed as described above as a mask. As a result, a minute space or a minute hole is formed in the underlying thin film, so that a semiconductor device having a desired specification can be manufactured.

  Hereinafter, an example of a method for manufacturing a semiconductor device using the above resist pattern forming method will be described. Specifically, a method for manufacturing a CMIS (Complementary Metal Insulator Semiconductor) device will be described with reference to FIGS.

  First, as shown in FIG. 5, a semiconductor substrate 1 made of p-type single crystal silicon is prepared. The semiconductor substrate 1 is a planar thin semiconductor plate generally called a semiconductor wafer.

  Next, the element isolation region 4 is formed on the main surface of the semiconductor substrate 1. For example, the semiconductor substrate 1 is etched to form a groove having a depth of 0.35 μm, and then an insulating film (for example, a silicon oxide film) is deposited on the main surface of the semiconductor substrate 1 by a CVD method. Next, the insulating film outside the trench is removed by a CMP (Chemical Mechanical Polishing) method. Thereby, the element isolation region 4 can be formed.

  Next, a p-type well 6 is formed by ion implantation of a p-type impurity (for example, boron) in the nMIS formation region of the semiconductor substrate 1. In addition, an n-type impurity (for example, phosphorus) is ion-implanted into the pMIS type and formation region of the semiconductor substrate 1 to form an n-type well 8. Thereafter, an impurity for controlling the threshold value of nMIS or pMIS may be ion-implanted into the p-type well 6 or the n-type well 8.

  Next, the surface of the semiconductor substrate 1 is cleaned by wet etching using a hydrofluoric acid aqueous solution. Next, the semiconductor substrate 1 is thermally oxidized to form, for example, a gate insulating film 9 having a thickness of 5 nm on the surface of the semiconductor substrate 1, specifically, on each surface of the p-type well 6 and the n-type well 8.

  Next, a conductive film for a gate electrode having a thickness of, for example, 0.14 μm is formed on the gate insulating film 9. Next, the gate electrode 10n, 10p made of the conductor film is formed by processing the gate electrode conductor film by dry etching using the resist pattern as a mask, and the structure of FIG. 6 can be obtained. Here, the present invention can be applied to the formation of the resist pattern to be used. According to the present invention, a good fine pattern is formed, so that the width of the gate electrodes 10n and 10p can be made fine.

  The conductor film for the gate electrode is made of, for example, a polycrystalline silicon film formed by a CVD method. Then, a gate electrode 10n made of a polycrystalline silicon film doped with n-type impurities is formed in the nMIS formation region, and a gate electrode 10p made of a polycrystalline silicon film doped with p-type impurities is formed in the pMIS formation region. Is formed.

  Next, an n-type impurity, for example, arsenic is ion-implanted into the p-type well 6 to form a relatively low concentration source / drain extension region 11 in a self-aligned manner with respect to the nMIS gate electrode 10n. Similarly, a p-type impurity, for example, boron fluoride is ion-implanted into the n-type well 8 to form a relatively low concentration source / drain extension region 12 in a self-aligned manner with respect to the gate electrode 10p of the pMIS. . The depth of the source / drain extension regions 11 and 12 is, for example, 30 nm.

  Next, as shown in FIG. 7, after a silicon oxide film 13 having a thickness of, for example, 10 nm is deposited on the main surface of the semiconductor substrate 1 by a CVD method, a silicon nitride film is further formed on the silicon oxide film 13 by a CVD method. It accumulates by. Subsequently, the silicon nitride film is anisotropically etched by RIE (Reactive Ion Etching) to form sidewalls 15 on the respective sidewalls of the nMIS gate electrode 10n and the pMIS gate electrode 10p. Thereafter, an n-type impurity, for example, arsenic is ion-implanted into the p-type well 6 to form a relatively high concentration source / drain diffusion region 16 in a self-aligned manner with respect to the gate electrode 10n and the sidewall 15 of the nMIS. . Similarly, a p-type impurity, for example, boron fluoride is ion-implanted into the n-type well 8, and the source / drain diffusion region 17 having a relatively high concentration is self-aligned with the gate electrode 10p and the sidewall 15 of the pMIS. Form. The depth of the source / drain diffusion regions 16 and 17 is, for example, 80 nm.

  Next, a low-resistance nickel silicide (NiSi) layer 18 is formed on the surface of the nMIS gate electrode 10n and the source / drain diffusion region 16 and the surface of the pMIS gate electrode 10p and the source / drain diffusion region 17 by salicide technology. To do. Although the nickel silicide layer 18 is illustrated here, other silicide layers such as a nickel alloy silicide layer, a cobalt silicide layer, a tungsten silicide layer, or a platinum silicide layer may be formed. The nickel silicide layer 18 is formed by, for example, a method described below.

  First, a nickel film and a titanium nitride film are sequentially deposited on the main surface of the semiconductor substrate 1 by sputtering. The nickel film has a thickness of 10 nm, for example, and the titanium nitride film has a thickness of 15 nm, for example. The titanium nitride film is provided on the nickel film in order to prevent oxidation of the nickel film. Note that a titanium film may be used instead of the titanium nitride film. Subsequently, the semiconductor substrate 1 is subjected to, for example, a heat treatment at a temperature of 350 ° C. for 30 seconds using an RTA (Rapid Thermal Anneal) method. As a result, the nickel film and the n-type polycrystalline silicon film constituting the nMIS gate electrode 10n and the single-crystal silicon constituting the semiconductor substrate 1 on which the nickel film and the nMIS source / drain diffusion regions 16 are formed are selected. Thus, a nickel silicide layer 18 is formed. Similarly, a nickel film and a p-type polycrystalline silicon film constituting the pMIS gate electrode 10p, and a single crystal silicon constituting the semiconductor substrate 1 on which the nickel film and the pMIS source / drain diffusion regions 17 are formed are selected. Thus, a nickel silicide layer 18 is formed. Subsequently, the unreacted nickel film and titanium nitride film are removed by wet cleaning using sulfuric acid or wet cleaning using sulfuric acid and hydrogen peroxide solution. Thereafter, the resistance of the nickel silicide layer 18 is reduced by performing a heat treatment at a temperature of 550 ° C. for 30 seconds using the RTA method on the semiconductor substrate 1.

  Next, as shown in FIG. 8, a silicon nitride film is deposited on the main surface of the semiconductor substrate 1 by a CVD method to form a first insulating film 19a. Subsequently, a TEOS (Tetra Ethyl Ortho Silicate) film is deposited on the first insulating film 19a by plasma CVD to form a second insulating film 19b. Thereby, an interlayer insulating film composed of the first and second insulating films 19a and 19b is formed. Thereafter, the surface of the second insulating film 19b is polished by a CMP method. Even if an uneven shape is formed on the surface of the first insulating film 19a due to the base step, by polishing the surface of the second insulating film 19b by the CMP method, an interlayer insulating film whose surface is flattened is formed. can get.

  Next, using the resist pattern as a mask, the first and second insulating films 19a and 19b are etched to form connection holes 20 at predetermined locations. For example, it is formed on the first and second insulating films 19a and 19b located above the gate electrode 10n and source / drain diffusion region 16 of nMIS and the gate electrode 10p and source / drain diffusion region 17 of pMIS. The diameter of the connection hole 20 is 0.1 μm or less, for example, 0.08 μm. Here, the present invention can be applied to the formation of the resist pattern to be used. According to the present invention, a good fine pattern is formed, so that the fine connection hole 20 can be formed in the first and second insulating films 19a and 19b.

  Next, as shown in FIG. 9, a titanium film and a titanium nitride film are sequentially formed on the main surface of the semiconductor substrate 1 including the inside of the connection hole 20 to form a barrier metal film 21 made of this laminated film. . Since the titanium film can dissolve oxygen atoms up to 25 at%, it is used as a reducing agent on the surface of the nickel silicide layer 18 and has a function of reducing contact resistance with the nickel silicide layer 18. Further, the titanium nitride film has a function of suppressing or preventing diffusion of constituent atoms of the metal film embedded in the connection hole 20 in a later step. The thickness of the barrier metal film 21 is, for example, 3 nm to 10 nm. In the following description, the titanium film and the titanium nitride film formed thereon are referred to as a barrier metal film 21 and are distinguished from a metal film, for example, a tungsten film, embedded in the connection hole 20 and serving as a main conductive material. To do.

  Next, as shown in FIG. 10, the surface of the tungsten film 22 is flattened by, for example, a CMP method to bury the tungsten film 22 in the connection hole 20 and form a plug using the tungsten film 22 as a main conductive material. To do.

  In the step of forming the plug in the connection hole 20 described above, the main conductive material of the plug is the tungsten film 22, and the barrier metal film 21 is a laminated film in which the titanium nitride film 21c is formed on the titanium films 21a and 21b. However, the present invention is not limited to this, and various changes can be made. For example, the barrier metal film can be the barrier metal film 21 described above, and the main conductive material of the plug can be a copper film. In this case, first, the barrier metal film 21 is formed in the same manner as the manufacturing method described above. Next, a seed layer, for example, a copper or ruthenium seed layer is formed on the barrier metal film 21 by CVD or sputtering. Thereafter, a copper plating film is formed on the seed layer using an electrolytic plating method, thereby embedding the copper plating film in the connection hole 20.

  Next, as shown in FIG. 11, the stopper insulating film 24 and the wiring forming insulating film 25 are sequentially formed on the main surface of the semiconductor substrate 1. The stopper insulating film 24 is a film that becomes an etching stopper when a groove is formed in the insulating film 25, and a material having an etching selectivity with respect to the insulating film 25 is used. The stopper insulating film 24 can be, for example, a silicon nitride film formed by a plasma CVD method. The insulating film 25 can be a silicon oxide film formed by, for example, a plasma CVD method. The stopper insulating film 24 and the insulating film 25 are formed with a first layer wiring described below.

  Next, a first layer wiring is formed by a single damascene method. First, wiring trenches 26 are formed in predetermined regions of the stopper insulating film 24 and the insulating film 25 by dry etching using a resist pattern as a mask. The resist pattern forming method of the present invention can be applied to the formation of the resist pattern to be used. Next, a barrier metal film 27 is formed on the main surface of the semiconductor substrate 1. For example, the barrier metal film 27 can be a laminated film in which a tantalum film is stacked on a titanium nitride film, a tantalum nitride film, or a tantalum nitride film. Alternatively, a laminated film in which ruthenium films are stacked on a tantalum nitride film can also be used. Subsequently, a copper seed layer is formed on the barrier metal film 27 by a CVD method or a sputtering method, and further a copper plating film is formed on the seed layer by an electrolytic plating method. The inside of the wiring groove 26 is embedded with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 27 in a region other than the wiring trench 26 are removed by CMP to form a first layer wiring M1 using the copper film as a main conductive material.

  Next, a second layer wiring is formed by a dual damascene method. First, as shown in FIG. 12, a cap insulating film 28, an interlayer insulating film 29, and a stopper insulating film 30 for wiring formation are sequentially formed on the main surface of the semiconductor substrate 1. As will be described later, connection holes are formed in the cap insulating film 28 and the interlayer insulating film 29. The cap insulating film 28 is made of a material having an etching selectivity with respect to the interlayer insulating film 29, and can be, for example, a silicon nitride film formed by a plasma CVD method. Further, the cap insulating film 28 has a function as a protective film for preventing diffusion of copper constituting the first-layer wiring M1. The interlayer insulating film 29 can be a TEOS film formed by plasma CVD, for example. The stopper insulating film 30 is made of an insulating material having an etching selection ratio with respect to the interlayer insulating film 29 and the wiring forming insulating film deposited later on the stopper insulating film 30. For example, a plasma CVD method is used. It can be set as the silicon nitride film formed by.

  Next, after the stopper insulating film 30 is processed by dry etching using a resist pattern for hole formation as a mask, an insulating film 31 for wiring formation is formed on the stopper insulating film 30. The insulating film 31 can be a TEOS film, for example. The resist pattern forming method of the present invention can be applied to the formation of the resist pattern to be used.

  Next, the insulating film 31 is processed by dry etching using a resist pattern for wiring trench formation as a mask. At this time, the stopper insulating film 30 functions as an etching stopper. Subsequently, the interlayer insulating film 29 is processed by dry etching using the stopper insulating film 30 and a wiring trench forming resist pattern as a mask. At this time, the cap insulating film 28 functions as an etching stopper. Subsequently, by removing the exposed cap insulating film 28 by dry etching, a connection hole 32 is formed in the cap insulating film 28 and the interlayer insulating film 29, and a wiring groove 33 is formed in the stopper insulating film 30 and the insulating film 31. The The resist pattern forming method of the present invention can be applied to the formation of each resist pattern.

  Next, a second layer wiring is formed inside the connection hole 32 and the wiring groove 33. The second layer wiring is composed of a barrier metal layer and a copper film that is a main conductive material, and the connecting member that connects this wiring to the first layer wiring M1 is a second layer wiring. And formed integrally. First, the barrier metal film 34 is formed on the main surface of the semiconductor substrate 1 including the insides of the connection holes 32 and the wiring grooves 33. For example, the barrier metal film 34 may be a laminated film in which a tantalum film is stacked on a titanium nitride film, a tantalum nitride film, or a tantalum nitride film. Alternatively, a laminated film in which ruthenium films are stacked on a tantalum nitride film can also be used. Before the barrier metal film 34 is formed, the above-described dry cleaning process is performed. At this time, heating at a temperature of 100 ° C. to 150 ° C. and heating at a temperature higher than 150 ° C. are performed on the semiconductor wafer, and generated on the bottom surfaces of the connection holes 32 and the side walls of the connection holes 32 and the wiring grooves 33. The product removed may be removed. As a result, variation in contact resistance between the barrier metal film 34 and the first-layer wiring M1 can be reduced, and from the cap insulating film 28, the interlayer insulating film 29, the stopper insulating film 30, and the insulating film 31. The barrier metal film 34 can be prevented from peeling off. Subsequently, a copper seed layer is formed on the barrier metal film 34 by a CVD method or a sputtering method, and further a copper plating film is formed on the seed layer by an electrolytic plating method. The inside of the connection hole 32 and the wiring groove 33 is embedded with a copper plating film. Subsequently, the copper plating film, the seed layer, and the barrier metal film 34 in regions other than the connection hole 32 and the wiring groove 33 are removed by CMP to form a second-layer wiring M2 using the copper film as a main conductive material. To do.

  After that, as shown in FIG. 13, for example, an upper layer wiring is formed by the same method as that for the second layer wiring M2. FIG. 13 illustrates a CMIS device in which wirings M3, M4, M5, and M6 from the third layer to the sixth layer are formed. Subsequently, a silicon nitride film 35 is formed on the sixth-layer wiring M 6, and a silicon oxide film 36 is formed on the silicon nitride film 35. These silicon nitride film 35 and silicon oxide film 36 function as a passivation film that prevents moisture and impurities from entering from the outside and suppresses the transmission of α rays.

  Next, the silicon nitride film 35 and the silicon oxide film 36 are processed by etching using a resist pattern as a mask to expose a part of the sixth-layer wiring M6 (bonding pad portion). Here, the resist pattern forming method of the present invention can be applied to the formation of the resist pattern to be used. Subsequently, a bump base electrode 37 made of a laminated film such as a gold film and a nickel film is formed on the exposed wiring M6 of the sixth layer. A bump electrode 38 made of gold, solder, or the like is formed on the bump base electrode 37, whereby the CMIS device is substantially completed. The bump electrode 38 serves as an external connection electrode. Thereafter, the semiconductor wafer SW is cut into individual semiconductor chips and mounted on a package substrate or the like to complete the semiconductor device, but the description thereof is omitted.

  The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

(A)-(c) is an example of the mask pattern for forming a resist pattern. It is a process flow figure explaining the formation method of a resist pattern. (A)-(i) is a figure explaining the formation method of a resist pattern. It is a figure which shows the relationship between the distance from the edge part of a 1st resist pattern, and the reactivity of a 2nd resist and an acid. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of a CMIS device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 1st resist 102 2nd resist 103 Semiconductor substrate 104 Crosslinking layer 101a 1st resist pattern 102a 2nd resist pattern

Claims (19)

Forming a first resist pattern capable of supplying an acid on a substrate;
A second solution containing any one of a water-soluble resin, a water-soluble cross-linking agent, and a mixture thereof that causes a cross-linking reaction in the presence of an acid without dissolving the first resist pattern on the first resist pattern. Forming a resist of
Forming a cross-linked layer at an interface portion of the second resist in contact with the first resist pattern by supplying an acid from the first resist pattern;
A method of forming a second resist pattern by removing a non-crosslinked portion of the second resist,
The step of forming the second resist pattern includes a first development step of developing with water,
After the first development step, a second development step of developing with a solution having a higher solubility in the second resist than water;
And a step of rinsing with water after the second development step.   2. The resist pattern forming method according to claim 1, wherein after the first development step, the second development step is performed after the water is removed.   3. The solution according to claim 1, wherein the solution having higher solubility in water than the second resist is an aqueous solution containing either TMAH (tetramethylammonium hydroxide) or IPA (isopropyl alcohol). Resist pattern forming method.   The resist pattern forming method according to claim 1, wherein the first resist pattern is formed of a resist that generates an acid by heating.   The resist pattern forming method according to claim 1, wherein the first resist pattern is formed of a resist that generates an acid upon exposure.   The resist pattern forming method according to claim 1, wherein the first resist pattern is formed of a resist that generates an acid by exposure and heating.   The resist pattern forming method according to claim 1, wherein the first resist pattern is formed of a resist containing an acid.   The resist pattern formation according to any one of claims 1 to 3, wherein an acid can be supplied by subjecting the first resist pattern to a surface treatment with an acidic liquid or an acidic gas. Method.   The resist pattern forming method according to claim 1, wherein the step of forming the cross-linked layer includes a step of selectively exposing a predetermined region of the first resist pattern.   The resist pattern according to any one of claims 1 to 8, wherein the step of forming the cross-linked layer includes a step of selectively irradiating a predetermined region of the first resist pattern with an electron beam. Forming method.   The resist pattern forming method according to claim 1, wherein the first resist pattern is formed using a resist containing a novolac resin and a naphthoquinone diazide-based photosensitizer.   The resist pattern forming method according to claim 1, wherein the first resist pattern is formed using a chemically amplified resist.   The water-soluble resin is polyacrylic acid, polyvinyl acetal, polyvinyl pyrrolidone, polyvinyl alcohol, polyethyleneimine, styrene-maleic anhydride copolymer, polyvinylamine, polyallylamine, oxazoline group-containing water-soluble resin, water-soluble urethane, water-soluble The water-soluble epoxy, water-soluble epoxy, water-soluble melamine resin, water-soluble urea resin, alkyd resin, sulfonamide and at least one selected from the group consisting of these salts, 2. The resist pattern forming method according to item 1.   The said water-soluble crosslinking agent is at least 1 sort (s) chosen from the group which consists of a melamine type crosslinking agent, a urea type crosslinking agent, and an amino type crosslinking agent, The any one of Claims 1-13 characterized by the above-mentioned. Resist pattern forming method.   The polyvinyl acetal resin is used as the second resist, and the reaction amount with the first resist pattern is controlled by adjusting the degree of acetalization of the polyvinyl acetal resin. 2. The resist pattern forming method according to claim 1.   Using a mixture of a water-soluble resin and a water-soluble crosslinking agent as the second resist and adjusting the amount of the water-soluble crosslinking agent to control the amount of reaction with the first resist pattern The method for forming a resist pattern according to claim 1, wherein:   The resist pattern forming method according to claim 1, wherein the second resist includes at least one plasticizer.   The resist pattern forming method according to claim 1, wherein the second resist contains at least one surfactant. A step of forming a resist pattern on a semiconductor substrate using the method according to any one of claims 1 to 18,
And a step of etching the semiconductor substrate using the resist pattern as a mask.

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