JP2008192676A - Semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the storage capacity of a capacitor in a semiconductor memory device. <P>SOLUTION: The semiconductor memory device is provided with a plurality of memory cells 12 each having a transistor 14 and a capacitor 16, and an element isolation section 22 for executing isolation separation between the memory cells. The element isolation section 22 includes an element isolation insulating film 22 buried in a first trench 6 formed in a first surface of a semiconductor substrate 2. The capacitor 16 includes a capacitor insulating film 34 formed on the side surface and the bottom surface in a second trench 8 formed in the first surface adjacent to the first trench 6, an upper electrode 36 buried on the capacitor insulating film 34 in the second trench 8, and a lower electrode 32 formed in the semiconductor substrate 2 so as to oppose the upper electrode 36. The transistor 14 includes a pair of source/drain layers 42 formed in the first surface adjacent to the second trench 8 and either of which is electrically connected to the lower electrode 32, and a gate electrode 46 disposed on the semiconductor substrate 2 via a gate insulating film 44 between the pair of source/drain layers 42. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor memory device having a capacitor such as a DRAM (Dynamic Random Access Memory) cell that can be manufactured with good consistency with a logic process.

  As a conventional semiconductor memory device, a DRAM in which each memory cell includes one transistor and one capacitor (or capacitor) is known as a memory suitable for high integration. Particularly in recent years, system LSIs in which DRAM and logic circuits are integrated on the same semiconductor chip to improve system performance have been put into practical use. However, as the design rule is reduced, a complicated process for forming a capacitor having a three-dimensional structure such as a trench type or a stack type is used in order to secure the capacitor capacity of the DRAM memory cell. As a result, there is a problem that the process consistency between the DRAM memory cell process and the logic process is deteriorated, the development period and the manufacturing period are prolonged, the yield is difficult to improve, and the manufacturing cost is increased.

  From this point of view, a DRAM cell structure capable of forming a DRAM capacitor structure with good consistency with a desired logic process has been proposed (FIGS. 3G to 3R of Patent Document 1). This DRAM cell has an element isolation insulating film (field insulating film) disposed on the upper surface of a semiconductor substrate and having a recess (cavity) formed in the upper portion thereof, and a side wall portion of the semiconductor substrate is exposed in the recess. The capacitor of the DRAM cell extends to the side wall portion exposed in the recess. As a result, the effective area of the capacitor can be increased to increase the capacitance. Further, the gate insulating film is used as a capacitor insulating film, and a gate electrode material such as polysilicon is used as a plate electrode material. Further, a field insulating film etching process using a mask material for forming the concave portion and an ion implantation for adjusting a threshold value of the capacitor portion using the same mask material as necessary are added to the logic process. As a result, a DRAM cell can be formed with good consistency with the logic process.

Other examples of the background art of the present invention include the following. Patent Document 2 discloses a semiconductor memory device including a memory region in which a memory cell transistor and a trench capacitor are disposed. Patent Document 3 discloses a semiconductor device including an isolation trench formed in a semiconductor substrate, an isolation insulating film embedded in the isolation trench, and a capacitor trench formed adjacent to the isolation trench. However, since the capacitor trench is completely formed in a separate process from the element isolation trench, the manufacturing process is increased with respect to Patent Document 1.
JP-T-2004-527901 International Publication No. 03/069675 Pamphlet JP 2004-235469 A

  SUMMARY OF THE INVENTION An object of the present invention is to increase the storage capacity of a capacitor in a semiconductor memory device having a plurality of memory cells each having a transistor and a capacitor, and to prevent a decrease in device reliability associated therewith.

  A first aspect of the present invention is a semiconductor memory device comprising a plurality of memory cells each having a transistor and a capacitor, and an element isolation part for isolating the memory cells, wherein the element isolation part is a semiconductor An isolation insulating film embedded in a first trench formed in a first surface of the substrate, wherein the capacitor is in a second trench formed in the first surface adjacent to the first trench; A capacitor insulating film formed on the side and bottom surfaces of the semiconductor substrate, an upper electrode embedded on the capacitor insulating film in the second trench, and a lower side located in the semiconductor substrate so as to face the upper electrode A pair of source / drain layers formed in the first surface adjacent to the second trench and one of which is electrically connected to the lower electrode. , Characterized in that it comprises a gate electrode disposed on the semiconductor substrate via a gate insulating film with the pair of source / drain layers.

  According to a second aspect of the present invention, there is provided a semiconductor memory device comprising a plurality of memory cells each having a transistor and a capacitor, and an element isolation part for isolating the memory cells, wherein the element isolation part is a semiconductor An isolation insulating film embedded in the bottom of the first and second trenches formed adjacent to each other in the first surface of the substrate; and the capacitor is disposed on a side surface of the first and second trenches. A capacitor insulating film formed, an upper electrode embedded on the element isolation insulating film and the capacitor insulating film in the first and second trenches, and a position in the semiconductor substrate so as to face the upper electrode The transistor comprises a pair of source / sources formed in the first surface adjacent to the second trench and one electrically connected to the lower electrode. And rain layer, characterized in that it comprises a gate electrode disposed on the semiconductor substrate via a gate insulating film with the pair of source / drain layers.

  A third aspect of the present invention is a semiconductor memory device comprising a plurality of memory cells each having a transistor and a capacitor, and an element isolation part for isolating the memory cells, wherein the element isolation part is a semiconductor An isolation insulating film embedded in a first trench formed in a first surface of the substrate, wherein the capacitor is in a second trench formed in the first surface adjacent to the first trench; And a capacitor insulating film formed on a side surface and a bottom surface in the region of the first trench on the side close to the second trench, and an upper electrode embedded on the capacitor insulating film in the first and second trenches And a lower electrode positioned in the semiconductor substrate to face the upper electrode, wherein the transistor is formed in the first surface adjacent to the second trench, and And a pair of source / drain layers electrically connected to the lower electrode, and a gate electrode disposed on the semiconductor substrate via a gate insulating film between the pair of source / drain layers. It is characterized by.

  According to a fourth aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising: a plurality of memory cells each having a MIS (Metal-Insulator-Semiconductor) transistor and a capacitor; and an element isolation portion for isolating the memory cells. A step of forming first and second trenches adjacent to each other in a first surface of a semiconductor substrate, a step of embedding an element isolation insulating film in the first and second trenches, and the second trench Removing a portion of the element isolation insulating film in a predetermined region in the substrate, forming a capacitor insulating film on the predetermined region in the second trench, and on the capacitor insulating film in the second trench. And embedding a capacitor upper electrode.

  According to a fifth aspect of the present invention, there is provided a memory cell unit including a plurality of memory cells each having a MIS (Metal-Insulator-Semiconductor) transistor and a capacitor, and a first element isolation unit that isolates the memory cells. A logic part including a plurality of semiconductor elements and a second element isolation part that partitions the semiconductor elements, and a method for manufacturing a semiconductor memory device, corresponding to the first and second element isolation parts Forming a mask layer having an opening for forming a trench on the first surface of the semiconductor substrate; and forming a resist film covering the logic portion and exposing the memory cell portion on the mask layer. Using the mask layer and the resist film as a mask, performing isotropic etching on the portion of the first surface corresponding to the first element isolation portion, After removing the resist film, anisotropic etching is performed on a portion of the first surface corresponding to the first and second element isolation portions, using the mask layer as a mask, and the first and second elements Forming a first trench and a second trench corresponding to the isolation portion; embedding an element isolation insulating film in the first trench; and the element isolation insulation in a predetermined region in the first trench. Removing a film portion; forming a capacitor insulating film on the predetermined region in the first trench; and embedding a capacitor upper electrode on the capacitor insulating film in the first trench. It is characterized by comprising.

  Furthermore, the embodiments of the present invention include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, when an invention is extracted by omitting some constituent elements from all the constituent elements shown in the embodiment, when the extracted invention is carried out, the omitted part is appropriately supplemented by a well-known common technique. It is what is said.

  According to the present invention, in a semiconductor memory device having a plurality of memory cells each having a transistor and a capacitor, it is possible to increase the storage capacity of the capacitor and to prevent a decrease in device reliability associated therewith.

  The inventors conducted research on the DRAM disclosed in Patent Document 1 in the course of development of the present invention. As a result, the following findings were obtained.

  FIG. 1 is a cross-sectional view schematically showing one memory cell of a memory cell portion MCS and one transistor of a logic portion LGS of a DRAM disclosed in Patent Document 1.

  The logic unit LGS includes a plurality of semiconductor elements such as the transistor 170 and an element isolation unit 172 that partitions the semiconductor elements. The element isolation portion 172 includes a trench 174 formed in the surface of the semiconductor substrate 102 and an element isolation insulating film 176 embedded therein.

  The memory cell unit MCS includes a plurality of memory cells 112 each having a MOS transistor 114 and a capacitor 116, and an element isolation unit 122 that isolates the memory cells 112 from each other. The element isolation part 122 includes a trench 124 formed in the surface of the N-type well 104 of the semiconductor substrate 102 and an element isolation insulating film 126 embedded therein.

  The portion of the element isolation insulating film 126 adjacent to the MOS transistor 114 is removed by etching so that a certain film thickness remains at the bottom, and a recess is formed. An upper electrode 136 of the capacitor 116 is disposed from the recess toward the MOS transistor 114 via the capacitor insulating film 134. Further, a P-type impurity diffusion layer functioning as the lower electrode 132 is formed in the semiconductor substrate 102 so as to face the upper electrode 136.

  On the other hand, MOS transistor 114 includes a pair of P-type source / drain layers 142 formed in the surface of N-type well 104 adjacent to trench 124. Between the source / drain layers 142, a gate electrode 146 is disposed on the N-type well 104 via a gate insulating film 144. One of the source / drain layers 142 is electrically connected to the lower electrode 132 of the capacitor 116. The other of the source / drain layers 142 is electrically connected to the bit line BL through a contact layer. Gate electrode 146 is electrically connected to word line WL.

  That is, in this DRAM cell, the side surface of the element isolation trench is also used as a part of the capacitor so as to increase the storage capacity of the capacitor. In this case, since a trench of STI (Shallow Trench Isolation) is used, a trench capacitor can be formed using a logic process. However, if the DRAM cell is further miniaturized, it becomes difficult to secure the capacitor area. In addition, when RIE (Reactive Ion Etching) is used for etching the element isolation insulating film, element characteristics and yield may be impaired due to damage to the capacitor formation surface and the like. On the other hand, when only wet etching is used, the element isolation insulating film is also etched in the lateral direction, so that the etching region is widened and the miniaturization of the device is limited.

  In addition, since this DRAM cell is limited to the STI process of the logic part to be embedded, if the STI trench used for the logic part is too shallow, it is difficult to secure a sufficient storage capacity as a memory cell. On the other hand, if the trench depth required for the memory cell portion is set, the trench in the logic portion is also deepened, and it is necessary to match the influence on the manufacturing process margin and device characteristics. Therefore, the development efficiency is poor, and in the worst case, the yield and device performance may be deteriorated. Further, since the portion from the substrate surface to the side surface of the trench is used as the capacitor surface, the edge of the opening end of the trench is included in the capacitor region. At this time, depending on the logic process to be used, the edge of the opening end of the trench has a steep angle, so that the breakdown voltage of the capacitor is deteriorated due to electric field concentration at this edge.

  Hereinafter, an embodiment of the present invention configured based on such knowledge will be described with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

(First embodiment)
FIG. 2 is a cross-sectional view schematically showing one memory cell of the DRAM (semiconductor memory device) according to the first embodiment of the present invention. FIG. 3 is a plan view schematically showing a state in which an etching mask is combined with a memory cell portion including a plurality of memory cells of the DRAM according to the first embodiment. A portion surrounded by a broken line 1MC in FIG. 3 corresponds to one memory cell shown in FIG.

  This DRAM includes a plurality of memory cells 12 each having a MOS transistor 14 and a capacitor 16 which are typical examples of MIS (Metal-Insulator-Semiconductor) transistors, and an element isolation unit 22 for isolating the memory cells 12 from each other. . As shown in FIG. 3, along each bit line BL, a configuration in which two memory cells 12 are arranged back to back around the element isolation portion 22, and two memory cells between the element isolation portions 22. 12 are arranged alternately so as to share the bit line contact layer 43.

  The element isolation portion 22 includes a first trench 6 formed in the surface of the N-type well 4 of the semiconductor substrate 2 and an element isolation insulating film 26 embedded therein. The structure of the element isolation part 22, for example, the depth of the first trench 6 and the material of the element isolation insulating film 26 are set to the same specifications as those of the element isolation part in the logic part (the logic part is not shown in FIG. It is substantially the same as the logic part LGS shown in FIG. 1).

  The capacitor 16 is formed by utilizing the side surface and the bottom surface of the second trench 8 formed in the surface of the N-type well 4 adjacent to the first trench 6. That is, the capacitor insulating film 34 is formed on the side surface and the bottom surface in the second trench 8. The upper electrode 36 of the capacitor 16 is embedded on the capacitor insulating film 34 in the second trench 8. A P-type impurity diffusion layer that functions as the lower electrode 32 of the capacitor 16 is formed in the semiconductor substrate 2 so as to face the upper electrode 36. As disclosed in Patent Document 1, the lower electrode 32 of the capacitor 16 is originally constituted by a channel region of a MOS capacitor. Here, a channel portion whose threshold value is adjusted to increase the margin as a capacitor operation is intended, that is, a configuration in which a diffusion layer having the same conductivity type as the channel is formed in the channel portion is taken as an example.

  On the other hand, the MOS transistor 14 includes a pair of P-type source / drain layers 42 formed in the surface of the N-type well 4 adjacent to the second trench 8. Between the source / drain layers 42, a gate electrode 46 is disposed on the N-type well 4 via a gate insulating film 44. One of the source / drain layers 42 is electrically connected to the lower electrode 32 of the capacitor 16. The other of the source / drain layers 42 is electrically connected to the bit line BL via the contact layer 43. The gate electrode 46 is electrically connected to the word line WL.

  In the present embodiment, the semiconductor substrate 2 is made of silicon. It is preferable in terms of process cost that the capacitor insulating film 34 and the gate insulating film 44 are configured using a common silicon oxide film. For example, the thickness of the silicon oxide film is set to about 1.5 nm to 7 nm (preferably about 2.5 nm to 4 nm) in the normal logic process of the generation of 130 nm to 180 nm. However, in a logic process having a high breakdown voltage transistor such as a liquid crystal driver, the upper limit is considered to be about 13 nm. The upper electrode 36 of the capacitor 16 and the gate electrode 46 of the MOS transistor 14 are made of a common polysilicon material doped with impurities, and these are formed together in the same process.

  4 to 7 are cross-sectional views showing the main parts of the steps of the DRAM manufacturing method shown in FIGS. 4 to 7 show a cross section of a portion along the line IV-IV in FIG.

  First, as shown in FIG. 4, first and second trenches 6 and 8 are formed adjacent to each other in the surface of the N-type well 4 of the semiconductor substrate 2. Then, the insulating films 26 and 28 are embedded in the first and second trenches 6 and 8. These steps can be performed in a known manner simultaneously with the step of forming the element isolation portion in the logic portion (not shown). In this case, the first and second trenches 6 and 8 are set to have the same depth as the trench of the element isolation part in the logic part. In other words, the consistency with the logic process is enhanced by forming the logic part by the same process as the element isolation part.

  Next, as shown in FIG. 5, a mask layer 52 having an opening 53 (see also FIG. 3) only at a position corresponding to the second trench 8 is formed on the semiconductor substrate 2. The mask layer 52 completely covers not only the portion of the memory cell portion other than the second trench 8 (the portion corresponding to the MOS transistor 14 and the first trench 6), but also the logic portion. Then, using the mask layer 52 as a mask, wet etching or RIE is performed to completely remove the insulating film 28 in the second trench 8.

At this time, since the second trench 8 has a structure isolated in the element region in this embodiment, only the insulating film 28 in the second trench 8 can be selectively removed even by wet etching. When wet etching is used, there is no risk of RIE damage being applied to the second trench 8 unlike in the case of RIE, so that an effect of improving problems such as generation of crystal defects and deterioration of capacitor leakage characteristics can be expected. . Further, as the mask layer 52, a hard mask material (SiN, SiO ₂ , polysilicon, or the like) that can withstand the etching of the insulating film 28 can be used as appropriate in addition to the resist.

  Next, as shown in FIG. 6, P-type carrier impurities are introduced into the semiconductor substrate 2 through the second trench 8. Thereby, a P-type impurity diffusion layer functioning as the lower electrode 32 of the capacitor 16 is formed in the N-type well 4 corresponding to the side surface and the bottom surface of the second trench 8. Next, a capacitor insulating film 34 is formed on the side and bottom surfaces in the second trench 8, and a gate insulating film 44 is formed on the surface of the N-type well 4 corresponding to the MOS transistor 14. The capacitor insulating film 34 and the gate insulating film 44 can be made of the same film or different films suitable for the respective use conditions. In addition, the capacitor insulating film 34 and the gate insulating film 44 are the same film as the gate insulating film of the transistor in the logic portion, so that consistency with the logic process is improved.

  Next, as shown in FIGS. 6 to 7, after an electrode material layer 56 such as polysilicon is deposited on the semiconductor substrate 2, the electrode material layer 56 is patterned. As a result, the upper electrode 36 of the capacitor 16 is embedded on the capacitor insulating film 34 in the second trench 8, and the gate electrode 46 is formed corresponding to the MOS transistor 14. Next, using the gate electrode 46 and the like as a mask, P-type carrier impurities are introduced into the semiconductor substrate 2 to form the P-type source / drain layer 42 in a self-aligning manner.

  As described above, in the first embodiment, the STI structure (also referred to as the dummy STI structure) 8 and 28 is once formed in the memory cell by using the STI process, and then the insulating film 28 having this STI structure is entirely formed. Remove. Then, by forming the capacitor insulating film 34 and the upper electrode 36 in the trench 8 of the STI structures 8 and 28, both side surfaces and the bottom surface of the trench 8 are utilized as capacitor regions. As a result, a larger capacitor capacity can be secured within the range of the logic process, and an operation margin can be secured and the elements can be miniaturized.

(Second Embodiment)
FIG. 8 is a plan view schematically showing a state in which an etching mask is combined with a memory cell portion including a plurality of memory cells of a DRAM (semiconductor memory device) according to the second embodiment of the present invention. 9 to 12 are cross-sectional views showing the main parts of the steps of the DRAM manufacturing method shown in FIG. A portion surrounded by a broken line 1MC in FIG. 8 corresponds to one memory cell. 9 to 12 show a cross section of a portion along line IX-IX in FIG.

  This DRAM includes a plurality of memory cells 12 each having a MOS transistor 14 and a capacitor 16 which are typical examples of MIS (Metal-Insulator-Semiconductor) transistors, and an element isolation unit 22 for isolating the memory cells 12 from each other. . As shown in FIG. 8, the arrangement of the memory cells 12 in the plan view is similar to that of the first embodiment.

  As shown in FIG. 12, the element isolation part 22 is embedded in the first and second trenches 6 and 8 formed adjacent to each other in the surface of the N-type well 4 of the semiconductor substrate 2 and in the bottom part thereof. Device isolation insulating films 26X and 28X. The element isolation insulating films 26X and 28X exist only at the bottoms of the first and second trenches 6 and 8, and the thickness thereof is set to be as small as possible within the range having the element isolation function. For example, the thickness of the element isolation insulating films 26X and 28X is set to about 50 nm to 200 nm.

  The capacitor 16 is formed using the side surfaces of the first and second trenches 6 and 8 above the element isolation insulating films 26X and 28X in the first and second trenches 6 and 8. That is, the capacitor insulating film 34 is formed on the side surfaces in the first and second trenches 6 and 8 and on the surface of the element region corresponding to the capacitor region outside the trenches. In the first and second trenches 6 and 8, the upper electrode 36 of the capacitor 16 is embedded on the element isolation insulating film 26 and the capacitor insulating film 34. In addition, a P-type impurity diffusion layer functioning as the lower electrode 32 of the capacitor 16 is formed in the semiconductor substrate 2 as necessary so as to face the upper electrode 36. The portion of the lower electrode (P-type impurity diffusion layer) 32 on the side surface of the first trench sandwiched between the first and second trenches 6 and 8 is below the surface of the element region as the capacitor region sandwiched between both trenches. The MOS transistor 14 is electrically connected to the electrode 32 and the lower electrode 32 that surrounds the side surfaces of the second trench 8.

  On the other hand, the MOS transistor 14 includes a pair of P-type source / drain layers 42 formed in the surface of the N-type well 4 adjacent to the second trench 8. Between the source / drain layers 42, a gate electrode 46 is disposed on the N-type well 4 via a gate insulating film 44. One of the source / drain layers 42 is electrically connected to the lower electrode 32 of the capacitor 16. The other of the source / drain layers 42 is electrically connected to the bit line BL via the contact layer 43. The gate electrode 46 is electrically connected to the word line WL.

  In manufacturing the DRAM, first, the structure shown in FIG. 9 is formed by the STI process described with reference to FIG. 4 of the first embodiment. That is, the first and second trenches 6 and 8 are formed adjacent to each other in the surface of the N-type well 4 of the semiconductor substrate 2, and the insulating films 26 and 28 are formed in the first and second trenches 6 and 8. Embed.

  Next, as shown in FIG. 10, a mask layer 52 </ b> X having an opening 53 </ b> X (see also FIG. 8) at a position corresponding to a wide range including the first and second trenches 6 and 8 is formed on the semiconductor substrate 2. . The mask layer 52X completely covers not only the portions other than the first and second trenches 6 and 8 (such as portions corresponding to the MOS transistor 14) of the memory cell portion but also the logic portion. Then, etching is performed using the mask layer 52X as a mask, and the upper portions of the insulating films 26 and 28 in the first and second trenches 6 and 8 are removed, so that the inside of the first and second trenches 6 and 8 is removed. The insulating films 26X and 28X are left at the bottom.

  Next, as shown in FIG. 11, a P-type carrier impurity is introduced into the semiconductor substrate 2 through the first and second trenches 6 and 8 as necessary, and the lower side of the capacitor 16 is introduced into the N-type well 4. A P-type impurity diffusion layer functioning as the electrode 32 is formed. Next, a capacitor insulating film 34 is formed on the side surfaces in the first and second trenches 6 and 8 and on the surface of the element region corresponding to the capacitor region outside the trenches, and the N-type well corresponding to the MOS transistor 14. A gate insulating film 44 is formed on the surface of 4.

  Next, as shown in FIGS. 11 to 12, the electrode material layer 56 such as polysilicon is processed, and the upper electrode 36 of the capacitor 16 is formed on the capacitor insulating film 34 in the first and second trenches 6 and 8. And a gate electrode 46 corresponding to the MOS transistor 14 is formed. Next, using the gate electrode 46 and the like as a mask, P-type carrier impurities are introduced into the semiconductor substrate 2 to form the P-type source / drain layer 42 in a self-aligning manner.

  As described above, in the second embodiment, the upper portions of the insulating films 26 and 28 are removed from both the STI structures 6 and 26 and the STI structures (which can be referred to as dummy STI structures) 8 and 28. Then, by forming the capacitor insulating film 34 and the upper electrode 36 in the trenches 6 and 8, the side surfaces of the trenches 6 and 8 are used as capacitor regions. In this case, since the entire upper portions of the insulating films 26 and 28 are removed together, the opening 53X of the mask layer 52X is considerably large unlike the first embodiment (see FIG. 8). Therefore, the patterning of the mask layer 52X in the second embodiment is easier than the fine patterning in the first embodiment.

  In order to maintain a function as element isolation (isolation between storage nodes of adjacent memory cells), it is necessary to leave an element isolation insulating film at least at the bottom of the first trench 6. In this embodiment, since the insulating films 26 and 28 in the trenches 6 and 8 are etched in the same process, an element isolation insulating film remains at the bottom of the second trench 8, and this portion is used as a capacitor region. Not available. Therefore, if the insulating film 28 of the second trench 8 is completely removed using the mask layer pattern of the first embodiment, this portion can also be used as a capacitor region.

(Third embodiment)
FIG. 13 is a plan view schematically showing a state in which an etching mask is combined with a memory cell portion including a plurality of memory cells of a DRAM (semiconductor memory device) according to the third embodiment of the present invention. 14 to 17 are cross-sectional views showing the main parts of the steps of the DRAM manufacturing method shown in FIG. A portion surrounded by a broken line 1MC in FIG. 13 corresponds to one memory cell. 14 to 17 show a cross section of a portion along line XIV-XIV in FIG.

  This DRAM includes a plurality of memory cells 12 each having a MOS transistor 14 and a capacitor 16 which are typical examples of MIS (Metal-Insulator-Semiconductor) transistors, and an element isolation portion 22Y for isolating the memory cells 12 from each other. . As shown in FIG. 13, the element isolation part 22Y is considerably longer than the element isolation part 22 of the first and second embodiments. Along the bit lines BL, the long element isolation portions 22Y and the configuration in which the two memory cells 12 share the bit line contact layer 43 between the element isolation portions 22Y are alternately arranged. In the adjacent bit lines BL, the long element isolation portions 22Y and the two memory cells 12 are alternately arranged.

  As shown in FIG. 17, the element isolation portion 22 </ b> Y includes a first trench 6 formed in the surface of the N-type well 4 of the semiconductor substrate 2 and an element isolation insulating film 26 embedded therein. In the region 7 near the MOS transistor 14 in the first trench 6, the portion of the element isolation insulating film 26 is removed, and this region 7 is used as a capacitor region as described below. In other respects, the structure of the element isolation part 22Y, for example, the depth of the first trench 6 and the material of the element isolation insulating film 26 are the same as the element isolation part in the logic part (not shown).

  The capacitor 16 is formed using the side surface and the bottom surface of the region 7 in the first trench 6 and the second trench 8 formed in the surface of the N-type well 4 adjacent to the region 7. That is, the capacitor insulating film 34 is formed on the side surface and the bottom surface in the region 7 and the second trench 8. The upper electrode 36 of the capacitor 16 is embedded on the capacitor insulating film 34 in the region 7 and the second trench 8. Further, a P-type impurity diffusion layer functioning as the lower electrode 32 of the capacitor 16 is formed in the semiconductor substrate 2 as necessary so as to face the upper electrode 36.

  On the other hand, the MOS transistor 14 includes a pair of P-type source / drain layers 42 formed in the surface of the N-type well 4 adjacent to the second trench 8. Between the source / drain layers 42, a gate electrode 46 is disposed on the N-type well 4 via a gate insulating film 44. One of the source / drain layers 42 is electrically connected to the lower electrode 32 of the capacitor 16. The other of the source / drain layers 42 is electrically connected to the bit line BL via the contact layer 43. The gate electrode 46 is electrically connected to the word line WL.

  In manufacturing the DRAM, first, the structure shown in FIG. 14 is formed by the STI process described with reference to FIG. 4 of the first embodiment. That is, the first and second trenches 6 and 8 are formed adjacent to each other in the surface of the N-type well 4 of the semiconductor substrate 2, and the insulating films 26 and 28 are formed in the first and second trenches 6 and 8. Embed.

  Next, as shown in FIG. 15, a mask layer 52 </ b> Y having an opening 53 </ b> Y (see also FIG. 13) only on the position corresponding to the range from the region 7 of the first trench 6 to the second trench 8 is formed on the semiconductor substrate 2. To form. The mask layer 52Y is not only a portion other than the range from the region 7 of the first trench 6 to the second trench 8 in the memory cell portion (a portion corresponding to the MOS transistor 14 and the remaining portion of the first trench 6). The logic part is also completely covered. Then, etching is performed using the mask layer 52Y as a mask, and the portion of the insulating film 26 corresponding to the region 7 and the insulating film 28 in the second trench 8 are completely removed.

  Next, as shown in FIG. 16, a P-type carrier impurity is introduced into the semiconductor substrate 2 from the region 7 of the first trench 6 through the second trench 8 as necessary, and a capacitor is introduced into the N-type well 4. A P-type impurity diffusion layer functioning as the lower electrode 32 of 16 is formed. Next, a capacitor insulating film 34 is formed on the side surface 7 and the bottom surface in the region 7 of the first trench 6 and the second trench 8, and a gate insulating film 44 is formed on the surface of the N-type well 4 corresponding to the MOS transistor 14. Form.

  Next, as shown in FIGS. 16 to 17, the electrode material layer 56 such as polysilicon is processed to form the capacitor 16 on the capacitor insulating film 34 in the region 7 of the first trench 6 and the second trench 8. The upper electrode 36 is embedded and a gate electrode 46 is formed corresponding to the MOS transistor 14. Next, using the gate electrode 46 and the like as a mask, P-type carrier impurities are introduced into the semiconductor substrate 2 to form the P-type source / drain layer 42 in a self-aligning manner.

  As described above, in the third embodiment, not only the STI structure (which can be called a dummy STI structure) 8 and 28 but also the region 7 of the element isolation STI structures 6 and 26 adjacent thereto are insulated. Remove all the film down to the bottom of the trench. Then, by forming the capacitor insulating film 34 and the upper electrode 36 in these portions, the side surface and the bottom surface of the trench are utilized as a capacitor region in a wider range. As shown in FIG. 13, since the element isolation portion 22Y that isolates the memory cells 12 is long, the range that can be diverted as a capacitor region becomes large.

  In the third embodiment, the region 7 of the STI structures 6 and 26 for element isolation is removed by etching until the insulating film 26 reaches the bottom of the trench 6. However, when the isolation between the storage nodes is impaired, the etching of the insulating film 26 can be suppressed to a shallow depth. This can be easily adjusted by adding a mask pattern.

(Matters common to the first to third embodiments)
According to the first to third embodiments, the effective capacitor region is increased using the dummy STI structure formed in the memory cell portion. Therefore, a sufficient storage capacity can be secured even in the STI process for forming a shallower structure than the conventional one. In the case where the dummy STI structure becomes an isolated structure in the element region, the insulating film of the dummy STI structure can be removed without using the original STI structure, even if wet etching is used. Further, the dummy STI structure can be formed simultaneously with that of the logic portion by the STI process. Therefore, after the dummy STI structure is formed once, the above-described great effect can be obtained only by adding a step of removing the insulating film of the dummy STI structure.

  It is preferable that the distance between the first and second trenches 6 and 8 be as small as possible. This is based not only from the viewpoint of miniaturization but also from the viewpoint of reducing leakage current. 18 and 19 are diagrams schematically showing different configurations in the case where the mutually adjacent surfaces of the two trenches T1 and T2 are used as a capacitor region. Such a situation appears, for example, in the second and third embodiments (the adjacent surfaces of the first and second trenches 6 and 8 are used as the capacitor region).

  In the case of the configuration shown in FIG. 18, the gap between the trenches T1 and T2 is narrow, and the P-type diffusion layer DL functions as the capacitor lower electrode (in the case of the configuration without the P-type diffusion layer DL, it becomes the capacitor lower electrode). All are filled with the depletion layer DP extending from the channel region. In this case, the effective contact area between the capacitor lower electrode on the side surfaces adjacent to each other of the two trenches T1 and T2 and the outer surface of the trench sandwiched between them and the N-type well NW is the gap between the trenches T1 and T2. It becomes below the area of the bottom. On the other hand, in the configuration shown in FIG. 19, the gap between the trenches T1 and T2 is wide and is not completely filled with the depletion layer DP extending from the P-type diffusion layer DL that functions as the capacitor lower electrode. In this case, the contact area between the P-type diffusion layer DL and the N-type well NW is considerably larger than that in the case of FIG. A large contact area causes an increase in junction leakage current. Therefore, the interval between the trenches T1 and T2 is preferably set to be narrow enough to be filled with a depletion layer extending from the P-type diffusion layer formed therein, and more preferably to be filled with a P-type diffusion layer. It is preferable.

(Fourth embodiment)
FIG. 20 is a cross-sectional view schematically showing one memory cell of the memory cell unit MCS and one transistor of the logic unit LGS side by side in a DRAM (semiconductor memory device) according to the fourth embodiment of the present invention.

  The logic unit LGS includes a plurality of semiconductor elements such as the transistor 70 and an element isolation unit 72 that partitions the semiconductor elements. The element isolation portion 72 includes a trench 74 formed in the surface of the semiconductor substrate 2 and an element isolation insulating film 76 embedded therein.

  The memory cell unit MCS includes a plurality of memory cells 12 each having a MOS transistor 14 and a capacitor 16 that are typical examples of MIS (Metal-Insulator-Semiconductor) transistors, and an element isolation unit 22 that isolates the memory cells 12 from each other. It has. The element isolation portion 22 includes a trench 24 formed in the surface of the N-type well 4 of the semiconductor substrate 2 and an element isolation insulating film 26 embedded therein. The trench 24 of the memory cell part MCS is deeper than the trench 74 of the logic part LGS. Further, the angle of the edge 24a at the opening end of the trench 24 on the MOS transistor 14 side is gentle. Desirably, the trench 24 is about 20 nm to 170 nm deeper than the trench 74. Further, the edge 24a of the opening end portion of the trench 24 on the MOS transistor 14 side is formed so that its inner angle is defined by a portion of about 100 degrees to 135 degrees.

  The portion of the element isolation insulating film 26 adjacent to the MOS transistor 14 is removed by etching so that a constant film thickness remains at the bottom, and a recess is formed. A capacitor insulating film 34 is formed in a range from the recess toward the MOS transistor 14 via the edge 24 a of the opening end of the trench 24. Further, the upper electrode 36 of the capacitor 16 is disposed on the capacitor insulating film 34. In addition, a P-type impurity diffusion layer functioning as the lower electrode 32 is formed in the semiconductor substrate 2 so as to face the upper electrode 36 as necessary.

  On the other hand, MOS transistor 14 includes a pair of P-type source / drain layers 42 formed in the surface of N-type well 4 adjacent to trench 24. Between the source / drain layers 42, a gate electrode 46 is disposed on the N-type well 4 via a gate insulating film 44. One of the source / drain layers 42 is electrically connected to the lower electrode 32 of the capacitor 16. The other of the source / drain layers 42 is electrically connected to the bit line BL via the contact layer 43. The gate electrode 46 is electrically connected to the word line WL.

  FIG. 21 is a cross-sectional view showing the main parts of the steps of the DRAM manufacturing method shown in FIG. In this manufacturing method, as shown in FIG. 21, first, openings 83a and 83b for forming trenches corresponding to the element isolation portions 22 and 72 of the memory cell portion MCS and the logic portion LGS are formed, for example, from SiN. A mask layer 82 to be formed is formed on the semiconductor substrate 2. Next, a resist film 84 that covers the logic part LGS and exposes the memory cell part MCS is formed on the mask layer 82. Next, isotropic etching such as CDE (Chemical Dry Etching) is performed on the surface of the semiconductor substrate 2 corresponding to the element isolation portion 22 of the memory cell portion MCS using the mask layer 82 and the resist film 84 as a mask. Thereby, only the surface of the semiconductor substrate 2 corresponding to the element isolation part 22 is dug down in advance to form the recess 86. At this time, due to the function of isotropic etching, the side surface of the recess 86 is inclined downward toward the center.

  Next, after removing the resist film 84, the element isolation portions 22 and 72 of the memory cell portion MCS and the logic portion LGS are formed by a normal STI process (see FIG. 20). That is, using the mask layer 82 as a mask, anisotropic etching is performed on the surface portion of the semiconductor substrate 2 corresponding to the element isolation portions 22 and 72, and the trenches 24 and 74 corresponding to the element isolation portions 22 and 72, respectively. Form. After the formation of the trenches 24 and 74, treatment (wet treatment or heat treatment) for removing damage or rounding the corners of the trench is accompanied depending on the process. Next, the element isolation insulating films 26 and 76 are embedded in the trenches 24 and 74.

  Next, a portion of the element isolation insulating film 26 in a predetermined region in the trench 24 of the memory cell portion MCS is removed to form a recess. Next, if necessary, P-type carrier impurities are introduced into the semiconductor substrate 2 through a predetermined region in the trench 24 to form a P-type impurity diffusion layer functioning as the lower electrode 32 of the capacitor 16 in the N-type well 4. Form. Next, a capacitor insulating film 34 is formed from a predetermined region of the trench 24 toward the MOS transistor 14, and a gate insulating film 44 is formed on the surface of the N-type well 4 corresponding to the MOS transistor 14.

  Next, the upper electrode 36 of the capacitor 16 is formed on the capacitor insulating film 34 (the upper electrode 36 is embedded in a predetermined region of the trench 24), and the gate electrode 46 is formed corresponding to the MOS transistor 14. Next, using the gate electrode 46 and the like as a mask, P-type carrier impurities are introduced into the semiconductor substrate 2 to form the P-type source / drain layer 42 in a self-aligning manner.

  As described above, in the fourth embodiment, the trench 24 of the element isolation part 22 of the memory cell part MCS is deeper than the trench 74 of the element isolation part 72 of the logic part LGS, and the side surface of the former trench 24 is formed. Is used as a capacitor area. As a result, the storage capacity of the capacitor 16 can be increased without impairing the element isolation function of the memory cell unit MCS. Further, the edge 24a of the opening end of the trench 24 on the MOS transistor 14 side, which is used as a capacitor region, is formed so as to have a gentle angle. Thereby, the breakdown voltage of the capacitor 16 can be improved.

  In addition, the structure according to the fourth embodiment only adds a step of performing isotropic etching only on the memory cell portion MCS as shown in FIG. 21 prior to the formation of the trench. Since the steps before and after that can be performed according to the conventional STI process of the logic portion, these effects can be realized without changing the structure and characteristics of the logic portion. However, when the breakdown voltage problem of the capacitor 16 does not occur, the etching performed only on the memory cell portion MCS in FIG. 21 is anisotropic etching, or isotropic (a condition of less than 20 nm can be selected) and anisotropy. Can be applied in combination. According to the latter, it is possible to optimize the increase of the capacitor capacity and the improvement of the capacitor breakdown voltage.

  FIG. 22 is a cross-sectional view schematically showing one memory cell in the memory cell unit MCS and one transistor in the logic unit LGS side by side in a DRAM (semiconductor memory device) according to a modification of the fourth embodiment. In this modification, after forming the trenches 24 and 74 in the memory cell portion MCS and the logic portion LGS, respectively, isotropic etching such as CDE is performed only on the trench 24 of the memory cell portion MCS. In this case, for this reason, not only the depth but also the width of the trench 24 increases, and the difference (so-called conversion difference) from the design dimension on the mask differs from that of the logic portion. However, even in this modification, the memory cell portion can be improved without changing the process and structure of the logic portion.

  As another modified example of the fourth embodiment, a thermal oxide film may be formed on the substrate surface as a method of removing the substrate surface by isotropic etching only with respect to the trench 24 of the memory cell unit MCS. However, in this case, first, a mask layer 82 made of SiN, for example, having an opening 83a for forming a trench corresponding to the element isolation part 22 only in the memory cell part MCS is formed on the semiconductor substrate 2. Then, an oxide film is formed on the surface of the opening 83a by heat treatment in the manner of LOCOS (LOCal Oxidation of Si) oxidation. Thereafter, an opening 83b for forming a trench is formed in the mask layer 82 corresponding to the element isolation portion 72 of the logic portion LGS. Then, the element isolation portions 22 and 72 of the memory cell portion MCS and the logic portion LGS are formed by a normal STI process using the mask layer 82 with the openings 83a and 83b as a mask. The thermal oxide film formed in the opening 83a is preferably removed by etching using the mask layer 82 as a mask before the STI process.

  FIG. 23 is a cross-sectional view showing the main parts of the steps of the DRAM manufacturing method according to still another modification of the fourth embodiment. In this modification, the resist film 84X used for additional etching for forming a capacitor is configured to have an opening 85 that exposes only a portion of the memory cell portion MCS where the capacitor 16 is formed. That is, the resist film 84X covers not only the logic part LGS but also a part other than the capacitor 16 (for example, a part corresponding to the MOS transistor 14) of the memory cell part MCS. Thereby, the part other than the capacitor 16 of the trench 24 of the memory cell part MCS has the same shape as the corresponding part of the trench of the logic part LGS. Further, the transistor 14 of the memory cell portion MCS can be formed with the same specifications as the transistor of the logic portion LGS.

(Items common to the first to fourth embodiments)
According to the first to fourth embodiments, in a DRAM including a plurality of memory cells 12 each having a MOS transistor 14 and a capacitor 16, the storage capacity of the capacitor 16 is increased and the device reliability associated therewith is increased. A decrease can be prevented.

It should be noted that various changes and modifications can be conceived by those skilled in the art within the scope of the idea of the present invention, and it is understood that these changes and modifications are also within the scope of the present invention. . For example, it may be a semiconductor substrate material, a structure or material of an element isolation part, a material of a gate insulating film or a capacitor insulating film (a compound film or composite film of SiO ₂ and SiN, a high dielectric film made of a compound such as Ha or Hf, etc. ), Material of the gate electrode and upper electrode (the surface or the whole of the polysilicon may be silicided, or may be composed of amorphous silicon, metal, etc.), transistor type (in the embodiment, P-MOS) , N-MOS), processes, wiring processes and the like are not limited to specific ones, and can be variously changed. Furthermore, a plurality of dummy trenches for increasing the storage capacity may be provided in each memory cell 12.

  In addition, according to the first to fourth embodiments of the present invention, in a DRAM including a plurality of memory cells 12 each having a MOS transistor 14 and a capacitor 16, the storage capacity of the capacitor 16 is increased and accompanying this. Although it has been said that a reduction in the reliability of the device can be prevented, it should be added that the present invention can also be applied to a capacitor used other than the memory cell portion. In this case, it is possible to reduce the pattern area of the capacitor used in other than the memory cell and improve the capacitor reliability. The configuration and the manufacturing method can be applied by replacing the memory cell portion with a capacitor portion other than the memory cell in the first to fourth embodiments of the present invention.

FIG. 10 is a cross-sectional view schematically showing one memory cell in a memory cell portion and one transistor in a logic portion of a DRAM disclosed in Patent Document 1 side by side. 1 is a cross-sectional view schematically showing one memory cell of a DRAM (semiconductor memory device) according to a first embodiment of the present invention. 2 is a plan view schematically showing a state in which an etching mask is combined with a memory cell portion including a plurality of memory cells of the DRAM according to the first embodiment. FIG. FIG. 4 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIGS. 2 and 3. FIG. 4 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIGS. 2 and 3. FIG. 4 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIGS. 2 and 3. FIG. 4 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIGS. 2 and 3. It is a top view which shows roughly the state which combined the etching mask with the memory cell part containing the several memory cell of DRAM (semiconductor memory device) concerning 2nd Embodiment of this invention. FIG. 9 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIG. 8. FIG. 9 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIG. 8. FIG. 9 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIG. 8. FIG. 9 is a cross-sectional view showing the main parts of the steps of a method for manufacturing the DRAM shown in FIG. 8. It is a top view which shows roughly the state which combined the etching mask with the memory cell part containing the several memory cell of DRAM (semiconductor memory device) concerning 3rd Embodiment of this invention. FIG. 14 is a cross-sectional view showing the main parts of steps of a method for manufacturing the DRAM shown in FIG. 13. FIG. 14 is a cross-sectional view showing the main parts of steps of a method for manufacturing the DRAM shown in FIG. 13. FIG. 14 is a cross-sectional view showing the main parts of steps of a method for manufacturing the DRAM shown in FIG. 13. FIG. 14 is a cross-sectional view showing the main parts of steps of a method for manufacturing the DRAM shown in FIG. 13. It is a figure which shows roughly a structure in case the surface where two trenches mutually adjoin is utilized with a capacitor area | region. It is a figure which shows schematically a different structure when the mutually adjacent surface of two trenches is utilized with a capacitor area | region. FIG. 9 is a cross-sectional view schematically showing one memory cell in a memory cell portion and one transistor in a logic portion of a DRAM (semiconductor memory device) according to a fourth embodiment of the present invention. FIG. 21 is a cross-sectional view showing a substantial part of a step of a method for manufacturing the DRAM shown in FIG. 20. FIG. 10 is a cross-sectional view schematically showing one memory cell in a memory cell portion and one transistor in a logic portion side by side in a DRAM (semiconductor memory device) according to a modification of the fourth embodiment. It is sectional drawing which shows the principal part of the process of the manufacturing method of DRAM which concerns on the further another modification of 4th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 2 ... Semiconductor substrate, 4 ... N type well, 6, 8, 24, 74 ... Trench, 12 ... Memory cell, 14 ... MOS transistor, 16 ... Capacitor, 22, 22Y, 72 ... Element isolation part, 26, 26X, 76 ... element isolation insulating film, 32 ... lower electrode, 34 ... capacitor insulating film, 36 ... upper electrode, 42 ... source / drain layer, 44 ... gate insulating film, 46 ... gate electrode, LGS ... logic part, MCS ... memory cell Department.

Claims (5)

A semiconductor memory device comprising: a plurality of memory cells each having a transistor and a capacitor; and an element isolation unit for isolating the memory cells.
The element isolation part includes an element isolation insulating film embedded in a first trench formed in a first surface of a semiconductor substrate,
The capacitor includes a capacitor insulating film formed on a side surface and a bottom surface in the second trench formed in the first surface adjacent to the first trench, and on the capacitor insulating film in the second trench. An upper electrode embedded in the semiconductor substrate, and a lower electrode located in the semiconductor substrate so as to face the upper electrode,
The transistor includes a pair of source / drain layers formed in the first surface adjacent to the second trench and one of which is electrically connected to the lower electrode, and the pair of source / drain layers. And a gate electrode disposed on the semiconductor substrate with a gate insulating film interposed therebetween. A semiconductor memory device comprising: a plurality of memory cells each having a transistor and a capacitor; and an element isolation unit for isolating the memory cells.
The element isolation part includes an element isolation insulating film embedded in the bottom of the first and second trenches formed adjacent to each other in the first surface of the semiconductor substrate,
The capacitor includes a capacitor insulating film formed on side surfaces in the first and second trenches, and an upper electrode embedded in the element isolation insulating film and the capacitor insulating film in the first and second trenches. And a lower electrode positioned in the semiconductor substrate so as to face the upper electrode,
The transistor includes a pair of source / drain layers formed in the first surface adjacent to the second trench and one of which is electrically connected to the lower electrode, and the pair of source / drain layers. And a gate electrode disposed on the semiconductor substrate with a gate insulating film interposed therebetween. A semiconductor memory device comprising: a plurality of memory cells each having a transistor and a capacitor; and an element isolation unit for isolating the memory cells.
The element isolation part includes an element isolation insulating film embedded in a first trench formed in a first surface of a semiconductor substrate,
The capacitor is formed on a side surface and a bottom surface in a second trench formed in the first surface adjacent to the first trench and in a region of the first trench on a side close to the second trench. A capacitor insulating film, an upper electrode embedded on the capacitor insulating film in the first and second trenches, and a lower electrode positioned in the semiconductor substrate so as to face the upper electrode,
The transistor includes a pair of source / drain layers formed in the first surface adjacent to the second trench and one of which is electrically connected to the lower electrode, and the pair of source / drain layers. And a gate electrode disposed on the semiconductor substrate with a gate insulating film interposed therebetween. A method for manufacturing a semiconductor memory device, comprising: a plurality of memory cells each having a MIS (Metal-Insulator-Semiconductor) transistor and a capacitor; and an element isolation portion for isolating the memory cells.
Forming first and second trenches in the first surface of the semiconductor substrate adjacent to each other;
Embedding an element isolation insulating film in the first and second trenches;
Removing a portion of the element isolation insulating film in a predetermined region in the second trench;
Forming a capacitor insulating film on the predetermined region in the second trench;
Embedding a capacitor upper electrode on the capacitor insulating film in the second trench;
A method of manufacturing a semiconductor memory device, comprising: A memory cell unit including a plurality of memory cells each having a MIS (Metal-Insulator-Semiconductor) transistor and a capacitor; a first element isolation unit for isolating the memory cells; and a plurality of semiconductor elements between the semiconductor elements And a logic part including a second element isolation part that partitions the semiconductor memory device,
Forming a mask layer having an opening for forming a trench corresponding to the first and second element isolation portions on the first surface of the semiconductor substrate;
Forming a resist film on the mask layer that covers the logic part and exposes the memory cell part;
Using the mask layer and the resist film as a mask, performing isotropic etching on the portion of the first surface corresponding to the first element isolation portion,
After removing the resist film, anisotropic etching is performed on the first surface portion corresponding to the first and second element isolation portions using the mask layer as a mask, and the first and second elements Forming first and second trenches corresponding to the isolation parts,
Embedding an element isolation insulating film in the first and second trenches;
Removing a portion of the element isolation insulating film in a predetermined region in the first trench;
Forming a capacitor insulating film on the predetermined region in the first trench;
Embedding a capacitor upper electrode on the capacitor insulating film in the first trench;
A method of manufacturing a semiconductor memory device, comprising:

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