JP2008192201A - Ddrsdram and data storage system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DDRSDRAM which does not need a delay circuit and is suitable for high-speed transfer and a data storage system using such DDRSDRAM. <P>SOLUTION: The DDRSDRAM1 of this invention has a phase adjustment circuit 3a which shifts a phase of a strobe signal to a data signal by only predetermined angle α, and when data is read, outputs the data signal and the strobe signal by shifting the phase of the strobe signal to the data signal only by a predetermined angle α by the phase adjustment circuit 3a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a DDR SDRAM that outputs a strobe signal and a data signal by shifting the phase of the data signal with respect to the strobe signal when data is read. The present invention also relates to a data storage system that stores data using the DDR SDRAM.

  FIG. 7 is a block diagram showing a configuration of a data storage system using a DDR SDRAM according to the background art. FIG. 8 is a diagram showing each configuration of the DDR SDRAM and the data control circuit. FIG. 9 is a diagram showing a time chart of the data storage system. 9A shows the case of a write (WRITE) operation to the DDR SDRAM of the data control circuit, and FIG. 9B shows the case of a read (READ) operation from the DDR SDRAM of the data control circuit.

  One of the storage elements is a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) having a high-speed data transfer function called a double data rate (DDR) mode. As shown in FIG. 7, the data storage system 100 using the DDR SDRAM writes a plurality of DDR SDRAMs 101 (101-1 to 101 -X) storing binary data, and reads data from the DDR SDRAM 101. And a data control circuit 102. Each DDR SDRAM 101-1 to 101-X includes a plurality of strobe lines DQS (DQS-1 to DQS-X) for transmitting strobe signals and a plurality of clock lines CLK (CLK-1 to CLK-X) for transmitting clock signals. The data control circuit 102 is connected to each other, and is connected to the data control circuit 102 through an N-bit data bus DQ for transmitting a data signal. FIG. 8 shows one DDR SDRAM 101 because each DDR SDRAM 101 has the same configuration and data is read and written from the data control circuit 102 by the same operation. Moreover, when referring generically, it shows with the reference symbol which abbreviate | omitted the suffix, and when referring to an individual structure, it shows with the reference symbol which added the suffix.

  The DDR SDRAM 101 includes a data transfer circuit 110 and a plurality of memory cells (not shown) that store data. As shown in FIG. 8, the data transfer circuit 110 of the DDR SDRAM 101 includes a clock adjustment circuit 111, an amplifier 112 that amplifies a strobe signal and outputs the strobe signal to the strobe line DQS, and an input line Din (Din1, Din1, Din1, Output flip-flop (hereinafter abbreviated as “output FF”) 113 (113a, 113b), a multiplexer 114 for multiplexing the output of the output FF 113, and a multiplexer An amplifier 115 that amplifies the output of 114 and outputs it to the data line DQ, and latches the data signal transferred from the data control circuit 102 via the data line DQ and outputs the memory via the output lines Dout (Dout1, Dout2). Input to output to cell Use flip-flops (hereinafter abbreviated as "input FF".) 116 (116a, 116 b) and configured with a. In FIG. 8, an output FF 113 and an input FF 116 for 1 bit are shown, and the other parts are omitted because they have the same configuration.

  The clock adjustment circuit 111 includes a PLL, for example, and is a circuit that generates an operation clock signal Clk for the output FF 113 and the multiplexer 114. The generated operation clock Clk is output as an operation clock to the output FF 113 and the multiplexer 114, and is also amplified by the amplifier 112 and output as a strobe signal to the strobe line DQS. The operation clock signal Clk is directly input to the output FF 113a, and the operation clock signal Clk is inverted and input to the output FF 113b. The strobe signal input from the data control circuit 102 via the strobe line DQS is input to the input FF 116. The strobe signal is input as it is to the input FF 116a, and the strobe signal is inverted and input to the input FF 116b. Since the clock adjustment circuit 111 further requires a propagation time for the strobe signal or data signal input to the terminal of the DDR SDRAM 101 to reach the input FF 116, the clock adjustment circuit 111 receives the strobe signal or data signal input to the terminal. The clock input from the data control circuit 102 via the clock line CLK is adjusted and the operation clock is output to the input FF 116 so that the input FF 116 operates at the timing of reaching the input FF 116.

  The data control circuit 102 includes a clock adjustment circuit 121, an amplifier 122 that amplifies the strobe signal and outputs the strobe signal to the strobe line DQS, and a delay that shifts the phase of the strobe signal from the DDRSDAM 101 via the strobe line DQS by 90 degrees. A circuit 123, an output FF 124 (124a, 124b) for latching data to be transferred input from an unillustrated circuit via the input line Din (Din1, Din2), and a multiplexer 125 for multiplexing the output of the output FF 124 And an amplifier 126 that amplifies the output of the multiplexer 125 and outputs the amplified signal to the data line DQ, and latches the data signal transferred from the DDR SDRAM 101 via the data line DQ and outputs the circuit via the output lines Dout (Dout1, Dout2). Go out Input FF127 (127a, 127b) which constituted a. In FIG. 8, an output FF 124 and an input FF 127 for one bit are illustrated, and others are omitted because they have the same configuration.

  The clock adjustment circuit 121 includes, for example, a PLL, and generates an operation clock signal Clk0 for the output FF 124 and the multiplexer 125, and generates a clock signal Clk90 whose phase is shifted by 90 degrees with respect to the operation clock signal Clk0. Circuit. The generated operation clock signal Clk0 is output as an operation clock to the output FF 124 and the multiplexer and to the clock line CLK. The operation clock signal Clk0 is directly input to the output FF 124a, and the operation clock signal Clk0 is inverted and input to the output FF 124b. Then, the generated clock signal Clk90 is amplified by the amplifier 122 and output to the strobe line DQS as a strobe signal. The strobe signal input from the DDR SDRAM 101 via the strobe line DQS is input to the input FF 127 by the delay circuit 123 with a phase delayed by 90 degrees. The strobe signal is directly input to the input FF 127a, and the strobe signal is inverted and input to the input FF 127b.

  In the data storage system 100 having such a configuration, the data control circuit 102 functions as a master, the DDR SDRAM 101 functions as a slave, and data is transferred to the DDR SDRAM 101 under the control of the data control circuit 102. Read and write.

  That is, in the write operation (WRITE operation) in which the data control circuit 102 writes data to the DDR SDRAM 101, first, the clock adjustment circuit 121 of the data control circuit 102 is 90 degrees out of phase with the operation clock signal Clk0 and the operation clock signal Clk0. The (delayed) clock signal Clk90 is generated, and the operation clock signal Clk0 is input, whereby the output FF 124 latches the data input from the circuit via the input line Din, and passes through the multiplexer 125 and the amplifier 126. The data signal is output to the data line DQ, and the clock signal Clk90 is output to the strobe line DQS via the amplifier 122. Therefore, as shown in FIG. 9A, in the DDR SDRAM 101, the data signal input to the DDR SDRAM 101 via the data line DQ is phase-shifted with respect to this data signal via the strobe line DQS in the input FF 116. Latched by the rising and falling edges of the strobe signal shifted (delayed) by 90 degrees, it is determined whether the data signal is 0 or 1, and data is written into the memory cell via the output line Dout.

  On the other hand, in a read operation (READ operation) in which the data control circuit 102 reads data from the DDR SDRAM 101, first, the clock adjustment circuit 111 of the DDR SDRAM 101 generates the operation clock signal Clk, and the operation clock signal Clk is input for output. The FF 113 latches data input from the memory cell via the input line Din, and a data signal is output to the data line DQ via the multiplexer 114 and the amplifier 115, and an operation clock signal Clk is supplied via the amplifier 112. Are output to the strobe line DQS. For this reason, as shown in FIG. 9B, in the data control circuit 102, the data signal input to the data control circuit 102 via the data line DQ and the data control circuit 102 input to the data control circuit 102 via the strobe line DQS. The strobe signal has the same phase. Therefore, the phase of the input strobe signal is delayed by 90 degrees by the delay circuit 123. Therefore, the data signal input to the data control circuit 102 can be latched by the rising edge and the falling edge of the strobe signal whose phase is delayed by 90 degrees in the input FF 127, and whether the data signal is 0 or 1 Then, the data is output to the circuit via the output line Dout.

  In the data storage system 100, data transfer is performed in this way, and data writing and reading in the DDR SDRAM 101 are executed.

On the other hand, as a background art related to data transfer, there is, for example, Patent Document 1. This patent document 1 discloses a data transfer circuit used as an interface for connecting a host processor in a personal computer and a storage device such as a hard disk drive or a CD-ROM. The data transfer circuit described in Patent Document 1 is a data transfer circuit that receives data and strobes transferred from a transmitting device, and a plurality of sets of data and strobes by shifting a plurality of phases of input data and input strobes. A CRC calculation phase control circuit for outputting a CRC, and a plurality of calculation circuits for calculating a CRC code based on each set of data and strobe output from the CRC calculation phase control circuit An arithmetic unit, a CRC latch circuit for latching a CRC code transferred from the transmitting device after completion of data transfer in response to a CRC strobe transferred from the transmitting device, and a plurality of outputs of the CRC calculating unit A plurality of CRC operation units so as to determine whether one of them matches the output of the CRC latch circuit. Corresponding to the judgment result of the CRC comparison circuit among the output of each set of data and strobe from the CRC calculation phase control circuit. A data determining unit for determining received data based on the output of the set. According to such a configuration, it is possible to prevent frequent CRC errors, prevent a decrease in transfer rate, and ensure high data reliability.
JP 2004-213438 A

  In the data storage system 100 using the DDR SDRAM 101, the data signal is latched at the rising edge and the falling edge of the strobe signal, while the data signal and the strobe signal are input from the DDR SDRAM 101 to the data control circuit 102 in the same phase. Therefore, the data control circuit 102 requires a delay circuit 123 that delays the phase of the strobe signal by 90 degrees with respect to the data signal.

  The delay circuit 123 has temperature dependency such that the delay amount (delay time) increases as the temperature rises. Therefore, it is necessary to consider the maximum delay time and the minimum delay time amount by which the strobe signal is delayed by the delay circuit 123. The setup time of the data, the hold time, the skew of the clock and the data The window of data, which is the time for which the data signal is correctly latched after subtracting the jitter of the clock, is shortened, which hinders high-speed transfer.

  On the other hand, the data transfer circuit disclosed in Patent Document 1 is an interface circuit for connecting a host processor in a personal computer and a storage device such as a hard disk drive or a CD-ROM, and a DDR SDRAM is not assumed. The data transfer circuit disclosed in Patent Document 1 uses a CRC calculation circuit and a CRC latch circuit because CRC is used for phase adjustment.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a DDR SDRAM that does not require a delay circuit and is suitable for high-speed transfer. Another object is to provide a data storage system using such a DDR SDRAM.

  As a result of various studies, the present inventor has found that the above object is achieved by the present invention described below. In other words, the DDR SDRAM according to one aspect of the present invention includes a phase adjustment circuit that shifts the phase of the strobe signal by a predetermined angle with respect to the data signal, and when the data is read, the phase adjustment circuit applies the data signal to the data signal. The data signal and the strobe signal are output by shifting the phase of the strobe signal by the predetermined angle.

  According to this configuration, when the DDR SDRAM reads data, the phase adjustment circuit shifts the phase of the strobe signal by a predetermined angle with respect to the data signal and outputs the data signal and the strobe signal. The control circuit does not require a delay circuit that delays the phase of the strobe signal by 90 degrees with respect to the data signal, and its temperature dependency can be suppressed. Since temperature dependence is suppressed, data transfer can be performed at high speed.

  In the DDR SDRAM described above, the phase adjustment circuit includes a search circuit that searches for the predetermined angle. Such a search circuit includes, for example, a test pattern data storage circuit for storing test pattern data used for searching for the predetermined angle, and a phase between a data signal of the test pattern data and a strobe signal. A test pattern data signal output circuit for sequentially outputting a plurality of sets of data signals and strobe signals with a plurality of shifts, each data obtained as a result of latching the sequentially input data signals with the strobe signals, and the test pattern data storage circuit A determination circuit that compares the stored data and determines the predetermined angle based on the comparison result is preferably configured.

  According to this configuration, since the search circuit searches for the predetermined angle, the predetermined angle optimum for the DDR SDRAM is automatically searched. For this reason, the data transfer speed is increased, and it is possible to cope with the product variation of DDSDRAM, the usage environment of DDRSDRAM, and the secular change.

  In the DDR SDRAM described above, the predetermined angle is preset by design.

  According to this configuration, the predetermined angle optimum for the DDR SDRAM is set, and the data transfer is speeded up.

  Further, the above-mentioned DDR SDRAM is characterized in that a clock generation circuit for generating an operation clock is provided outside.

  According to this configuration, there is no need to provide a clock generation circuit inside.

  In another aspect of the present invention, in the data storage system including one or a plurality of DDR SDRAMs and a data control circuit that reads / writes data from / to the DDR SDRAM, the DDR SDRAM is any one of the above. DDR SDRAM.

  According to this configuration, a data storage system in which temperature dependency is suppressed and data transfer is speeded up is provided.

  According to the DDR SDRAM of the present invention, the data control circuit that reads data does not need a delay circuit that delays the phase of the strobe signal by 90 degrees with respect to the data signal, and its temperature dependency can be suppressed. Data transfer speed can be increased. According to the data storage system of the present invention, temperature dependency is suppressed and data transfer is speeded up.

  Embodiments according to the present invention will be described below with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

  FIG. 1 is a block diagram showing a configuration of a data storage system in the embodiment. FIG. 2 is a diagram illustrating a configuration of a data transfer circuit (data control circuit) in the embodiment.

  The data storage system S of the embodiment is a device that stores data using one or more DDR SDRAMs 1 as storage elements. As shown in FIG. 1, one or more DDR SDRAMs 1 that store binary data and DDR SDRAM 1 And a data control circuit 2b for reading data from DDRSDAM1. In the example illustrated in FIG. 1, the data storage system S includes a plurality of X DDR SDRAMs 1-1 to 1-X. Each of the DDR SDRAMs 1-1 to 1-X is connected to the data control circuit 2b by a plurality (X in the example of FIG. 1) of strobe lines DQS (DQS-1 to DQS-X). The data control circuit 2b is connected by an N-bit data bus DQ for transmitting a data signal. The bit width of the data bus DQ may be an arbitrary bit width such as 8 bits, 16 bits, or 32 bits.

  In the present specification, when referring generically, it is indicated by a reference symbol without a suffix, and when referring to an individual configuration, it is indicated by a reference symbol with a suffix.

  The DDR SDRAM 1 has a function as a so-called general DDR SDRAM, and further performs data transfer with the data control circuit 2b in order to execute data writing and reading at high speed under the control of the data control circuit 2b. A data transfer circuit 2a to be executed is provided. The data transfer circuit 2a includes a phase adjustment circuit 3a that shifts the phase of the strobe signal with respect to the data signal by a predetermined angle α. When the data is read by the data control circuit 2b and the data signal of the data is output, The phase adjustment circuit 3a shifts the phase of the strobe signal by the predetermined angle α with respect to the data signal, and outputs the data signal and the strobe signal. The data control circuit 2 b includes a phase adjustment circuit 3 b that shifts the phase of the strobe signal with respect to the data signal by a predetermined angle α, and outputs the data signal of the data to write the data to the DDR SDRAM 1. Accordingly, the phase of the strobe signal is shifted by the predetermined angle α with respect to the data signal, and the data signal and the strobe signal are output.

  Since the data transfer circuit 2a and the data control circuit 2b of the DDR SDRAM 1 are configured in substantially the same manner, the data transfer circuit 2a and the data control circuit 2b of the DDR SDRAM 1 are collectively referred to as the data transfer circuit 2. The phase adjustment circuit 3a in the data transfer circuit 2a of the DDR SDRAM 1 and the phase adjustment circuit 3b in the data control circuit 2b are collectively referred to as the phase adjustment circuit 3.

  As shown in FIG. 2, the data transfer circuit 2 has a phase adjustment circuit 3, a clock adjustment circuit 21, and a strobe flip-flop for generating a strobe signal (hereinafter abbreviated as “strobe FF”). 22 (22a, 22b), a multiplexer 23 that multiplexes the output of the strobe FF 22, an amplifier 24 that amplifies the output of the multiplexer 23 with a predetermined amplification factor and outputs it to the strobe line DQS, and a phase adjustment circuit 3 and a multiplexer 25 (25a, 25b) that multiplexes the data to be transferred input from the input line Din (Din1, Din2), and an output flip-flop (hereinafter referred to as “output”) that latches the output of the multiplexer 25. FF ") 26) (26a, 26b) and the output of the output FF 26 are multiplexed. The multiplexer 27, the amplifier 28 that amplifies the output of the multiplexer 27 with a predetermined amplification factor set in advance and outputs the amplified data signal to the data line DQ, latches the data signal transferred via the data line DQ, and outputs the output line Dout ( Dout1, Dout2) and an input flip-flop (hereinafter abbreviated as “input FF”) 29 (29a, 29b) that outputs to the phase adjustment circuit 3. The output of the multiplexer 25 is test pattern data to be described later or data to be transferred input from the input line Din (Din1, Din2). The input terminal of the strobe FF 22a is pulled up with a predetermined voltage Vdd, and the input terminal of the strobe FF 22b is grounded. In FIG. 2, an output FF 26 and an input FF 29 for 1 bit are illustrated, and others are omitted because they have the same configuration.

  The clock adjustment circuit 21 includes, for example, a PLL and generates the second clock signal ClkX whose phase is adjusted with respect to the first clock signal Clk0 by the control of the first clock signal Clk0 and the phase adjustment circuit 3. As will be described later, when the clock adjustment circuit 21 searches for the optimum phase of the strobe signal with respect to the data signal during data transfer, the phase of the second clock signal with respect to the first clock signal Clk0 is controlled by the phase adjustment circuit 3. Are sequentially shifted by a predetermined angle Δθ within a range from 0 degrees to 360 degrees to generate the second clock signal ClkX. The clock adjustment circuit 21 is shifted by a predetermined angle α with respect to the first clock signal Clk0 so that the searched optimum phase is obtained by the control of the phase adjustment circuit 3 at the time of data transfer. A second clock signal having a phase is generated. The first clock signal Clk0 is input to the output FF 26 as an operation clock and also input to the multiplexer 27. The first clock signal Clk0 is input as it is to the output FF 26a and the multiplexer 27, and the first FF 26b is input to the output FF 26b. One clock signal Clk0 is inverted and input. The second clock signal ClkX is input to the strobe FF 22 as an operation clock and also input to the multiplexer 23. The second clock signal ClkX is input as it is to the strobe FF 22a and the multiplexer 23, and the strobe FF 22b receives the first clock signal ClkX. The two clock signal ClkX is inverted and input.

  The strobe signal input via the strobe line DQS is input to the input FF 29 and the phase adjustment circuit 3. The strobe signal is input to the input FF 29a and the phase adjustment circuit 3 as it is, and the strobe signal is inverted and input to the input FF 29b.

  The phase adjustment circuit 3 includes, for example, a phase shift value calculation circuit 31, a test pattern data storage circuit 32, a counter circuit 33, a comparison circuit 34, and a register circuit 35.

  The phase shift value calculation circuit 31 is a circuit that outputs to the clock adjustment circuit 21 a control signal that indicates the phase difference of the second clock signal ClkX with respect to the first clock signal Clk0. When the phase shift value calculation circuit 31 searches for the optimum phase of the strobe signal with respect to the data signal during data transfer, the phase of the second clock signal ClkX is sequentially increased by a predetermined angle Δθ with respect to the first clock signal Clk0. A control signal is output to the clock adjustment circuit 21 so as to shift, and a clock signal is output to the multiplexer 25. Then, the phase shift value calculation circuit 31 transmits the control signal to the clock adjustment circuit so that the phase of the second clock signal ClkX becomes the searched optimum phase with respect to the first clock signal Clk0 at the time of data transfer. To 21.

  For example, when the clock adjustment circuit 21 can shift the phase of the second clock signal ClkX by 360/256 with respect to the first clock signal Clk0, the phase shift value calculation circuit 31 performs the strobe signal for the data signal during data transfer. When searching for the optimum phase, positive values from 0 to 255 are sequentially output as control signals. The clock adjustment circuit 21 generates a second clock signal ClkX whose phase is shifted by (360/256 × (control signal)) with respect to the first clock signal Clk0. As a result of the search, for example, when an optimum phase is obtained at 64, the phase shift value calculation circuit 31 outputs 64 as a control signal to the clock adjustment circuit 21 during data transfer.

  The test pattern data storage circuit 32 is a circuit for storing test pattern data used for searching for a predetermined angle by which the phase of the strobe signal is shifted with respect to the data signal. As will be described later, this test pattern data is output as a data signal when searching for the optimum phase of the strobe signal relative to the data signal during data transfer. The test pattern data storage circuit 32 outputs test pattern data to the comparison circuit 34 and the multiplexer 25. The test pattern data may be an arbitrary number of bits, but there are two types of data signals, a high level signal (high signal) and a low level signal (low signal), and the rise time until it reaches the high level from the low level Since the fall time from the high level to the low level is different, this embodiment is composed of, for example, two bits of a high level bit and a low level bit. The high level represents 1 data, and the low level represents 0 data.

  The counter circuit 33 is a circuit for determining whether or not the search for the optimum phase of the strobe signal with respect to the data signal has been completed during the data transfer. The strobe signal input via the strobe line DQS is input to the counter circuit 33. The counter circuit 33 counts (counts) rising edges of the strobe signal, and the count value is (360 / Δθ) × 2. If it is determined that the search for the optimum phase has been completed, an enable signal (ENABLE) is output to the comparison circuit 34 as a signal indicating the fact. Since the phase of the second clock signal ClkX is sequentially shifted by an angle Δθ, 360 / Δθ represents the number of searches (the number of shifts). When the test pattern data is N bits, the optimum phase The count value when the search is completed is (360 / Δθ) × N. In this embodiment, since the test pattern data is 2 bits, the count value is (360 / Δθ) × 2.

  The register circuit 35 is a circuit that stores a data signal input via the data line DQ and latched by the input FF 29.

  The comparison circuit 34 is a circuit that determines the optimum phase of the strobe signal with respect to the data signal during data transfer. The comparison circuit 34 compares the data stored in the register circuit 35 with the test pattern data stored in the test pattern data storage circuit 32 and holds the determination result. When the enable signal is notified from the counter circuit 33, the comparison circuit 34 determines an optimum phase from the stored determination result. Then, the comparison circuit 34 outputs an optimum phase to the phase shift value calculation circuit 31.

  The counter circuit 33, the comparison circuit 34, and the register circuit 35 compare each data obtained by latching sequentially input data signals with the strobe signal and the data stored in the test pattern data storage circuit 32. Then, an example of a determination circuit that determines the predetermined angle α based on the comparison result is configured. The phase shift value calculation circuit 31 and the clock adjustment circuit 21 are test pattern data signal output circuits that sequentially output a plurality of sets of data signals and strobe signals by shifting the phases of the data signal of the test pattern data and the strobe signal by a plurality of phases. Configure an example. Then, the phase shift value calculation circuit 31, the test pattern data storage circuit 32, the counter circuit 33, the comparison circuit 34, the register circuit 35, and the clock adjustment circuit 21 search for a predetermined angle of the phase in the strobe signal shifted with respect to the data signal. An example of a search circuit is configured.

  Such a data transfer circuit 2 can be configured by, for example, an FPGA or the like, and the clock adjustment circuit 21 can be configured to shift the phase by, for example, 360/256 degrees (= Δθ = about 1.41 degrees), for example. Is possible.

  Next, a search operation for the optimum phase of the strobe signal with respect to the data signal during data transfer will be described.

  FIG. 3 is a flowchart showing the search operation for the optimum phase of the strobe signal with respect to the data signal during data transfer. FIG. 4 is a time chart for explaining the search operation of the optimum phase of the strobe signal with respect to the data signal during data transfer. FIG. 5 is a diagram illustrating the determination result.

  In the data storage system S having such a configuration, when the DDR SDRAM 1 and the data control circuit 2 b are activated by turning on a power switch (not shown), the data control circuit 2 b functions as a master and the data transfer circuit 2 a of the DDR SDRAM 1. Functions as a slave, and in the data transfer in the data transfer circuit 2a of the DDR SDRAM 1, a search operation for the optimum phase of the strobe signal with respect to the data signal is started. When this search operation is completed, the data transfer circuit 2a of the DDR SDRAM functions as a master. At the same time, the data control circuit 2b functions as a slave, and an operation of searching for an optimum phase of the strobe signal with respect to the data signal is started when data is transferred in the data control circuit 2b. Thus, in the data transfer circuit 2a and the data control circuit 2b of the DDR SDRAM 1, the optimum phase of the strobe signal with respect to the data signal is searched for during the data transfer, and the phase of the strobe signal with respect to the data signal is optimized during the data transfer. As a result, data transfer is speeded up.

  The search operation for the optimum phase of the strobe signal with respect to the data signal during data transfer in the data transfer circuit 2a of the DDR SDRAM 1 and the search operation for the optimum phase of the strobe signal with respect to the data signal during data transfer in the data control circuit 2b are the same. Therefore, it explains collectively below.

  In FIG. 3, in step # S1, a master unit (Unit) and a slave unit (Unit) are activated by turning on an unillustrated power switch.

  In the case of the search operation of the optimum phase of the strobe signal with respect to the data signal at the time of data transfer in the data transfer circuit 2a of the DDR SDRAM 1, the master unit is the data control circuit 2b, and the slave unit is the data transfer circuit 2a. In the case of the search operation of the optimum phase of the strobe signal with respect to the data signal at the time of data transfer in the data control circuit 2b, the master unit is the data transfer circuit 2a, and the slave unit is the data control circuit 2b.

  Next, in step # S2, a test signal data signal and a strobe signal whose phase is shifted from the data signal by a first angle (1 × Δθ) are output from the master unit to the slave unit. Is done.

  Next, in step # 3, the data signal and the strobe signal of the test data are transmitted to the data line DQ and the strobe line DQS, respectively, and input to the slave unit. In the slave unit, the data signal of the test data is latched by the input FF 29 at the rising edge and the falling edge of the strobe signal, and is output to the register circuit 35 and stored.

  Next, in step # S4, it is determined whether or not the test data has been correctly latched in the slave unit, and the determination result is recorded. More specifically, the comparison circuit 34 compares the data stored in the register circuit 35 with the test pattern data stored in the test pattern data storage circuit 32, and if they match, the comparison circuit 34 is correctly latched. If it does not match, it is determined that the latch has not been correctly performed, and the determination result is held.

  Next, in step # S5, it is determined whether or not it has been repeated 360 / Δθ times, and if it has not been repeated 360 / Δθ times (No), step # S6 is executed and 360 / Δθ times. If it is repeated (Yes), Step # S7 is executed. More specifically, when the enable signal is not input from the counter circuit 33, the comparison circuit 34 determines that 360 / Δθ is not repeated (No), and the enable signal is received from the counter circuit 33. If it has been input, it is determined that it has been repeated 360 / Δθ times (Yes).

  In step # S6, the phase adjustment value of the master unit is added by Δθ, the process is returned to step # S2, and step # S2 is executed. More specifically, the phase shift value calculation circuit 31 of the master unit determines that the phase of the strobe signal with respect to the data signal is a second angle (2 × Δθ = ((first angle 1 × Δθ) + A control signal is output to the clock adjustment circuit 21 so that a strobe signal shifted by Δθ)) is output, and step # S2 is executed.

  Thus, step # S2, step # 3, step # S4, step # S5 and step # S6 are repeated until it is determined in step # S5 that 360 / Δθ has been repeated. As a result, the master unit outputs a control signal to the clock adjustment circuit 21 so that the phase of the second clock signal ClkX is sequentially shifted by a predetermined angle Δθ with respect to the first clock signal Clk0. As shown in FIGS. 4B to 4F, the phase of the signal is sequentially shifted by a predetermined angle Δθ with respect to the data signal. The data signal of the test data is latched by the input FF 29 by the strobe signal whose phase is sequentially shifted by a predetermined angle Δθ with respect to the data signal, and is sequentially stored in the register circuit 35. Then, the data sequentially stored in the register circuit 35 and the test pattern data stored in the test pattern data storage circuit 32 are sequentially compared by the comparison circuit 34. In the example shown in FIG. 4, when the predetermined angles are (N + 3) · Δθ and (N + 4) · Δθ (N is a certain positive number), it is determined that the latch is correctly performed, and the remaining case is not latched correctly. For example, as shown in FIG. 5, a predetermined angle (phase shift value) N · Δθ is associated with the determination result and held in the comparison circuit 34. In the example illustrated in FIG. 5, a case where the determination is correct is indicated by “◯”, and a case where the determination is not correct is indicated by “x”.

  In step # S7, in the slave unit, the comparison circuit 34 selects and determines the optimum phase from the held determination result. In the case where there are a plurality of cases where the determination result held is correctly latched, for example, it is arbitrarily selected from a plurality of cases where it is correctly latched. If they are arranged in the order, the median is selected. If there are two medians, one of them is selected.

  By operating in this way, the optimum phase of the strobe signal with respect to the data signal is searched for during data transfer.

  When the data transfer circuit 2 transfers the data, the phase shift value calculation circuit 31 sends a control signal whose phase of the second clock signal ClkX is the searched optimum phase with respect to the first clock signal Clk0. By outputting to the clock adjusting circuit 21, the phase of the strobe signal is shifted by an optimum predetermined angle α with respect to the data signal, and the data signal and the strobe signal are output.

  Thus, when data is read out, the DDR SDRAM 1 outputs the data signal and the strobe signal by shifting the phase of the strobe signal by a predetermined angle α with respect to the data signal by the phase adjustment circuit 3a. The circuit 2b does not require a delay circuit that delays the phase of the strobe signal by 90 degrees with respect to the data signal as in the background art, and the temperature dependency thereof can be suppressed. Since this temperature dependency is suppressed, it is possible to speed up data transfer.

  The search for the predetermined angle α is automatically performed, and the predetermined angle α optimum for the DDR SDRAM 1 is searched. For this reason, the data transfer is speeded up, and it is possible to cope with the product variation of the DDSDRAM 1, the use environment of the DDR SDRAM 1, and the secular change.

  In the above-described embodiment, the strobe line DQS is provided for each DDR SDRAM 1. However, as shown in FIG. 6, a single-wire strobe line DQS ′ may be used by each DDR SDRAM 1 ′. Such a data storage system S ′ is configured to include one or a plurality of DDR SDRAMs 1 ′ and a data control circuit 2b ′, and each DDR SDRAM 1′-1 to 1′-X is formed by one strobe line DQS ′. The data control circuit 2b 'is connected to the data control circuit 2b' and the data bus DQ is connected to the data control circuit 2b '. The DDR SDRAM 1 ′ is configured in substantially the same manner as the DDR SDRAM 1 shown in FIG. 1, further stores an identifier for identifying and identifying the own device, and further adds this identifier to the data signal when outputting a data signal. When a signal is input, it is further configured to determine whether or not the data signal is addressed to the own device from an identifier added to the data signal. This identifier is placed in the first part of the data signal, for example. The data control circuit 2b ′ is configured in substantially the same manner as the data control circuit 2 shown in FIG. 1, further stores an identifier for identifying and identifying the DDR SDRAM 1 ′, and outputs a data signal when the data signal is output. An identifier of the DDR SDRAM 1 ′ at the output destination is further added, and when the data signal is input, the DDR SDRAM 1 ′ at the output source of the data signal is determined from the identifier added to the data signal. This identifier is placed in the first part of the data signal, for example.

  In the above-described embodiment, a clock generation circuit that generates an operation clock is provided outside, and the clock adjustment circuit 21 includes a phase shift circuit that shifts the phase of the operation clock from the external clock generation circuit. The operation clock may be output as it is as the first clock signal Clk0, and the phase of the operation clock may be shifted by the phase shift circuit and output as the second clock signal ClkX. With this configuration, the clock adjustment circuit 21 does not need to be provided with a clock generation circuit. As the external clock generation circuit, for example, a clock generation circuit that generates an operation clock of the microprocessor can be used.

  In the above-described embodiment, the data transfer circuit 2 is configured so that the search for the predetermined angle α is automatically performed. However, the predetermined angle α is configured to be preset by design. Also good. The predetermined angle α is the frequency of the data signal and the strobe signal, the wiring length, the wiring width, the wiring thickness and the wiring material from the clock adjustment circuit 21 to each FF 22, 26, 29, the wiring length, the wiring width, the wiring of the data bus DQ. Thickness and wiring material, strobe line DQS wiring length, wiring width, wiring thickness and wiring material, rise time from low level to high level, fall time from high level to low level, operating temperature range, From the supply voltage range of each FF 22, 26, 29 (supply voltage range of the data control circuit), the jitter of the first clock signal Clk0, the setup time / hold time of each FF 22, 26, 29, and from each FF 22, 26, 29 It is designed based on the wiring length to the terminal pin, wiring width, wiring thickness, wiring material, and the like. Even with such a configuration, the optimum predetermined angle α is set in the data transfer circuit 2 and the data transfer is speeded up.

  In order to express the present invention, the present invention has been properly and fully described through the embodiments with reference to the drawings. However, those skilled in the art can easily change and / or improve the above-described embodiments. It should be recognized that this is possible. Accordingly, unless the modifications or improvements implemented by those skilled in the art are at a level that departs from the scope of the claims recited in the claims, the modifications or improvements are not limited to the scope of the claims. To be construed as inclusive.

It is a block diagram which shows the structure of the data storage system in embodiment. It is a figure which shows the structure of the data transfer circuit (data control circuit) in embodiment. It is a flowchart which shows the search operation | movement of the optimal phase of the strobe signal with respect to a data signal at the time of data transfer. 6 is a time chart for explaining an operation of searching for an optimum phase of a strobe signal with respect to a data signal during data transfer. It is a figure which shows a determination result. It is a block diagram which shows the other structure of the data storage system in embodiment. 1 is a block diagram showing a configuration of a data storage system using a DDR SDRAM according to background art. It is a figure which shows each structure of a DDR SDRAM and a data control circuit. It is a figure which shows the time chart of a data storage system.

Explanation of symbols

S, S 'data storage system 1, 1' DDR SDRAM
2, 2a, 2a ′ data transfer circuit 2b, 2b ′ data control circuit 3, 3a, 3a ′, 3b, 3b ′ phase adjustment circuit 21, 111, 121 clock adjustment circuit 31 phase shift value calculation circuit 32 test pattern data storage circuit 33 counter circuit 34 comparison circuit 35 register circuit

Claims (6)

A phase adjustment circuit that shifts the phase of the strobe signal with respect to the data signal by a predetermined angle,
A DDR SDRAM that outputs a data signal and a strobe signal by shifting the phase of the strobe signal by the predetermined angle with respect to the data signal by the phase adjustment circuit when data is read. The DDR SDRAM according to claim 1, wherein the phase adjustment circuit includes a search circuit that searches for the predetermined angle. The search circuit includes:
A test pattern data storage circuit for storing test pattern data used for searching for the predetermined angle;
A test pattern data signal output circuit for sequentially outputting a plurality of sets of data signals and strobe signals by shifting a plurality of phases of the data signal and the strobe signal of the test pattern data;
A determination circuit that compares each data obtained by latching sequentially input data signals with a strobe signal and data stored in the test pattern data storage circuit, and determines the predetermined angle based on the comparison result The DDR SDRAM according to claim 2, further comprising: The DDR SDRAM according to claim 1, wherein the predetermined angle is preset by design. The DDR SDRAM according to any one of claims 1 to 4, wherein a clock generation circuit for generating an operation clock is provided outside. In a data storage system comprising one or more DDR SDRAMs and a data control circuit for reading and writing data to and from the DDR SDRAMs,
6. The data storage system according to claim 1, wherein the DDR SDRAM is the DDR SDRAM according to any one of claims 1 to 5.

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