JP2008187281A - Solid-state imaging device and imaging device equipped with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging device which has less power consumption and a smaller circuit scale than usual, and a solid-state imaging device used therefor. <P>SOLUTION: The imaging device includes (n) solid-state imaging devices 1, a control unit selecting them, and a signal processing unit. The control unit inputs a select signal having binary logic to the respective solid-state imaging devices 1. An output circuit 21 of each solid-state imaging device 1 comprises a transistor 21 to which a pixel input signal is input, a transistor 22, a transistor 23, and an output wiring 20 which outputs an output signal. A conduction terminal 21b is connected to a power source, a conduction terminal 21b is connected to a conduction terminal 22b and the output wiring 20, and a conduction terminal 22c is connected to a ground 24. The select signal is input to a gate terminal 23a and an inversion signal is input to a gate terminal 22a. Conduction terminals 23b and 23c are disposed so that the output signal is output when the logic of the select signal indicates selection and not output when not. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device equipped with an output circuit and an imaging device equipped with a plurality of solid-state imaging devices.

  2. Description of the Related Art Conventionally, an imaging device including a plurality of solid-state imaging devices has been developed to capture a plurality of still images and moving images with different shooting directions (see, for example, Patent Document 1). The imaging device described in Patent Document 1 will be described with reference to FIG. FIG. 12 is a block diagram illustrating a schematic configuration of a conventional imaging device including a plurality of solid-state imaging devices.

  As shown in FIG. 12, the imaging device includes solid-state imaging devices 31 (1) to (n), a signal selection circuit 32, a signal processing device 33, and a control circuit 34. n is an integer of 2 or more. The solid-state imaging devices 31 (1) to (n) are MOS type imaging devices or CCD (charge coupled device) imaging devices, and a plurality of them are provided. The light receiving region 31a shows a pixel array configured by arranging a plurality of pixels (not shown) in a matrix. All the output signals (VOUT (1) to (n)) output from the solid-state imaging devices 31 (1) to (n) are input to the signal selection circuit 32.

  The control circuit 34 selects one solid-state imaging device 31 in the set cycle according to the set order. The signal selection circuit 32 selects only the output signal of the solid-state imaging device 31 selected by the control circuit 34 and outputs it to the signal processing device 33 as imaging data (AFEIN).

  The signal processing device 33 includes an AFE (Analog Front End) that performs analog signal processing, a DSP (Digital Signal Processor) that performs digital signal processing, and the like. The imaging data (AFEIN) is subjected to signal processing by the signal processing device 33 and then input to a display device (not shown). A still image or a moving image captured by the selected solid-state imaging device 31 is displayed on a display screen (not shown) of the display device.

  Such applications of the imaging device shown in FIG. 12 include, for example, a safety confirmation device that captures a plurality of blind spots from an automobile driver, or a camera that captures images from two directions to obtain a stereoscopic image (stereoscopic image capturing). Camera). Other applications include capsule endoscopes. Capsule-type endoscope apparatuses are required to mount a plurality of solid-state imaging devices because it is necessary to reliably capture the state of the body.

  By the way, among the applications described above, a stereoscopic image capturing camera and a capsule endoscope apparatus are required to reduce power consumption. In particular, since capsule-type endoscope apparatuses perform long-time imaging within a human body, reduction of power consumption is an important issue. However, in the image pickup apparatus shown in FIG. 12, the solid-state image pickup devices 31 (1) to (n) continue to output image pickup data regardless of whether or not they are selected. In this case, it is difficult to reduce power consumption.

  In order to solve such a problem, attempts have been made to reduce the power consumption of the solid-state imaging device (see, for example, Patent Document 2). Patent Document 2 proposes a new output circuit for a solid-state imaging device in order to reduce power consumption of the solid-state imaging device. The output circuit disclosed in Patent Document 2 reduces power consumption by stopping unnecessary current from flowing through the output circuit when reading out a plurality of pixel signals accumulated in the solid-state imaging device pixel by pixel. ing. The configuration and operation of the output circuit described in Patent Document 2 will be described with reference to FIGS.

  FIG. 13 is a circuit diagram showing an output circuit for a conventional solid-state imaging device. As shown in FIG. 13, the output circuit 35 includes a switching transistor 36, a drive transistor 37, a bias transistor 38, and an output wiring 40.

  In the switching transistor 36, the power supply voltage (VDD) is applied to one conduction terminal 36b, and one conduction terminal 37b of the drive transistor 37 is connected to the other conduction terminal 36c. An inverted reset signal (/ ΦR) is input to the gate terminal 36 a of the switching transistor 36. Note that a conduction terminal in this specification refers to a source terminal or a drain terminal of a transistor.

  The other conduction terminal 37 c of the drive transistor 37 is connected to one conduction terminal 38 b of the bias transistor 38. The output wiring 40 is connected to each of the mutually connected conduction terminals of the drive transistor 37 and the bias transistor 38. In other words, the output wiring 40 is branched from the wiring connecting the conduction terminal 37c and the conduction terminal 38b. The other conduction terminal 38 c of the bias transistor 38 is connected to the ground 39.

  Further, the pixel input signal (VIN) is input to the gate terminal 37 a of the drive transistor 37. A DC bias signal (VG) that determines the operating point of the output circuit 35 is input to the gate terminal of the bias transistor 38.

  Here, the operation of the output circuit shown in FIG. 13 will be described with reference to FIG. 14 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 13. FIG. 14A shows a reset signal and an inverted reset clock signal, and FIG. 14B is outputted from the output wiring. FIG. 3C shows the current flowing through the output circuit.

  In FIG. 14A, the upper waveform indicates the reset signal (ΦR), and the lower waveform indicates the inverted reset signal (/ ΦR). The reset signal (ΦR) maintains the voltage level high for a certain period (period T) each time a pixel signal of one pixel is read from the floating diffusion (not shown) to the gate terminal 37a of the drive transistor 37. , Reset floating diffusion. The inverted reset signal (/ ΦR) is a signal obtained by inverting the reset signal (ΦR) as described above, and is input to the gate terminal 36 a of the switching transistor 36.

  By the way, it is assumed that a signal that always turns on the switching transistor 36 is applied to the gate terminal 36a instead of the inverted reset signal (/ ΦR) shown in FIG. In this case, the waveform of the output signal (VOUT) from the output wiring 40 has a shape shown in FIG.

  Specifically, as shown in FIG. 14B, a noise waveform 41 due to the leakage of the reset signal (ΦR) is generated in response to the input of the reset signal (ΦR) (reset period T1). Thereafter, when the floating diffusion is in a reset state, the voltage level of the output signal becomes a constant value (feedthrough period T2). When the pixel signal is supplied to the floating diffusion, the voltage level of the output signal changes in proportion to the charge amount of the pixel signal and becomes a value that specifies the charge amount of the pixel signal (data period T3).

  As described above, when the switching transistor 36 is always in a conductive state, an unnecessary voltage is applied in the reset period T1 as shown in FIG. 14B, thereby causing an unnecessary current to flow in the output circuit.

  On the other hand, when the inverted reset signal (/ ΦR) is input to the gate terminal 36a of the switching transistor 36, the switching transistor 36 is turned off in the period T, and the supply of the power supply voltage VDD is stopped. As a result, as shown in FIG. 14C, the current value of the current (circuit current) I flowing through the output circuit in the reset period T1 becomes 0 (zero).

For this reason, if the output circuit shown in FIG. 13 is attached to a solid-state imaging device, power consumption in the solid-state imaging device can be reduced. Therefore, if the imaging device shown in FIG. 12 is constructed using the solid-state imaging device to which the output circuit shown in FIG. 13 is attached, the power consumption of the entire imaging device can be reduced.
JP-A-7-007653 Japanese Patent Laid-Open No. 8-023478

  However, even if the output circuit shown in FIG. 13 is attached to each solid-state imaging device 31 of the imaging device shown in FIG. 12, the output from the unselected solid-state imaging device 31 is not 0 (zero). Absent. Therefore, even in this aspect, reduction in power consumption is not sufficient.

  In addition, in devices equipped with an imaging device, downsizing is required, but at the same time, downsizing of imaging devices is also required. However, in the imaging device shown in FIG. 12, the signal selection circuit 32 is necessarily required to send only the imaging data of the selected solid-state imaging device to the signal processing device, so that the circuit scale is large and miniaturization is difficult. There is also a problem.

  An object of the present invention is to provide an imaging apparatus capable of solving the above-described problems and reducing the power consumption and the circuit scale as compared with the prior art, and a solid-state imaging apparatus used therefor.

  In order to achieve the above object, an imaging device according to the present invention includes a plurality of solid-state imaging devices, a control unit that selects a solid-state imaging device that performs imaging from the plurality of solid-state imaging devices, and a signal processing unit. Each of the plurality of solid-state imaging devices includes an output circuit, and the control unit specifies a logic signal that specifies whether or not each of the plurality of solid-state imaging devices is selected, or the inversion of the logic signal and the logic signal. A signal is input, and the output circuit of each of the solid-state imaging devices includes a drive transistor, a bias transistor, a switching transistor, and an output signal corresponding to the pixel input signal, to which a pixel input signal is input to a gate terminal. Output wiring for outputting to the processing unit, and one conduction terminal of the two conduction terminals of the driver transistor is a power source. The remaining conduction terminal of the driver transistor is connected to one conduction terminal of the two conduction terminals of the bias transistor and the output wiring, and the remaining conduction terminal of the bias transistor is connected to the ground. The logic signal is input to a gate terminal of the switching transistor, the logic signal or the inverted signal is input to a gate terminal of the bias transistor, and two conduction terminals of the switching transistor are gates thereof. When the logic of the logic signal input to the terminal indicates the selection of the solid-state imaging device including the switching transistor, the output signal is output from the output wiring, and when the selection does not indicate the selection, the output wiring The output signal is arranged not to be output.

  In order to achieve the above object, a solid-state imaging device according to the present invention is a solid-state imaging device including an output circuit, and the output circuit includes a drive transistor in which a pixel input signal is input to a gate terminal, a bias transistor, A switching transistor and an output wiring for outputting an output signal corresponding to the pixel input signal, wherein one of the two conduction terminals of the driver transistor is connected to a power source, and the remaining of the driver transistor The conduction terminal is connected to one conduction terminal of the two conduction terminals of the bias transistor and the output wiring, the remaining conduction terminal of the bias transistor is connected to the ground, and the two conduction terminals of the switching transistor Is a logic signal from the outside to the gate terminal of the switching transistor. And when the logic signal or the inverted signal of the logic signal is input to the gate terminal of the bias transistor and the logic signal is one logic, the output from the output wiring When the signal is output and the logic signal has another logic, the output signal is not output from the output wiring.

  As described above, according to the solid-state imaging device and the imaging device of the present invention, it is possible to operate only a necessary solid-state imaging device from a plurality of solid-state imaging devices and to stop the operation of the unnecessary solid-state imaging device. For this reason, power consumption can be reduced as compared with the prior art. In addition, since a signal selection circuit as in the prior art is not required for selecting a solid-state imaging device to be operated, the circuit scale can be reduced in the solid-state imaging device and the imaging device of the present invention.

  An imaging device according to the present invention includes a plurality of solid-state imaging devices, a control unit that selects a solid-state imaging device that performs imaging from the plurality of solid-state imaging devices, and a signal processing unit, and each of the plurality of solid-state imaging devices. Includes an output circuit, and the control unit inputs, for each of the plurality of solid-state imaging devices, a logic signal specifying whether or not the logic signal is selected, or the logic signal and an inverted signal of the logic signal. The output circuit of each imaging device outputs a drive transistor, a bias transistor, a switching transistor, and an output signal corresponding to the pixel input signal to the signal processing unit. Output wiring, and one conduction terminal of the two conduction terminals of the driver transistor is connected to a power source, and the driver transistor The remaining conduction terminal of the transistor is connected to one conduction terminal of the two conduction terminals of the bias transistor and the output wiring, and the remaining conduction terminal of the bias transistor is connected to the ground. The logic signal is input to the gate terminal, the logic signal or the inverted signal is input to the gate terminal of the bias transistor, and the two conduction terminals of the switching transistor are input to the gate terminal. The output signal is output from the output wiring when the logic of the logic signal indicates the selection of the solid-state imaging device including the switching transistor, and the output signal is output from the output wiring when the selection does not indicate the selection. It is arranged so that it is not done.

  In the imaging device according to the present invention, output wirings provided in output circuits of the plurality of solid-state imaging devices are all connected to a common single wiring, and the signal processing unit is connected via the single wiring. It is good that it is the aspect connected to. According to this aspect, the circuit configuration can be simplified, and the circuit scale can be reduced and the cost can be reduced.

  In the imaging device according to the present invention, in each output circuit of the plurality of solid-state imaging devices, one conduction terminal of the two conduction terminals of the switching transistor is connected to the ground, and the remaining conduction terminals of the switching transistor. However, it is connected to the output wiring, the inverted signal is input to the gate terminal of the bias transistor, a capacitance is provided in the output wiring, and the output signal is output via the capacitance. Is preferred. According to this aspect, when noise enters the output circuit of the solid-state imaging device that is not selected, the influence of this noise can be minimized.

  In the imaging device according to the present invention, in each output circuit of the plurality of solid-state imaging devices, one conduction terminal of the two conduction terminals of the switching transistor is connected to the power source, and the remaining conduction terminals of the switching transistor However, it is connected to the output wiring, the inverted signal is input to the gate terminal of the bias transistor, a capacitance is provided in the output wiring, and the output signal is output via the capacitance. It is also preferable. Also in this aspect, when noise enters the output circuit of the solid-state imaging device that is not selected, the influence of this noise can be minimized.

  In the imaging device according to the present invention, in the output circuit of each of the plurality of solid-state imaging devices, a portion between two conduction terminals in the switching transistor constitutes a part of the output wiring, and the gate of the bias transistor It is also preferable that the logic signal is input to the terminal. According to this aspect, the number of parts can be reduced by further reducing the circuit scale, and the cost of the imaging apparatus can be reduced.

  The solid-state imaging device according to the present invention is a solid-state imaging device including an output circuit, and the output circuit includes a drive transistor, a bias transistor, a switching transistor, and the pixel input, each of which receives a pixel input signal at a gate terminal. An output wiring for outputting an output signal corresponding to the signal, one conduction terminal of the two conduction terminals of the driver transistor is connected to a power source, and the remaining conduction terminal of the driver transistor is connected to the bias transistor. One of the two conduction terminals is connected to the output wiring, and the other conduction terminal of the bias transistor is connected to the ground. The two conduction terminals of the switching transistor are the gate terminals of the switching transistor. And a logic signal is input from the outside to the bias In the case where the logic signal or the inverted signal of the logic signal is input to the gate terminal of the transistor, the output signal is output from the output wiring when the logic of the logic signal is one logic. When the logic of the signal is another logic, the output signal is arranged so as not to be output from the output wiring.

  In the solid-state imaging device according to the present invention, one conduction terminal of the two conduction terminals of the switching transistor is connected to the ground, the remaining conduction terminal of the switching transistor is connected to the output wiring, and the bias The inverted signal may be input to the gate terminal of the transistor.

  In the solid-state imaging device according to the present invention, one conduction terminal of the two conduction terminals of the switching transistor is connected to the power supply, the remaining conduction terminal of the switching transistor is connected to the output wiring, and the bias The inverted signal may be input to the gate terminal of the transistor.

  In the solid-state imaging device according to the present invention, the portion between the two conduction terminals of the switching transistor constitutes a part of the output wiring, and the logic signal is input to the gate terminal of the bias transistor. There may be.

(Common configuration of the solid-state imaging device in each of the first to third embodiments)
First, a configuration common to all the solid-state imaging devices according to Embodiments 1 to 3 of the present invention to be described later will be described with reference to FIG. FIG. 1 is a configuration diagram showing the overall configuration of the solid-state imaging device according to Embodiments 1 to 3 of the present invention.

  As shown in FIG. 1, the solid-state imaging device 1 in each of Embodiments 1 to 3 of the present invention is a MOS type imaging device. The solid-state imaging device 1 includes an output circuit 2, a vertical scanning circuit 3, a horizontal scanning circuit 4, a column reading unit 5, a timing generator 6, and a pixel array 7. The pixel array 7 is a MOS sensor array and includes a plurality of pixels 8 as in the case of a conventional MOS imaging device. The plurality of pixels 8 are arranged in a matrix along the row direction (horizontal direction) and the column direction (vertical direction). Although not shown, the pixel includes a photodiode, a reset transistor, an amplifying transistor, and a reading transistor.

  The vertical scanning circuit 3 selects one row (one horizontal line) from a plurality of rows constituting the pixel array 7 based on the address selection signal supplied from the timing generator 6. In the first to third embodiments, the vertical scanning circuit 3 sequentially selects rows from the top to the bottom in the drawing. Further, the vertical scanning circuit 3 reads out the pixels in the effective area by the column parallel method, and the signal charges accumulated in the pixels arranged in the horizontal direction in the pixel array 7 are read out simultaneously, and each column is read out. Is provided to a vertical signal line provided in the.

  Specifically, the vertical scanning circuit 3 first causes each pixel in the selected row to output a reset level signal toward the vertical signal line (so-called P-phase reading). Then, the vertical scanning circuit 3 causes a photodiode constituting each pixel to output a pixel signal corresponding to the amount of charge accumulated therein toward the vertical signal line (so-called D-phase reading). The vertical scanning circuit 3 performs such a reading operation for each row. Further, reading of pixel signals from the pixels in the selected row is performed within a horizontal blanking period in one horizontal period. In the horizontal blanking period, the pixel signal of each pixel is output in parallel to each vertical signal line in the row selected by the vertical scanning circuit 3.

  The pixel signal transferred from each pixel to the vertical signal line is input to the column readout unit 5. The column reading unit 5 includes a CDS (Correlated Double Sampling) circuit, and calculates the difference between the P-phase reading level (reset level) and the D-phase reading level (data level) for each column. The obtained value is sampled as a pixel signal. Then, the column reading unit 5 outputs the obtained pixel signals to the output circuit 2 one by one in order according to an instruction from the horizontal scanning circuit 4.

  The timing generator 6 generates a reference pulse serving as a reference for operation timing based on the vertical synchronization signal and the horizontal synchronization signal for the vertical scanning circuit 3, the horizontal scanning circuit 4, the column reading unit 5, and the output circuit 2. And output this.

  In the first to third embodiments, the selection signal (/ VSEL) is input to the output circuit 2 via the timing generator 6. The selection signal (/ VSEL) is a binary logic signal, as will be described later, and is used by the control unit (see FIG. 2) to control the operation of the output circuit 2. The control unit switches the logic (voltage level) of the selection signal (/ VSEL) to cause the output circuit 2 to output the output signal (VOUT) or to stop the output.

  In the first to third embodiments, the selection signal (/ VSEL) is input to the output circuit 2 via the timing generator 6, but is not limited to this example. The selection signal may be input directly to the output circuit 2 by the control unit. However, from the viewpoint of facilitating the synchronization between the operation of the output circuit 2 and the operation of the column reading unit 5, the selection signal is input to the output circuit 2 via the timing generator 6 as shown in FIG. Is preferred.

(Embodiment 1)
Next, the solid-state imaging device and the imaging device according to Embodiment 1 of the present invention will be described with reference to FIGS. First, the overall configuration of the imaging apparatus according to the first embodiment will be described. FIG. 2 is a configuration diagram showing the overall configuration of the imaging apparatus according to Embodiment 1 of the present invention.

  As shown in FIG. 2, the solid-state imaging device according to the first embodiment includes n (an integer greater than or equal to 2) solid-state imaging devices 1, a control unit 10, and a signal processing unit 11. The control unit 10 selects a solid-state imaging device that performs imaging from the n solid-state imaging devices 1. Each individual imaging apparatus 1 includes an output circuit 2 as shown in FIG.

  In addition, the control unit 10 inputs a selection signal (/ VSEL) that specifies whether or not the solid-state imaging device 1 is selected, specifically, to the output circuit 2. The selection signal is a binary logic signal as described above (see FIG. 4 described later), and the output circuit 2 outputs or does not output the output signal (VOUT) according to the logic. It is configured.

  In the first embodiment, 1 (1), 1 (2),..., 1 (n) respectively indicate that the solid-state imaging device has the first, second,. ). In addition, in order to indicate which one of the first, second,..., Nth solid-state imaging devices the signal of the selection signal is input, (/ VSEL1), (VSEL2),. -(VSELn). Similarly, in order to indicate which of the first, second,..., Nth solid-state imaging devices is the other output signal, the sign of the output signal is (VOUT1), (VOUT2),. -(VOUTn). If there is no number indicating the number, the number is not limited.

  Moreover, in this Embodiment 1, the control part 10 selects one solid-state imaging device 1 in order for every fixed period from solid-state imaging device 1 (1)-(n). Therefore, output signals (VOUT1 to VOUTn) are sequentially output from any one of the output circuits 2 at regular intervals. At this time, the operation of the non-selected solid-state imaging device 1 is stopped, and the output signals (VOUT1 to VOUTn) are not output from these output circuits 2. In FIG. 2, 20 is an output wiring for outputting an output signal.

  The first embodiment may be an aspect in which the control unit 10 inputs the inverted signal (VSEL) to each individual imaging device in addition to the selection signal (/ VSEL). Furthermore, the first embodiment may be an aspect in which each solid-state imaging device 1 generates an inverted signal (VSEL) therein. Further, the first embodiment may be a mode in which each of the n solid-state imaging devices 1 captures the same subject, or a mode in which each different subject is captured. The signal processing unit 11 includes an AFE, a DSP, and the like, similar to the conventional signal processing circuit shown in FIG. The configuration of the signal processing unit 11 will be described later with reference to FIG.

  Here, an output circuit mounted on the solid-state imaging device according to the first embodiment and its operation will be described. FIG. 3 is a circuit diagram showing a configuration of an output circuit mounted on the solid-state imaging device according to Embodiment 1 of the present invention. 4 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 3, FIG. 4 (a) shows a selection signal, FIG. 4 (b) shows an output signal output from the output wiring, FIG. 4C shows the current flowing through the output circuit. 3 and 4, only the first and second solid-state imaging devices among n solid-state imaging devices 1 are illustrated.

  As shown in FIG. 3, in any solid-state imaging device 1, the output circuit 2 includes a drive transistor 21, a bias transistor 22, a switching transistor 23, and an output wiring 20. The pixel input signal VIN1 (or VIN2) is input to the gate terminal 21a of the drive transistor 21. An output signal corresponding to the pixel input signal (VIN1 or VIN2) is output to the signal processing unit 11 via the output wiring 20.

  One conduction terminal (source terminal) 21b of the two conduction terminals of the driver transistor 21 is connected to a power source. The power supply voltage VDD is applied to the conduction terminal 21b. The remaining conduction terminal (drain terminal) 21 c of the driver transistor 21 is connected to one conduction terminal (drain terminal) 22 b of the two conduction terminals of the bias transistor 22. The output wiring 20 is also connected to the conduction terminal 22b. The remaining conduction terminal (source terminal) 22 c of the bias transistor 22 is connected to the ground 24.

  Further, a selection signal (/ VSEL1 or / VSEL2) is input to the gate terminal 23a of the switching transistor 23. On the other hand, the inverted signal (VSEL1 or VSEL2) of the selection signal is input to the gate terminal 22a of the bias transistor 22. As will be described later, the bias transistor 22 is, for example, an n-channel MOS transistor, and an intermediate bias potential using the constant current transistor as long as it is applied to the gate terminal 22a.

  In addition, the conduction terminals 23b and 23c of the switching transistor 23 output the output signal VOUT when the logic of the selection signal input to the gate terminal 23a indicates the selection of the solid-state imaging device including the switching transistor 23, and the selection is performed. When not shown, the output signal VOUT is not output.

  Specifically, in the first embodiment, one conduction terminal (source terminal) 22c of the two conduction terminals of the switch transistor 23 is connected to the ground 24, and the remaining conduction terminals (drain terminals) 23b are Are connected to the output wiring 20. Furthermore, in the first embodiment, the driver transistor 21, the bias transistor 22, and the switching transistor 23 are n-channel MOS transistors.

  Therefore, for example, when selecting the solid-state imaging device 1 (1), the logic of the selection signal (/ VSEL1) is set to a low level as shown on the left side of FIGS. The logic of (/ VSEL2) may be set to a high level. At this time, the logic of the inverted signal (VSEL1) is naturally set to a high level, and the logic of the inverted signal (VSEL2) is set to a low level.

  In this case, in the solid-state imaging device 1 (1), the bias transistor 22 is turned on, the switching transistor 23 is turned off, and an output signal (VOUT 1) corresponding to the pixel input signal (VIN 1) is output from the output wiring 20. The On the other hand, in the solid-state imaging device 1 (2), the bias transistor 22 is cut off, the switching transistor 23 is turned on, and the output wiring 20 is short-circuited to the ground 24. Therefore, the potential of the output signal VOUT (2) is fixed to the ground potential (0 [V]), and the current flowing through the output circuit 2 (output wiring 20) of the solid-state imaging device 1 (2) is 0 (zero).

  Conversely, when selecting the solid-state imaging device (2), as shown on the right side of FIGS. 4A to 4C, the logic of the selection signal (/ VSEL2) is set to low level and the selection signal (/ VSEL1) is selected. ) Should be set to a high level. The logic of the inverted signal (VSEL1) is set to a low level, and the logic of the inverted signal (VSEL2) is set to a high level.

  In this case, in the solid-state imaging device 1 (2), the output signal VOUT (2) corresponding to the pixel input signal (VIN 2) is output from the output wiring 20. On the other hand, the potential of the output signal (VOUT (1)) in the solid-state imaging device 1 (1) is fixed to the ground potential, and the current flowing through the output circuit 2 (wiring 22c) of the solid-state imaging device 1 (1) is 0 (zero). It becomes.

  Thus, since the current flowing through the output circuit 2 of the solid-state imaging device 1 that has not been selected becomes 0 (zero), the power consumption there also becomes 0 (zero). Therefore, according to the first embodiment, it is possible to significantly reduce power consumption in the imaging apparatus as compared with the conventional example. Note that, as shown in FIG. 4B, an output signal serving as imaging data (AFEIN) is input to the signal processing unit 11 regardless of which solid-state imaging device is selected. The signal processing unit 11 can operate efficiently.

  Furthermore, in the first embodiment, since a solid-state imaging device can be selected without using a signal selection circuit as in the conventional example, a wiring structure in which each output wiring 20 is short-circuited by a single wiring 19 can be achieved. . Each output wiring 20 is connected to the signal processing unit 11 via a wiring 19. As described above, in the imaging apparatus according to the first embodiment, the circuit configuration is simplified and the scale thereof is reduced as compared with the imaging apparatus of the conventional example, so that the imaging apparatus can be downsized.

  Further, as described above, in the first embodiment, in the solid-state imaging device 1 that is not selected, the potential of the output signal (VOUT) is fixed. For this reason, when noise is applied from the outside in the output circuit 2 of the solid-state imaging device 1 that is not selected, this noise can be prevented from propagating to the signal processing unit 11.

  As shown in FIGS. 2 and 3, in the first embodiment, each output wiring 20 is provided with a capacitor 9, and an output signal (VOUT) is sent to the signal processing unit 11 via the capacitor 9. It is output. This is because, in the solid-state imaging device 1 that is not selected, the potential of the output signal is fixed to a fixed potential (the ground potential in the first embodiment), and therefore the selected solid-state imaging when the capacitor 9 is not provided. This is because the potential of the output signal is also fixed at a fixed potential in the device 1.

  Next, the signal processing unit 11 shown in FIG. 2 will be specifically described with reference to FIG. FIG. 5 is a block diagram showing a configuration of the signal processing unit shown in FIG. As shown in FIG. 5, the signal processing unit 11 includes an AFE 12 that performs analog signal processing, an A / D conversion circuit 13, a DSP 14 that performs digital signal processing, and a D / A conversion circuit 15.

  The AFE 12 mainly includes a CDS (correlated double sampling) circuit and an AGC (automatic gain control) circuit. The CDS circuit calculates the difference between the voltage level in the field through period T2 and the voltage level in the data period T3, and obtains the voltage level of the signal generated by the incidence of light therefrom. The AGC circuit automatically adjusts the gain so that the amplitude of the input signal becomes an optimum amplitude with respect to the input dynamic range of the A / D conversion circuit 13.

  The signal analog-processed by the AFE 12 is input to the A / D conversion circuit 13 and converted into a digital signal. The obtained digital signal is input to the DSP 14 and digitally processed. Specifically, the DSP 14 performs conversion to an image format, white balance adjustment, and the like. The signal digitally processed by the DSP 14 is input to the D / A conversion circuit 15, where it is converted into an analog signal to become an image signal. The image signal is input to a display device or the like, and a captured image is displayed.

  Next, an example in which the solid-state imaging device and the imaging device according to the first embodiment are used in a capsule endoscope apparatus will be described. FIG. 6 is a configuration diagram illustrating a schematic configuration of a solid-state imaging device and a capsule endoscope device equipped with the imaging device according to the first embodiment.

  As shown in FIG. 6, the endoscope device 16 includes an imaging device similar to the imaging device shown in FIG. 2, and a power source 18 that supplies power to each part of the endoscope device 16. In the example of FIG. 6, the number of solid-state imaging devices 1 is two, but is not limited to this. The solid-state imaging device 1 is disposed at one end and the other end. Each solid-state imaging device 1 includes a lens element 17. In the first embodiment, signals are sent from the control unit 10 to the solid-state imaging device 1, from the solid-state imaging device 1 to the signal processing unit 11, and from the control unit 10 to the signal processing unit 11, respectively.

  When this endoscopic device 16 is administered to the inside of a human body, the solid-state imaging device 1 is alternately operated to perform photographing inside the human body. At this time, the power supply to the solid-state imaging device 1 is provided by the power source 18. However, since the solid-state imaging device 1 that has not performed imaging does not consume power, occurrence of a situation where the power supply by the power source 18 is insufficient is suppressed. The For this reason, if the endoscope apparatus 16 in this Embodiment 1 is used, each part in a patient's body can be imaged reliably, and it can contribute to an early lesion finding.

  In the example of FIG. 6, the control unit 10 performs control necessary for the entire endoscope apparatus 16 in addition to supplying the selection signal (/ VSEL) to the solid-state imaging device 1. As the control unit 10, a microcomputer including a CPU and a memory can be used. In this case, the microcomputer can also function as a DSP.

(Embodiment 2)
Next, a solid-state imaging device and an imaging device according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 7 is a circuit diagram showing a configuration of an output circuit mounted on the solid-state imaging device according to Embodiment 2 of the present invention. 8 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 7, FIG. 8 (a) shows a selection signal, FIG. 8 (b) shows an output signal output from the output wiring, FIG. 8C shows the current flowing through the output circuit.

  As shown in FIG. 7, the output circuit 25 in the second embodiment is different from the output circuit 2 shown in FIG. 3 in the first embodiment in the arrangement of the switching transistor 23. Specifically, one conduction terminal (drain terminal) 23c of the switching transistor 23 is connected to a power source, not to ground.

  In other respects, the output circuit 25 is configured similarly to the output circuit 2 shown in FIG. A capacitor 9 is also provided in the output wiring 20 of each output circuit 25. Also in the second embodiment, as in the first embodiment, as shown on the left side of FIGS. 8A to 8C, for example, when the solid-state imaging device 1 (1) is selected, the selection is performed. The logic of the signal (/ VSEL1) is set to a low level, and the logic of the selection signal (/ VSEL2) is set to a high level. Further, when the solid-state imaging device (2) is selected, as shown on the right side of FIGS. 8A to 8C, the logic of the selection signal (/ VSEL2) is set to the high level, and the selection signal (/ VSEL1) Logic is set low.

  However, due to the differences described above, in the solid-state imaging device 1 that has not been selected, the output wiring 20 is short-circuited to the power source. Therefore, as shown in FIG. 8C, the potential of the output signal VOUT (2) is fixed to the power supply potential (VDD), and the current flowing through the output circuit 2 (conduction terminal 22c) of the solid-state imaging device 1 that is not selected. Becomes 0 (zero).

  As described above, also in the second embodiment, as in the first embodiment, the current flowing through the output circuit 2 of the unselected solid-state imaging device 1 becomes 0 (zero). Is also 0 (zero). Therefore, even when the second embodiment is used, power consumption in the imaging apparatus can be significantly reduced as compared with the conventional example. Furthermore, also in the second embodiment, since the solid-state imaging device can be selected without using a signal selection circuit as in the conventional example, the scale of the circuit configuration is reduced and the imaging device can be downsized.

  As described above, also in the second embodiment, the potential of the output signal (VOUT) is fixed in the unselected solid-state imaging device 1 as in the first embodiment. For this reason, when noise is applied from the outside in the output circuit 2 of the solid-state imaging device 1 that is not selected, this noise can be prevented from propagating to the signal processing unit 11.

(Embodiment 3)
Next, a solid-state imaging device and an imaging device according to Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 9 is a configuration diagram showing the overall configuration of the imaging apparatus according to Embodiment 3 of the present invention. FIG. 10 is a circuit diagram showing a configuration of an output circuit mounted on the solid-state imaging device according to Embodiment 3 of the present invention. 11 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 10, FIG. 11 (a) shows a selection signal, FIG. 11 (b) shows an output signal output from the output wiring, FIG. 11C shows a current flowing through the output circuit.

  As shown in FIGS. 9 and 10, the output circuit 26 in the third embodiment is different from the output circuit 2 and the second embodiment shown in FIG. 3 in the first embodiment in terms of the configuration and arrangement of the switching transistors. This is different from both of the output circuits 25 shown in FIG.

  Specifically, as shown in FIG. 10, in the third embodiment, the portion between the two conduction terminals (between the source and the drain) in the switching transistor 23 constitutes a part of the output wiring 20. . That is, one conduction terminal (source terminal) 23 b of the switching transistor 23 is connected to the conduction terminal (source terminal) 21 c of the driver transistor 21, and the other conduction terminal (drain terminal) 23 c of the switching transistor is connected to the signal processing unit 21. It is in a connected state.

  Further, because of such a configuration, in the third embodiment, the selection signal (/ VSEL) is input to the gate terminal 22a of the bias transistor 22 as well as the gate terminal 23a of the switching transistor 23. Therefore, unlike the first and second embodiments, the control unit 10 (see FIG. 9) inputs only the selection signal (/ VSEL) and does not input the inverted signal (VSEL) to each individual imaging device 1.

  Therefore, in the third embodiment, for example, when selecting the solid-state imaging device 1 (1), the logic of the selection signal (/ VSEL1) is high as shown on the left side of FIGS. The logic level of the selection signal (/ VSEL2) is set to a low level.

  In this case, in the solid-state imaging device 1 (1), the bias transistor 22 is in a conductive state, and the switching transistor 23 is also in a conductive state. In the solid-state imaging device 1 (1), an output signal (VOUT1) corresponding to the pixel input signal (VIN1) is output from the output wiring 20. On the other hand, in the solid-state imaging device 1 (2), the bias transistor 22 is cut off and the switching transistor 23 is also cut off, and the current flowing through the output circuit 2 (conduction terminal 22c) of the solid-state imaging device 1 (2) is 0 (zero). It becomes.

  Conversely, when selecting the solid-state imaging device (2), as shown on the right side of FIGS. 11A to 11C, the logic of the selection signal (/ VSEL2) is set to high level and the selection signal (/ VSEL1) is selected. ) Logic is set to low level. In this case, in the solid-state imaging device 1 (2), the output signal VOUT (2) corresponding to the pixel input signal (VIN 2) is output from the output wiring 20. On the other hand, the current flowing through the output circuit 2 (conduction terminal 22c) of the solid-state imaging device 1 (1) is 0 (zero).

  Further, according to the configuration of the output circuit 26 as described above, in the third embodiment, it is not necessary to provide a capacity (see FIGS. 3 and 7) for each output wiring 20. This is because in the output circuit 2 of the solid-state imaging device 1 that is not selected, a part of the output wiring 20 is in a floating state (that is, connected to the diffusion layer), and the potential of the output signal (VOUT) is It is because it is not fixed. Therefore, according to the third embodiment, the circuit configuration can be further simplified as compared with the first and second embodiments.

  As described above, since the switching transistor 23 provided in the solid-state imaging device is in a conductive state only during the period in which the solid-state imaging device is selected, the output circuit 2 of the solid-state imaging device 1 that is not selected also in the third embodiment. The current flowing through the (conduction terminal 22c) is 0 (zero). Therefore, even when the third embodiment is used, the power consumption in the unselected solid-state imaging device 1 is 0 (zero), and the power consumption in the imaging device can be significantly reduced as compared with the conventional example. it can. Further, in the third embodiment, the solid-state imaging device can be selected without using a signal selection circuit as in the conventional example, so that the scale of the circuit configuration is reduced and the imaging device can be downsized.

  As described above, by using the solid-state imaging device and the imaging device according to the present invention, it is possible to reduce power consumption and a circuit scale in an imaging device including a plurality of solid-state imaging devices. The solid-state imaging device and the imaging device according to the present invention have industrial applicability.

FIG. 1 is a configuration diagram showing the overall configuration of the solid-state imaging device according to Embodiments 1 to 3 of the present invention. FIG. 2 is a configuration diagram showing the overall configuration of the imaging apparatus according to Embodiment 1 of the present invention. FIG. 3 is a circuit diagram showing a configuration of an output circuit mounted on the solid-state imaging device according to Embodiment 1 of the present invention. 4 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 3, FIG. 4 (a) shows a selection signal, FIG. 4 (b) shows an output signal output from the output wiring, FIG. 4C shows the current flowing through the output circuit. FIG. 5 is a block diagram showing a configuration of the signal processing unit shown in FIG. FIG. 6 is a configuration diagram illustrating a schematic configuration of a solid-state imaging device and a capsule endoscope device equipped with the imaging device according to the first embodiment. FIG. 7 is a circuit diagram showing a configuration of an output circuit mounted on the solid-state imaging device according to Embodiment 2 of the present invention. 8 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 7, FIG. 8 (a) shows a selection signal, FIG. 8 (b) shows an output signal output from the output wiring, FIG. 8C shows the current flowing through the output circuit. FIG. 9 is a configuration diagram showing the overall configuration of the imaging apparatus according to Embodiment 3 of the present invention. FIG. 10 is a circuit diagram showing a configuration of an output circuit mounted on the solid-state imaging device according to Embodiment 3 of the present invention. 11 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 10, FIG. 11 (a) shows a selection signal, FIG. 11 (b) shows an output signal output from the output wiring, FIG. 11C shows a current flowing through the output circuit. FIG. 12 is a block diagram illustrating a schematic configuration of a conventional imaging device including a plurality of solid-state imaging devices. FIG. 13 is a circuit diagram showing an output circuit for a conventional solid-state imaging device. 14 is a diagram showing signal timing and waveforms in the output circuit shown in FIG. 13. FIG. 14A shows a reset signal and an inverted reset clock signal, and FIG. 14B is outputted from the output wiring. FIG. 3C shows the current flowing through the output circuit.

Explanation of symbols

1 (1) to (n) Solid-state imaging device 2 Output circuit 3 Vertical scanning circuit 4 Horizontal scanning circuit 5 Column readout unit 6 Timing generator 7 Pixel array 8 Pixel 9 Capacitance 10 Control unit 11 Signal processing unit 12 AFE
13 A / D conversion circuit 14 DSP
15 D / A conversion circuit 19 Wiring 20 Output wiring 21 Drive transistor 21a Drive transistor gate terminal 21b, 21c Drive transistor conduction terminal 22 Bias transistor 22a Bias transistor gate terminal 22b, 22c Bias transistor conduction terminal 23 Switching transistor 23a Switching Transistor gate terminals 23b, 23c Switching transistor conduction terminal 24 Ground 25 Output circuit 26 Output circuit

Claims (9)

A plurality of solid-state imaging devices; a control unit that selects a solid-state imaging device that performs imaging from the plurality of solid-state imaging devices; and a signal processing unit,
Each of the plurality of solid-state imaging devices includes an output circuit,
The control unit inputs, for each of the plurality of solid-state imaging devices, a logic signal that specifies whether or not the logic signal is selected, or the logic signal and an inverted signal of the logic signal,
The output circuit of each of the solid-state imaging devices outputs a drive transistor, a bias transistor, a switching transistor, and an output signal corresponding to the pixel input signal to the signal processing unit. Output wiring for
One conduction terminal of the two conduction terminals of the driver transistor is connected to a power source,
The remaining conduction terminal of the driver transistor is connected to one conduction terminal of the two conduction terminals of the bias transistor and the output wiring,
The remaining conduction terminal of the bias transistor is connected to ground,
The logic signal is input to the gate terminal of the switching transistor,
The logic signal or the inverted signal is input to the gate terminal of the bias transistor,
The two conduction terminals of the switching transistor output the output signal from the output wiring when the logic of the logic signal input to the gate terminal indicates selection of a solid-state imaging device including the switching transistor. The image pickup apparatus is arranged so that the output signal is not output from the output wiring when selection is not indicated.   The output wiring provided in the output circuit of each of the plurality of solid-state imaging devices is all connected to a common single wiring, and is connected to the signal processing unit via the single wiring. The imaging device described. In each output circuit of the plurality of solid-state imaging devices,
One conduction terminal of the two conduction terminals of the switching transistor is connected to the ground,
The remaining conduction terminal of the switching transistor is connected to the output wiring;
The inverted signal is input to the gate terminal of the bias transistor,
The solid-state imaging device according to claim 1, wherein a capacitance is provided in the output wiring, and the output signal is output via the capacitance. In each output circuit of the plurality of solid-state imaging devices,
One conduction terminal of the two conduction terminals of the switching transistor is connected to the power source,
The remaining conduction terminal of the switching transistor is connected to the output wiring,
The inverted signal is input to the gate terminal of the bias transistor,
The solid-state imaging device according to claim 1, wherein a capacitance is provided in the output wiring, and the output signal is output via the capacitance. In each output circuit of the plurality of solid-state imaging devices,
A portion between two conduction terminals in the switching transistor constitutes a part of the output wiring,
The solid-state imaging device according to claim 1, wherein the logic signal is input to a gate terminal of the bias transistor. A solid-state imaging device having an output circuit,
The output circuit includes a drive transistor in which a pixel input signal is input to a gate terminal, a bias transistor, a switching transistor, and an output wiring that outputs an output signal corresponding to the pixel input signal,
One conduction terminal of the two conduction terminals of the driver transistor is connected to a power source,
The remaining conduction terminal of the driver transistor is connected to one conduction terminal of the two conduction terminals of the bias transistor and the output wiring,
The remaining conduction terminal of the bias transistor is connected to ground,
In the two conduction terminals of the switching transistor, a logic signal is inputted from the outside to the gate terminal of the switching transistor, and the logic signal or an inverted signal of the logic signal is inputted to the gate terminal of the bias transistor. The output signal is output from the output wiring when the logic signal logic is one logic, and the output signal is output from the output wiring when the logic signal logic is another logic. A solid-state image pickup device arranged so as not to be moved. One conduction terminal of the two conduction terminals of the switching transistor is connected to the ground,
The remaining conduction terminal of the switching transistor is connected to the output wiring;
The solid-state imaging device according to claim 6, wherein the inverted signal is input to a gate terminal of the bias transistor. One conduction terminal of the two conduction terminals of the switching transistor is connected to the power source,
The remaining conduction terminal of the switching transistor is connected to the output wiring;
The solid-state imaging device according to claim 6, wherein the inverted signal is input to a gate terminal of the bias transistor. A portion between two conduction terminals in the switching transistor constitutes a part of the output wiring,
The solid-state imaging device according to claim 6, wherein the logic signal is input to a gate terminal of the bias transistor.

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