JP2008186476A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer in which onboard writing can be performed by user exclusive use communication protocol even if serial interface is not made on a mounting board, and in which the user exclusive use communication protocol codes are not destroyed even if the microcomputer runs away. <P>SOLUTION: The microcomputer is provided with a CPU (2), a non-volatile memory (13), and a RAM (3). The non-volatile memory includes a first domain (Tmat) which possesses a communication control program processed by the CPU, a second domain (Umat) in which interface with the outside is established by the processing of the communication control program by the CPU and deleting and writing are enabled, and a third domain (Mmat) in which interface with the outside is established by the processing of the communication control program by the CPU, deleting and writing are enabled, and deleting and writing are enabled by the processing of the program of the second domain by the CPU. The second domain and the third domain can be selected exclusively by a register. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a microcomputer having an electrically erasable and writable non-volatile memory and a CPU (central processing unit), and more particularly to permission and prohibition of erasing and writing operations for the non-volatile memory. The present invention relates to an effective technology applied to microcomputers.

  An electrically erasable and writable nonvolatile memory such as a flash memory stores information according to a difference in threshold voltage programmed in the memory cell. In the flash memory, the difference in threshold voltage is realized by the difference in the amount of electrons or holes held in the floating gate. For example, a relatively high threshold voltage state with respect to a threshold voltage in a thermal equilibrium state is referred to as a write state, and a relatively low threshold voltage state is referred to as an erase state (the reverse definition is also possible). At this time, although not particularly limited, in each of the erasing operation for setting the memory cell in the erasing state and the writing operation for setting the memory cell in the writing state, the application of the high voltage pulse and the verification of the threshold voltage state are repeated. As an operation mode that enables erasing and writing to an on-chip flash memory of a microcomputer, there are those having a writer mode and a boot mode. The writer mode is an operation mode in which, for example, a microcomputer is apparently equivalent to a flash memory chip and is connected to a writing device such as an EPROM writer to enable erasing and writing. The boot mode is an operation mode that enables erasing and writing by establishing communication with the mounting system via an asynchronous or asynchronous serial interface (UART) with the microcomputer mounted on the system, for example. The writer mode can be used to write programs and data to the on-chip flash memory initially before system mounting. On the other hand, when the information stored in the on-chip flash memory is rewritten for system version upgrade or data tuning after system installation, the boot mode can be used.

  Conventionally, a serial interface is used as a basic interface method in the boot mode. Therefore, when performing on-board rewriting using the boot mode, a serial interface such as start-stop synchronization is used on the microcomputer mounting system board. A circuit was installed.

  However, there are systems that do not originally require a serial interface circuit such as start-stop synchronization. For example, CD-ROM (Compact Disk-Read Only Memory), CD-RW (Compact Disk-rewritable), DVD-ROM (Digital Video Disk-Read Only Memory), DVD-RAM (Digital Video Disk-Random Access Memory), etc. In such disk drive systems, interfaces such as ATAPI (AT Attachment Packet Interface) and SCSI (Small Computer System Interface) inevitably exist. In an automotive control system such as an engine or transmission, there is an area network interface called HCAN. Thus, even if an interface such as ATAPI, SCSI, or HCAN exists on the system board of each user, it is necessary to additionally provide a serial interface such as start-stop synchronization in order to perform on-board rewriting in the boot mode. For example, this creates an overhead problem for the user's system board.

  In order to avoid this, on-board writing may be performed in a user program mode in which a program can be executed in a storage area (that is, a user memory area) on the flash memory that is allowed to be freely used. That is, a communication protocol processing program dedicated to the user system board such as ATAPI is written in advance in the user memory area in the writer mode, for example. After implementing this, if the microcomputer is mounted on the user's system board and the communication protocol processing program dedicated to the user is executed by the CPU, the user memory area can be stored even if the user's system board does not have a serial interface. Program version upgrade and tuning data rewrite can be performed.

  However, when the dedicated communication protocol processing program is also written in the user area where the user's control program and tuning data are written, when the user creates the control program, the program of the dedicated communication protocol is not easily deleted by mistake. There is a concern that it will be a heavy burden for the user to create a program. In addition, when the CPU runs out of control in the user program mode after being mounted on the system board, if the processing program of the communication protocol that can be executed in the user program mode disappears by mistake, the user system is deleted for erasing and writing. An interface cannot be established with the board again. The present inventor has revealed a problem that rewriting cannot be performed unless the microcomputer chip is removed from the mounting substrate and the writer mode is used. In this specification, the user means a user of a semiconductor device such as a microcomputer in a broad sense. Therefore, if a manufacturer of a semiconductor device uses the semiconductor device in any sense, the manufacturer is also a user.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer having a configuration in which program information such as a communication protocol with a mounting board that will receive a fatal blow on the system when erased is unlikely to disappear from a nonvolatile memory. It is in.

  Another object of the present invention is to provide a microcomputer capable of guaranteeing the establishment of an interface even for an individual communication protocol supported by a mounting board of the microcomputer.

  An object of the present invention is to provide a microcomputer capable of suppressing the loss of stored information in an on-chip nonvolatile memory as much as possible even when a CPU runs away.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  [1] The outline of representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the on-chip nonvolatile memory of the microcomputer, a second area (user boot mat) is prepared in addition to the third area (user mat) in which a user (microcomputer user) control program is written. This user boot mat is used, for example, as a storage area (mat) for writing a user-specific communication protocol, and a user boot mode for executing a program from the mat is also prepared as a dedicated mode. In this user boot mode, the user boot mat is disabled from being erased and writable.

  The effect by the above is as follows. (1) Since a user boot mat capable of storing a user-specific communication protocol is prepared, any interface provided in the microcomputer can be used. (2) Since it is possible to employ any user interface for erasing and writing to the nonvolatile memory, it is not necessary to prepare a serial interface on the user mounting board. (3) By separating the user boot mat from the user mat, it is possible to realize a user-specific writing interface for erasing and writing without writing a dedicated communication protocol processing program in the user mat. It is easy to create a control program to be used. In short, it is not necessary to pay special consideration to prevention of erasure of the communication control program used in the user program mode. (4) In the user boot mode that rises from the user boot mat, the user boot mat cannot be erased and written by hardware, so that the stored information of the user boot mat is not destroyed due to runaway or the like, and the CPU is used during debugging. If the program runs out of control, the program that controls the external interface will not be destroyed, so the user mat can be freely rewritten on-board without removing the mounted microcomputer chip.

  [2] A microcomputer according to a more detailed first aspect of the present invention includes a CPU, an electrically erasable and writable first area (boot mat), a second area (user boot mat), and a third area ( A non-volatile memory having a user mat) and an operation mode instruction means. The operation mode instruction means causes the CPU to process the program in the first area, makes the first area unerasable and non-writable (boot mode), and causes the CPU to process the program in the second area. In addition, a second mode (user boot mode) for making the first area and the second area unerasable and non-writable, and causing the CPU to process a program for the third area and not erasing and writing the first area and the second area. The third mode (user mode) to be enabled is instructed, and is realized by, for example, a mode signal input circuit.

  The microcomputer according to this aspect is in a state in which no specific program is stored in the second area and the third area, that is, a state before the user has stored the desired program in the second and third areas. Also means. When the microcomputer is mounted on the system board, a communication protocol processing program for establishing an interface unique to the system board is stored in the second area, a user program for controlling the system board, tuning data, etc. in the third area Is used to control the user system. When performing on-board writing, a second mode such as a user boot mode is designated, the CPU processes the communication protocol processing program in the second area, etc., and an interface unique to the system board is established. The user program in the area can be upgraded or the tuning data can be rewritten. Therefore, the effects (1) to (4) can be obtained.

  [3] A microcomputer according to the second aspect of the present invention further includes a CPU, an electrically erasable and writable first area (boot mat), a second area (user boot mat), and a third area ( Non-volatile memory having a user mat) and instruction means for selectively specifying the first mode, the second mode, or the third mode. The CPU processes the program in the first area by designating the first mode, processes the program in the second area by designating the second mode, and processes the program in the third area by designating the third mode. In the nonvolatile memory, the second area and the third area are made erasable and writable by the designation of the first mode, and the first area is made erasable and writable, and the third area is made to be designated by the second mode. The first area and the second area are made erasable and writable, and the third area is made erasable and writable by the designation of the third mode, and the first area and the second area are erased and writable. Writable. Also in the microcomputer of this aspect, the effects (1) to (4) can be obtained.

  The first area may have a first communication control program for establishing an interface with the outside of the microcomputer. Since the first area cannot be erased or written in any of the first to third operation modes, it is initially written using a writing device such as an EPROM writer in the manufacturing process of the microcomputer. The first communication control program may be a serial interface program based on basic start-stop synchronization.

  The second area may have a second communication control program for establishing an interface with the outside of the microcomputer. Since the second area can be erased and written in the first mode, the second communication control program is a communication control program that satisfies a user-specific communication protocol, that is, an interface specification (for example, ATAPI) specific to the system board. It's okay.

  Since the first area cannot be erased or written in any of the first to third operation modes, if the first area has an erase and write control program for the nonvolatile memory, Can be prevented from disappearing undesirably.

  Similarly, the first area may have a transfer control program for the erase and write control program.

  A RAM to which the erasing and writing control program is transferred by processing of the transfer control program by the CPU may be built in the microcomputer. The CPU can execute the erase and write control program on the built-in RAM.

  From the viewpoint of preventing undesired rewriting of the non-volatile memory due to a runaway of the CPU, the non-volatile memory performs an erasing and a writing operation instruction from the external terminal separately from the mode designation by the instruction means. Add to the requirements to make it possible.

  [4] Focusing on the reset vector address of the CPU in the microcomputer according to the second aspect (vector address to be referred to after the reset is released), the first address in each of the first area, the second area, and the third area is the CPU. The first register means (FMATS) that exclusively designates whether the head address used by the CPU is the second area or the third area is arranged in the address space of the CPU. Can be adopted.

  In this configuration, when a program in the first area is executed by specifying the first mode, if the program in the first area itself does not include a processing routine for erasing and writing to the first area, erasing the first area And no writing is performed. Assuming that the development of a program to be stored in the first area and the writing of the program are performed by a microcomputer manufacturer, it is perfectly possible to make erasure and writing to the first area impossible. After executing the program in the first area by specifying the first mode, it is possible to transition to a state where the program in the second area or the third area can be executed according to the setting of the first register means. After this, it is basically impossible to return to the state in which the program in the first area can be executed only by the program stored in the second area or the third area, and hardware that allows the temporary return is provided. However, the first area cannot be erased and written.

  If the RAM is arranged in the address space of the CPU, the CPU can transfer and execute the program on the RAM.

  If the setting change of the first register means is permitted on the condition that the CPU is processing the program on the RAM, it is different from the state in which the program is fetched in any one of the first to third areas. The transition of program execution in this area can be smoothed. The setting change of the first register means may be permitted on condition that the bus control means (BSC) detects that the CPU is processing the program on the RAM.

  There is provided second register means (FKEY) in which information for giving permission to the operation of storing the erase and write control program in the RAM is set, and the non-volatile memory has the permission information of the second register means reset. It may be necessary to make the erase and write operations possible. According to this, even if the CPU goes out of control when it is not necessary to transfer the erase and write control program to the RAM, the erase and write control program is erroneously transferred to the RAM due to the reset state of the second register means. The probability of undesired execution can be reduced. In addition, even if the CPU runs out of control while transferring the erase and write control program to the RAM, the set state of the second register means is a condition for inhibiting the erase and write operations. Can reduce the probability that the execution is erroneously started.

  [5] Attention is paid to the erase and write control program in the microcomputer according to the second aspect. A RAM is arranged in the address space of the CPU, and an erase and write control program is stored in the first area. The CPU controls the transfer of the erase and write control program to the RAM in response to the first mode. The erase and write control program may be fetched from the transfer destination RAM and executed. Microcomputer users do not need to develop erase and write control programs. If the erase and write control program is executed on the RAM, the erase and write to the second area and the third area can be facilitated in the first mode.

  In order to make the erase and write control program for the first area usable also in the second mode, for example, in the second mode, the CPU responds to the first set value of the third register means (SCO) in the second mode. The state may be changed to a state where a program in one area is processed, and the erase and write control program is controlled to be transferred to the RAM so as to return to a state where the program in the second area is processed.

  In order to make the erase and write control program for the first area usable also in the third mode, for example, in the third mode, the CPU responds to the first set value of the third register means (SCO) in response to the first set value. The state may be changed to a state where a program in one area is processed, and the erase and write control program is controlled to be transferred to the RAM so as to return to a state where the program in the third area is processed.

  Second register means (FKEY) in which a second set value is set as information for giving permission to the operation of storing the erase and write control program in the RAM is provided. The nonvolatile memory has permission information of the second register means. The reset to the third set value is a necessary condition for enabling the erase and write operations, and a state in which the second set value is set in the second register means is set in the third register means. It may be a necessary condition for enabling the value to be set. In short, if the program runs out of control where the user does not want to perform erasing and writing, and the erasing and writing control program is transferred, there is a high possibility that the user program will be destroyed. In order to avoid this, the user stores the second setting value in the second register means before setting the first setting value in the third register means. When the second set value is not stored, the third register means cannot be set to the first set value. When the second set value is stored in the second register means, it is possible to set the third register means to the first set value, thereby enabling program transfer.

  Considering the case where the program runs away after the erase and write control program is transferred, the second register is used. Basically, even if the CPU runs out of control due to other conditions, erasure and writing are not performed, but in order to further improve the reliability, the user must A third set value is set in the second register means. When the third set value is not stored, the erase and write operations remain disabled even if other erase and write conditions are erroneously enabled.

  [6] Pay attention to a storage area open to the user in the nonvolatile memory. The microcomputer includes a CPU and an electrically erasable and writable nonvolatile memory. The nonvolatile memory includes a first memory mat (user boot mat) and a second memory mat (user mat). The mat and the second memory mat can be selected exclusively by a register. When the first memory mat is selected, the erase and write operations on the first memory mat are suppressed, and the second memory mat is selected. In such a case, transition to the program execution state on the RAM is used as a release condition, and the erase and write operations are suppressed. As a result, it is possible to prevent the occurrence of an inconvenient state due to erasing and writing of the memory mat that is currently executing the program.

  [7] Focus on the entire storage area of the nonvolatile memory. The microcomputer has a CPU and an electrically erasable and writable nonvolatile memory, and the nonvolatile memory is a communication control program (serial communication PGM) processed by the CPU to establish an interface with the outside. ) Possessing a first area (boot mat), a second area (user boot mat) that is made erasable and writable by establishing an interface with the outside by processing of the communication control program by the CPU, and by the CPU A third area (user mat) that has an interface with the outside established by the processing of the communication control program and can be erased and written, and can be erased and written by the program of the second area by the CPU; .

  [8] A microcomputer according to still another aspect is a microcomputer to be mounted on a mounting board having a first interface (ATAPI, SCSI, HCAN), and a central processing unit and a second interface different from the first interface. A first storage area (boot mat) for storing a first communication processing program for establishing a communication protocol (UART) using an interface (SCI), and a communication protocol for establishing the communication protocol using the first interface A second storage area (user boot mat) in which a second communication processing program is stored, and a third storage area (user mat) in which a control program executed by the central processing unit in a predetermined first operation mode is stored A non-volatile memory.

  The first storage area further stores a write control program. At this time, the second communication processing program stored in the second storage area stores the write control program and the first communication processing program in the center. The data is written into the second storage area by the first write mode executed by the processing device.

  The control program stored in the third storage area is executed by the central processing unit by the first write mode or the write control program and the second communication processing program stored in the first storage area. The data is written into the third storage area according to any of the second write modes.

  The first storage area further stores an erasure control program. At this time, the second communication processing program stored in the second storage area stores the erasure control program and the first communication processing program in the center. Erasing from the second storage area is enabled by the first erasing mode executed by the processing device.

  The control program stored in the third storage area is the first erasing mode or the erasing control program and the second communication processing program stored in the first storage area are executed by the central processing unit. The data can be erased from the third storage area by any one of the two erase modes.

  Further, the microcomputer according to the aspect different from the above stores the first communication processing program and the write control program for establishing the communication protocol (UART) using the central processing unit and the first interface (SCSI). A storage area; a second storage area for storing a second communication processing program for establishing a communication protocol using the second interface (ATAPI, SCSI, HCAN) different from the first interface; and a predetermined first A non-volatile memory having a third storage area for storing a control program executed by the central processing unit in an operation mode.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, even if a serial interface is not necessarily created on the user's mounting board, on-board writing can be performed with a user-specific communication protocol, and even if runaway occurs, the user-specific communication protocol code is not destroyed.

  A user control program may be created for the user mat, and the creation of the program is facilitated. In short, by separating the user boot mat from the user mat, it is possible to realize a user-specific writing interface for erasing and writing without writing a dedicated communication protocol in the user mat. It is easy to create a control program. Therefore, it is not necessary to pay special consideration to prevention of erasure of the communication control program used in the user program mode.

  In the user boot mode that rises from the user boot mat, the user boot mat cannot be erased or written in hardware, so the stored information in the user boot mat will not be destroyed due to runaway, etc., and the CPU will runaway during debugging. However, since the program for controlling the external interface is not destroyed, the user mat can be freely rewritten on-board without removing the mounted microcomputer chip.

<Microcomputer>
FIG. 1 shows a microcomputer as a data processing apparatus according to an example of the present invention. The microcomputer 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique.

  The microcomputer 1 has a central processing unit (CPU) 2 as an arithmetic control device, a RAM 3 as a nonvolatile memory, a bus state controller (BSC) 4, a flash memory 13, and other modules 7 generically including other built-in circuits. . The flash memory 13 is an example of an electrically rewritable nonvolatile memory, and includes a flash memory module 5 and a flash control module 6. As the other module 7, mask ROM 8, interrupt controller (INTC) 9, timer (TMR) 10, input / output port (I / O) 11, serial interface controller (SCI) 12, other interface controller 16, DMAC (Direct Memory Access Controller) ) 17 and the system controller 15. These circuit modules are interfaced via buses IAB, IDB, PAB, PDB, CONT.

  The buses IAB and IDB are an internal address bus and an internal data bus having a relatively high information transmission speed. The buses PAB and PDB are a peripheral address bus and a peripheral data bus whose information transmission speed is relatively low. The bus CONT is a generic name for control signal lines that transmit bus commands, bus access control signals, timing control signals, and the like. The BSC 4 optimally controls the access operation timing and the like according to the access address in response to the difference in operation speed between the internal buses IDB and IAB and the peripheral buses PDB and PAB, or the difference in the access form specific to the access target. Chip selection or module selection control is also performed.

  The system controller 15 receives a multi-bit mode signal 14 and a reset signal RES from the outside. When the reset signal RES is set to the low level by the power-on reset or the hardware reset of the microcomputer 1, the reset operation is performed inside the microcomputer 1 during the low level period. After canceling the reset by the reset signal RES, the operation mode of the microcomputer 1 is determined according to the state of the multi-bit mode signal 14. The CPU 2 reads the reset vector in the program area corresponding to the operation mode, fetches the instruction at the address, decodes the fetched instruction, and starts instruction execution.

  The RAM 3 is also used as a work area for the CPU 2 or a temporary storage area for data or programs. The mask ROM 8 is a storage area such as a data table. The flash memory module 5 is a storage area for programs and data of the CPU 2.

  The interrupt controller 10 receives an interrupt request given from the outside of the microcomputer 1 or an interrupt request generated from the built-in circuit module according to the internal state of the microcomputer 1 and competes according to the interrupt priority level, interrupt mask, etc. Interrupt request arbitration and interrupt mask processing based on interrupt priority level. The interrupt controller 10 gives an interrupt signal IRQ to the CPU 2 according to the result of the interrupt request arbitration and the interrupt mask process, and also gives the CPU 2 an interrupt vector address corresponding to the interrupt factor of the received interrupt request. The CPU 2 branches the process to a program designated by the interrupt vector address. The interrupt controller 9 receives interrupt mask data (IMSK) from the CPU 2 and masks reception of an interrupt request lower than the interrupt priority level indicated by the interrupt mask data (IMSK).

  The I / O 11 is used for connection to an external address bus and an external data bus, an external interface of the SCI 12, an external event signal input of the TMR 10, an external interface of the interface controller 16, and the like. The interface controller 16 is applicable to an interface such as ATAPI or SCSI, for example.

  FIG. 2 shows a specific example of the CPU 2. The CPU 2 is not particularly limited, but an arithmetic unit such as a shifter SFT and an arithmetic logic unit ALU, a register group such as a 32-bit general purpose registers R0 to R31, a program counter PC, a status register SR and a temporary register TR, and read data The execution unit includes buffer circuits such as a buffer RDB, a write data buffer WDB, and an address buffer AB, which are connected to a predetermined internal bus among the first to third internal buses IB1 to IB3. The CPU 2 includes an instruction register IR, an instruction decoder IDEC, and an instruction sequence logic INTL as an instruction control unit.

  The read data buffer RDB supplies, for example, data input from a 32-bit data bus IDB to the internal bus IB2. The status register SR has a field for interrupt mask data IMSK. The interrupt mask data IMSK is given to the interrupt controller 9. The interrupt controller 9 masks an interrupt request lower than the interrupt priority level indicated by the interrupt mask data IMSK.

  The program counter PC holds an instruction address to be executed next, and when the instruction address is output from the address buffer AB to the internal address bus IAB, the instruction read from the corresponding address of the RAM 3 or the like uses the internal data bus IDB. To the instruction register IR. The instruction decoder IDEC decodes the instruction in the instruction register IR, generates a control signal inside the CPU 2, and controls arithmetic processing by the execution unit. The instruction sequence logic INTL controls to change the instruction execution order in response to the interrupt signal IRQ and the like.

  In FIG. 1, a flash memory module 5 includes a memory cell array 20, an X decoder / driver (XDE / DV) 21, a sense amplifier array (SAA) 22, a Y switch array (YSW) 23, a Y decoder (YDE) 24, and an input / output circuit. (IFB) 25, power supply circuit (VGN) 26, and timing generator (TGN) 27. The memory cell array 20 has flash memory cells (not shown) arranged in a matrix. Although the flash memory cell is not particularly limited, the flash memory cell has a stack structure in which a source and a drain are provided in a semiconductor substrate or a well region, and a floating gate and a control gate are formed above the channel via an insulating film, respectively. The source line is connected to the bit line and the control gate is connected to the word line.

  The flash memory cell is programmable in threshold voltage and retains information according to the programmed threshold voltage. For example, when one flash memory cell holds 1-bit information, a relatively high threshold voltage state is referred to as a write state, and a relatively low threshold voltage state is referred to as an erase state. The write operation for obtaining the write state is not particularly limited, but 10 V is applied to the control gate, 5 V is applied to the drain, and 0 V is applied to the source and the substrate, and a current is caused to flow between the drain and source, thereby injecting hot electrons. Occurs, electrons are accumulated in the floating gate, and the threshold voltage of the memory cell increases. The erase operation for obtaining the erased state is not particularly limited, but 10V is applied to the control gate, -10V is applied to the source and the substrate, and the drain is opened (floating), for example. Are released to the substrate, which lowers the threshold voltage of the memory cell.

  The input / output circuit 25 inputs addresses, control signals, and commands and inputs / outputs data with the buses IAB, IDB, PAB, PDB, and CONT. The address signal input to the input / output circuit 25 is input to the XDEC / DV 21 and the YDE 24 and decoded. The XDEC / DV 21 selects a word line according to the decoding result. The YDE 24 selects a bit line via the YSW 23 according to the decoding result. A flash memory cell is selected by word line selection and bit line selection. In the read operation, read data of the selected flash memory cell is detected by the SAA 22 and output to the bus PDB or IDB via the input / output circuit 25. In the write operation, write data given from the bus PDB or IDB to the input / output circuit 25 is latched by the write latch circuit in the input / output circuit 25, and the memory cell selected by the word line is prevented from being written / written according to the latch data. Be controlled. Before the writing process, the flash memory cells are erased in units of blocks.

  The power supply circuit 26 includes a clamp circuit, a charge pump circuit, and the like, and supplies various voltages used in operations such as writing, erasing, and reading of the flash memory. The timing generator 27 performs interface control with the outside of the flash memory based on a strobe signal supplied via the control bus CONT and a command input via the data buses PDB and IDB.

  In FIG. 1, the flash control module 6 includes various control registers 30 and a control logic circuit 29 related to erasure and writing to the flash memory module 5 and program transfer therefor. FIG. 1 representatively shows FCCS, FKEY, FMATS, writer mode related registers, and write / erase related registers as control registers. The storage area of the RAM 3 and the general-purpose register of the CPU 2 are also used for controlling the erase and write operations for the flash memory module 5.

<Flash memory mat>
FIG. 3 illustrates a memory mat of a flash memory. The memory cell array 20 of the flash memory module 5 includes an electrically erasable and writable boot mat (first area) Tmat, a user boot mat (second area) Umat, a user mat (third area) Mmat, and repair and trimming. It has a mat Rmat. The boot mat Tmat, the user boot mat Umat, and the user mat Mmat are each allocated a memory space with the start address 0 (H′0000000) in the address space of the CPU 2 as a start address. In short, the boot mat Tmat, the user boot mat Umat, and the user mat Mmat are overlapped in address space, and the address decoder YDEC and XDEC / DV select the address decoding logic in response to an instruction on which mat is used. Will be. Which mat is used is determined by the operation mode of the microcomputer indicated by the mode signal 14. The repair and trimming mat Rmat stores setting data of a trimming circuit for alignment according to a defect relief address and circuit characteristics in the memory cell array.

"action mode"
In the flash memory, as the process generation progresses, the program related to writing and erasing is becoming more complicated. Under such circumstances, if the user has to create an erase and write control program, the burden on the user increases. In the microcomputer 1, it is considered that the user can reduce the burden of creating an erasing and writing program and can perform erasing and writing in any mode with a simple procedure. In particular, when tuning parameters such as the high voltage pulse application time for erasing and writing the flash memory 13 or changing the processing flow, it can be performed using software without depending on hardware, and can There is an operation mode that can be erased and written in a simple procedure without imposing a burden. Briefly describing the contents, the erase and write control program held by the boot mat Tmat can be referred to in any operation mode, and the program of the boot mat Tmat has a description about the security. The user can use the program as long as there is no inconvenience.

  The operation mode of the macro computer 1 will be described in detail. Focusing on erasing and writing to the flash memory 13, the microcomputer 1 has a writer mode, a boot mode (first mode), a user boot mode (second mode), and a user mode (third mode). Although not particularly limited, the mode signal 14 is 2 bits, and the system controller 15 decodes the combination of the logical values, and the designated operation mode is the writer mode, boot mode, user boot mode, or It is determined which of the user modes.

  The writer mode is an operation mode that enables erasing and writing of the flash memory 13 using a writing device such as an EPROM writer. When the writer mode is designated, after reset processing, the CPU 2 performs vector fetch from the head address of the boot mat Tmat and starts execution of the program (starts from the boot mat). Then, as a process necessary for the writer mode, all of the command determination program and the erase and write related programs are transferred to the RAM 3. Thereafter, the CPU 2 shifts to the execution of the program transferred to the RAM 3, and the flash memory 13 is made erasable and writable by the EPROM writer. This writer mode is suitable for storing an arbitrary user control program or the like in the user mat Mmat and the user boot mat Umat off-board (in a state where the microcomputer is not mounted on the system board).

  The boot mode is an operation mode in which all of the mats Tmat, Umat, and Mmat are erased and writing can be performed using the SCI 12. In this boot mode, the CPU 2 processes the program of the boot mat Tmat and makes the boot mat Tmat unerasable and writable. Specifically, when the boot mode is designated, after the reset process, the CPU 2 performs vector fetch from the head address of the boot mat Tmat and starts executing the program. Then, as processing necessary for the boot mode, an erase and write related program and a command determination program in the boot mat Tmat are transferred to the RAM 3. After completion of the transfer and other processing, the CPU 2 proceeds to execute the program on the RAM 3. After erasing all of the mats Umat and Mmat by executing the program on the RAM 3, the command determination program is started and writing can be performed using the SCI 12. This boot mode is an on-board equipped with a serial communication interface, and is suitable for storing an arbitrary user control program or the like in the user mat Mmat and the user boot mat Umat.

  The user boot mode allows the CPU 2 to process the program of the user boot mat Umat so that erasure and writing can be performed using any user interface, and the boot mat Tmat and the user boot mat Umat can be erased and written. This is the operation mode to be disabled. Specifically, the user boot mode is started from the boot mat Tmat, and the CPU 2 executes the program in the boot mat Tmat and transfers the user boot mat switching program to the RAM 3. Thereafter, the CPU 2 proceeds to execute a program on the RAM 3. By executing a program on the RAM 3 by the CPU 2, the mat on the flash memory 13 visible in the address space of the CPU 2 is switched from the default user mat Mmat to the user boot mat Umat, and after jumping to the area after reading the vector address of the user boot mat Umat To do. When security is applied, the jump is executed after the user mat Mmat is erased. When writing is performed, a necessary erase and write program is downloaded from the boot mat Tmat to the RAM 3 using the SCO mode described later, and then the user mat Mmat is written using the erase and write control program. . In short, a user-specific interface program is prepared in the user boot mat Umat, and write data transfer suitable for the user's mounting board can be realized. This user boot mode is suitable for writing a user control program or the like to the user mat Mmat using an on-board interface provided on the user system board. In this operation, erasure of the user boot mat Umat is prevented. Therefore, even if the user's system board does not have a serial interface and the boot mode cannot be used on-board, instead, writing via the on-board interface provided by the user's system board is guaranteed. it can.

  The user mode is an operation mode in which erasing and writing can be performed using a program held by the user mat Mmat, and erasing and writing of the boot mat Tmat and the user boot mat Umat are disabled. Specifically, the CPU 2 is activated from the user mat Mmat, and the program on the user mat Mmat is executed. In particular, when the user needs to enable the SCO bit, which will be described later, the boot mat Tmat and the user mat Mmat are automatically switched, and the program starts from the address where the boot mat Tmat is located, and erase and write control on the boot mat Tmat is performed. When the program is transferred to the RAM 3 and the transfer of the program is completed, the user mat Mmat and the boot mat Tmat are automatically switched to return to the user process, and the user program uses the erase and write control program, Erasing and writing can be performed on the user mat Mmat. In short, in the user program mode, the erase and write control program on the boot mat Tmat is transferred to the RAM 3 using the SCO mode described later, and the program is made available. This user mode is suitable for rewriting parameters on the user mat Mmat during execution of the user control program on board.

  4A and 4B show an access mode according to each operation mode of each mat. The access mode shown in the figure is an arrangement of the access modes described in the operation mode. As can be seen from the figure, the repair and trimming mat Rmat and the boot mat Tmat cannot be erased or written in any operation mode, and the user boot mat Umat is a user boot mode in which a user control program can be executed. In the user mode (user program mode), erasure and writing are disabled. This user boot mode is suitable for writing a user control program or the like to the user mat Mmat using an on-board interface provided on the user system board. In this operation, erasure of the user boot mat Umat is prevented. Therefore, even if the user's system board does not have a serial interface and the boot mode cannot be used on-board, the writing via the on-board interface provided on the user's system board can be guaranteed instead. . In FIG. 4, “access” means read access, and the symbol Δ means that read access is possible according to the program stored in the boot mat, and it does not mean that arbitrary read access is possible according to the user control program.

  FIG. 5 schematically shows the location and execution of the program executed by the CPU. In FIG. 5, the CPU 2 is not shown, and CN 1 virtually shows a control signal group obtained as a result of the CPU 2 decoding the erase and write control program transferred from the boot mat Tmat to the RAM 3. CN2 virtually represents a control signal group as a result of the CPU 2 decoding the serial interface control program transferred from the boot mat Tmat to the RAM 3. CN3 virtually represents a control signal group obtained as a result of the CPU 2 decoding the user interface control program of the user boot mat Umat. CN4 virtually indicates a control signal group obtained as a result of the CPU 2 decoding the user interface control program of the user mat Mmat. Although the control signals CN3 and CN4 are illustrated as the decoding results of the program fetched directly from the user boot mat Umat and the user mat Mmat, they may be the decoding results of the program once transferred to the RAM 3 and fetched from the RAM 3. . Sig1 to Sig4 mean the decoding result of the mode signal 14 after the reset release by the system controller 15, Sig1 means the boot mode, Sig2 means the user boot mode, Sig3 means the user mode, and Sig4 means the write mode. The signals Sig1 to Sig4 are actually supplied to the CPU 2, but the state thereof is omitted here.

  When the boot mode is instructed by the mode signal 14, in response to the signal Sig1, the flash control module 6 transfers the boot mat Tmat erase / write control program, serial communication control program, and the like to the RAM 3 (path P1). In accordance with the decoding result (CN2) of the serial communication control program by the CPU 2, write data is taken into the RAM 3 (path P2) from the on-board serial interface to the host device HST1, and the decoding result of the erase and write control program by the CPU 2 ( The flash memory 13 is erased according to CN1), and the user control program is written to the user boot mat Umat and the user mat Mmat using the write data on the RAM 3 (paths P3 and P4).

  When the user boot mode is instructed by the mode signal 14, the mat control control program or the like is transferred from the boot mat Tmat to the RAM 3 by the flash control module 6 in response to the signal Sig2 (path P1) and switched to the user boot mat Umat. The first vector of the user boot mat Umat is fetched and executed. When writing is performed, an erase and write program is downloaded from the boot mat Tmat to the RAM 3. In accordance with the decoding result (CN3) of the user interface control program held by the user boot mat Umat, the write data is taken into the RAM 3 from the on-board user interface to the host device HST2 (path P5), and the erase and write control program by the CPU 2 is decoded. The flash memory 13 is erased according to the result (CN1), and the user control program and user data are written to the user mat Mmat using the write data on the RAM 3 (paths P3 and P4). The user interface is, for example, an ATAPI interface realized by the interface controller 16. Note that the user interface control program stored in the user boot mat Umat may be a serial interface control program similar to or different from that stored in the boot mat Tmat.

  When the user mode is instructed by the mode signal 14, it is transmitted to the flash control module 6 by the signal Sig 3, and when performing writing, an erasing and writing program is downloaded from the boot mat Tmat to the RAM 3. In accordance with the decoding result (CN4) of the user interface control program held by the user mat Mmat, the write data is taken into the RAM 3 (path P5) from the on-board user interface to the host device HST2, and the decoding result of the erase and write control program by the CPU 2 The flash memory 13 is erased in accordance with (CN1), and the user control program and user data are written to the user mat Mmat using the write data on the RAM 3 (paths P3 and P4). The user interface control program stored in the user mat Mmat may be a serial interface control program similar to or different from that stored in the boot mat Tmat.

  Although not particularly illustrated, a microcomputer that does not include the user boot mat Umat and the user boot mode is assumed as a comparative example of the microcomputer 1. In this case, if the user interface program stored in the user boot mat Umat is stored in the user mat Mmat, the program and data can be transmitted to the user via the on-board user interface of the host device HST2 as in the microcomputer 1. The mat Mmat can be written or rewritten. However, as is the case with the macro computer 1, the user interface program stored in the user mat Mmat may be erased because the user mat Mmat can be freely rewritten. If the host device HST2 is not equipped with an on-board serial interface that can be used in the boot mode when erased, the microcomputer according to the comparative example can no longer input and output information to and from the host device HST2.

  According to the microcomputer 1 having the above operation mode, the following operational effects can be obtained. (1) Since the user boot mat Umat capable of storing a user-specific communication protocol is prepared, any interface provided in the microcomputer 1 can be used for erasing and writing of the flash memory 13. (2) Since it is possible to employ any user interface for erasing and writing the flash memory 13, it is not necessary to provide a serial interface in the host device HST2. (3) Since the user boot mat Umat and the user mat Mmat are separated, an arbitrary writing interface for erasing and writing can be realized without writing a dedicated communication protocol in the user mat Mmat. It is easy to create a control program to be stored and used. In short, it is not necessary to pay special consideration to prevention of erasure of the communication control program used in the user program mode. (4) In the user boot mode that rises from the user boot mat Umat, the user boot mat Umat cannot be erased and written by hardware, so that the stored information of the user boot mat Umat is not destroyed due to runaway or the like. Even if the CPU 2 runs out of control sometimes, the program for controlling the external interface is not destroyed, so that the user mat Mmat can be freely rewritten on-board without removing the mounted microcomputer chip.

《Erase and write protection》
FIG. 6 illustrates a logical configuration for protection against erasure and writing of the flash memory 13. The logic of the figure is positive logic, and the configuration is realized by the flash control module 6.

  Erase and write operations to the flash memory are made possible by setting control data necessary for processing with respect to the initial value of the write / erase related register group 30A. Setting of control data for the write / erase related register group 30A is enabled when the control bit SWE has a logical value "1". In short, unless the control bit SWE is set to the logical value “1”, erasing and writing of the flash memory 13 are disabled.

  The first condition for setting the control bit SWE to the logical value “1” is to set the enable bit FWE of the register FCCS to the logical value “1” by the external terminal Pfwe.

  The second condition is to obtain an operation mode selection state in which the output of the NAND gate 40 is a logical value “1” and a mat selection state of the flash memory. That is, the operation mode is a test mode (TESTTM = 1), a writer mode (WRTM = 1), or a boot mode (BOOT = 1). Alternatively, the user boot mat Umat is not selected in the user mode or the user boot mode (UMATSEL = 0). Note that the test mode is an operation mode used by the microcomputer manufacturer for the device test, and all operations are possible. However, the operation mode is not disclosed to the user, that is, cannot be set by the user. Has been paid.

  The signal UMATSEL is a determination result of the AA determination circuit 41 with respect to the register FMATS and the set value of the register FMATS. The register FMATS is used when switching between the user mat Mmat and the user boot mat Umat. By using the register FMATS, the operation of the CPU 2 can be changed from the user mat Mmat to the user boot mat Umat. However, there are restrictions on mat switching. That is, the condition for setting the user boot mat selection bit of the register FMATS is that the operation of the CPU 2 is executing the program of the RAM 3. This condition is determined by the BSC 4 detecting that the address area of the instruction fetch by the CPU 2 is the address area of the RAM 3. The initial value of the register FMATS is other than H'AA and indicates the user mat selection state. The user boot mat selection state is indicated by H'AA. FIG. 7 shows a state transition when the operation (OP) of the CPU 2 is switched between the user mat Mmat and the user boot mat Umat.

  According to the second condition, the user boot mat Umat can be accessed in any mode, but writing / erasing can be performed only in the writer mode and the boot mode (and the test mode).

  The third condition is that the register FKEY is set to an erasing and writing allowable value. The register FKEY is provided in order to prevent the program from running out of control due to a voltage drop, noise, or the like, and thereby destroying the program. The register FKEY is used in consideration of a case where the program runs away after the erase and write control program (write / erase program) is transferred. Basically, the terminal Pfwe and the control bit SWE prevent the writing / erasing even if the CPU 2 runs out of control. However, in order to further improve the reliability, the user must perform the writing / erasing. Then, a value of “5A” is set in the register FKEY. When this “5A” is not stored, the control bit SWE cannot be set even if the FWE is enabled (“1”). The state in which “5A” is stored in the register FKEY is detected by the A5, 5A determination circuit 42, and the signal fwemkp = 1 is set, so that the SWE can be set to the logical value “1”.

  The register FKEY functions as a program transfer relationship in addition to functioning as the above-described write / erase program relationship. In other words, the flash memory erase and write control program is stored in the boot mat Tmat, and the boot mat Tmat can be used in the user boot mode and the user mode in addition to the boot mode. When the control bit SCO is enabled in the register FCCS for transfer to the RAM 3, and the control bit SCO is enabled, the user mat Mmat and the boot mat Tmat are automatically switched, and the erase and write control program is transferred from the boot mat Tmat to the RAM 3. A return instruction is executed after the process is completed, and the process returns to the user process. At this time, if the program runs away in a place where the user does not want to perform writing / erasing and the writing / erasing program is transferred, there is a high possibility that the user program is destroyed. To avoid this, the register FKEY is used. The user stores “A5” in this register FKEY before setting the control bit SCO. When this “A5” is not stored, the control bit SCO cannot be set. The CPU 2 is also required to operate a program on the RAM 3. When “A5” is stored and the CPU 2 is operating on the RAM 3, the SCO bit can be set, and the erase and write control program is allowed to be transferred from the boot mat Tmat to the RAM 3.

  As described above, with regard to erasing and writing with respect to the flash memory 13, since the program transfer and erasure writing are exclusively controlled by the register FKEY, it is difficult to execute writing / erasing if the program runs away without being transferred. .

<Program mode judgment processing>
Here, details of the processing in each of the operation modes will be described. FIG. 8 illustrates a flowchart 13 of the program mode determination process. The SCO mode means an operation mode when the flash memory is erased and written in the user mode. The boot mode, writer mode, user boot mode, and user mode may be canceled by setting the corresponding mode terminal. The SCO mode is set by setting the logical value “1” to the control bit SCO during the user mode. Mode information is set in the mode determination register according to the set operation mode.

  When the operation mode is set, the CPU 2 executes a program in the boot mat (OP in the boot mat). In boot mode, writer mode, and user boot mode, a vector is fetched from the top address in the boot mat and program execution is started (S1). In the SCO mode, a predetermined address other than the top in the boot mat, for example, priority is given. The processing is started from the user break address which is the exception processing with the highest frequency.

  When the processing starts, the mode determination register is read (S2), the contents thereof are determined, and necessary preprocessing such as erasure and transfer of the write control program is performed (S2 to S5), and the process proceeds to the corresponding processing (S6). To S9). Note that “user” shown in each processing column of the flowchart means that the processing is performed based on a program defined by the user, and “boot” shown in the processing column indicates that the processing is a boot mat. This means that the process is performed based on the Tmat program.

<Writer mode processing>
FIG. 9 illustrates a flowchart of the writer mode process. When the writer mode is set, the writer mode control program is transferred to the RAM 3 as shown in FIG. First, the command / data register (CDL) and flag register (FLG) used for erasing and writing in the writer mode are cleared, the command flag (CDF) is set to “1” (S11), and the power is turned off. While referring to the states of the flag register (FLG) and the command flag (CDF), the user mat Mmat and the user boot mat Umat are erased according to the command and write data set from the EPROM writer to the command data register (CDL) ( S14, S15) and writing (S12, S13) are performed. The write mode process is an operation in the RAM 3.

《Boot mode processing》
FIG. 10 illustrates a flowchart of boot mode processing. First, transmission / reception between the on-board serial interface and the SCI 12 is established (S20), and necessary parameters such as the oscillation frequency of the microcomputer 1 are downloaded and set (S21). Next, a command from the host device is determined, a status such as a microcomputer product name and the number of erase blocks is returned to the host device (S22), and a command determination program and an erase program are transferred to the RAM 3 (using the SCO mode). It is also possible to make a transition to the operation on the RAM 3 (S23). Then, after the user mat Mmat and the user boot mat Umat are completely erased (S24), the user mat write process (S25), the user boot mat write process (S26), and the write verify process (S27, S28) while responding to the command. Etc.

<< User boot mode processing >>
FIG. 11 illustrates a flowchart of user boot mode processing. In the user boot mode, although not particularly limited, the operation is started from the top vector of the boot mat Tmat, the program for switching to the user boot mat Umat is transferred from the boot mat Tmat to the RAM 3 (S30), and the operation shifts to the operation on the RAM 3. Then, H'AA is set in the register FMATS, and the user mat instruction state (initial value) by the register FMATS is switched to the user boot mat (S32). Here, it is determined whether there is an error in the area setting of the user boot mat Umat (S33, S34). If there is no error, the head vector address of the user boot mat Umat is read (S35), and a subroutine jump is made to the read vector address. (S36). The CPU 2 executes a program on the user boot mat Umat, first establishes user-defined communication, and transfers a user program necessary for writing to the RAM 3 (S37). The CPU 2 transitions to program execution on the RAM 3 (S38), operates the register FMATS again, and switches the processing target mat from the user boot mat Umat to the user mat Mmat (S39). Then, the user program on the RAM 3 is executed and the control bit SCO is set to “1” (S40), and the process shifts to the SCO mode process to transfer the erase and write control program in the boot mat Tmat to the RAM 3 (S41). ), A write / erase process using the transferred erase and write control program is performed (S42).

《User mode processing》
FIG. 12 illustrates a flowchart of user mode processing. When the user mode is designated, vector fetch is performed from the top of the user mat Mmat (S50), and the user control program is executed (S51). If writing to the user mat Mmat becomes necessary during the execution of the user program, an operation is performed on the RAM 3 to set the SCO bit to “1” (S52), transition to the SCO mode processing, and deletion in the boot mat. Then, the write control program is transferred to the RAM 3 (S53), and write / erase processing using the transferred erase and write control program is performed (S54).

<Write / Erase Processing>
FIG. 13 illustrates a flowchart of the write / erase process in steps S42 and S54. Steps S60 to S63 are write / erase initialization processes. Here, the erase and write control program is held in the boot mat Tmat in advance by the manufacturer of the microcomputer 1. In short, the program does not specify user-specific conditions. For example, the application time of the erase voltage pulse and the write voltage pulse is determined according to the characteristics of the flash memory cell, and the pulse application time must be controlled by the operation clock signal of the microcomputer 1, and the operation necessary for that. The frequency data is set in the control register FPEFEQ (S60). The control register FPEFEQ is not particularly limited, but the general-purpose register R4 of the CPU 2 is assigned.

  The address of the branch destination process for the user branch process (details will be described later) is set in the register FUBRA in order to eliminate the inconvenience that the user process is completely interrupted during the erase voltage pulse, the write voltage pulse, and the verify operation cycle. (S61).

  Thereafter, the subroutine jumps to the initialization program area (S62), the initialization program is executed (S64), and the parameters for erasing and writing are erased and written according to the initial setting contents such as the frequency and the user branch address. It is automatically set on the control program.

  Next, in order to cancel the hard protection of erasure and writing, the control bit FWE is set to the logical value “1” via the terminal Pfwe to cancel the hard protection, and the process proceeds to the execution of the user program (S64). In this operation state, write data is prepared (S65), and write / erase to be performed by the user is executed (S66). The processes in steps S65 and S66 are repeated until the process intended by the user is completed.

<< User branch >>
The user branch process will be described with further details of the write / erase process of FIG.

  FIG. 14 is a schematic flowchart focusing on the writing process of FIG. The write process is roughly divided into a process (T1) for transferring a source code (such as an erase and write control program) from the boot mat Tmat to the RAM 3, a write initialization execution (T2), and a write execution (T3).

  In the transfer process (T1), a program to be transferred is selected, the register FKEY is set, and the control bit SCO is enabled. By executing this, the transfer program starts automatically from the boot mat. The program is transferred from the start address of the RAM 3 only in a necessary area. At this time, the initialization program is also transferred.

  In the initialization execution (T2), the initialization program is executed, and the setting of the number of wait time loops depending on the operating frequency and the user branch address are set for the transferred program.

  In the write execution (T3), any method may be used before writing, but write data is transferred onto the RAM 3. At this time, it is necessary to arrange the data in a certain order. The transfer area can be arbitrarily set by the user, and after executing necessary procedures and executing the transfer, a subroutine jump is executed at a predetermined address in the program. Writing is executed by executing this subroutine jump.

  FIG. 15 illustrates details of the transfer process (T1) to the RAM 3. First, the register FKEY is set to “A5” (T10), and the source code to be transferred is selected (T11). The source code is selected for the write / erase related register 30A. The selectable source code is not particularly limited, but includes a write and write verify program, an erase and erase verify program, and the like. Then, the control bit SCO is set to “1”, and the selected source code is transferred to a predetermined area of the RAM 3 (T12). When the control bit SCO is enabled, the CPU 2 needs to perform an operation outside the flash memory 13. This is because the program runs out of control because the operable mat changes from the user mat Mmat to the boot mat Tmat. When the control bit SCO is enabled, the program automatically starts from the boot mat Tmat. This boot program saves the value of the general-purpose register to the stack by software processing. When returning to the user process, the process returns to the user process by a return instruction. Before carrying out this restoration, the transfer program in the boot mat Tmat restores the value of the general-purpose register that has been saved. Finally, it is determined whether the transfer has been completed normally (T13).

  FIG. 16 illustrates details of the write initialization process (T2). First, the operating frequency of the microcomputer 1 is set in the register FPEFEQ (R4) (T20), and the user branch address is set in the register FUBRA. A general-purpose register R5 of the CPU 2 is assigned to the register FUBRA. Thereafter, the write initialization program is executed (T22). For example, the write-related initialization program determines the number of wait time loops with reference to the set chip operating frequency value. Processing for embedding the determined wait time in the write control program transferred to the RAM 3 is performed. Further, the write initialization program refers to the value of the register FUBRA (R5), and executes the user branch or changes the write program to which address to jump to when executed. In short, the value of the register FUBRA (R5) is embedded as a branch destination address in a subroutine jump instruction for executing a user branch. Finally, it is determined that the initialization process has ended normally (T23), and the process ends.

  Here, the register FUBRA is a register for designating a user branch address during writing / erasing, and this area exists in the general-purpose register R5. When it is not desired to execute the user branch, H'00000000 is set in this register. In order not to cause a malfunction due to the user branch, the user branch is prohibited for the area in the flash memory area that is in the middle of writing / erasing, and the user branch to the area of the built-in RAM to which the writing / erasing program is transferred. It is desirable to prohibit the program data from being rewritten and to prohibit the execution of the SCO mode, the write / erase routine, and the write / erase initialization routine after the user branch is executed.

  FIG. 18 shows the data connection relationship between the built-in RAM 3, the write program, the initialization process, and the registers R4 and R5 at the time of write initialization in FIG. From the figure, it is clear that the initialization program refers to the registers R4 and R5, reflects the reference result in the user branch processing of the writing program, and reflects it in the weight related parameters.

  FIG. 17 illustrates details of the write execution (T3). First, the branch destination when an unmaskable interrupt (NMI) is received is changed to the RAM3 address area (T30). For example, the vector base register may be changed to the address area of the RAM 3. This is because it is preferable from the viewpoint of preventing malfunction to avoid the flash memory area in the middle of writing. Such an NMI may be used to call a user-defined error handling routine. Then, an interrupt having an interrupt priority level lower than that of NMI is masked (T31). For example, the next lowest interrupt priority level after the NMI of the interrupt mask data IMSK may be set in the status register SR. This is because a high voltage is applied to the flash memory depending on the state during writing / erasing. Even if an interrupt such as IRQ enters in this state, it cannot be guaranteed that the vector of the flash memory can be read. Therefore, interrupts other than NMI are prohibited during writing / erasing.

  Then, the setting area for the write address is set in the general-purpose register R5 (T32). That is, the head address of the write address area written in the built-in RAM 3 is set in the general-purpose register R5. Then, the setting area for the write data address is set in the general-purpose register R4 (T33). That is, the head address of the write data address area written in the built-in RAM 3 is set in the general-purpose register R4. Thereafter, the write / erase code “5A” is set in the register FKEY (T34), and the program jumps to the write program and executed (T35). Finally, it is determined whether the writing has been normally completed (T36).

  FIG. 19 illustrates a data connection relationship between the RAM 3, the general-purpose registers R4 and R5, and the writing program at the time of writing. Here, since dual bank writing is assumed, it is necessary to be able to refer to the start address of the write address area and the start address of the write data address area for each bank. Therefore, the RAM areas FMPDR0 and FMPDR1 are registered in the register R4. The RAM areas FMPAR0 and FMPAR1 can be referred to by the register R5.

  FIG. 20 illustrates a processing flow of the writing program corresponding to step T35 of FIG. This processing flow includes a step (T43) of determining whether to jump to a user branch address during a processing cycle of a write data latch (T40), a write pulse application (T41), and a write verify (T42). If a subroutine jump instruction is given according to the set value by the initialization process (when the user branch address is other than H'00000000), the process branches to the user branch address and executes the subroutine (T44). After execution, the program returns to the write operation routine. If the predetermined threshold state cannot be obtained by the write verify, the pulse application count N is incremented and the same loop is repeated again (T45), and the normal write state can be obtained before the repeat count reaches the maximum number (WMAX). At that time, the flow returns to the flow of FIG. 17 (T46). If the normal end cannot be completed even when the maximum number of times is reached, a write error process is performed (T47), and the flow returns to the flow of FIG.

  In this way, if it is possible to branch to the subroutine processing indicated by the user branch address during the write pulse application and write verify cycles, the user control program is controlled at a certain interval even during writing. Can be returned. In addition, since it is implemented by software, it is also possible to change the interval for returning to the user's control by software. Even during writing, by returning to the user control program at regular intervals, erasing and writing can be performed without stopping the system using the macro computer 1 for a long time. Therefore, it is possible to execute erasure and writing during the execution of the user's program for a system that needs to confirm internal and external events at regular intervals, or a system with a learning function.

  FIG. 21 is a schematic flowchart focusing on the erasing process of FIG. The erasure process is roughly divided into a process (T5) for transferring a source code (such as an erasure and write control program) from the boot mat to the RAM 3, an erasure initialization execution (T6), and an erasure execution (T7).

  The transfer process (T5) is the same as the transfer process (T1). In the initialization execution (T6), the initialization program is executed for setting the number of wait time loops depending on the operating frequency and setting the user branch for the transferred program.

  In the erasure execution (T7), erasure is executed by executing a jump subroutine at a predetermined address of the erasure program transferred to the RAM 3.

  FIG. 22 illustrates details of the erase initialization process (T6). First, the operating frequency of the microcomputer 1 is set in the register FPEFEQ (R4) (T60), and the user branch address is set in the register FUBRA (T61). A general-purpose register R5 of the CPU 2 is assigned to the register FUBRA. Thereafter, an erase initialization program is executed (T62). In the erase program when transferred, the number of wait loops is in an initial setting state. For this reason, all the wait loop times of the erase program are changed by using this initialization program. To perform this calculation, the user sets register FPEFEQ (R4). In setting the register FUBRA (R5), the user branch of the erase program is set. The erase initialization program refers to the set value of the register FUBRA and changes the erase program regarding whether to execute the user branch or to which address to jump to when executed. To implement this change, the user sets a value in register FUBRA. Finally, it is determined that the initialization process has been completed normally (T63), and the process ends.

  Here, the significance of the register FUBRA is the same as that in the case of writing, and H'00000000 is set in this register when the user branch is not desired to be executed.

  FIG. 24 shows the data connection relationship between the built-in RAM 3, the erase program, the initialization process, and the registers R4 and R5 at the time of the erase initialization shown in FIG. From the figure, it is clear that the initialization program refers to the registers R4 and R5, reflects the reference result in the user branch processing of the writing program, and reflects it in the weight related parameters.

  FIG. 23 illustrates details of the execution of erasure (T7). First, the branch destination when an unmaskable interrupt (NMI) is received is changed to the RAM3 address area (T70). For example, the vector base register may be changed to the address area of the RAM 3. This is because it is preferable from the viewpoint of preventing malfunction to avoid the flash memory area in the process of erasing. Such an NMI may be used to call a user-defined error handling routine. Then, an interrupt having an interrupt priority level lower than that of NMI is masked (T71). For example, the next lowest interrupt priority level after the NMI of the interrupt mask data IMSK may be set in the status register SR. This is because a high voltage is applied to the flash memory depending on the state during erasing. Even if an interrupt such as IRQ enters in this state, it cannot be guaranteed that the vector of the flash memory can be read. Therefore, interrupts other than NMI are prohibited during erasure.

  Then, the erase block number is set in the general-purpose register R4 (T72). Thereafter, the write / erase code “5A” is set in the register FKEY (T73), and the program jumps to the erase program and executes (T74). Finally, the normal end of erasure is determined (T75).

  FIG. 25 illustrates a data connection relationship between the RAM 3, the general-purpose registers R4 and R5, and the erase program at the time of erasure. Since the user does not create an erase program, this connection relationship is implemented by passing an erase block number via the register FEBS (R4) as an erase mat selection interface method.

  FIG. 26 illustrates a processing flow of the erase program corresponding to step T74 of FIG. This processing flow includes a step (T83) of determining whether to make a subroutine jump to the user branch address during the processing cycle of the erase data latch (T80), erase pulse application (T81), and erase verify (T82). If a subroutine jump instruction is given according to the set value by the initialization process (when the user branch address is other than H'00000000), the process branches to the user branch address and executes the subroutine (T84). After execution, the process returns to the erase operation routine. If the predetermined threshold state cannot be obtained by the erase verify, the pulse application count N is incremented and the same loop is repeated again (T85), and the normal erase state can be obtained before the repeat count reaches the maximum number (EMAX). At that time, the flow returns to the flow of FIG. 23 (T86). If the normal end cannot be completed even if the maximum number of times is reached, an erasure error process is performed (T87), and the flow returns to the flow of FIG.

  In this way, if it is possible to branch to the subroutine processing indicated by the user branch address during the erase pulse application and erase verify cycle, the control program of the user is controlled at a certain interval even during the erase. Can be returned. Even during erasure, by returning to the user control program at regular intervals, erasure can be performed without stopping the system using the macro computer 1 for a long time. Therefore, it is possible to execute erasure and writing during the execution of the user's program for a system that needs to confirm internal and external events at regular intervals, or a system with a learning function.

<< Program runaway at user branch destination >>
When the program / erase program is transferred and the terminal Pfwe is enabled (“1”), it is completely guaranteed that the storage information held in the flash memory 13 is normally held in any case. It is difficult. FIG. 27 exemplifies a write / erase processing technique that can prevent the CPU 2 from running away at the user branch destination and destroying the information stored in the flash memory 13. That is, in the user branch processing in steps T44 and T84 executed at the end of each process in the write / erase flow, the write / erase operation power supply is initialized and transitioned to the read operation power supply (T90), and then the register The value of FKEY is changed to any value other than the writable / erasable value “5A” (T91). For example, 7X (X = 0 to F) is set. By implementing this, the control bit SWE cannot be set, so that even if the CPU runs away at the user branch destination, writing / erasing cannot be performed easily.

  In the process of step T91, if the code set in the register FKEY is a code meaningful to the process, for example, a code indicating the progress of the erase / write, the program is written in an unfinished state due to runaway When the process returns from the / erase processing routine or when the value of the register FKEY has changed to a value other than the expected value, an abnormality can be detected by referring to the value of the register FKEY. In the example of FIG. 27, “71” is set between pulse application and verify, “72” is set between verify and write data recalculation, and “73” is set between rewrite and dummy write before write pulse is applied. When exiting from the processing, it is determined whether the value of the register FKEY is “7X (X = 1 to F)” (T92). Otherwise, it is considered that there is some abnormality, and writing / erasing is failed. Processing is performed (T93). If FKEY is “7X”, it is considered that processing is normally completed, and FKEY is returned to “5A” (T93).

  Note that the register that holds the progress status does not have to be FKEY. However, in consideration of the fact that it is a good idea to rewrite to a value other than “5A” in the case of the user branch, it is possible to use the register FKEY. Economical in terms of both hardware resources and processing burden.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the erasable and writable nonvolatile memory is not limited to a binary flash memory. It may be a multi-level flash memory, for example, a multi-level flash memory capable of holding stored information of 2 bits or more in one flash memory cell. That is, one flash memory cell is set to one threshold voltage among four or more types of threshold voltages specified by a plurality of bits of write data at the time of information storage, and a plurality of threshold voltages corresponding to the state of the threshold voltage at the time of information reading. This is a memory in which the storage information of one flash memory cell, which is output as bit storage information, is converted into a plurality of bits. Here, an example is a flash memory in which 2-bit information can be written into one flash memory cell and the information can be read out. In the multi-value information storage technology to be realized by such a flash memory, the information storage state of one memory cell is, for example, an erase state (“11”), a first write state (“10”), a second One state selected from the write state (“00”) and the third write state (“01”). A total of four information storage states are determined by 2-bit data. That is, 2-bit data is stored in one memory cell.

  In addition, the flash memory cell is not limited to a vertically stacked structure of floating gates and control gates, and the channel region is controlled through a MOS gate capacitor formed by extending the gate electrode using the gate electrode of the MOS transistor as a floating gate electrode. A device structure used for a gate may be adopted. The nonvolatile memory element is not limited to a flash memory, but is an EEPROM (Electrically Erasable and Programmable Read Only Memory) using a MNOS (Metal Nitride Oxide Semiconductor) transistor as a memory element. A non-volatile memory or a ferroelectric memory may be used.

  The circuit module provided on-chip by the microcomputer is not limited to the above example, and can be changed as appropriate.

  The present invention is not limited to a configuration in which the erase and write control programs are initially held in the boot mat. A configuration downloaded from the system board may be adopted. The various register means may be a peripheral register with a built-in flash memory, a general-purpose register with a built-in CPU, or a memory mapped I / O register composed of a memory such as SRAM. .

  It has been described that the user branch executes the program after performing the initialization process for rewriting the jump destination code of the jump subroutine instruction in advance based on the set value of the register FUBRA (R5). Alternatively, a branch may be made by directly referring to the register FUBRA (R5) with a jump subroutine instruction. In this case, the compiler for the erase and write control program must be able to refer to the general-purpose register R5 within the limit of the number of general-purpose registers that can be used as an argument in one function.

It is a block diagram of a microcomputer according to an example of the present invention. It is a block diagram which shows the specific example of CPU2. It is explanatory drawing which illustrates the memory mat of flash memory. It is explanatory drawing which illustrates the access mode by each operation mode for every memory mat of flash memory. It is explanatory drawing which shows typically the effect | action by the location and execution of the program which CPU runs. 3 is a logic circuit diagram illustrating a logic configuration for erasing and writing protection of a flash memory. FIG. It is a state transition diagram when operation of CPU is switched between a user mat and a user boot mat. It is a flowchart of a program mode determination process. It is a flowchart of a writer mode process. It is a flowchart of a boot mode process. It is a flowchart of a user boot mode process. It is a flowchart of a user mode process. 13 is a flowchart of write / erase processing in step S42 in FIG. 11 and step S54 in FIG. 14 is a schematic flowchart focusing on the writing process of FIG. 13. It is a flowchart which illustrates the detail of the transfer process (T1) to RAM. It is a flowchart which illustrates the detail of a write initialization process (T2). It is a flowchart which illustrates the detail of write execution (T3). FIG. 17 is an explanatory diagram exemplifying a data connection relationship between a built-in RAM, a writing program, initialization processing, and registers (R4, R5) at the time of writing initialization in FIG. 16; It is explanatory drawing which illustrates the data connection relationship between RAM at the time of writing, general purpose registers (R4, R5), and a writing program. It is a processing flow of the writing program corresponding to step T35 of FIG. 14 is a schematic flowchart focusing on the erasing process of FIG. 13. It is a flowchart which illustrates the detail of an erasure | elimination initialization process (T6). It is a flowchart which illustrates the detail of deletion execution (T7). FIG. 23 is an explanatory view exemplifying a data connection relationship between a built-in RAM, an erase program, an initialization process, and registers (R4, R5) at the time of erase initialization in FIG. 22; It is explanatory drawing which illustrates the data connection relationship between RAM at the time of erasing, general purpose registers (R4, R5), and an erasing program. FIG. 24 is a processing flow of an erasing program corresponding to step T74 in FIG. It is a flowchart of the user branch process which can suppress the situation where CPU runs away in a user branch destination and the memory information of flash memory is destroyed.

Explanation of symbols

1 Microcomputer 2 CPU
3 RAM
4 bus state controller 5 flash memory module 6 flash control logic 9 interrupt controller RES reset signal 13 flash memory 14 mode signal 15 system controller 20 memory cell array FMATS control register FKEY control register FCCS control register SCO control bit Rmat repair and trim mat Tmat Bootmat Umat User bootmat Mmat Usermat Pfwe External terminal

Claims (21)

A microcomputer having a CPU, an erasable and writable nonvolatile memory, and a RAM arranged in the address space of the CPU,
The non-volatile memory has a first area that holds a communication control program processed by the CPU to establish an interface with the outside;
A second area in which an interface with the outside is established by the processing of the communication control program by the CPU and can be erased and written;
An interface with the outside is established by the processing of the communication control program by the CPU and can be erased and written, and the third area can be erased and written by the program of the second area by the CPU; ,
A microcomputer having a configuration in which the second area and the third area of the nonvolatile memory can be exclusively selected by a register. A microcomputer to be mounted on a mounting board having a first interface,
A central processing unit;
A first storage area for storing a first communication processing program for establishing a communication protocol using a second interface different from the first interface, and a second for establishing a communication protocol using the first interface A non-volatile memory having a second storage area for storing a communication processing program, and a third storage area for storing a control program executed by the central processing unit in a predetermined first operation mode;
A microcomputer comprising: a register for exclusively selecting the second storage area and the third storage area. The first storage area further stores a write control program,
The second communication processing program stored in the second storage area is written to the second storage area in a first write mode in which the write control program and the first communication processing program are executed by the central processing unit. The microcomputer according to claim 2.   The control program stored in the third storage area is a program that causes the central processing unit to execute the first write mode or the write control program and the second communication processing program stored in the first storage area. 4. The microcomputer according to claim 3, wherein writing to the third storage area is performed in any one of two writing modes.   3. The microcomputer according to claim 2, wherein the first interface is an ATAPI interface, a SCSI interface, or an HCAN interface.   3. The microcomputer according to claim 2, wherein the second interface is a serial interface using start-stop synchronization.   3. The microcomputer according to claim 2, wherein the nonvolatile memory has a plurality of nonvolatile memory cells each having a floating gate.   8. The microcomputer according to claim 7, wherein the nonvolatile memory is a flash memory. The first storage area further stores an erase control program,
The second communication processing program stored in the second storage area can be erased from the second storage area in a first erasure mode in which the central processing unit executes the erasure control program and the first communication processing program. The microcomputer according to claim 2, wherein:   The control program stored in the third storage area is the first erasing mode or the erasing control program and the second communication processing program stored in the first storage area are executed by the central processing unit. 10. The microcomputer according to claim 9, wherein the microcomputer can be erased from the third storage area by any one of the two erase modes. The first storage area further stores a write control program,
The second communication processing program stored in the second storage area is written to the second storage area in a first write mode in which the write control program and the first communication processing program are executed by the central processing unit. The microcomputer according to claim 10.   The control program stored in the third storage area is a program that causes the central processing unit to execute the first write mode or the write control program and the second communication processing program stored in the first storage area. 12. The microcomputer according to claim 11, wherein writing to the third storage area is performed in any one of two writing modes. A central processing unit;
A first storage area for storing a first communication processing program and a write control program for establishing a communication protocol using the first interface, and a communication protocol using the second interface different from the first interface are established. A non-volatile memory having a second storage area for storing a second communication processing program for storing, and a third storage area for storing a control program executed by the central processing unit in a predetermined first operation mode; Have
The microcomputer, wherein the second storage area and the third storage area can be selected exclusively.   The second communication processing program stored in the second storage area is written to the second storage area in a first write mode in which the write control program and the first communication processing program are executed by the central processing unit. The microcomputer according to claim 13.   The control program stored in the third storage area is a program that causes the central processing unit to execute the first write mode or the write control program and the second communication processing program stored in the first storage area. 15. The microcomputer according to claim 14, wherein writing to the third storage area is performed in any one of two writing modes. The first storage area further stores an erase control program,
The second communication processing program stored in the second storage area is erased from the second storage area in a first erasure mode in which the central processing unit executes the erasure control program and the first communication processing program. 14. The microcomputer according to claim 13, wherein:   The control program stored in the third storage area is the first erasing mode or the erasing control program and the second communication processing program stored in the first storage area are executed by the central processing unit. 17. The microcomputer according to claim 16, wherein the microcomputer is erased from the third storage area by any one of the two erase modes.   14. The microcomputer according to claim 13, wherein the first interface is at least one interface selected from an ATAPI interface, a SCSI interface, and an HCAN interface.   14. The microcomputer according to claim 13, wherein the second interface is a serial interface using start-stop synchronization.   14. The microcomputer according to claim 13, wherein the nonvolatile memory has a plurality of nonvolatile memory cells each having a floating gate.   21. The microcomputer according to claim 20, wherein the nonvolatile memory is a flash memory.

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