JP2008186081A - Device for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit designing device capable of arranging cells on the shared clock route of a plurality of clock signals at positions by which a clock propagation delay time is made to be shortest. <P>SOLUTION: The multiple clock input cell extracting part 11 of the semiconductor integrated circuit designing device 1 extracts the cell where the plurality of clock signals are inputted. A shared clock route cell extracting part 12 extracts the cells existing in the multiple clock shared clock route for transmitting the output of the multiple clock input cell. A cell destination position calculating part 13 calculates the destination positions of the multiple clock input cell and the shared clock route cells, capable of shortening the propagation delay time of the shared clock route, based on the cell arrangement position information of the shared clock route cells. A cell arrangement position change part 14 changes the arrangement positions of the multiple clock input cell and the shared clock route cells into the calculated movement destination positions. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design apparatus.

  In recent large-scale and high-speed semiconductor integrated circuits, it is important to reduce the skew due to the wiring resistance of the clock signal when distributing the clock signal into the chip. Therefore, conventionally, a semiconductor integrated circuit design apparatus for designing a layout of a semiconductor integrated circuit automatically generates a clock tree for clock distribution to reduce clock skew.

  The clock tree is generated by arranging the cells such as logic circuits constituting the semiconductor integrated circuit, and then transmitting the clock signal to the clock signal distribution destination cells with an equal delay time according to the arrangement position. This is done by arranging buffers in a shape.

  By the way, in a semiconductor integrated circuit in which such a clock tree is generated, a test circuit such as a scan test circuit may be inserted for ease of testing. In this case, two system clocks, that is, a system operation clock and a test clock, are switched by an operation mode switching selector, and the output of the selector is distributed as a clock signal. In this case, the clock signal path from the output of the selector to the logic cell at the clock signal distribution destination terminal is a shared clock path of two clocks.

  When a clock tree is generated for a semiconductor integrated circuit having two clocks having such a shared clock path, the propagation delay time is adjusted so that no clock skew occurs for either clock. There is a need.

  For example, if there is a large difference in the wiring length of the two clocks up to the selector cell depending on the position of the selector cell to which the two clocks are input, the clock is adjusted to the clock with the longer wiring length. It is necessary to adjust the delay time.

  As one method of adjusting the delay time, a delay adjustment circuit is inserted in the generation of the clock tree (see, for example, Patent Document 1).

  However, when such a delay adjustment circuit is inserted and the delay time is adjusted in accordance with the clock having the longer wiring length, the clock timing of the entire chip is delayed with respect to the external signal. There arises a problem that the operating margin is lowered.

Further, as a countermeasure when a large difference occurs in the wiring lengths of the above-mentioned two systems of clocks, the cell placement process of the semiconductor integrated circuit is executed again to change the placement position of the selector cells, and the clock tree is regenerated. Things are also done. However, an optimal solution is not always obtained by one re-execution. In some cases, cell placement and clock tree generation are repeated until an optimal solution is obtained, which causes a problem that it takes time to design a semiconductor integrated circuit.
JP 2006-93249 A (page 4-5, FIG. 1)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit design apparatus capable of arranging cells on a shared clock path of a plurality of clock signals at a position where the clock propagation delay time is the shortest.

  According to one aspect of the present invention, there is provided a semiconductor integrated circuit design apparatus to which cell arrangement position data and net data of a semiconductor integrated circuit are input, and a cell to which a plurality of clock signals are input is extracted as a plurality of clock input cells. A plurality of clock input cell extracting means, and a plurality of the plurality of clock input cells from the output end of the plurality of clock input cells to a terminal cell in which a clock path signal output from the plurality of clock input cells is input to the clock input end A shared clock path cell extracting means for extracting a cell existing in a shared clock path shared by the clock signal as a shared clock path cell, and a propagation delay of the shared clock path based on cell arrangement position information of the shared clock path cell Move destination position of the multiple clock input cells and the shared clock path cell to reduce time Cell move destination position calculating means for calculating the cell placement position changing means for changing the placement position of the plurality of clock input cells and the shared clock path cell to the move destination position and outputting the clock tree generation cell placement position data A semiconductor integrated circuit design apparatus is provided.

  According to the present invention, cells on a shared clock path for a plurality of clock signals can be arranged at a position where the clock propagation delay time is the shortest.

  FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention.

  In the semiconductor integrated circuit design apparatus 1 of the present embodiment, cell placement position data 100 after cell placement of a semiconductor integrated circuit having cells to which a plurality of clock signals are inputted and net data 200 of the semiconductor integrated circuit are inputted. The device outputs the clock tree generation cell arrangement position data 300 in which the arrangement positions of the cells on the shared clock path of the plurality of clock signals are changed.

  The semiconductor integrated circuit design device 1 includes a plurality of clock input cell extraction units 11 that extract a cell to which a plurality of clock signals are input as a plurality of clock input cells from the net data 200, and an output terminal of the extracted plurality of clock input cells. To the cell that is present in the shared clock path shared by multiple clock signals, from the output of the multiple clock input cells to the terminal cell that is transmitted as the clock path signal to the clock input terminal. Multiple clock input cells and shared clocks that reduce the propagation delay time of the shared clock path based on the shared clock path cell extraction unit 12 that is extracted from the net data 200 and the cell arrangement position information of the shared clock path cell as path cells A cell destination calculation unit 13 for calculating the destination location of the clock path cell; Has been to the destination position by changing the arrangement position of the plurality of clocks input cells and sharing the clock path cell comprises a cell placement position changing unit 14 for outputting a clock tree generation cell layout position data 300, a.

  According to the semiconductor integrated circuit design apparatus of this embodiment as described above, the arrangement positions of the multiple clock input cells and the shared clock path cell to the position where the propagation delay time of the shared clock path is shortened with respect to the initial cell arrangement position. Therefore, the propagation delay time of the shared clock path can be minimized.

  Here, since there are several methods for calculating the cell movement destination position in the cell movement destination position calculation unit 13, those methods are shown in Embodiments 1 to 4.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a flowchart showing the processing procedure of cell move destination position calculation in the present embodiment of the cell move destination position calculation unit 13.

  Upon receiving the output of the shared clock path cell information 121 from the shared clock path cell extracting unit 12, the cell move destination position calculation unit 13 first sets the shared clock path cell arrangement area including all the shared clock path cells as its end. Is calculated as a boundary (step S01).

  Next, in this shared clock path cell arrangement region, a position that is equidistant from any clock source of the plurality of clock signals input to the plurality of clock input cells is calculated (step S02).

  Then, the position is determined as the movement destination position of the plurality of clock input cells (step S03), and the information is output as the movement destination position information 131.

  FIG. 3 shows the movement destination position determination process for a plurality of clock input cells according to this embodiment. Here, a signal serving as a shared clock path P is output from a plurality of clock input cells M1 (for example, a selector) to which the clock A from the clock source S1 and the clock B from the clock source S2 are input, and this shared clock path P It is assumed that shared clock path cells C1 to C3 are connected to each other. The shared clock path cells C1 to C3 are end cells to which signals of the common clock path P are input to the clock input terminal, and specifically, cells such as flip-flops.

  FIG. 3A shows a state in which the shared clock path cell arrangement region R is calculated by the procedure S01 in FIG.

  Here, the shape of the shared clock path cell arrangement region R is rectangular, and the region is determined with a line in contact with the outer edge of the cell arranged at the end as a boundary.

  FIG. 3B shows a state where the positions that are equidistant from the clock sources S1 and S2 are calculated in the shared clock path cell arrangement region R by the procedure S02 of FIG.

  That is, a line segment having the same length is extended from the output end of the clock source S1 and the output end of the clock source S2, and the intersection point in the shared clock path cell arrangement region R is set as the movement destination position T of the plurality of clock input cells M1. .

  FIG. 3C shows a cell arrangement when the plurality of clock input cells M1 are moved to the movement destination position T in step S03 of FIG.

  According to this embodiment, a plurality of clock input cells can be arranged at the same distance from any clock source of the input clock signal. Propagation delay times due to wiring to a plurality of clock input cells can be made substantially equal. Therefore, it is not necessary to insert a delay adjusting circuit for adjusting the delay time when generating the clock tree, and the clock propagation delay time can be minimized.

  FIG. 4 is a flowchart showing the processing procedure of cell move destination position calculation in the present embodiment of the cell move destination position calculation unit 13.

  Upon receiving the output of the shared clock path cell information 121 from the shared clock path cell extracting unit 12, the cell move destination position calculation unit 13 first sets the shared clock path cell arrangement area including all the shared clock path cells as its end. Is calculated as a boundary (step S11).

  Next, in this shared clock path cell arrangement area, the position of the center of gravity based on the arrangement position of the shared clock path cell is calculated (step S12).

Here, the position of the center of gravity is expressed as (Xm, Ym).
Xm = the average value of the X coordinate of the arrangement position of each shared clock cell Ym = the average value of the Y coordinate of the arrangement position of each shared clock cell.

  Then, the position is determined as the movement destination position of the plurality of clock input cells (step S13), and the information is output as the movement destination position information 132.

  FIG. 5 shows the movement destination position determination process for a plurality of clock input cells according to this embodiment. Here, the arrangement of each cell is the same as that shown in FIG.

  FIG. 5A shows a state where the shared clock path cell arrangement region R is calculated by the procedure S11 of FIG. Also in the present embodiment, as in the first embodiment, the shared clock path cell arrangement region R has a rectangular shape, and the region is defined by using a line in contact with the outer edge of the cell arranged at the end as a boundary.

  In FIG. 5B, the position of the center of gravity based on the arrangement position of the shared clock path cell is calculated in the shared clock path cell arrangement region R by the procedure S12 of FIG. 4, and the position of the plurality of clock input cells M1 is moved. A state where the tip position T is set is shown.

Here, assuming that the central coordinates of the shared clock path cells C1 to C3 are (X1, Y1), (X2, Y2), (X3, Y3), the coordinates of the center of gravity of the shared clock path cell arrangement region R (Xm, Ym) )
Xm = (X1 + X2 + X3) / 3
Ym = (Y1 + Y2 + Y3) / 3
Is calculated as

  FIG. 5C shows a state of the cell arrangement when the plurality of clock input cells M1 are moved to the movement destination position T in step S13 of FIG.

  Here, it is assumed that the plurality of clock input cells M1 are moved so that the center coordinates of the plurality of clock input cells M1 become the movement destination position T.

  According to this embodiment, since a plurality of clock input cells can be arranged at a well-balanced position of clock distribution to the shared clock path cell, the clocks can be transmitted with equal propagation delay time to any shared clock path cell. Can be distributed. Since no imbalance occurs in the propagation delay time of the clock, it is possible to prevent the insertion of a delay adjustment circuit for adjusting the delay time when generating the clock tree.

  FIG. 6 is a flowchart showing the processing procedure of cell move destination position calculation in the present embodiment of the cell move destination position calculation unit 13.

  Upon receiving the output of the shared clock path cell information 121 from the shared clock path cell extracting unit 12, the cell move destination position calculation unit 13 first sets the shared clock path cell arrangement area including all the shared clock path cells as its end. Is calculated as a boundary (step S21).

  Next, weighting of the wiring order is performed on the shared clock path so that the wiring of the shared clock path is performed first in preference to other wirings (step S22), and the wiring start point position where the wiring length of the shared clock path becomes shorter Is calculated (step S23).

  Then, the position is determined as the movement destination position of the plurality of clock input cells (step S24), and the information is output as the movement destination position information 133.

  FIG. 7 shows a state of the movement destination position determination process of the plurality of clock input cells according to the present embodiment. Here, the arrangement of each cell is the same as that shown in FIG.

  FIG. 7A shows an example in which the shared clock path cell arrangement region R is calculated by the procedure S21 of FIG. 6 and the shared clock path P is weighted by the procedure S22 of FIG. In the present embodiment, similarly to the first embodiment, the shared clock path cell arrangement region R has a rectangular shape, and the region is defined by using a line in contact with the outer edge of the cell arranged at the end as a boundary.

  In FIG. 7B, it is assumed that the wiring length of the shared clock path P is the shortest when the weighted shared clock path P is preferentially routed over other wirings by the procedure S23 of FIG. The state where the wiring start point position is calculated as the movement destination position T is shown.

  FIG. 7C shows a cell arrangement when the multiple clock input cells M1 are moved to the movement destination position T by the procedure S24 of FIG. Here, it is assumed that the plurality of clock input cells M1 are moved so that the output ends of the plurality of clock input cells M1 are at the movement destination position T.

  According to this embodiment, since the wiring length of the shared clock path from the multiple clock input cells to the shared clock path cell can be minimized, the propagation delay time of the clock propagating through the shared clock path can be minimized. It can be.

  In each of the above-described embodiments, the movement of one cell is shown as an example. However, in this embodiment, a processing procedure when moving a plurality of cells is shown. In addition, about the movement of each cell, the process procedure in any one of the above-mentioned Example shall be taken.

  FIG. 7 is a flowchart showing a processing procedure when moving a plurality of cells.

  When the process is started, first, the cell arrangement information in the shared clock path is cut out from the cell arrangement position data 100 with reference to the net data 200 (step S31).

  Next, a cell closest to the end of the shared clock path is extracted from the cells included in the cell arrangement information (step S32).

  Any one of the processes of the first to third embodiments is executed for this cell, and the arrangement position of the cell is determined (procedure S33).

  Next, it is determined whether or not there is an unplaced cell in which the placement position is not determined in the cell placement information in the shared clock path cut out in step S31 (step S34).

  If there is no unarranged cell (NO), this process is terminated. If there is an unarranged cell (YES), the process returns to step S31 to select from the cells included in the cell arrangement information in the shared clock path. The next cell closest to the end of the shared clock path is taken out and the subsequent processing is repeated.

  In this way, when the arrangement positions are determined for all the cells included in the cell arrangement information in the shared clock path, the processing according to this flow is finished.

  FIG. 9 shows a state of cell movement processing according to this flow.

  FIG. 9A shows a state of cell arrangement in the shared clock path. Here, the shared clock path cells C1 to C4 are cells at the end of the shared clock path such as flip-flops, and the shared clock path cell M2 is a cell through which a clock signal passes, such as a logic gate.

  The shared clock path cells C1 to C2 are directly supplied with a clock from the plurality of clock input cells M1, and the shared clock path cells C3 to C4 are supplied with a clock from the plurality of clock input cells M1 via the shared clock path cell M2. , Shall be supplied. Therefore, in this case, the shared clock path cells C3 to C4 are the end cells of the shared clock path P.

  When the process shown in the flow of FIG. 8 is performed on the cells in the shared clock path, the shared clock path cell M2 is extracted as the cell closest to the end of the shared clock path P in step S32. In step S33, the arrangement position of the shared clock path cell M2 is determined.

  FIG. 9B shows how the arrangement position of the shared clock path cell M2 is determined. In this case, an area including the shared clock path cells C3 to C4 connected to the shared clock path cell M2 is calculated as the shared clock path cell arrangement area R1. Then, the arrangement position of the shared clock path cell M2 is determined so as to move the shared clock path cell M2 to the shared clock path cell arrangement region R1.

  Next, an unplaced cell is determined in step S33 of FIG. In this case, since the plurality of clock input cells M1 remain as non-arranged cells, the arrangement position of the plurality of clock input cells M1 is subsequently determined.

  FIG. 9C shows how the arrangement positions of the multiple clock input cells M1 are determined. In this case, an area including all the shared clock path cells connected to the shared clock path P is calculated as the shared clock path cell arrangement area R2. Then, the arrangement position of the plurality of clock input cells M1 is determined so that the plurality of clock input cells M1 are moved to the shared clock path cell arrangement region R2.

  According to the present embodiment, a plurality of cells connected to the shared clock path cell are sequentially moved to positions where the propagation delay time is shortened, so that the propagation delay time of the entire shared clock path cell is minimized. can do.

The block diagram which shows the example of a structure of the semiconductor integrated circuit design apparatus which concerns on embodiment of this invention. 1 is a flowchart showing a processing procedure in a semiconductor integrated circuit design apparatus according to Embodiment 1 of the present invention. The figure which shows the mode of the process in the semiconductor integrated circuit design apparatus of Example 1 of this invention. The flowchart which shows the process sequence in the semiconductor integrated circuit design apparatus of Example 2 of this invention. The figure which shows the mode of the process in the semiconductor integrated circuit design apparatus of Example 2 of this invention. The flowchart which shows the process sequence in the semiconductor integrated circuit design apparatus of Example 3 of this invention. The figure which shows the mode of the process in the semiconductor integrated circuit design apparatus of Example 3 of this invention. The flowchart which shows the process sequence in the semiconductor integrated circuit design apparatus of Example 4 of this invention. The figure which shows the mode of the process in the semiconductor integrated circuit design apparatus of Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit design apparatus 11 Multiple clock input cell extraction part 12 Common clock path cell extraction part 13 Cell movement destination position calculation part 14 Cell arrangement position change part

Claims (5)

A semiconductor integrated circuit design apparatus to which cell arrangement position data and net data of a semiconductor integrated circuit are input,
A plurality of clock input cell extracting means for extracting a cell to which a plurality of clock signals are input as a plurality of clock input cells;
The shared clock path shared by the plurality of clock signals from the output terminal of the plurality of clock input cells to the terminal cell input to the clock input terminal of the signal of the clock path output from the plurality of clock input cells A shared clock path cell extracting means for extracting a cell existing in the network as a shared clock path cell;
Cell movement destination position calculating means for calculating the movement destination position of the plurality of clock input cells and the shared clock path cell, which reduces the propagation delay time of the shared clock path based on the cell arrangement position information of the shared clock path cell When,
Cell placement position changing means for changing the placement position of the plurality of clock input cells and the shared clock path cell to the destination position and outputting cell placement position data for generating a clock tree Design equipment. The cell destination position calculating means is
The shared clock path cell arrangement area including all of the shared clock path cells is calculated with the cell arranged at the end thereof as a boundary, and from the clock sources of any of the plurality of clock signals in the shared clock path cell arrangement area 2. The semiconductor integrated circuit design apparatus according to claim 1, wherein positions that are equidistant are calculated, and the positions are determined as the movement destination positions of the plurality of clock input cells. The cell destination position calculating means is
The shared clock path cell placement area including all of the shared clock path cells is calculated with the cell placed at the end as a boundary, and the center of gravity based on the placement position of the shared clock path cell in the shared clock path cell placement area is calculated. 2. The semiconductor integrated circuit design apparatus according to claim 1, wherein a position is calculated and the position is determined as a movement destination position of the plurality of clock input cells. The cell destination position calculating means is
The shared clock path cell including all of the shared clock path cells is calculated with a cell disposed at an end thereof as a boundary, weighting is performed so that the wiring order is given priority to the shared clock path, and the shared clock path cell 2. The semiconductor integrated circuit design apparatus according to claim 1, wherein a position at which the shared clock path wiring length is shortened in an arrangement area is calculated, and the position is determined as a movement destination position of the plurality of clock input cells. 2. The semiconductor integrated circuit design apparatus according to claim 1, wherein when there are a plurality of cascade-connected cells on the shared clock path cell, the destination positions of the cells are sequentially determined one by one.

Images