JP2008182029A - Polishing method of semiconductor wafer - Google Patents

Polishing method of semiconductor wafer Download PDF

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JP2008182029A
JP2008182029A JP2007013950A JP2007013950A JP2008182029A JP 2008182029 A JP2008182029 A JP 2008182029A JP 2007013950 A JP2007013950 A JP 2007013950A JP 2007013950 A JP2007013950 A JP 2007013950A JP 2008182029 A JP2008182029 A JP 2008182029A
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semiconductor wafer
carrier
polishing
semiconductor
wafer
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Ei Uematsu
鋭 植松
Shoji Masuyama
尚司 増山
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a polishing method of a semiconductor wafer, which provides high planarity. <P>SOLUTION: Semiconductor wafers 9 are inserted into semiconductor insertion holes 8 which are formed in a carrier 7 in such a manner that they penetrate the carrier 7 from one to the other face. The semiconductor wafers 9 are held from both faces by polishing plates 3 and 5 each having polishing cloth 6 pasted thereon. By scrub-moving the carrier 7 and the surface plates 3 and 5 relatively to each other, both faces of the semiconductor wafers 9 are polished. As for the carrier 7, the thickness ratio of the carrier 7 to the target processing thickness of the semiconductor wafers 9 is not less than 0.4 and not more than 0.7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、高い平坦性が得られる半導体ウェハの研磨方法に関する。   The present invention relates to a method for polishing a semiconductor wafer that provides high flatness.

化合物半導体は、ショットキーゲート電界効果トランジスタ(MESFET)、高移動度トランジスタ(HEMT)、ヘテロ接合バイポーラトランジスタ(HBT)などの種々の受発光デバイスに用いられている。これらの素子の能動層は、分子線エピタキシャル成長(MBE)法、有機金属層エピタキシャル成長(MOVPE)法、イオン打ち込み法などにより、鏡面ウェハの表面に作成される。   Compound semiconductors are used in various light emitting and receiving devices such as Schottky gate field effect transistors (MESFET), high mobility transistors (HEMT), and heterojunction bipolar transistors (HBT). The active layer of these elements is formed on the surface of the mirror wafer by a molecular beam epitaxial growth (MBE) method, an organic metal layer epitaxial growth (MOVPE) method, an ion implantation method, or the like.

鏡面ウェハは、次の手順で作成される。   The mirror wafer is created by the following procedure.

まず、結晶インゴットをスライスしてウェハを切り出す。このスライスウェハを#800〜#3000のアルミナ砥粒でラッピングすることにより、ソーマークを除去すると共に平坦性を高める。その後、研磨液として次亜鉛素酸系水溶液や次亜鉛素酸水溶液と砥粒(シリカ、アルミナ、ジルコニウム)の混合液を用い、研磨布として表面に多孔質を有する研磨布を用い、メカノケミカル研磨により鏡面に仕上げる。この研磨をポリッシングと言う。次に、脱脂洗浄を行い、ごく僅かなエッチング作用を持つ洗浄液での洗浄を行い、超純水洗浄を行う。最後にウェハを乾燥させる。   First, a crystal ingot is sliced and a wafer is cut out. By wrapping the slice wafer with # 800 to # 3000 alumina abrasive grains, the saw mark is removed and the flatness is enhanced. Then, mechanochemical polishing using a hypozinc acid aqueous solution or a mixture of hypozinc acid aqueous solution and abrasive grains (silica, alumina, zirconium) as the polishing liquid, and a polishing cloth having a porous surface as the polishing cloth To finish the mirror surface. This polishing is called polishing. Next, degreasing cleaning is performed, cleaning is performed with a cleaning solution having a very slight etching action, and ultrapure water cleaning is performed. Finally, the wafer is dried.

両面が鏡面であるウェハを作成する場合、ポリッシングを1次と2次に分ける。   When creating a wafer having both mirror surfaces, polishing is divided into primary and secondary.

1次ポリッシングでは、ウェハの両面を同時に研磨し、ウェハが1次ポリッシングの加工目標厚さになるまで加工する。このとき、ウェハの平坦性(平坦度とも言う)がいかに保てるかが重要なポイントとなる。それは、1次ポリッシングにて数十μmの研磨量(研磨する厚さ)を研磨するのに対し、次工程である2次ポリッシングでは、数μmまたは1μm以下の研磨量しか研磨しないため、1次ポリッシングで損なわれた平坦性を2次ポリッシングで修正することができないためである。   In the primary polishing, both surfaces of the wafer are simultaneously polished and processed until the wafer reaches a processing target thickness for the primary polishing. At this time, an important point is how to maintain the flatness (also referred to as flatness) of the wafer. In contrast to polishing a polishing amount (thickness to be polished) of several tens of μm by primary polishing, secondary polishing, which is the next step, polishes only a polishing amount of several μm or 1 μm or less. This is because the flatness damaged by polishing cannot be corrected by secondary polishing.

特開平5−169365号公報JP-A-5-169365 特開平5−177539号公報JP-A-5-177539

しかしながら、従来の両面1次ポリッシングでは、ウェハの平坦性は、研磨布の硬度の変化、目詰まり、研磨液の温度変化などの影響を受けるため、高い平坦性を得ることが困難である。ウェハに高い平坦性が得られないと、このウェハを用いて作製された製品である受発光デバイスの歩留まりに大きく影響する。   However, in conventional double-sided primary polishing, the flatness of the wafer is affected by changes in the hardness of the polishing cloth, clogging, temperature changes in the polishing liquid, and so on, making it difficult to obtain high flatness. If high flatness cannot be obtained for a wafer, the yield of light emitting and receiving devices, which are products manufactured using this wafer, is greatly affected.

そこで、本発明の目的は、上記課題を解決し、高い平坦性が得られる半導体ウェハの研磨方法を提供することにある。   SUMMARY OF THE INVENTION An object of the present invention is to provide a method for polishing a semiconductor wafer that solves the above-described problems and provides high flatness.

上記目的を達成するために本発明は、キャリアを片面から反対面に貫通する半導体ウェハ挿入穴に半導体ウェハを挿入し、そのキャリアの両面から上記半導体ウェハをそれぞれ研磨布が貼付された定盤で挟み、上記キャリアと上記定盤とを相対的に擦り動かすことにより、上記半導体ウェハの両面を研磨する際に、上記キャリアとして上記半導体ウェハの加工目標厚さに対し、0.4以上0.7以下の厚さ比を有するキャリアを用いるものである。   In order to achieve the above object, the present invention provides a surface plate in which a semiconductor wafer is inserted into a semiconductor wafer insertion hole penetrating the carrier from one side to the opposite side, and the semiconductor wafer is attached to each side of the carrier with a polishing cloth. By sandwiching and relatively rubbing the carrier and the surface plate, when polishing both surfaces of the semiconductor wafer, 0.4 to 0.7 with respect to the processing target thickness of the semiconductor wafer as the carrier A carrier having the following thickness ratio is used.

上記半導体ウェハの半導体がIII−V族化合物半導体であってもよい。   The semiconductor of the semiconductor wafer may be a III-V group compound semiconductor.

上記III−V族化合物がGaAsであってもよい。   The III-V group compound may be GaAs.

上記III−V族化合物が半絶縁性GaAsであってもよい。   The III-V group compound may be semi-insulating GaAs.

上記半導体ウェハの半導体がII−VI族化合物半導体であってもよい。   The semiconductor of the semiconductor wafer may be a II-VI group compound semiconductor.

本発明は次の如き優れた効果を発揮する。   The present invention exhibits the following excellent effects.

(1)高い平坦性が得られる   (1) High flatness is obtained

以下、本発明の一実施形態を添付図面に基づいて詳述する。   Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

図1に示されるように、本発明の研磨方法を実施する研磨装置1は、中心を下側回転軸2に支承された円盤形の下側定盤3と、この下側定盤3に対向し、中心を上側回転軸4に支承された円盤形の上側定盤5と、下側定盤3の上面及び上側定盤5の下面に貼り付けられた研磨布6と、これら定盤3,5間に設置され、これら定盤3,5より小径の円盤形のキャリア7とを備える。   As shown in FIG. 1, a polishing apparatus 1 that performs the polishing method of the present invention is a disk-shaped lower surface plate 3 that is supported by a lower rotating shaft 2 at the center, and is opposed to the lower surface plate 3. A disc-shaped upper surface plate 5 whose center is supported by the upper rotating shaft 4; a polishing cloth 6 affixed to the upper surface of the lower surface plate 3 and the lower surface of the upper surface plate 5; And a disk-shaped carrier 7 having a diameter smaller than those of the surface plates 3 and 5.

この研磨装置1の構成は、キャリアの厚さを除けば、特許文献1,2などにより周知のものである。簡単に説明すると、下側定盤3及び上側定盤5は、各々下側回転軸2又は上側回転軸4の回転に随伴して回転することができる。キャリア7は、図示しない駆動ギアに噛み合う歯(図示せず)を外周部に有することにより、当該キャリア7の中心を軸にして回転することができる。   The configuration of the polishing apparatus 1 is well known from Patent Documents 1 and 2 except for the thickness of the carrier. Briefly described, the lower surface plate 3 and the upper surface plate 5 can rotate as the lower rotating shaft 2 or the upper rotating shaft 4 rotates. The carrier 7 can rotate around the center of the carrier 7 by having teeth (not shown) meshing with a drive gear (not shown) on the outer peripheral portion.

この実施形態では、キャリア7が4つ設けられている。また、各々のキャリア7には半導体ウェハ挿入穴8が4つ設けられている。キャリア7の個数、半導体ウェハ挿入穴8の個数はこれに限定されない。   In this embodiment, four carriers 7 are provided. Each carrier 7 is provided with four semiconductor wafer insertion holes 8. The number of carriers 7 and the number of semiconductor wafer insertion holes 8 are not limited to this.

半導体ウェハ挿入穴8は、キャリア7を片面から反対面に貫通するものである。また、半導体ウェハ挿入穴8は、これに挿入される半導体ウェハ9の径とほぼ同じ径を有する。   The semiconductor wafer insertion hole 8 penetrates the carrier 7 from one side to the opposite side. Moreover, the semiconductor wafer insertion hole 8 has a diameter substantially the same as the diameter of the semiconductor wafer 9 inserted therein.

図2に示されるように、下側定盤3と上側定盤5の距離を狭めていくと、半導体ウェハ9が研磨布付きの定盤3,5で挟まれる。このとき、キャリア7の厚さは、加工開始前の半導体ウェハ9の厚さより薄いことはもちろん、上記半導体ウェハの加工目標厚さに対し0.4以上0.7以下の厚さ比を有するキャリアを用いる。   As shown in FIG. 2, when the distance between the lower surface plate 3 and the upper surface plate 5 is reduced, the semiconductor wafer 9 is sandwiched between the surface plates 3 and 5 with polishing cloth. At this time, the carrier 7 has a thickness ratio of 0.4 or more and 0.7 or less with respect to the processing target thickness of the semiconductor wafer, as well as the thickness of the semiconductor wafer 9 before the start of processing. Is used.

ここで、上記半導体ウェハの加工目標厚さに対し0.7以下の厚さ比を有するキャリアを用いる理由は、図3に示す実験結果による。すなわち、横軸に加工目標厚さに対するキャリアの厚さ比、縦軸に研磨後の半導体ウエハの平坦性(TTV)を示すと、厚さ比0.7において顕著な改善効果が認められた。ここで、平坦性の測定は、トロペル社製平坦度測定器Ultra Sortを用いた。   Here, the reason why the carrier having a thickness ratio of 0.7 or less with respect to the processing target thickness of the semiconductor wafer is based on the experimental result shown in FIG. That is, when the carrier thickness ratio with respect to the processing target thickness is shown on the horizontal axis and the flatness (TTV) of the semiconductor wafer after polishing is shown on the vertical axis, a remarkable improvement effect was recognized at a thickness ratio of 0.7. Here, the flatness was measured using a Tropel flatness measuring device Ultra Sort.

一方、上記半導体ウェハの加工目標厚さに対し0.4以上の厚さ比を有するキャリアを用いる理由は、図4に示す実験結果による。すなわち、横軸に加工目標厚さに対するキャリアの厚さ比、縦軸に各々10回の研磨作業を実施した場合、作業中にウエハがキャリアから外れてしまうトラブルの発生回数を示している。キャリアが薄くなりすぎると、ウエハの保持力が低減してしまうため、このようなトラブルが増加すると考えられる。   On the other hand, the reason why a carrier having a thickness ratio of 0.4 or more with respect to the processing target thickness of the semiconductor wafer is based on the experimental results shown in FIG. That is, the horizontal axis represents the carrier thickness ratio relative to the processing target thickness, and the vertical axis represents the number of occurrences of trouble that the wafer is detached from the carrier during the operation. If the carrier becomes too thin, the holding force of the wafer is reduced, and it is considered that such troubles increase.

以上の結果から、本発明にあっては、キャリア7を片面から反対面に貫通する半導体ウェハ挿入穴8に半導体ウェハ9を挿入し、そのキャリア7の両面から半導体ウェハ9をそれぞれ研磨布6が貼付された定盤3,5で挟み、キャリア7と定盤3,5とを相対的に擦り動かすことにより、半導体ウェハ9の両面を研磨する際に、キャリア7として半導体ウェハ9の加工目標厚さに対し0.4以上0.7以下の厚さ比を有するキャリア7を用いる。   From the above results, in the present invention, the semiconductor wafer 9 is inserted into the semiconductor wafer insertion hole 8 penetrating the carrier 7 from one surface to the opposite surface, and the polishing cloth 6 is attached to the semiconductor wafer 9 from both surfaces of the carrier 7. When the both surfaces of the semiconductor wafer 9 are polished by sandwiching them between the affixed surface plates 3 and 5 and moving the carrier 7 and the surface plates 3 and 5 relatively, the processing target thickness of the semiconductor wafer 9 as the carrier 7 The carrier 7 having a thickness ratio of 0.4 to 0.7 is used.

これにより、加工中の半導体ウェハ9の平坦性を向上させることができ、かつウエハがキャリアから外れてしまうというトラブルも生じない。   Thereby, the flatness of the semiconductor wafer 9 being processed can be improved, and the trouble that the wafer is detached from the carrier does not occur.

なお、加工目標厚さに対し0.7以下の厚さ比を有するキャリア7を用いることで平坦性が向上する理由については、ウエハにかかる圧力の均一性が向上するためと考えているが、現在のところ、なぜ圧力の均一性が向上するのかについての好適な説明モデルを見出すに至ってはいない。しかし、本出願人は、鋭意研究の結果、実験により図3に示す事実を見出し、本発明に想到した。   The reason why the flatness is improved by using the carrier 7 having a thickness ratio of 0.7 or less with respect to the processing target thickness is considered to be because the uniformity of pressure applied to the wafer is improved. At present, no suitable explanatory model has been found for why pressure uniformity is improved. However, as a result of diligent research, the present applicant has found the fact shown in FIG. 3 through experiments and arrived at the present invention.

本発明の研磨方法が適用される半導体ウェハ9の半導体として、III−V族化合物半導体があり、そのIII−V族化合物としてGaAs、半絶縁性GaAsがある。また、本発明の研磨方法が適応される半導体ウェハ9として、II−VI族化合物半導体がある。これらの半導体ウェハ9を本発明によって高い平坦性で加工することにより、高精度な化合物半導体ウェハが安定して生産でき、その結果、受発光デバイスの歩留まりが高まる。   The semiconductor of the semiconductor wafer 9 to which the polishing method of the present invention is applied includes a III-V group compound semiconductor, and the III-V group compound includes GaAs and semi-insulating GaAs. Further, as a semiconductor wafer 9 to which the polishing method of the present invention is applied, there is a II-VI group compound semiconductor. By processing these semiconductor wafers 9 with high flatness according to the present invention, a highly accurate compound semiconductor wafer can be stably produced, and as a result, the yield of light receiving and emitting devices is increased.

研磨装置1として、浜井産業製16B両面ポリッシャを用い、研磨液には、次亜鉛素酸水溶液とシリカを混合した研磨液を用い、研磨布6にはポリウレタン製の研磨布を用いた。キャリア7には、厚さ600μmのキャリア(比較例)と厚さ400μmのキャリア(実施例)とを用いた。半導体ウェハ9の初期厚さは670μmであり、加工目標厚さは630μmとした。   A 16B double-side polisher manufactured by Hamai Sangyo Co., Ltd. was used as the polishing apparatus 1, a polishing liquid in which a hypozincic acid aqueous solution and silica were mixed was used as the polishing liquid, and a polyurethane polishing cloth was used as the polishing cloth 6. As the carrier 7, a carrier having a thickness of 600 μm (comparative example) and a carrier having a thickness of 400 μm (example) were used. The initial thickness of the semiconductor wafer 9 was 670 μm, and the processing target thickness was 630 μm.

これら2種類のキャリア(比較例、実施例)を用いて半導体ウェハ9を加工目標厚さまで研磨し、研磨後の半導体ウェハの平坦性(TTV)をトロペル社製平坦度測定器Ultra Sortで測定した。   Using these two types of carriers (comparative example, example), the semiconductor wafer 9 was polished to the processing target thickness, and the flatness (TTV) of the polished semiconductor wafer was measured with a Tropel flatness measuring instrument Ultra Sort. .

この結果、比較例のキャリアを用いて研磨した半導体ウェハの平坦性は、1.28μmとなったが、実施例のキャリアを用いて研磨した半導体ウェハの平坦性は、0.79μmとなった。このように、比較例では良好な平坦性を得られなかったのに対し、実施例では良好な平坦性を得ることができた。   As a result, the flatness of the semiconductor wafer polished using the carrier of the comparative example was 1.28 μm, but the flatness of the semiconductor wafer polished using the carrier of the example was 0.79 μm. As described above, good flatness could not be obtained in the comparative example, whereas good flatness could be obtained in the example.

本発明の一実施形態を示す研磨装置の斜視図である。1 is a perspective view of a polishing apparatus showing an embodiment of the present invention. 図1の研磨装置の部分断面図である。It is a fragmentary sectional view of the polish device of Drawing 1. 加工目標厚さに対するキャリアの厚さ比を変えて研磨後の半導体ウエハの平坦性を調べた実験結果を示す図である。It is a figure which shows the experimental result which investigated the flatness of the semiconductor wafer after grinding | polishing by changing the thickness ratio of the carrier with respect to process target thickness. 加工目標厚さに対するキャリアの厚さ比を変えて作業中にウエハがキャリアから外れてしまうトラブルの発生回数を調べた実験結果を示す図である。It is a figure which shows the experimental result which investigated the frequency | count of occurrence of the trouble which changes the thickness ratio of the carrier with respect to process target thickness, and a wafer remove | deviates from a carrier during a process.

符号の説明Explanation of symbols

1 研磨装置
3 下側定盤
5 上側定盤
6 研磨布
7 キャリア
8 半導体ウェハ挿入穴
9 半導体ウェハ
DESCRIPTION OF SYMBOLS 1 Polishing apparatus 3 Lower surface plate 5 Upper surface plate 6 Polishing cloth 7 Carrier 8 Semiconductor wafer insertion hole 9 Semiconductor wafer

Claims (5)

キャリアを片面から反対面に貫通する半導体ウェハ挿入穴に半導体ウェハを挿入し、そのキャリアの両面から上記半導体ウェハをそれぞれ研磨布が貼付された定盤で挟み、上記キャリアと上記定盤とを相対的に擦り動かすことにより、上記半導体ウェハの両面を研磨する際に、上記キャリアとして上記半導体ウェハの加工目標厚さに対し、0.4以上0.7以下の厚さ比を有するキャリアを用いることを特徴とする半導体ウェハの研磨方法。   A semiconductor wafer is inserted into a semiconductor wafer insertion hole that penetrates the carrier from one side to the opposite side, and the semiconductor wafer is sandwiched between both surfaces of the carrier by a surface plate to which a polishing cloth is attached, and the carrier and the surface plate are When polishing both surfaces of the semiconductor wafer, the carrier having a thickness ratio of 0.4 to 0.7 with respect to the processing target thickness of the semiconductor wafer is used as the carrier. A method for polishing a semiconductor wafer. 上記半導体ウェハの半導体がIII−V族化合物半導体であることを特徴とする請求項1記載の半導体ウェハの研磨方法。   2. The semiconductor wafer polishing method according to claim 1, wherein the semiconductor of the semiconductor wafer is a III-V group compound semiconductor. 上記III−V族化合物がGaAsであることを特徴とする請求項2記載の半導体ウェハの研磨方法。   3. The method for polishing a semiconductor wafer according to claim 2, wherein the III-V group compound is GaAs. 上記III−V族化合物が半絶縁性GaAsであることを特徴とする請求項2記載の半導体ウェハの研磨方法。   3. The method of polishing a semiconductor wafer according to claim 2, wherein the III-V group compound is semi-insulating GaAs. 上記半導体ウェハの半導体がII−VI族化合物半導体であることを特徴とする請求項1記載の半導体ウェハの研磨方法。   2. The semiconductor wafer polishing method according to claim 1, wherein the semiconductor of the semiconductor wafer is a II-VI group compound semiconductor.
JP2007013950A 2007-01-24 2007-01-24 Polishing method of semiconductor wafer Pending JP2008182029A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011020239A (en) * 2009-07-21 2011-02-03 Kyocera Kinseki Corp Polishing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011020239A (en) * 2009-07-21 2011-02-03 Kyocera Kinseki Corp Polishing apparatus

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