JP2008182029A - Polishing method of semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a polishing method of a semiconductor wafer, which provides high planarity. <P>SOLUTION: Semiconductor wafers 9 are inserted into semiconductor insertion holes 8 which are formed in a carrier 7 in such a manner that they penetrate the carrier 7 from one to the other face. The semiconductor wafers 9 are held from both faces by polishing plates 3 and 5 each having polishing cloth 6 pasted thereon. By scrub-moving the carrier 7 and the surface plates 3 and 5 relatively to each other, both faces of the semiconductor wafers 9 are polished. As for the carrier 7, the thickness ratio of the carrier 7 to the target processing thickness of the semiconductor wafers 9 is not less than 0.4 and not more than 0.7. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for polishing a semiconductor wafer that provides high flatness.

  Compound semiconductors are used in various light emitting and receiving devices such as Schottky gate field effect transistors (MESFET), high mobility transistors (HEMT), and heterojunction bipolar transistors (HBT). The active layer of these elements is formed on the surface of the mirror wafer by a molecular beam epitaxial growth (MBE) method, an organic metal layer epitaxial growth (MOVPE) method, an ion implantation method, or the like.

  The mirror wafer is created by the following procedure.

  First, a crystal ingot is sliced and a wafer is cut out. By wrapping the slice wafer with # 800 to # 3000 alumina abrasive grains, the saw mark is removed and the flatness is enhanced. Then, mechanochemical polishing using a hypozinc acid aqueous solution or a mixture of hypozinc acid aqueous solution and abrasive grains (silica, alumina, zirconium) as the polishing liquid, and a polishing cloth having a porous surface as the polishing cloth To finish the mirror surface. This polishing is called polishing. Next, degreasing cleaning is performed, cleaning is performed with a cleaning solution having a very slight etching action, and ultrapure water cleaning is performed. Finally, the wafer is dried.

  When creating a wafer having both mirror surfaces, polishing is divided into primary and secondary.

  In the primary polishing, both surfaces of the wafer are simultaneously polished and processed until the wafer reaches a processing target thickness for the primary polishing. At this time, an important point is how to maintain the flatness (also referred to as flatness) of the wafer. In contrast to polishing a polishing amount (thickness to be polished) of several tens of μm by primary polishing, secondary polishing, which is the next step, polishes only a polishing amount of several μm or 1 μm or less. This is because the flatness damaged by polishing cannot be corrected by secondary polishing.

JP-A-5-169365 JP-A-5-177539

  However, in conventional double-sided primary polishing, the flatness of the wafer is affected by changes in the hardness of the polishing cloth, clogging, temperature changes in the polishing liquid, and so on, making it difficult to obtain high flatness. If high flatness cannot be obtained for a wafer, the yield of light emitting and receiving devices, which are products manufactured using this wafer, is greatly affected.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for polishing a semiconductor wafer that solves the above-described problems and provides high flatness.

  In order to achieve the above object, the present invention provides a surface plate in which a semiconductor wafer is inserted into a semiconductor wafer insertion hole penetrating the carrier from one side to the opposite side, and the semiconductor wafer is attached to each side of the carrier with a polishing cloth. By sandwiching and relatively rubbing the carrier and the surface plate, when polishing both surfaces of the semiconductor wafer, 0.4 to 0.7 with respect to the processing target thickness of the semiconductor wafer as the carrier A carrier having the following thickness ratio is used.

  The semiconductor of the semiconductor wafer may be a III-V group compound semiconductor.

  The III-V group compound may be GaAs.

  The III-V group compound may be semi-insulating GaAs.

  The semiconductor of the semiconductor wafer may be a II-VI group compound semiconductor.

  The present invention exhibits the following excellent effects.

  (1) High flatness is obtained

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  As shown in FIG. 1, a polishing apparatus 1 that performs the polishing method of the present invention is a disk-shaped lower surface plate 3 that is supported by a lower rotating shaft 2 at the center, and is opposed to the lower surface plate 3. A disc-shaped upper surface plate 5 whose center is supported by the upper rotating shaft 4; a polishing cloth 6 affixed to the upper surface of the lower surface plate 3 and the lower surface of the upper surface plate 5; And a disk-shaped carrier 7 having a diameter smaller than those of the surface plates 3 and 5.

  The configuration of the polishing apparatus 1 is well known from Patent Documents 1 and 2 except for the thickness of the carrier. Briefly described, the lower surface plate 3 and the upper surface plate 5 can rotate as the lower rotating shaft 2 or the upper rotating shaft 4 rotates. The carrier 7 can rotate around the center of the carrier 7 by having teeth (not shown) meshing with a drive gear (not shown) on the outer peripheral portion.

  In this embodiment, four carriers 7 are provided. Each carrier 7 is provided with four semiconductor wafer insertion holes 8. The number of carriers 7 and the number of semiconductor wafer insertion holes 8 are not limited to this.

  The semiconductor wafer insertion hole 8 penetrates the carrier 7 from one side to the opposite side. Moreover, the semiconductor wafer insertion hole 8 has a diameter substantially the same as the diameter of the semiconductor wafer 9 inserted therein.

  As shown in FIG. 2, when the distance between the lower surface plate 3 and the upper surface plate 5 is reduced, the semiconductor wafer 9 is sandwiched between the surface plates 3 and 5 with polishing cloth. At this time, the carrier 7 has a thickness ratio of 0.4 or more and 0.7 or less with respect to the processing target thickness of the semiconductor wafer, as well as the thickness of the semiconductor wafer 9 before the start of processing. Is used.

  Here, the reason why the carrier having a thickness ratio of 0.7 or less with respect to the processing target thickness of the semiconductor wafer is based on the experimental result shown in FIG. That is, when the carrier thickness ratio with respect to the processing target thickness is shown on the horizontal axis and the flatness (TTV) of the semiconductor wafer after polishing is shown on the vertical axis, a remarkable improvement effect was recognized at a thickness ratio of 0.7. Here, the flatness was measured using a Tropel flatness measuring device Ultra Sort.

  On the other hand, the reason why a carrier having a thickness ratio of 0.4 or more with respect to the processing target thickness of the semiconductor wafer is based on the experimental results shown in FIG. That is, the horizontal axis represents the carrier thickness ratio relative to the processing target thickness, and the vertical axis represents the number of occurrences of trouble that the wafer is detached from the carrier during the operation. If the carrier becomes too thin, the holding force of the wafer is reduced, and it is considered that such troubles increase.

  From the above results, in the present invention, the semiconductor wafer 9 is inserted into the semiconductor wafer insertion hole 8 penetrating the carrier 7 from one surface to the opposite surface, and the polishing cloth 6 is attached to the semiconductor wafer 9 from both surfaces of the carrier 7. When the both surfaces of the semiconductor wafer 9 are polished by sandwiching them between the affixed surface plates 3 and 5 and moving the carrier 7 and the surface plates 3 and 5 relatively, the processing target thickness of the semiconductor wafer 9 as the carrier 7 The carrier 7 having a thickness ratio of 0.4 to 0.7 is used.

  Thereby, the flatness of the semiconductor wafer 9 being processed can be improved, and the trouble that the wafer is detached from the carrier does not occur.

  The reason why the flatness is improved by using the carrier 7 having a thickness ratio of 0.7 or less with respect to the processing target thickness is considered to be because the uniformity of pressure applied to the wafer is improved. At present, no suitable explanatory model has been found for why pressure uniformity is improved. However, as a result of diligent research, the present applicant has found the fact shown in FIG. 3 through experiments and arrived at the present invention.

  The semiconductor of the semiconductor wafer 9 to which the polishing method of the present invention is applied includes a III-V group compound semiconductor, and the III-V group compound includes GaAs and semi-insulating GaAs. Further, as a semiconductor wafer 9 to which the polishing method of the present invention is applied, there is a II-VI group compound semiconductor. By processing these semiconductor wafers 9 with high flatness according to the present invention, a highly accurate compound semiconductor wafer can be stably produced, and as a result, the yield of light receiving and emitting devices is increased.

  A 16B double-side polisher manufactured by Hamai Sangyo Co., Ltd. was used as the polishing apparatus 1, a polishing liquid in which a hypozincic acid aqueous solution and silica were mixed was used as the polishing liquid, and a polyurethane polishing cloth was used as the polishing cloth 6. As the carrier 7, a carrier having a thickness of 600 μm (comparative example) and a carrier having a thickness of 400 μm (example) were used. The initial thickness of the semiconductor wafer 9 was 670 μm, and the processing target thickness was 630 μm.

  Using these two types of carriers (comparative example, example), the semiconductor wafer 9 was polished to the processing target thickness, and the flatness (TTV) of the polished semiconductor wafer was measured with a Tropel flatness measuring instrument Ultra Sort. .

  As a result, the flatness of the semiconductor wafer polished using the carrier of the comparative example was 1.28 μm, but the flatness of the semiconductor wafer polished using the carrier of the example was 0.79 μm. As described above, good flatness could not be obtained in the comparative example, whereas good flatness could be obtained in the example.

1 is a perspective view of a polishing apparatus showing an embodiment of the present invention. It is a fragmentary sectional view of the polish device of Drawing 1. It is a figure which shows the experimental result which investigated the flatness of the semiconductor wafer after grinding | polishing by changing the thickness ratio of the carrier with respect to process target thickness. It is a figure which shows the experimental result which investigated the frequency | count of occurrence of the trouble which changes the thickness ratio of the carrier with respect to process target thickness, and a wafer remove | deviates from a carrier during a process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Polishing apparatus 3 Lower surface plate 5 Upper surface plate 6 Polishing cloth 7 Carrier 8 Semiconductor wafer insertion hole 9 Semiconductor wafer

Claims (5)

  A semiconductor wafer is inserted into a semiconductor wafer insertion hole that penetrates the carrier from one side to the opposite side, and the semiconductor wafer is sandwiched between both surfaces of the carrier by a surface plate to which a polishing cloth is attached, and the carrier and the surface plate are When polishing both surfaces of the semiconductor wafer, the carrier having a thickness ratio of 0.4 to 0.7 with respect to the processing target thickness of the semiconductor wafer is used as the carrier. A method for polishing a semiconductor wafer.   2. The semiconductor wafer polishing method according to claim 1, wherein the semiconductor of the semiconductor wafer is a III-V group compound semiconductor.   3. The method for polishing a semiconductor wafer according to claim 2, wherein the III-V group compound is GaAs.   3. The method of polishing a semiconductor wafer according to claim 2, wherein the III-V group compound is semi-insulating GaAs.   2. The semiconductor wafer polishing method according to claim 1, wherein the semiconductor of the semiconductor wafer is a II-VI group compound semiconductor.

Images