JP2008177760A - Solid-state imaging apparatus, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a reset noise in a horizontal transfer circuit equipped with a capacity feedback type amplifier circuit. <P>SOLUTION: In a solid-state imaging apparatus, a noise voltage Vnrst0 when an initialization switch 326 is turned on is maintained to a parasitic capacity 18C of a horizontal signal line 18, and amplified in the case of reset release, and output as a noise voltage Vnrst1. The noise voltage Vnrst1 is acquired by a sample hold circuit 340b before a pixel signal is transferred. In the case of transferring the pixel signal, a signal voltage V2 acquired by amplifying the pixel signal voltage V1 stored in a storage capacity 266 and the signal voltage V3 of the composite components of the signal voltage V4 of the noise voltage Vnrst1 are acquired by a sample hold circuit 340a. A signal addition part 360 calculates a difference between the signal voltage V3 of composite components acquired by the sample hold circuit 340a and the signal voltage 4 of the noise voltage Vnrst1 acquired by the sample hold circuit 340b in advance to extract only the signal voltage V2 by amplifying the pixel signal voltage V1. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an imaging device which are an example of a semiconductor device for physical quantity distribution detection. Specifically, for example, an electric signal indicating a physical quantity distribution in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged and converted into an electric signal by the unit components Is related to the mechanism to output to the outside.

  For example, a plurality of unit components (for example, pixels) that are sensitive to changes in physical quantity such as electromagnetic waves input from the outside such as light and radiation or pressure (contact, etc.) are arranged in a matrix (matrix). Physical quantity distribution detection semiconductor devices are used in various fields.

  For example, in the field of video equipment, a CCD (Charge Coupled Device) type, a MOS (Metal Oxide Semiconductor) or CMOS (Complementary Metal-oxide) that detects a change in light (an example of an electromagnetic wave) which is an example of a physical quantity. A solid-state imaging device using a semiconductor (complementary metal oxide semiconductor) type imaging device (imaging device) is used.

  In recent years, MOS and CMOS image sensors that can overcome various problems associated with CCD image sensors have been attracting attention as an example of solid-state imaging devices. For example, low power consumption compatibility for portable devices. It is mounted on an imaging device such as a solid-state imaging device, an electronic still camera, or a digital video camera device.

  In the field of computer equipment, fingerprint authentication devices that detect fingerprint images based on changes in electrical characteristics based on pressure and changes in optical characteristics are used. These read out, as an electrical signal, a physical quantity distribution converted into an electrical signal by a unit component (a pixel in a solid-state imaging device).

  On the other hand, some solid-state imaging devices have an amplification driving transistor such as an electrostatic induction transistor or a MOS transistor in a pixel signal generation unit that generates a pixel signal corresponding to the signal charge generated in the charge generation unit. There is an amplifying solid-state imaging device including a pixel having a solid-state imaging device (APS: Active Pixel Sensor / gain cell) configuration. For example, many CMOS solid-state imaging devices have such a configuration.

  In such an amplification type solid-state imaging device, in order to read out a pixel signal to the outside, address control is performed on a pixel unit in which a plurality of unit pixels are arranged, and signals from individual unit pixels are arbitrarily selected. I am trying to read it out. That is, the amplification type solid-state imaging device is an example of an address control type solid-state imaging device.

  For example, an amplification type solid-state imaging device which is a kind of XY address type solid-state imaging device in which unit pixels are arranged in a matrix form an active element (MOS transistor) such as a MOS structure in order to give the pixel itself an amplification function. ) To form a pixel. That is, signal charges (photoelectrons) accumulated in a photodiode which is a photoelectric conversion element are amplified by the active element and read out as image information.

  In this type of XY address type solid-state imaging device, for example, a plurality of pixel transistors are arranged in a two-dimensional matrix to form a pixel unit, and a signal charge corresponding to incident light for each line (row) or each pixel. Accumulation is started, and a current or voltage signal based on the accumulated signal charge is read from each pixel in a predetermined order by addressing. Here, in the MOS (including CMOS) type, as an example of address control, one row is accessed simultaneously and pixel signals are read out from the pixel unit in units of rows, and then the pixel signals for one row are sequentially transmitted. A method of reading to the output side is often used.

  For example, a CMOS image sensor has an amplifying circuit such as a floating diffusion amplifier for each pixel arranged in a matrix, and when reading a pixel signal, one row in the pixel array unit is used as an example of address control. So-called column parallel output type or column that reads out pixel signals from the pixel array section in units of rows, that is, simultaneously in parallel for all the pixels of one row. A system called a mold is often used (see, for example, Patent Document 1).

JP 2004-356791 A

  Further, in a general solid-state imaging device, pixel signals acquired by unit pixels in each column are read in the column direction (generally referred to as vertical transfer), and then pixel signals in each column are selected in a predetermined order. The signals are collected on a horizontal signal line and sequentially transferred to a subsequent circuit (generally referred to as horizontal transfer).

  There are various configurations of the horizontal transfer circuit. For example, the horizontal transfer circuit includes an amplifier circuit for amplifying an input signal with an appropriate gain. There are various types of amplifier circuits, but as an example, an amplifier such as an operational amplifier, an input capacitor connected to the input side of the amplifier, and connected between the input and output of the amplifier are connected. There is a capacitor feedback type amplifier circuit that includes a feedback capacitor and an initialization switch that initializes the voltage across the feedback capacitor when the pixel signal is not transferred. In this amplifier circuit, when the pixel signal component is transferred while the initialization switch is OFF, the pixel signal held in the input capacitor is amplified and output with a signal amplification factor represented by the ratio of the input capacitor and the feedback capacitor. The

  In the capacitive feedback type amplifier circuit, reset noise (also called thermal noise) when the initialization switch is turned on to reset the voltage across the feedback capacitor is accumulated in the parasitic capacitance of the horizontal signal line, and the subsequent pixel signal At the time of component transfer, not only the pixel signal is amplified and output with the signal amplification factor, but also the reset noise is amplified and output with the noise amplification factor represented by the ratio of the parasitic capacitance and the feedback capacitance. / N will deteriorate.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a mechanism capable of suppressing a reset noise component in a signal output from a capacitive feedback amplifier circuit.

  In one embodiment of a display device according to the present invention, first, a pixel array unit in which unit pixels are arranged in a matrix, and a capacitive element that holds pixel signals read in the column direction from each unit pixel of the pixel array unit A column-parallel configuration including a plurality of pixel signal holding units including

  Then, in the subsequent stage of the pixel signal holding unit, a selection unit that sequentially selects the pixel signal holding unit, a signal line that transmits a pixel signal output from the pixel signal holding unit selected by the selection unit, an amplification element, and an amplification element A feedback capacitor connected between the input and output of the capacitor, a capacitance feedback type amplifier circuit comprising an initialization switch for initializing the voltage across the feedback capacitor, and noise generated in the output signal of the amplifier circuit due to the initialization of the amplifier circuit ( In particular, a noise suppression unit that suppresses amplifier reset noise or thermal noise) is provided. The capacitive feedback type amplifier circuit operates using the capacitive element of the pixel signal holding unit as an input capacitance.

  The noise suppression unit uses an amplification circuit to generate a noise component that is generated when the initialization switch is turned on when the initialization switch is off and the selection unit does not select the pixel signal holding unit and is held in the capacitor attached to the signal line. The reference information that is amplified and output, and when the initialization switch is off and the selection unit selects the pixel signal holding unit, the pixel signal held in the input capacitor is amplified by the amplification circuit and output. The noise is generated in the output signal of the amplifier circuit by initialization based on the pixel information in the signal transfer state.

  Therefore, for example, a reference information acquisition unit that acquires and holds reference information, a signal transfer information acquisition unit that acquires and holds pixel information in a signal transfer state, and reference information and signals acquired by the reference information acquisition unit A difference information acquisition unit that performs a difference process with the pixel information acquired by the transfer information acquisition unit is provided. This is a configuration that faithfully reflects the function of the noise suppression unit that obtains the difference between the output information (composition component of the pixel signal component and the noise component) at the time of pixel signal transfer and the noise component, and is a compact configuration. Preferably, the reference information acquisition unit and the signal transfer information acquisition unit are configured to be capable of aligning the output timings of the reference information and the pixel information used for processing in the difference information acquisition unit. Good.

  In such a configuration, the noise component when the initialization switch is turned on to reset the voltage across the feedback capacitor is held in the capacitor attached to the signal line, and is amplified and output when the reset is released. The amplified noise component at the time of reset cancellation is acquired by the reference information acquisition unit as reference information before transferring the pixel signal. Thereafter, at the time of pixel signal transfer for selecting the pixel signal holding unit by the selection unit, a component obtained by amplifying the pixel signal held in the capacitor element of the pixel signal holding unit and the reference information (amplified noise component) are combined. Obtained by the signal transfer information obtaining unit. Then, the difference information acquisition unit obtains the difference between the composite component acquired by the signal transfer information acquisition unit and the reference information (amplified noise component) acquired in advance by the reference information acquisition unit, and is acquired at the time of pixel signal transfer. The noise component in the output information is made smaller by using the noise component acquired before the pixel signal transfer with respect to the output information (the combined component of the pixel signal component and the noise component).

  The solid-state imaging device may be in a form formed as a single chip, or may be in a module-like form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together. .

  Further, the present invention can be applied not only to a solid-state imaging device but also to an imaging device. In this case, the same effect as the solid-state imaging device can be obtained as the imaging device. Here, the imaging device indicates, for example, a camera (or camera system) or a portable device having an imaging function. “Imaging” includes not only capturing an image during normal camera shooting, but also includes fingerprint detection in a broad sense.

  According to an embodiment of the present invention, output information of an amplification circuit of a noise component caused by resetting a capacitance feedback type amplification circuit is obtained before pixel signal transfer, and the amplification circuit at the time of pixel signal transfer Since the output information of the noise component is processed using the output information of the amplification circuit of the noise component, the amplifier reset noise can be suppressed in the output signal of the noise suppression unit. The noise component in the output information is made smaller by using the noise component acquired before the pixel signal transfer with respect to the output information (the combined component of the pixel signal component and the noise component) acquired during the pixel signal transfer. Because it makes it.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following, a case where a CMOS solid-state imaging device, which is an example of an XY address type solid-state imaging device, is used as a device will be described as an example. The CMOS solid-state imaging device will be described on the assumption that all pixels are made of NMOS.

  However, this is an example, and the target device is not limited to the MOS type solid-state imaging device. All the semiconductor device for physical quantity distribution detection in which a plurality of unit components that are sensitive to electromagnetic waves input from outside such as light and radiation are arranged in a line or matrix form, and all implementations described later. Forms are applicable as well.

<Overview of solid-state imaging device>
FIG. 1 is a schematic configuration diagram of a CMOS solid-state imaging device (CMOS image sensor) which is an embodiment of the solid-state imaging device according to the present invention.

  The solid-state imaging device 1 has a pixel unit in which a plurality of pixels including a light receiving element (an example of a charge generation unit) that outputs a signal corresponding to an incident light amount is arranged in rows and columns (that is, in a two-dimensional matrix form). The signal output from each pixel is a voltage signal, and a CDS (Correlated Double Sampling) processing function unit and other analog signal processing units are provided in parallel in a column.

  “A CDS processing function unit and other analog signal processing units are provided in parallel in a column” means that a plurality of CDS processes are substantially parallel to a vertical signal line (an example of a column signal line) 19 in a vertical column. This means that a functional unit and other analog signal processing units are provided.

  Each of the plurality of functional units is arranged only on one end side in the column direction with respect to the pixel array unit 10 (output side arranged on the lower side of the drawing) when the device is viewed in plan view. Or one end side in the column direction (output side arranged on the lower side of the figure) and the other end side opposite to the pixel array unit 10 (upper side in the figure). ) May be arranged separately. In the latter case, it is preferable that the horizontal scanning unit that performs readout scanning (horizontal scanning) in the row direction is also arranged separately on each edge side so that each can operate independently.

  For example, as a typical example in which a CDS processing function unit and other analog signal processing units are provided in parallel in a column, a CDS processing function unit and other analog signals are provided in a portion called a column area provided on the output side of the imaging unit. A processing unit is provided for each vertical column, and the vertical column and the CDS processing function unit and other analog signal processing units that are sequentially read out to the output side are connected in a one-to-one relationship.

  In addition to the column type (column parallel type), one CDS processing function unit and other analog signal processing units are allocated to a plurality of adjacent (for example, two) vertical signal lines 19 (vertical columns). Or one CDS processing function unit or other analog signal processing for N vertical signal lines 19 (vertical columns) every N (N is a positive integer; N-1 in-between) The form which allocates a part etc. can also be taken.

  Except for the column type, in any form, the plurality of vertical signal lines 19 (vertical columns) commonly use one CDS processing function unit and other analog signal processing units. A switching circuit (switch) is provided for supplying pixel signals for a plurality of columns supplied from the side to one CDS processing function unit and other analog signal processing units. Depending on the subsequent processing, a separate measure such as providing a memory for holding the output signal is required.

  In any case, the signal processing of each pixel signal is performed in units of pixel columns by adopting a form in which one CDS processing function unit and other analog signal processing units are assigned to a plurality of vertical signal lines 19 (vertical columns). Compared with the case where the same signal processing is performed in each unit pixel, the configuration in each unit pixel is simplified and the number of pixels of the image sensor, size reduction, and cost reduction are supported. it can.

  In addition, since a plurality of signal processing units arranged in parallel in a column can simultaneously process pixel signals for one row, one CDS processing function unit or other analog signal is provided on the output circuit side or outside the device. Compared with processing in the processing unit, the signal processing unit can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like. In other words, when the power consumption and bandwidth performance are the same, the entire sensor can be operated at high speed.

In the case of a column type configuration, it can be operated at a low speed, which is advantageous in terms of power consumption, bandwidth performance, noise, and the like, and has an advantage that a switching circuit (switch) is unnecessary. In the following embodiments, this column type will be described unless otherwise specified.
As shown in FIG. 1, the solid-state imaging device 1 of the present embodiment includes a pixel array unit 10 that is also referred to as a pixel unit or an imaging unit in which a plurality of unit pixels 3 are arranged in rows and columns, and a pixel array unit 10. Drive control unit 7 provided outside, a read current source unit 24 for supplying an operation current (read current) for reading a pixel signal to the unit pixels 3 of the pixel array unit 10, and a column arranged for each vertical column A column processing unit 26 having a signal processing unit 25 and an output circuit 28 are provided. Each of these functional units is provided on the same semiconductor substrate.

  In FIG. 1, some of the rows and columns are omitted for the sake of simplicity, but in reality, tens to thousands of unit pixels 3 are arranged in each row and each column. The unit pixel 3 typically includes a photodiode as a light receiving element (charge generation unit) that is an example of a detection unit, and an intra-pixel amplifier (for example, a transistor) of an amplification semiconductor element (for example, a transistor). Example).

  Note that the solid-state imaging device 1 can make the pixel array unit 10 compatible with color imaging by using a color separation (color separation) filter. That is, color separation comprising a combination of a plurality of color filters for capturing a color image on a light receiving surface on which electromagnetic waves (light in this example) of each charge generation unit (photodiode, etc.) in the pixel array unit 10 are incident. Any color filter of the filter is provided in, for example, a so-called Bayer array, so that color image capturing is supported.

  The drive control unit 7 has a control circuit function for sequentially reading signals from the pixel array unit 10. For example, as the drive control unit 7, a horizontal scanning unit (column scanning circuit) 12 that controls column addresses and column scanning, a vertical scanning unit (row scanning circuit) 14 that controls row addresses and row scanning, and an internal clock are generated. And a communication / timing control unit 20 having functions such as

  The unit pixel 3 includes a vertical scanning unit 14 through a row control line 15 for row selection, and a column processing unit 26 in which a column signal processing unit 25 is provided for each vertical column through a vertical signal line 19. , Each connected. Here, the row control line 15 indicates the entire wiring that enters the pixel from the vertical scanning unit 14.

  The vertical scanning unit 14 selects a row of the pixel array unit 10 and supplies a necessary pulse to the row. For example, the vertical scanning unit 14 defines a readout row in the vertical direction (selects a row of the pixel array unit 10). It has a vertical address setting unit 14a and a vertical drive unit 14b that supplies a pulse to the row control line 15 for the unit pixel 3 on the readout address (in the row direction) defined by the vertical address setting unit 14a and drives it. Note that the vertical address setting unit 14a selects not only a row from which a signal is read (reading row: also referred to as a selection row or a signal output row) but also a row for an electronic shutter.

  The horizontal scanning unit 12 selects the column signal processing unit 25 of the column processing unit 26 in a predetermined order in synchronization with the clock, and reads the pixel signal S1 processed by the column signal processing unit 25 to the horizontal signal line 18. It has the function of a readout scanning unit. For example, the horizontal scanning unit 12 is defined by a horizontal address setting unit 12a that defines a horizontal readout row (selects each column signal processing unit 25 in the column processing unit 26) and a horizontal address setting unit 12a. The horizontal drive unit 12b guides each pixel signal S1 of the column processing unit 26 to the horizontal signal line 18 in accordance with the read address.

  Although not shown, the communication / timing control unit 20 is externally connected via a functional block of a timing generator TG (an example of a read address control device) that supplies a clock signal required for the operation of each unit and a pulse signal of a predetermined timing, and a terminal 5a. The master clock CLK0 supplied from the main control unit of the main unit, the data for instructing the operation mode supplied from the external main control unit via the terminal 5b, etc., and various kinds of information including the operation information of the solid-state imaging device 1 And a functional block of a communication interface that outputs the data to an external main control unit.

  For example, the horizontal address signal is output to the horizontal address setting unit 12a, and the vertical address signal is output to the vertical address setting unit 14a, and each address setting unit 12a, 14a receives it and selects a corresponding row or column. The horizontal scanning unit 12 and the vertical scanning unit 14 include address setting units 12a and 14a for address setting, and shift operation (scanning) in response to control signals CN1 and CN2 given from the communication / timing control unit 20. The read address is switched by, for example.

  At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, the analog pixel signal S0 generated by the pixel signal generation unit provided in the unit pixel 3 and output in the column direction via the vertical signal line 19 is generated. Pixels processed by each column signal processing unit 25 of the column processing unit 26 by accessing the row direction (column parallel) and performing (vertical) scan reading, and then accessing the row direction as the arrangement direction of the vertical columns. It is preferable to increase the reading speed of the pixel signal by performing (horizontal) scan reading for reading the signal S1 to the output side. Of course, not only scanning reading but also random access for reading out only the information of the necessary unit pixel 3 is possible by directly addressing the unit pixel 3 to be read out.

  The column signal processing unit 25 according to the present embodiment includes a pixel signal level (hereinafter referred to as a reset level S0_rst) immediately after a pixel reset that is a reference level of the pixel signal So output from the unit pixel 3 of the pixel array unit 10 and the unit pixel 3. By executing the difference processing between the pixel signal level (hereinafter referred to as signal level S0_sig) reflecting the signal component obtained by detecting electromagnetic waves (such as visible light) at, the reset level S0_rst and the signal level S0_sig A difference processing unit that acquires information on the signal component indicated by the difference is provided. The function of the difference processing unit is equivalent to a process of taking a difference between a general reset level and a true signal level (according to the amount of received light) (equivalent to a so-called CDS (Correlated Double Sampling) process). It is possible to remove noise signal components called fixed pattern noise (FPN) and reset noise.

  The column processing unit 26 includes a column signal processing unit 25 for each vertical column (column), and simultaneously receives the pixel signals S0 of each column for one row, and each column signal processing unit 25 corresponds. The column pixel signal S0 (_1 to _h; pixel number in one row) is processed to output a processed pixel signal S1 (_1 to _h; pixel number in one row). Various drive pulses CN3 for controlling analog signal processing are supplied from the communication / timing control unit 20 to the column processing unit 26.

  For example, the column signal processing unit 25 is provided with a function of noise removal means using CDS processing. The column signal processing unit 25 may be provided with an AGC (Auto Gain Control) circuit having a signal amplification function, other processing function circuits, or the like as required after the CDS processing function unit.

  When performing the CDS processing in the column signal processing unit 25, for example, based on two sample pulses such as the sample pulse SHP and the sample pulse SHD included in the drive pulse CN3 given from the communication / timing control unit 20, the vertical signal For the pixel information (pixel signal S0) in the voltage mode input via the line 19, the pixel level (reset level S0_rst) immediately after the pixel reset and the signal level S0_sig obtained by superimposing the true signal component V_sig on the reset level S0_rst By performing the process of taking the difference, a fixed pattern noise (FPN) due to fixed variation for each pixel and a noise signal component called reset noise are removed. Various mechanisms are known as a circuit configuration for performing the CDS process, and illustration and description of the configuration are omitted here.

  In the subsequent stage of the column signal processing unit 25, the column signal processing unit 25 is provided for each column that holds the pixel signal S <b> 1 read in the column direction from each unit pixel 3 of the pixel array unit 10 and processed by the column signal processing unit 25 of each column. A pixel signal holding unit including a plurality of storage capacitors 266 is provided. The other end of the storage capacitor 266 is connected to ground (GND) which is a reference potential. The storage capacitor 266 is also used as an input capacitor of a switched capacitor amplifier 320 described later. The pixel signal holding units in each column including the storage capacitors 266 are collectively referred to as a line memory 266C.

  The pixel signal S1 held in the storage capacitor 266, which is the output (pixel signal S1) of the column signal processing unit 25 in each column of the column processing unit 26, is a horizontal selection provided with a switch (for example, MOS transistor) 62 for horizontal reading. Input to the switch unit 60. The horizontal scanning unit 12, the horizontal signal line 18, the output circuit 28, and the horizontal selection switch unit 60 constitute a horizontal transfer unit.

  The output of each column signal processing unit 25 of the column processing unit 26 is output from the horizontal selection switch 62 for horizontal reading corresponding to each column for sequentially reading out the charges held in the storage capacitor 266 via the column output line 268. Are connected to each. A horizontal signal line 18 as a transmission line for sequentially transferring and outputting pixel signals in the row direction is commonly connected to the output end side of the horizontal selection switch unit 60. On the other hand, each control gate end of the horizontal selection switch unit 60 is constituted by a horizontal shift register, a decoder, or the like, and drives a horizontal address setting unit 12a that controls a horizontal read address and a horizontal selection switch 62 of the horizontal selection switch unit 60. It is connected to a horizontal scanning unit 12 having a horizontal driving unit 12b.

  The horizontal signal line 18 is an array of vertical signal lines 19 (column output lines 268) that is transmitted from the unit pixels 3 via the vertical signal lines 19 and processed by the column signal processing unit 25. The pixel signal selected by the horizontal selection switch 62 existing for each vertical column is extracted from the column signal processing unit 25 and output to the output circuit 28. hand over.

  That is, the voltage signal of each vertical column corresponding to the signal charge representing the pixel information processed by the column signal processing unit 25 is driven by the driving pulses φg1 to φgh corresponding to the horizontal selection signals φH1 to φHh from the horizontal scanning unit 12. The horizontal selection switch 62 provided for each vertical column is selected at a predetermined timing and read out to the horizontal signal line 18. Then, the signal is input to an output circuit 28 provided at the rear end of the horizontal signal line 18.

  The output circuit 28, which will be described in detail later, has a switched capacitor amplifier (SCA) circuit and a sample-and-hold (Sample & Hold) circuit, and includes two signal transfer states and a reset state. It operates by switching states and outputs signals for each operation state. Correspondingly, various drive pulses CN4 such as a pulse for switching between a signal transfer state and a reset state and a pulse for sampling a signal in the signal transfer state are supplied from the communication / timing control unit 20. Is done. The output circuit 28 amplifies the pixel signals S1_1 to _h of each unit pixel 3 output from the pixel array unit 10 through the horizontal signal line 18 with an appropriate gain (signal amplification factor) by a switched capacitor amplifier circuit, and then drives a drive pulse. Under the control of CN4, the image signal S3 is supplied to an external circuit via the output terminal 5c.

  For example, as shown in FIG. 1B, the output circuit 28 in the imaging chip is output from a switched capacitor amplifier 320 having a function of amplifying an input signal with an appropriate gain and the switched capacitor amplifier 320. And a sample hold unit 340 for extracting a necessary portion in the analog imaging signal S2. Note that an output buffer 360 is provided downstream of the sample hold unit 340 as necessary.

  The switched capacitor amplifier 320 is an example of an analog signal processing unit that operates a pixel signal generated in each unit pixel 3 of the pixel array unit 10. The sample hold unit 340 outputs an imaging signal for output based on the signal S2_sig in the signal transfer state and the signal S2_rst in the reset state in the imaging signal S2 output from the switched capacitor amplifier 320 which is an example of the analog signal processing unit. It is an example of the output signal generation part which produces | generates S3. When an output buffer is provided after the sample hold unit 340, it can be considered that the output signal generation unit is configured by the sample hold unit 340 and the output buffer.

  The sample hold unit 340 operates while the switched capacitor amplifier 320 alternately repeats the signal transfer state and the reset state in order to read the signal S2_sig in the signal transfer state after resetting the horizontal signal line 18 to the reference level for each vertical column. As shown in the figure, it has a sample switch 340SW and a hold capacitor (capacitance element) 340C, which are actually necessary as an image. It has a function to extract a signal in a simple signal transfer state.

  The sample hold unit 340 of the present embodiment is characterized in that it includes two systems of sample switches 340SW and hold capacitors 340C. Preferably, each of the two systems is characterized by including a two-stage sample and hold circuit. Details of these points will be described later.

  The elements of the drive control unit 7 such as the horizontal scanning unit 12 and the vertical scanning unit 14 are formed integrally with the pixel array unit 10 in a semiconductor region such as single crystal silicon using a technique similar to the semiconductor integrated circuit manufacturing technique. As a so-called one-chip (provided on the same semiconductor substrate), a CMOS image sensor which is an example of a semiconductor system is configured to form part of the solid-state imaging device 1 of the present embodiment. .

  The external circuit provided in the subsequent stage of the output circuit 28 is on a substrate (printed substrate or semiconductor substrate) different from the solid-state imaging device in which the pixel array unit 10 and the drive control unit 7 are integrally formed in the same semiconductor region. The circuit configuration corresponding to each photographing mode is adopted.

  Although not shown, a functional unit (AD (Analog to Digital) conversion unit) that converts the analog imaging signal S3 output from the output circuit 28 into digital imaging data is provided outside the imaging chip, which is a subsequent stage of the output circuit 28. ) And a functional unit (digital signal processing unit) that performs digital signal processing based on digitized imaging data.

  The digital signal processing unit has a function of a digital amplifier unit that appropriately amplifies and outputs digital data output from the AD conversion unit, for example. Further, for example, color separation processing is performed to generate image data RGB representing each image of R (red), G (green), and B (blue), and other signal processing is performed on the image data RGB for monitoring. Output image data D3 is generated. Further, the digital signal processing unit is provided with a functional unit that performs signal compression processing for storing imaging data in a recording medium.

  The external circuit includes a DA (Digital to Analog) conversion unit that converts image data digitally processed by the digital signal processing unit into an analog image signal. The image signal output from the DA converter is sent to a display device such as a liquid crystal monitor. The operator can perform various operations such as switching the imaging mode while viewing the menu and images displayed on the display device.

  That is, in the column type solid-state imaging device 1 of the present embodiment, the output signal (voltage signal) from the unit pixel 3 is the vertical signal line 19 → column processing unit 26 (column signal processing unit 25) → horizontal signal line 18. → Transmission is performed in the order of the output circuit 28. The drive is such that the pixel output signals for one row are sent in parallel to the column processing unit 26 via the vertical signal line 19, and the processed signals are serially output via the horizontal signal line 18.

  As long as driving for each vertical column or horizontal column is possible, each pulse signal is supplied to the unit pixel 3 from either the horizontal direction or the vertical column direction, that is, driving for applying a pulse signal. The physical wiring method of the clock line is free.

  In the solid-state imaging device 1 having such a configuration, the horizontal scanning unit 12 and the vertical scanning unit 14 and the communication / timing control unit 20 that controls them are used to sequentially select each pixel of the pixel array unit 10 in the horizontal unit. A CMOS image sensor of a type that simultaneously reads out the information of the selected one horizontal parallel pixel is configured.

  Here, an example in which the external circuit in charge of signal processing in the subsequent stage of the solid-state imaging device is performed outside the solid-state imaging device (imaging chip) is shown, but all or a part of the external circuit (for example, an A / D conversion unit or digital) A functional element such as an amplifier unit may be built in a chip of the solid-state imaging device.

  Further, it is not a requirement that the entire horizontal selection switch unit 60 and the drive control unit 7 or the one functional part be integrally formed in the same semiconductor region as the pixel array unit 10. The horizontal selection switch unit 60 and the drive control unit 7 are formed on a circuit board different from the pixel array unit 10 (which means not only another semiconductor substrate but also a general circuit board), for example, a circuit board on which an external circuit is provided. May be.

  Note that the solid-state imaging device 1 may be configured as one chip in which each unit is integrally formed in the semiconductor region as described above. Although not illustrated, the pixel array unit 10 and the drive control unit are omitted. 7. In addition to various signal processing units such as the column processing unit 26, an imaging function in which these are collectively packaged in a state including an optical system such as a photographing lens, an optical low-pass filter, or an infrared light cut filter It is good also as a modular form which has.

<Detailed Configuration of Output Circuit: First Configuration Example and Comparative Example>
FIG. 2 is a block diagram illustrating a first configuration example of this embodiment of the output circuit 28. FIG. 3 is a block diagram illustrating a configuration example of a general output circuit when the configuration of the present embodiment is not taken as a comparative example.

  2 and 3, the switched capacitor amplifier (CSA) 320 includes a differential amplifier 322 composed of an operational amplifier (op amp) and the like, an inverting input terminal (−) and an output terminal of the differential amplifier 322. And a feedback switch 324 having a capacitance value Cfb connected between and a reset switch (for example, a MOS transistor) 326, and as a whole, a capacitive feedback type amplification by a combination with an input capacitor connected to the input side It is configured to function as a circuit. The amplifier gain (amplification factor) Gamp is determined by the capacitance value Cin of the input capacitor and the capacitance value Cfb of the feedback capacitor 324, and Gamp = Cin / Cfb. Any capacitance component connected to the inverting input terminal (−) of the feedback capacitor 324 can be an input capacitor, and the switched capacitor amplifier 320 exhibits various characteristics depending on the type. This point will be described later.

  The horizontal signal line 18 connected to the output side of the horizontal selection switch 62 of the horizontal selection switch unit 60 is connected to the inverting input terminal (−) of the differential amplifier 322 constituting the switched capacitor amplifier 320. A reference voltage Vref is supplied to the non-inverting input terminal (+) of the differential amplifier 322.

  A pixel signal S0 (Signal Input) detected by the pixel array unit 10 (not shown) is stored in the photoelectric conversion element in each unit pixel 3 in the signal output row by the CDS function unit of the column signal processing unit 25. For example, the difference between the signal level S0_sig corresponding to the electron) and the reset level S0_rst after resetting the photoelectric conversion element is taken, the fixed variation is removed, and the difference is supplied to the storage capacitor 266 having the capacitance value C1. Once held. Up to this point is vertical transfer.

  When the vertical transfer is completed, the horizontal transfer is subsequently performed. For example, first, in order to sequentially select the storage capacitors 266 as line memories by the horizontal scanning unit 12, the horizontal selection switches 62 of the horizontal selection switch unit 60 are sequentially turned on / off, and the common signal lines for a plurality of vertical columns are used. The pixel signal S 1 held in the storage capacitor 266 on a certain horizontal signal line 18 is read out to the horizontal signal line 18. As a result, the potential of the horizontal signal line 18 changes. The signal potential on the horizontal signal line 18 is amplified by the switched capacitor amplifier 320 constituting the capacitive feedback type amplifier circuit and then output to the sample hold unit 340.

  The amplifier gain (signal amplification factor) Gamp0 for the pixel signal at that time is the capacitance value C1 of the storage capacitor 266 or the feedback capacitor 324 where the capacitance value Cp of the parasitic capacitance 18C attached (parasitic) to the horizontal signal line 18 is a hold capacitance. If the capacitance value Cfb is sufficiently smaller than the capacitance value Cfb, only the storage capacitor 266 may be considered as the input capacitance Cin. The capacitance value C1 of the storage capacitor 266 and the capacitance value Cfb of the feedback capacitor 324 of the switched capacitor amplifier 320 Gamp0 = C1 / Cfb.

  At this time, a plurality of configurations of the feedback capacitors 324 are arranged in parallel, and various measures such as switching them with a switch are adopted, and the capacitance value of the feedback capacitor 324 is configured to be variable, so that the setting of the amplifier gain Gamp0 is variable. Amplification can be performed with an appropriate gain setting according to the signal amount. The imaging signal S2 amplified by the switched capacitor amplifier 320 is output by the sample hold unit 340 while holding each information.

  When the pixel signal S1 is continuously read, the parasitic capacitance Cp and the feedback capacitor 324 of the horizontal signal line 18 are reset with the reference voltage Vref in order to make the reference voltage of each pixel signal S1 the same. An initialization switch 326 is used for this reset. Further, since the switched capacitor amplifier 320 constituting the capacitive feedback amplifier circuit maintains the signal output (reset signal S2_rst) in the subsequent stage even during the reset operation, the sample hold unit is disposed in the subsequent stage of the switched capacitor amplifier 320. 340 and a signal adder 360 in the subsequent stage of the sample hold unit 340.

  The sample hold unit 340 includes two systems of sample hold circuits 340a and 230b. The signal adder 360 adds the signal S3_sig in the signal transfer state and the signal S3_rst in the reset state output from the analog amplifiers 346a2 and 346b2 in the subsequent stages. The signal addition unit 360 functions as a difference information acquisition unit that acquires a difference result between the pixel information acquired by the sample hold circuit 340a and the reference information acquired by the sample hold circuit 340b. The differential processing is performed in which the signal S3_sig and the signal S3_rst in the reset state are differentially added.

  Here, when the signal adder 360 differentially adds the signal S3_sig in the signal transfer state and the signal S3_rst in the reset state, the signal S3_sig and the signal S3_rst respectively input from the sample hold circuits 340a and 340b are the same. When it is a sign, the signal adding unit 360 itself inverts the sign in advance with respect to one of the signals S3_sig and S3_rst, and then performs addition processing. On the other hand, when the signal S3_sig and the signal S3_rst respectively input from the sample hold circuits 340a and 340b have different signs, the signal adder 360 only needs to add the input signals S3_sig and S3_rst as they are. In the present embodiment, the latter mode in which the signals S3_sig and S3_rst are different signs is adopted.

  The sample hold circuit 340a extracts and holds the signal S2_sig in the signal transfer state in the imaging signal S2, and adjusts the output time at an appropriate signal output speed (data rate). On the other hand, the sample hold circuit 340b extracts and holds the reset state signal S2_rst in the imaging signal S2 in parallel (synchronization) with the operation of the sample hold circuit 340a, and outputs it in accordance with the signal output of the sample hold circuit 340a. Is.

  Specifically, the switched capacitor amplifier 320 operates by switching between two states of a signal transfer state and a reset state in accordance with a reset pulse RST included in the drive pulse CN4 from the communication / timing control unit 20 (not shown). . Specifically, the switched capacitor amplifier 320 resets the switched capacitor amplifier 320 during the active period of the reset pulse RST, and the control output corresponding to the read column during the inactive period (the drive pulse φgk corresponding to the horizontal selection signal φHk). ) Is activated, the pixel signal S1 of the readout column is extracted, and the imaging signal S2 is acquired as a whole.

  Here, in the present embodiment, the sample hold unit 340 is provided in the subsequent stage of the switched capacitor amplifier 320. The sample hold unit 340 has two sample hold circuits (sample hold circuits 340a and 340b) having the same configuration on the circuit diagram, and each system has two stages of sample hold circuits (sample hold circuit 340a1). , 340a2, 340b1, 340b2).

  The sample-and-hold circuit 340a is for original pixel information extraction, and is an example of a signal transfer information acquisition unit that extracts and holds the signal level at the time of pixel signal transfer output from the switched capacitor amplifier 320. In the sample hold circuit 340a1 in the previous stage, among the signal levels output from the switched capacitor amplifier 320, when the initialization switch 326 is off and the horizontal scanning unit 12 controls the horizontal selection switch 62, any one of the storage capacitors A signal transfer state in which the pixel signal held in the storage capacitor 266 as the input capacitor is amplified by the switched capacitor amplifier 320 and output based on the sample pulse Spa1 that becomes an active level in accordance with the timing when the H.266 is selected. It is an example of the signal transmission information acquisition part of the front | former stage which acquires and hold | maintains this pixel information report. The post-stage sample hold circuit 340a2 is an example of a post-stage signal transfer information acquisition unit that acquires and holds the pixel information held in the pre-stage sample hold circuit 340a1 based on the sample pulse SPa2 that becomes an active level at a predetermined timing. is there.

  The sample-and-hold circuit 340b is an example of a reference information acquisition unit that extracts and holds a noise component generated in the switched capacitor amplifier 320 that constitutes the capacitive feedback type amplifier circuit. The sample-and-hold circuit 340b1 in the previous stage is activated in accordance with the timing after the initialization when the initialization switch 326 is turned on until the horizontal selection switch 62 selects any storage capacitor 266 under the control of the horizontal scanning unit 12. Based on the level sample pulse SPb1, the noise component generated when the initialization switch 326 is turned on and held in the parasitic capacitor 18C attached to the horizontal signal line 18 is amplified by the switched capacitor amplifier 320 to obtain reference information output. It is an example of the reference | standard information acquisition part of the front | former stage held in the. The latter-stage sample hold circuit 340b2 is an example of a later-stage reference information acquisition unit that acquires and holds the reference information held in the previous-stage sample hold circuit 340b1 based on the sample pulse SPb2 that becomes an active level at a predetermined timing. .

  Each sample hold circuit 340a1, 340a2, 340b1, 340b2 includes a sample switch 342 (342a1, 342a2, 342b1, 342b2), a hold capacitor 344 (344a1, 344a2, 344b1, 344b2), and a single-ended analog amplifier 346 (346a1, 346a1, 342b1). 346a2, 346b1, 346b2). The analog amplifiers 346a1, 346a2, and 346b1 are non-inverting types, whereas the analog amplifier 346b2 is an inverting type. Therefore, the signal addition unit 360, which is an example of the difference information acquisition unit, effectively functions as a subtraction circuit that outputs the signal “S3_sig−S3_rst” as the imaging signal S3.

  As described above, the sample hold unit 340 includes a switched capacitor amplifier 320 that constitutes a capacitive feedback type amplifier circuit in a separate system from the original pixel information extraction sample hold circuit 340a as a configuration unique to the present embodiment. A sample hold circuit 340b for extracting and holding the generated noise component separately from the signal S2_sig in the signal transfer state is provided. As described above, the circuit configuration is the same as that of the sample hold circuit 340a.

  The capacitance value of the hold capacitor 344a1 provided in the previous sample hold circuit 340a1 for pixel information extraction is Csha1, the capacitance value of the hold capacitor 344a2 provided in the subsequent sample hold circuit 340a2 is Csha2, and the reference information extraction (actual noise) The capacitance value of the hold capacitor 344b1 provided in the sample hold circuit 340b1 in the preceding stage of the sample hold circuit 340b (for extraction) is Cshb1, and the capacitance value of the hold capacitor 344b2 provided in the sample hold circuit 340b2 in the subsequent stage is Cshb2. These capacitance values Csha1, Csha2, Cshb1, and Cshb2 are set optimally according to the circuit configuration of each output buffer 346 in the subsequent stage, and it cannot be determined whether the capacitance is generally small or large.

  The sample and hold circuit 340a for extracting pixel information is an example of a signal extraction unit that extracts the signal S2_sig in the signal transfer state from the pixel signal S2 output from the switched capacitor amplifier 320. The sample and hold circuit 340a for extracting pixel information is switched to read the signal S2_sig in the signal transfer state after resetting the horizontal signal line 18 to the reference level for each column output line 268 (effectively the vertical signal line 19). The capacitor amplifier 320 has two states, ie, a signal transfer state and a reset state, and is provided corresponding to the operation that switches between these two states according to the control of the reset pulse RST.

  The sample switch 342a1 in the previous stage (first stage) is a horizontal drive that is a timing pulse for switching between two states of the sampling period and the hold period, which is included in the drive pulse CN4 from the communication / timing control unit 20 (not shown). A sample pulse Spa1 having the same frequency as the frequency (switching frequency of each horizontal selection signal φH) and synchronized is input, and an on / off operation is performed based on the sample pulse Spa1, thereby allowing a sampling period and a hold period. Switch to operate. Specifically, the sample switch 342a1 samples only the signal S2_sig in the signal transfer state that is actually required as an image of the imaging signal S2 into the hold capacitor 344a1 when the sample pulse SPA1 is at the active level, and holds the hold capacitor 344a1. Store in 344a1. The stored signal S2_sig in the signal transfer state is supplied to the analog amplifier 346a1.

  The latter-stage (second stage) sample switch 342a2 is a horizontal drive that is a timing pulse for switching between two states of the sampling period and the hold period, which is included in the drive pulse CN4 from the communication / timing control unit 20 (not shown). A sample pulse SPA2 having the same frequency as the frequency and synchronized is input, and the on / off operation is performed based on the sample pulse Spa2, thereby switching between the sampling period and the hold period. Specifically, the sample switch 342a2 is a signal transfer state sampled by the previous sample hold circuit 340a1 held in the hold capacitor 344a1 output from the analog amplifier 346a1 when the sample pulse SPA2 is at the active level. The signal S2_sig is sampled in the hold capacitor 344a2 and stored as the signal S3_sig in the hold capacitor 344a2. The stored signal transfer state signal S3_sig is supplied to the analog amplifier 346a2. The analog amplifier 346a2 supplies the signal S3_sig in the signal transfer state held in the hold capacitor 344a2 to the signal adder 360 without being inverted (as positive information). The basic configuration and operation are the same as those of the sample-and-hold circuit 340a1 in the previous stage, but the timing of the active level of the sample pulse SPA2 is different from the timing of the active level of the sample pulse SPA1.

  A sample switch 342b1 provided in the previous sample hold circuit 340b1 for extracting reference information switches between two states of a sampling period and a hold period included in a drive pulse CN4 from a communication / timing control unit 20 (not shown). The sampling pulse SPb1, which is the same frequency as the horizontal drive frequency, which is the timing pulse for synchronization, is input, and the sampling period and hold period are switched by turning on / off based on the sample pulse SPb1. Works. The sample hold circuit 340b1 in the previous stage has a function as a signal extraction unit that extracts the reference level (= Vref) of the horizontal signal line 18 output immediately after the switched capacitor amplifier 320 is reset. Specifically, the sample switch 342b1 determines that the sample pulse SPb1 is active level (H level) until the reset pulse RST becomes inactive level (L level) and the sample pulse SPa1 becomes active level (H level). At this time, by sampling only the reset state signal S2_rst output from the switched capacitor amplifier 320, the reference level (= Vref) of the horizontal signal line 18 is extracted, sampled by the hold capacitor 344b1, and held capacitor 344b1 To remember. The stored reset state signal S2_rst is supplied to the analog amplifier 346b1.

  The latter sample hold circuit 340b1 has the same frequency as the horizontal drive frequency, which is a timing pulse for switching between two states of the sampling period and the hold period, which is included in the drive pulse CN4 from the communication / timing control unit 20 (not shown). In addition, a synchronized sample pulse SPb2 is input, and an on / off operation is performed based on the sample pulse SPb2, thereby switching between a sampling period and a hold period. Specifically, the sample switch 342b2 is in the reset state sampled by the previous sample hold circuit 340b1 held in the hold capacitor 344b1 output from the analog amplifier 346b1 when the sample pulse SPb2 is at the active level. The signal S2_rst is sampled in the hold capacitor 344b2, and stored in the hold capacitor 344b2 as the signal S3_rst. The stored reset state signal S3_rst is supplied to the analog amplifier 346b2. The analog amplifier 346b2 inverts the reset signal S3_rst held in the hold capacitor 344b2 (as negative information) and supplies it to the signal adder 360. The basic configuration and operation are the same as those of the sample-and-hold circuit 340b1 in the previous stage, but the timing of the active level of the sample pulse SPb2 is different from the timing of the active level of the sample pulse SPb1.

  In the present embodiment, the two paths of the sample and hold unit 340 are divided into a front stage, a rear stage, and two sample and hold circuits, respectively, so that sampling can be performed at different timings in the front stage and the rear stage, so that the signal S2_sig2 in the signal transfer state and The reset noise transmission timing included in the reset state signal S2_rst2 can be adjusted and output.

  In particular, in the first configuration example, the sampling timings are aligned in the subsequent stages of the two paths, that is, the reference information acquisition timing and the subsequent signal transfer information acquisition unit in the subsequent sample hold circuit 340b2 as the subsequent reference information acquisition unit. By matching the pixel information acquisition timing in the subsequent sample hold circuit 340a2 (more specifically, sampling at the same time), reset noise included in the signal S3_sig in the signal transfer state and the signal S3_rst in the reset state ( The transmission timing of information of the thermal noise Vnrst0) is matched.

  On the other hand, the output circuit 28 of the comparative example shown in FIG. 3 includes only the sample hold circuit 340 for extracting pixel information as the sample hold unit 340 but does not include the sample hold circuit for extracting reference information. The sample hold circuit 340 has a one-stage configuration.

  The output circuit 28 of the present embodiment divides the sample and hold unit 340 into two systems for pixel information extraction and reference information extraction, and is the same for both the signal transfer state signal S2_sig in the signal transfer state and the reset signal S2_rst. Signal extraction is performed on the processed imaging signal S2 output from the signal processing unit (switched capacitor amplifier 320 in this example). Thereby, a noise component (for example, thermal noise component) generated in the switched capacitor amplifier 320 is included in the two systems of signals in the same manner. The noise component is included in both signals in the same way, and the output signal is generated by taking the difference between them, so that the output signal (in this example, the imaging signal S3) does not contain the noise component. become. The processing is similar to the CDS processing, and the noise component generated in the switched capacitor amplifier 320 can be suppressed more than in the comparative example. Hereinafter, the difference between the operations will be described in detail.

<Detailed Operation of Output Circuit: First Configuration Example and Comparative Example>
FIG. 4 is a timing chart for explaining the operation of the output circuit 28 of the comparative example shown in FIG. FIG. 5 is a timing chart for explaining the operation of the output circuit 28 of the first configuration example of the present embodiment shown in FIG.

  For comparison with the characteristics of the operation of the output circuit 28 of the first configuration example of the present embodiment shown in FIG. 2, first, a horizontal transfer method of the output circuit 28 of the comparative example shown in FIG. 3 will be described with reference to FIG. explain.

  The signal processing for one unit pixel 3 is completed in an amplifier reset period t10 to t14 that is a period for reading the reset state signal S2_rst and a data transfer period t20 to t28 that is a period for reading the signal S2_sig in the signal transfer state. In the description and drawings, the unit pixel 3 to be processed is distinguished from each other as necessary by using a number “@@” of the unit pixel 3 at each timing and adding a “_ @” reference.

<Operation of Comparative Example>
In the output circuit 28 of the comparative example shown in FIG. 4, when the switched capacitor amplifier 320 of the @th unit pixel 3 (first pixel in the figure) is reset, the horizontal selection signal φH is set to inactive L and the horizontal The horizontal selection switch 62 for transfer is turned off, the reset pulse RST is set to active H with the sample pulse SP set to inactive L and the sample switch 342 of the sample hold unit 340 for pixel information extraction turned off. The unpreset initialization switch 326 is turned on (t10_ @ to t14_ @). At this time, the potential across the feedback capacitor 324 becomes the potential of the reference voltage Vref, and the charge accumulated in the feedback capacitor 324 is initialized to zero. As a result, when the input offset voltage of the differential amplifier 322 is ignored, the output potential of the switched capacitor amplifier 320 becomes equal to the reference voltage Vref.

  On the other hand, at the time of pixel signal transfer, with the reset pulse RST set to inactive L and the amplifier reset initialization switch 326 turned off, the horizontal selection signal φH is set to active H to turn on the horizontal selection switch 62 for horizontal transfer. (T20_ @ to t28_ @), and the sample pulse SP is set to active H within the active H period (t20_ @ to t28_ @) of the horizontal selection signal φH, and the sample switch 342a of the sample hold unit 340 for extracting pixel information Is turned on (t22_ @ to t26_ @).

  The output circuit 28 repeats such an operation for each unit pixel 3 in the same row, that is, as shown in FIG. 4, the signal transfer state and the reset state are changed according to the control of the horizontal selection signal φH and the reset pulse RST. The imaging signal S3 is acquired by operating while repeating alternately.

  As can be seen from the above description, in the output circuit 28, the switched capacitor amplifier 320 is inactivated by the reset pulse RST after the reset pulse RST resets the switched capacitor amplifier 320 during the active period (t10_ @ to t14_ @). During the period (t14_ @ to t10 _ @ + 1), the horizontal scanning unit 12 sets the control output (horizontal transfer clock φHk / φgk) corresponding to the read column to active H (t20_ @ to t28_ @), so that the switched capacitor The amplifier 320 takes out the pixel signal of the readout column and acquires the imaging signal S2 as a whole.

  At this time, since the differential amplifier 322 receives negative feedback through the feedback capacitor 324, the inverting input terminal becomes the potential of the reference voltage Vref. As a result, the pixel signal voltage V1_ @ of the target pixel corresponding to the amount of charge in the storage capacitor 266 (which reflects the pixel signal S1) fluctuates to C1 · (V1 _ @ − Vref), and this fluctuating charge C1 · (V1_ @ -Vref) is sampled and held in the feedback capacitor 324. At this time, the pixel signal voltage V2_ @ of the target pixel in the imaging signal S2_sig that is the output of the differential amplifier 322 is C1 / Cfb * (Vref−V1_ @). In effect, the sign is inverted because the capacitive feedback amplifier circuit composed of the switched capacitor amplifier 320 or the like functions as an inverted amplifier circuit.

  Here, since only the signal transfer state is actually required as an image, a sample hold unit 340 is provided at the subsequent stage of the switched capacitor amplifier 320 as shown in FIG. Then, as shown in FIG. 4, in the sample hold unit 340, only the signal S2_sig in the signal transfer state in the imaging signal S2 is taken out in the active period (t20_ @ to t28_ @) of the sample pulse SP, and this is taken as an analog amplifier It outputs as an imaging signal S3 via 346.

  Here, as a problem in the output circuit 28 of the comparative example shown in FIG. 3, the thermal noise of the switched capacitor amplifier 320 generated when the switched capacitor amplifier 320 is reset (when the initialization switch 326 is turned on) ( Vnrst0) is amplified by a capacitance feedback type amplifier circuit composed of a switched capacitor amplifier 320 or the like and is superimposed on the original pixel signal voltage V2_ @ at the time of reset release when the initialization switch 326 is turned off. It is to be output as an imaging signal S3.

  That is, the thermal noise Vnrst0 generated when the switched capacitor amplifier 320 is reset is once held in the parasitic capacitance 18C having the capacitance value Cp incidental (parasitic) to the horizontal signal line 18. The parasitic capacitance 18C also functions as an input capacitance connected to the input side of the switched capacitor amplifier 320. Therefore, when transferring the pixel signal component after reset, the pixel signal S1 held in the storage capacitor 266 is not only amplified and output with the amplifier gain (signal amplification factor) Gamp0 = C1 / Cfb, but also the parasitic capacitance 18C. Is amplified by a gain (noise amplification factor) Gamp1 = Cp / Cfb expressed by the ratio of each capacitance value of the parasitic capacitance 18C and the feedback capacitance 324 and is output (referred to as output after folding). It will be. The thermal noise after the gain Gamp1 = Cp / Cfb multiplied and turned back is assumed to be thermal noise Vnrst1 (= Cp / Cfb * (Vref−Vnrst0); signal voltage is V4_ @). Since “S2_sig + Vnrst1: As a signal voltage, V3 _ @ = V2 _ @ + V4_ @” is held in the hold capacitor 344 of the sample hold unit 340, the S / N of the imaging signal S3 output from the analog amplifier 346 is deteriorated.

  As a technique for solving such a problem of thermal noise, the capacitance value Cp of the parasitic capacitance 18C parasitic on the horizontal signal line 18 is made sufficiently smaller than the capacitance value Cfb of the feedback capacitance 324, in other words, feedback. It is conceivable to increase the capacitance value of the capacitor 324. This is because if the capacitance value Cp is sufficiently smaller than the capacitance value Cfb, the thermal noise Vnrst1 becomes smaller than the signal S2_sig in the signal transfer state, so there is no problem. However, in the present day when a large number of pixels and high resolution are required, it is very important to reduce the junction capacitance of the transistor for the horizontal selection switch 62 connected to the horizontal signal line 18 and the wiring capacitance of the horizontal signal line 18 itself. It is difficult, and occupies a large proportion as a factor that deteriorates the S / N (Signal (to) Noise ratio). For example, in a CMOS sensor mounted on a digital video camera, since the pixel cell size is narrowed for increasing the number of pixels and the resolution, an improvement in S / N at low illuminance is a major issue.

  Under such circumstances, noise (heat) caused by the above-described problem in the output circuit 28 of the comparative example shown in FIG. 3, that is, the reset of the capacitive feedback type amplifier circuit accumulated in the parasitic capacitance 18C of the horizontal signal line 18 is obtained. The noise (Vnrst0) is multiplied by the gain (Cp / Cfb) at the time of pixel signal transfer and turned back, and is added to the signal S2_sig in the signal transfer state. This is where it is desired.

<Operation of First Configuration Example>
Therefore, in the output circuit 28 of the present embodiment, the sample hold circuit 340b is provided in a system different from the original sample hold circuit 340a for extracting pixel information, and the switched capacitor amplifier 320 constituting the capacitance feedback type amplifier circuit is used. The generated noise component is extracted and held from the reference voltage Vref separately from the signal S2_sig in the signal transfer state by the sample hold circuit 340b, and the noise component included in the signal output from the sample hold circuit 340a is also included. By removing by the difference processing, the thermal noise of the switched capacitor amplifier 320 is reduced and the S / N is improved.

  Specifically, as shown in FIG. 5, when the switched capacitor amplifier 320 of the @th unit pixel 3 (first pixel in the figure) is reset, first, the horizontal selection signal φH is set to inactive L. In this state, the horizontal selection switch 62 for horizontal transfer is turned off, the sample pulses Spa1 and SPb1 are set to inactive L, and the sample switches 342a1 and 342b1 of the previous sample hold circuits 340a1 and 340b1 are turned off. Is activated H to turn on the initialization switch 326 for resetting the amplifier (t10_ @ to t14_ @). At this time, the potential across the feedback capacitor 324 becomes the potential of the reference voltage Vref, and the charge accumulated in the feedback capacitor 324 is initialized to zero. The thermal noise Vnrst0 generated at this time is held in the parasitic capacitance 18C of the horizontal signal line 18.

  At this time, in the sample hold circuit 340a for extracting pixel information, the sample pulse SPA2 is set to active H during the inactive L period (t26 _ @-1 to t22_ @) of the sample pulse Spa1, and the sample hold circuit 340a2 in the subsequent stage is set. By turning on the sample switch 342a2, information held in the hold capacitor 344a1 of the previous sample hold circuit 340a1 is taken in and held in the hold capacitor 344a2 (t11_ @ to t16_ @). In this example, t10_ @ ≈t11_ @.

  In the sample hold circuit 340b for extracting the reference information, the active H period (t10_ @ to t14_ @) of the sample pulse SPb1 is preferably used within the inactive L period (t18 _ @-1 to t15_ @) of the sample pulse Spa1. ), The sample pulse SPb2 is set to active H and the sample switch 342b2 of the subsequent sample hold circuit 340b2 is turned on to hold the information previously held in the hold capacitor 344b1 of the previous sample hold circuit 340b1. Capturing and holding in the capacitor 344b2 (t12_ @ to t13_ @). In this example, t10_ @ ≈t11_ @ ≈t12_ @.

  Next, the interval between the active H period of the reset pulse RST and the active H period of the horizontal selection signal φH (t14_ @) in order to capture the information of the thermal noise Vnrst0 held in the parasitic capacitor 18C by the sample hold circuit 340b for extracting the reference information. At ~ t20_ @), the sample pulse SPb1 is set to active H to turn on the sample switch 342b1 of the previous sample hold circuit 340b1 (t15_ @ to t18_ @). As a result, information S2_rst (= Cp / Cfb * (Vref−Vnrst0); signal voltage V4_ @) is a hold capacitor including the thermal noise Vnrst1 obtained by multiplying the thermal noise Vnrst0 held in the parasitic capacitor 18C by a gain Cp / Cfb. 344b1 is taken in and held.

  At the time of signal transfer after sampling of the reset noise (thermal noise Vnrst1) is completed, the reset pulse RST is set to inactive L and the initialization switch 326 for resetting the amplifier is turned off, and the sample pulses Spa2, SPb1,. With SPb2 inactive L and the sample switches 342a2, 342a2, 342b2 turned off, the horizontal selection signal φH is made active H to turn on the horizontal selection switch 62 for horizontal transfer (t20_ @ to t28_ @). Within the active H period (t20_ @ to t28_ @) of the horizontal selection signal φH, the sample pulse Spa1 is set to active H to turn on the sample switch 342a1 of the sample hold unit 340a1 for pixel information extraction (t22_ @ to t26_). @).

  As a result, the information of the thermal noise Vnrst0 is also transferred simultaneously with the pixel signal S1 and is held in the sample switch 342a1. That is, the pixel signal S2_sig including information obtained by multiplying the pixel signal S1 (the pixel signal voltage V1_ @ thereof) by the gain C1 _ @ / Cfb, which is the output of the switched capacitor amplifier 320, is captured and held in the hold capacitor 344a1. At this time, the imaging signal S2_sig including the true signal component V2_ @ (= C1 _ @ / Cfb * (Vref−V1_ @)) obtained by multiplying the pixel signal voltage V1_ @ by the gain (C1 _ @ / Cfb) and the parasitic capacitance 18C are held. The hold capacitor 344a1 holds a signal voltage V3_ @ which is a composite component with the signal voltage V4_ @ of the thermal noise Vnrst1 (= Cp / Cfb * (Vref−Vnrst0)) obtained by multiplying the thermal noise Vnrst0 being gain Cp / Cfb.

  Thereafter, the sample hold circuit 340a for extracting pixel information and the amplifier reset timing (t10 _ @ + 1 to t14 _ @ + 1) of the next “@ + 1” -th unit pixel 3 (second pixel in the figure) The voltages V3_ @ and V4_ @ held in the hold capacitors 344a1 and 340b1 of the preceding sample and hold circuits 340a1 and 340b1 of the sample and hold circuit 340b for extracting the reference information are sampled through the analog amplifiers 346a1 and 346b1, respectively. The signals are transmitted almost simultaneously (in parallel) to the hold capacitors 344a2 and 340b2 of the hold circuits 340a2 and 340b2, and are held as the corresponding imaging signals S3_sig and S3_rst, respectively (t11 _ @ + 1 to t16 _ @ + 1, t12 _ @ + 1 to t13 _ @ + 1). By setting t11_ @ ≈t12_ @, it is possible to match the sampling timing of the signal components to the subsequent sample hold circuits 340a2 and 340b2 with the thermal noise.

  Information on pixel signal extraction held in the hold capacitor 344a2 (composite component of the pixel signal voltage V2_ @ and voltage V4_ @ reflecting the thermal noise Vnrst1 = voltage V3_ @), and information on reset noise held in the hold capacitor 344b2 (The voltage V4_ @ reflecting the thermal noise Vnrst1) is immediately supplied to the signal adding unit 360 via the analog amplifiers 346a2 and 346b2, respectively. At this time, the analog amplifier 346a2 supplies the signal V360 as the voltage V5_ @ without inverting the sign of the voltage V3_ @ (= V2 _ @ + V4_ @), while the analog amplifier 346b2 supplies the reset noise information (voltage V4_ @ ) Is inverted and supplied to the signal adder 360 as the voltage V6_ @.

  The signal adding unit 360 is supplied from the analog amplifier 346a2 and the pixel signal extraction information (the combined component of the pixel signal voltage V2_ @ and the voltage V4_ @ reflecting the thermal noise Vnrst1 = V5_ @) and the analog amplifier 346b2. Addition processing (actual difference processing) according to “V5 _ @ + V6 _ @ = (V2 _ @ + V4 _ @) − V4_ @)” with the negative information (V6 _ @ = − V4_ @) of thermal noise Vnrst1 Output as imaging signal S3. As a result, in the imaging signal S3, the information (= V4_ @) of the thermal noise Vnrst1 is canceled while maintaining the voltage amplitude (= V2_ @) of the pixel signal, so that the imaging signal S3 having a high S / N is signaled. Output from the adder 360. In other words, the signal processing unit connected to the subsequent stage of the signal adding unit 360 is not affected by the reset noise generated in the switched capacitor amplifier 320 constituting the capacitance feedback type amplifier circuit.

  The output circuit 28 repeats such an operation for each unit pixel 3 in the same row, that is, as shown in FIG. 5, the signal transfer state and the reset state are changed according to the control of the horizontal selection signal φH and the reset pulse RST. By operating while repeating alternately, one row of pixel signals can be transferred continuously, and horizontal transfer of pixel signals for 1H is completed.

  Thus, in the output circuit 28 of the first configuration example of the present embodiment, the signal component (the pixel signal voltage V2 of the signal S2_sig in the signal transfer state) in the imaging signal S2 that is the output of the switched capacitor amplifier 320 is sampled. The signal is extracted by the hold circuit 340a and supplied to one input terminal of the signal adder 360. The reference voltage Vref out of the output of the same switched capacitor amplifier 320 is extracted by the sample hold circuit 340b and the other of the signal adder 360 is extracted. Supplied to the input terminal.

  As a result, the subsequent signal processing is not affected by the reset noise generated in the switched capacitor amplifier 320 constituting the capacitive feedback amplifier circuit. Reset noise (thermal noise) generated by the switched capacitor amplifier 320 is held by a sample hold circuit 340b prepared separately from the signal transfer sample hold circuit 340a, and the signal adder 360 cancels the reset noise differentially. By adopting such a driving method, the influence of reset noise is suppressed and the S / N is improved. High S / N can be realized by reducing thermal noise generated at the time of resetting by a capacitive feedback amplifier circuit without impairing the signal amplitude transmitted from the unit pixel 3 of the pixel array unit 10.

  Further, as an additional effect, in order to reduce thermal noise in the case of the output circuit 28 of the comparative example shown in FIG. 3, the capacitance value of the feedback capacitor 324 used in the capacitive feedback type amplifier circuit must be increased. However, in the output circuit 28 of the first configuration example of the present embodiment shown in FIG. 2, the thermal noise in the image pickup signal S3 can be reduced without increasing the capacitance value of the feedback capacitor 324, so that the layout area can be reduced and the chip cost can be reduced. Can be lowered.

  As another additional effect, output information (noise component and pixel signal component) of the amplifier circuit at reset release is superimposed on the signal level in the reset state and output, so the capacitor feedback type amplifier circuit is reset. When the output information of the amplification circuit of the noise component due to this is acquired by the sample hold circuit 340b before the pixel signal transfer, the information on the offset voltage of the differential amplifier 322 is also acquired at the same time. Of course, the same applies when the pixel signal component is acquired by the sample and hold circuit 340a. Therefore, for both the signal level in the pixel signal transfer state and the signal level in the reset state, signal extraction can be performed on the processed signal output from the same signal processing unit, and the influence of element variation is extracted. Both signals are included in the same way. If the output signal is generated by taking the difference between the two elements so that the influence of the element variation is included in the same manner, the output signal does not include the element variation component. In the processing circuit, it is possible to eliminate the influence of variations in elements constituting the capacitive feedback amplifier circuit.

  In particular, in the first configuration example, both the sample hold circuits 340a and 340b have a two-stage configuration, and the sample hold circuit 340a1 and 340b1 first sample the pixel signal voltage V2 and the reference voltage Vref at a timing suitable for the sample hold circuit 340a1 and 340b1. The information held in the hold capacitors 344a1 and 344b1 of 340a1 and 340b1 is sampled at the same timing in the subsequent sample hold circuits 340a2 and 340b2 and transmitted to the signal adder 360. The influence of the reset noise can be suppressed with higher accuracy than in the case of doing so. By matching the timing in the second-stage sample hold, the noise accumulation period is made the same so that high S / N data can be obtained regardless of the portion of one data.

  That is, as a concept, the information V3_ @ a and V3_ @ b held in the hold capacitors 344a1 and 344b1 in the sample-and-hold circuits 340a1 and 340b1 in the previous stage are transmitted to the signal adder 360 to perform addition processing (actual subtraction processing) It is also conceivable to adopt a configuration (referred to as a first modified example) that executes ().

  However, in the case of the first modification, the pixel signal extraction information (pixel signal voltage V2_ @ and the combined component of thermal noise Vnrst1 = V3_ @ a) supplied from the analog amplifier 346a1 and the reset noise information supplied from the analog amplifier 346b1. There is a deviation (t15 to t22) in the sample hold timing with respect to (negative information of thermal noise Vnrst1 = −V3_ @ b). On the other hand, the signal adding unit 360 always performs differential processing for adding the signals S3_sig and S3_rst in a differential manner. For this reason, at timings t15 to t22, the signal S3_sig and the signal S3_rst handled by the signal addition unit 360 have different pixels to be processed, and an error corresponding to the difference processing result occurs, resulting in a decrease in accuracy. However, when the reset noise in the switched capacitor amplifier 320 can be considered to be the same regardless of the pixel to be processed, no problem usually occurs. However, since the noise accumulation period differs only with one-stage sample hold, the amount of noise after subtraction processing varies in one data. Considering this point, it is preferable to decide whether to adopt a two-stage configuration for high precision or to make the circuit compact by using a one-stage configuration.

  In addition, in the point that the signal output timings of the difference processing targets in the signal adding unit 360 are aligned, it is only necessary that the reset noise information of the switched capacitor amplifier 320 can be synchronized with the output timing of the signal components. There is no need for each sample and hold circuit to have a two-stage configuration.

  For example, it may be possible to adopt a configuration in which only the sample hold circuit 340b side has two stages (referred to as a second modification). In the case of the second modification, the sampling timing in the sample hold circuit 340b2 in the subsequent stage of the information of the thermal noise Vnrst1 sampled in the hold capacitor 344b1 in the sample hold circuit 340b1 in the previous stage is the sampling timing in the sample hold circuit 340a for extracting pixel information. It is good to match (t22 to t26). By doing so, there is an advantage that the circuit can be made compact and the reset noise in the switched capacitor amplifier 320 can be dealt with with high accuracy even when the reset noise differs among the pixels to be processed.

<Detailed Configuration of Output Circuit: Second Configuration Example>
FIG. 6 is a block diagram illustrating a second configuration example of the output circuit 28 according to the present embodiment. In the output circuit 28 of the second configuration example, the signal adder 360 and the analog amplifiers 346a2 and 346b2 on the input side in the first configuration example are collectively replaced by a differential amplifier 348 configured by an operational amplifier (op amp). It is. There is no doubt that the differential amplifier 348 is also an analog amplifier. The sample switch 342a2, the hold capacitor 344a2, and the differential amplifier 348 constitute a sample-and-hold circuit 340a2 for extracting pixel information, and the sample switch 342b2, the hold capacitor 344b2, and the differential amplifier 348 constitute a latter-stage for extracting reference information. A sample hold circuit 340b2 is configured.

  In the differential amplifier 348, the pixel signal extraction information (the combined component of the pixel signal voltage V2_ @ and the thermal noise Vnrst1 = voltage V4_ @ a) held in the hold capacitor 344a2 is supplied to the non-inverting input terminal (+). The reference voltage Vref information including the reset noise information (thermal noise Vnrst1 = V4_ @ b) held in the hold capacitor 344b2 is supplied to the inverting input terminal (−). The differential amplifier 348 is connected between pixel signal extraction information (pixel signal voltage V2_ @ and thermal noise Vnrst1 combined component = voltage V4_ @ a) and reset noise information (thermal noise Vnrst1 information = V4_ @ b). , The difference processing is performed in accordance with “(combined component of pixel signal voltage V2_ @ 2 and thermal noise Vnrst1) −thermal noise Vnrst1” and output as an imaging signal S3. Thereby, also in the second configuration example, the thermal noise Vnrst1 is canceled while the voltage amplitude V2_ @ of the pixel signal is maintained, so that the imaging signal S3 having a high S / N is output from the differential amplifier 348.

  By replacing the signal adder 360 in the first configuration example and the analog amplifiers 346a2 and 346b2 on the input side together with a single differential amplifier 348, the circuit configuration can be made compact and the operational effects in the first configuration example can be enjoyed as they are. There are advantages you can do.

  The mechanism of the second configuration example in which the signal adding unit 360 and the two analog amplifiers 346 on the input side thereof are collectively replaced with one differential amplifier 348 is the first modification example or the second modification example of the first configuration example. In this case, the present invention can be applied in the same manner, and the effects of the modifications of the first configuration example can be enjoyed in the same manner.

<Imaging device>
FIG. 7 is a diagram illustrating a schematic configuration of an imaging apparatus (camera system) that is an example of a physical information acquisition apparatus that uses a mechanism similar to that of the solid-state imaging apparatus 1 of the present embodiment described above. The imaging device 8 is an imaging device that obtains a visible light color image.

  Specifically, the imaging device 8 includes a photographing lens 802 that guides light L carrying an image of the subject Z under the light source 801 such as sunlight or a fluorescent lamp to the imaging device side, and an optical lens. A low-pass filter 804, a color filter group 812 in which, for example, R, G, and B color filters are arranged in a Bayer array, a pixel array unit 10, a drive control unit 7 that drives the pixel array unit 10, and a pixel array unit 10 A column processing unit 26 that performs analog signal processing such as CDS processing on the pixel signal output from the output unit 28, an output circuit 28 that processes and outputs the pixel signal S1 output from the column processing unit 26, and an output circuit 28 A camera signal processing unit 810 that performs predetermined signal processing on the output imaging signal S3 is provided.

  The camera signal processing unit 810 includes an imaging signal processing unit 820 and a camera control unit 900 that functions as a main control unit that controls the entire imaging apparatus 8. The imaging signal processing unit 820 supplies an AD conversion unit 821 that converts the imaging signal supplied from the output circuit 28 into digital data, and an AD conversion unit 821 that uses a color filter other than the primary color filter. The signal separation unit 822 having a primary color separation function for separating the digital imaging signal to be separated into R (red), G (green), and B (blue) primary color signals, and the primary color signal R, separated by the signal separation unit 822 And a color signal processing unit 830 that performs signal processing on the color signal C based on G and B.

  The imaging signal processing unit 820 also converts the luminance signal Y / color signal C into a luminance signal processing unit 840 that performs signal processing on the luminance signal Y based on the primary color signals R, G, and B separated by the signal separation unit 822. And an encoder unit 860 that generates a video signal VD based on the encoder 860.

  The camera control unit 900 according to the present embodiment is a microprocessor that forms the center of an electronic computer whose representative example is a CpU (Central Processing Unit) in which the functions of computation and control performed by a computer are integrated into a very small integrated circuit. 902, a ROM (Read Only Memory) 904 that is a read-only storage unit, a RAM (Random Access Memory) 906 that is an example of a volatile storage unit that can be written and read at any time, and others that are not illustrated The peripheral member is included. The microprocessor 902, the ROM 904, and the RAM 906 are collectively referred to as a microcomputer.

  In the above description, the “volatile storage unit” means a storage unit in which the stored contents are lost when the power of the apparatus is turned off. On the other hand, the “nonvolatile storage unit” means a storage unit in a form that keeps stored contents even when the main power supply of the apparatus is turned off. Any memory device can be used as long as it can retain the stored contents. The semiconductor memory device itself is not limited to a nonvolatile memory device, and a backup power supply is provided to make a volatile memory device “nonvolatile”. You may comprise as follows.

  The camera control unit 900 controls the entire system. The ROM 904 stores a control program for the camera control unit 900. In this example, in particular, the camera control unit 900 controls various control pulses (especially for controlling the output circuit 28 in relation to the above embodiment). The program for setting the on / off timing is stored. The RAM 906 stores data for the camera control unit 900 to perform various processes.

  The camera control unit 900 is configured so that a recording medium 924 such as a memory card can be inserted and removed, and can be connected to a communication network such as the Internet. For example, the camera control unit 900 includes a memory reading unit 907 and a communication I / F (interface) 908 in addition to the microprocessor 902, the ROM 904, and the RAM 906.

  The recording medium 924 includes, for example, program data for causing the microprocessor 902 to perform software processing, a convergence range of the photometric data DL based on the luminance system signal from the luminance signal processing unit 840, and exposure control processing (including electronic shutter control). It is used for registering data such as various set values such as on / off timing of various control pulses for the purpose.

  The memory reading unit 907 stores (installs) the data read from the recording medium 924 in the RAM 906. The communication I / F 908 mediates transfer of communication data with a communication network such as the Internet.

  In addition, although such an imaging device 8 shows the drive control unit 7 and the column processing unit 26 in a module form separately from the pixel array unit 10, as described for the solid-state imaging device 1, Needless to say, the one-chip solid-state imaging device 1 integrally formed on the same semiconductor substrate as the pixel array unit 10 may be used.

  In the figure, in addition to the pixel array unit 10, the drive control unit 7, the column processing unit 26, and the camera signal processing unit 810, an optical system such as a photographing lens 802, an optical low-pass filter 804, or an infrared light cut filter 805 is provided. In this state, the imaging device 8 is shown. This aspect is suitable for a module-like form having an imaging function packaged together.

  Here, in relation to the modules in the solid-state imaging device 1 described above, as shown in the figure, the pixel array unit 10 (imaging unit), the column processing unit 26 having an AD conversion function and a difference (CDS) processing function, and the like A solid-state imaging device in the form of a module having an imaging function in a state where signal processing units closely related to the pixel array unit 10 side (excluding the camera signal processing unit following the column processing unit 26) are packaged together 1 is provided, and a camera signal processing unit 810, which is the remaining signal processing unit, is provided in the subsequent stage of the solid-state imaging device 1 provided in the module form so that the entire imaging device 8 is configured. Also good.

  Alternatively, although not shown, the solid-state imaging device 1 is provided in a modular form having an imaging function in a state where the pixel array unit 10 and the optical system such as the photographing lens 802 are packaged together. In addition to the solid-state imaging device 1 provided in the form of a module, a camera signal processing unit 810 may be provided in the module to constitute the entire imaging device 8.

  Further, as a module form in the solid-state imaging device 1, a camera signal processing unit 810 corresponding to the camera signal processing unit 200 may be included. In this case, the solid-state imaging device 1 and the imaging device 8 are practically the same. It can also be regarded as a thing.

  Such an imaging device 8 is provided as a portable device having an imaging function, for example, for performing “imaging”. Note that “imaging” includes not only capturing an image during normal camera shooting but also includes fingerprint detection in a broad sense.

  The imaging device 8 having such a configuration is configured to include all the functions of the solid-state imaging device 1 described above, and can be the same as the basic configuration and operation of the solid-state imaging device 1 described above. By applying any of the above-described configuration examples or modifications thereof as the output circuit 28, the problem of reset noise (thermal noise) of the switched capacitor amplifier 320 in horizontal data transfer can be solved.

It is a schematic block diagram of the CMOS solid-state imaging device which is one Embodiment of the solid-state imaging device concerning this invention. It is a block diagram explaining the 1st structural example of an output circuit. It is a block diagram explaining the comparative example of an output circuit. It is a timing chart explaining operation | movement of the output circuit of a comparative example. It is a timing chart explaining operation | movement of the output circuit of a 1st structural example. It is a block diagram explaining the 2nd structural example of an output circuit. It is a figure which shows schematic structure of the imaging device using the structure similar to the solid-state imaging device of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 10 ... Pixel array part, 12 ... Horizontal scanning part, 14 ... Vertical scanning part, 15 ... Vertical control line, 18 ... Horizontal signal line, 18C ... Parasitic capacitance, 19 ... Vertical signal line, 20 ... Communication Timing control unit, 24 ... Read current source unit, 25 ... Column signal processing unit, 26 ... Column processing unit, 266 ... Storage capacity (input capacity), 266C ... Line memory, 268 ... Column output line, 28 ... Output circuit, DESCRIPTION OF SYMBOLS 3 ... Unit pixel, 320 ... Switched capacitor amplifier, 322 ... Differential amplifier, 324 ... Feedback capacity, 326 ... Initialization switch, 340 ... Sample hold part, 340a ... Sample hold circuit, 340a1 ... Pre-stage sample hold circuit, 340a2 ... latter stage sample hold circuit, 340b ... sample hold circuit, 340b1 ... previous stage sample hold circuit, 340b2 ... later stage support Pull hold circuit, 342 ... sample switch, 344 ... hold capacitor, 346 ... analog amplifier, 348 ... differential amplifier, 360 ... signal addition unit, 60 ... horizontal selection switch unit, 62 ... horizontal selection switch, 7 ... drive control unit, 8 ... Imaging device, 900 ... Camera control unit

Claims (4)

A pixel array unit in which unit pixels are arranged in a matrix;
A plurality of pixel signal holding units each including a capacitive element that holds a pixel signal read in a column direction from each unit pixel of the pixel array unit;
A selection unit for sequentially selecting the pixel signal holding unit;
A signal line for transmitting a pixel signal output from the pixel signal holding unit selected by the selection unit;
An amplifying element, a feedback capacitor connected between the input and output of the amplifying element, and an initialization switch that initializes a voltage across the feedback capacitor, and operates using the capacitor element of the pixel signal holding unit as an input capacitor A capacitive feedback amplifier circuit;
When the initialization switch is off and the selection unit does not select the pixel signal holding unit, a noise component generated when the initialization switch is turned on and held in a capacitor attached to the signal line The amplification circuit outputs the reference information that is amplified and output and the pixel signal held in the input capacitor when the initialization switch is off and the selection unit selects the pixel signal holding unit A solid-state imaging device comprising: a noise suppression unit that suppresses noise generated in the output signal of the amplifier circuit by the initialization based on the pixel information of the signal transfer state that is amplified and output in step. The noise suppression unit is acquired by a reference information acquisition unit that acquires and holds the reference information, a signal transfer information acquisition unit that acquires and holds pixel information of the signal transfer state, and the reference information acquisition unit The solid-state imaging device according to claim 1, further comprising a difference information acquisition unit that acquires a difference result between reference information and pixel information acquired by the signal transfer information acquisition unit. The reference information acquisition unit and the signal transfer information acquisition unit are configured to be able to align each output timing of reference information and pixel information used for processing in the difference information acquisition unit. The solid-state imaging device according to claim 2. A pixel array unit in which unit pixels are arranged in a matrix;
A plurality of pixel signal holding units each including a capacitive element that holds a pixel signal read in a column direction from each unit pixel of the pixel array unit;
A selection unit for sequentially selecting the pixel signal holding unit;
A signal line for transmitting a pixel signal output from the pixel signal holding unit selected by the selection unit;
An amplifying element, a feedback capacitor connected between the input and output of the amplifying element, and an initialization switch that initializes a voltage across the feedback capacitor, and operates using the capacitor element of the pixel signal holding unit as an input capacitor A capacitive feedback amplifier circuit;
When the initialization switch is off and the selection unit does not select the pixel signal holding unit, a noise component generated when the initialization switch is turned on and held in a capacitor attached to the signal line The amplification circuit outputs the reference information that is amplified and output and the pixel signal held in the input capacitor when the initialization switch is off and the selection unit selects the pixel signal holding unit And a noise suppression unit that suppresses noise generated in the output signal of the amplification circuit by the initialization based on the pixel information of the signal transfer state that is amplified and output in step, and for controlling the amplification circuit and the noise suppression unit An imaging apparatus comprising: a main control unit that generates control information.

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