JP2008177695A - Demodulating device and encoding device, and demodulating method and encoding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the processing time needed to update a communication path value in repetitive demodulation. <P>SOLUTION: A demodulating device includes communication path value update units 51-1 and 51-2 which generate communication path values using a post value and a likelihood obtained in a stage of repetitive decoding, a DMUX 54-1 which allocates the likelihood 212 read out of a symbol likelihood memory to the communication path update units according to use rules in the communication path value update units respectively, a DMUX 54-2 which allocates the post value 213 obtained in the stage of repetitive decoding to the communication value update units according to the use rules of the communication path update units, and a MUX 55 which multiplexes communication value series generated by the communication path value update units 51-1 to 51-2 respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a demodulation device and an encoding device, and a demodulation method and an encoding method.

  Conventionally, MAP (Maximum A posteriori Probability) decoding is known as one of decoding methods of turbo codes. In MAP decoding, iterative decoding is performed by inputting an external value output from a subsequent element decoder of two element decoders to a previous element decoder as a prior value. As specific examples of MAP decoding, for example, Max-Log-MAP decoding and Log-MAP decoding are known. Non-Patent Document 1 discloses a decoding method called “twin turbo decoding”, which is a further development of the MAP decoding. In twin-turbo decoding, in addition to iterative decoding in which the external value output from the downstream element decoder is input to the upstream element decoder as a prior value in the same manner as MAP decoding, in the decoding process, it is output from the downstream element decoder. The posterior value is fed back to update the channel value input to the preceding element decoder. Furthermore, the channel value input to the subsequent element decoder is updated using the a posteriori value output from the preceding element decoder. According to the twin turbo decoding, in addition to iterative decoding, the demodulation operation is repeated (repeated demodulation) in which the channel value is updated using the posterior value obtained in the iterative decoding process. This improves the error correction capability of the turbo code.

  FIG. 11 is a block diagram showing a configuration of a conventional wireless communication system using a turbo code. In FIG. 11, the transmission device 10 includes a turbo encoder 11, a modulator 12, a wireless transmitter 13, and an antenna 14. The receiving apparatus 20 includes an antenna 21, a radio receiver 22, a demodulator / decoder 300, and a bit determination unit 24.

  In the transmission device 10 of FIG. 11, the turbo encoder 11 turbo-encodes the transmission information bit sequence 101 to create an encoded bit sequence 102. The modulator 12 creates a modulation symbol sequence 103 in which the encoded bit sequence 102 is mapped. The wireless transmitter 13 wirelessly transmits the modulation symbol sequence 103 via the antenna 14.

  FIG. 12 is a block diagram showing the configuration of the turbo encoder 11. In FIG. 12, the element encoder 31-1 creates a parity bit sequence 111 from the transmission information bit sequence 101. Element encoder 31-2 creates parity bit sequence 112 from the bit sequence in which transmission information bit sequence 101 is rearranged by interleaver 32. Channel interleaving section 33 rearranges transmission information bit sequence 101 according to a predetermined rule to create bit sequence 113. The channel interleaving unit 34 rearranges and multiplexes the parity bit sequence 111 and the parity bit sequence 112 according to a predetermined rule to create a bit sequence 114. The puncturing unit 35 creates a bit sequence 115 by thinning out parity bits from the bit sequence 114 according to a predetermined rule. The MUX 36 multiplexes the bit sequence 113 and the bit sequence 115 to create an encoded bit sequence 102.

  In the receiving apparatus 20 of FIG. 11, the wireless receiver 22 outputs a received symbol sequence 201 that is wirelessly received via the antenna 21. Demodulator / decoder 300 performs twin turbo decoding on received symbol sequence 201 to generate a posteriori value sequence 202. The bit decision unit 24 makes a hard decision on the posterior value series 202 to create a reception information bit series 203.

  FIG. 13 is a block diagram showing a configuration of a conventional demodulator / decoder 300 to which twin turbo decoding is applied. In FIG. 13, the symbol likelihood calculator 41 calculates the likelihood 211 of each received symbol from the received symbol sequence 201. The symbol likelihood memory 42 stores the likelihood 211 of each received symbol. The likelihood 212 read from the symbol likelihood memory 42 is input to the channel value updaters 301-1 and 301-2.

  The channel value updater 301-1 updates the channel value using the likelihood 212 and the posterior value (Xa, Xc) 213-1 and creates the updated channel value (Xa, Xb) 214-1. . Xa corresponds to the transmission information bit sequence 101. Xb corresponds to the parity bit sequence 111. Xc corresponds to the parity bit sequence 112. Since the posterior value (Xa, Xc) 213-1 has not yet been obtained at the time of starting the iterative decoding and iterative demodulation operations, for example, the posterior value “0” is set as the initial value of the posterior value (Xa, Xc). Use.

  The element decoder 43-1 corresponds to the element encoder 31-1 in FIG. Element decoder 43-1 creates external value (Xa) and posterior value (Xa, Xb) 213-2 using channel value (Xa, Xb) 214-1 and prior value (Xa). The external value (Xa) is rearranged by the interleaver 44 and input to the element encoder 43-2 as a prior value (Xa). The interleaver 44 corresponds to the interleaver 32 of FIG. Note that since the prior value (Xa) has not yet been obtained at the start of the iterative decoding and iterative demodulation operations, for example, the prior value “0” is used as the initial value of the prior value (Xa).

  The channel value updater 301-2 updates the channel value using the likelihood 212 and the posterior value (Xa, Xb) 213-2, and creates the channel value (Xa, Xc) 214-2. The channel values (Xa, Xc) 214-2 are rearranged by the interleaver 45 and input to the element encoder 43-2 as updated channel values (Xa, Xc). The interleaver 45 corresponds to the interleaver 32 in FIG.

  The element decoder 43-2 corresponds to the element encoder 31-2 in FIG. The element decoder 43-2 creates the external value (Xa) and the posterior value (Xa, Xc) using the updated channel value (Xa, Xc) and the prior value (Xa). The external value (Xa) is rearranged by the deinterleaver 46 and input to the element encoder 43-1 as a prior value (Xa). Further, the posterior values (Xa, Xc) are rearranged by the deinterleaver 47 and input to the channel value updater 301-1 as the posterior values (Xa, Xc) 213-1. The deinterleavers 46 and 47 correspond to the interleavers 44 and 45. Of the posterior values (Xa, Xc), the posterior value (Xa) is output as a series 202 of posterior values (Xa).

  FIG. 14 is a block diagram showing a configuration of conventional channel value updaters 301-1 and 301-2. In FIG. 14, the channel value updaters 301-1 and 301-2 are not particularly distinguished and will be described as the channel value updater 301. Therefore, the posterior value input to the channel value updater 301 is simply referred to as the posterior value 213, and the channel value output from the channel value updater 301 is simply referred to as the channel value 214.

  In FIG. 14, the channel value update unit 51 uses the likelihood 212 and the posterior value 213 to create a channel value. The created sequence of communication channel values corresponds to the encoded bit sequence 102 of FIG. Next, the depuncture unit 52 performs parity bit interpolation on the created channel value series. The depuncture unit 52 inserts the channel value of the parity bit according to a predetermined rule corresponding to the puncture unit 35 of FIG. As the communication channel value to be inserted, for example, a likelihood value “0” is used. The likelihood value “0” indicates that the probability that the bit value is “0” or “1” is equal. Next, the channel deinterleaving unit 53 rearranges the channel values for the channel value series after parity bit interpolation. The channel deinterleaving unit 53 rearranges the communication path values according to each predetermined rule corresponding to the channel interleaving units 33 and 34 of FIG. By this rearrangement, a series of channel values 214 is created.

The number of likelihoods (number of readout units) read at a time from the symbol likelihood memory 42 of FIG. 13 is the number of predetermined received symbols used for twin turbo decoding. Further, from the symbol likelihood memory 42, the same likelihood for the number of read units is repeatedly read each time the channel value is updated in the channel value updaters 301-1 and 301-2. That is, iterative decoding and iterative demodulation are performed using the same likelihood for a predetermined number of received symbols, and a posteriori value sequence 202 for the predetermined number of received symbols is created. The channel value update in the channel value updaters 301-1 and 301-2 is performed by repeating the decoding process in the iterative decoding process (the element decoder 43- of the external value (Xa) from the element encoder 43-2). (Feedback to 1) may be performed by feeding back the a posteriori values (Xa, Xc) from the element encoder 43-2, or at a predetermined number of repetitions of the decoding process in the iterative decoding process. The a posteriori values (Xa, Xc) from the element encoder 43-2 may be fed back.
N. Miyazaki, Y. Hatakawa, T. Yamamoto, H. Ishikawa, T. Suzuki, “A Study on Likelihood Estimation Method Taking Account of Mutual Information in Multi-Level Symbol ~ A Proposal of Twin Turbo Decoder ~” Proc. PIMRC ' 06 Fall, TH-1 # 3, Sep. 2006.

  However, in the conventional demodulator / decoder 300 described above, since the likelihood is read from the symbol likelihood memory 42 every time the channel value is updated in the repeated demodulation, the memory access time is long and the processing time is shortened. There is a problem that it is difficult. In addition, the amount of computation required for updating the communication channel value is larger than that of other processes, which also hinders the reduction of the processing time.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a demodulating device, an encoding device, and a demodulating method capable of shortening a processing time required for updating a channel value in iterative demodulation. And providing an encoding method.

  In order to solve the above problems, a demodulator according to the present invention receives a modulation symbol to which a coded bit sequence subjected to error correction coding that can be iteratively decoded is mapped, and repeatedly performs the received symbol. In a demodulation device that performs decoding and iterative demodulation, communication is performed using a symbol likelihood calculator that calculates the likelihood of each received symbol from a received symbol sequence, and the posterior value obtained in the process of iterative decoding and the likelihood. At least two channel value update units for creating a path value, a symbol likelihood memory for storing the likelihood, and the likelihood read from the symbol likelihood memory, in each of the channel value update units, The first allocator for allocating according to the usage rule of the channel value update unit and the posterior value obtained in the iterative decoding process are transmitted to the channel value update unit, respectively. A second distributor for distributing according to usage rules parts, characterized by comprising a multiplexer for multiplexing the channel value series made by each of the channel value updating section.

  A demodulating apparatus according to the present invention receives a modulation symbol to which a coded bit sequence subjected to error correction coding capable of iterative decoding is mapped, and performs iterative decoding and iterative demodulation on the received symbol. A symbol likelihood calculator that calculates the likelihood of each received symbol from the received symbol sequence, a symbol likelihood memory that is provided corresponding to each of the channel value update units and stores the likelihood, and the iterative decoding And at least two channel value update units that create channel values using the posterior value obtained in the process of step 1 and the likelihood read from the symbol likelihood memory, and the calculation result of the symbol likelihood calculator A first allocator that distributes the likelihood to each of the symbol likelihood memories according to a usage rule of a channel value update unit corresponding to the symbol likelihood memory; The posterior value obtained in the decoding process is generated by each of the channel value update unit by each of the second distributor and the channel value update unit that distributes the posterior value according to the usage rule of the channel value update unit. And a multiplexer for multiplexing the received channel value series.

  The encoding apparatus according to the present invention is an encoding apparatus that generates an encoded bit sequence from an information bit sequence and a parity bit sequence by error correction encoding capable of iterative decoding, and a parity bit obtained in the encoding process. An equal-interval puncturing unit that thins out parity bits at regular intervals from the sequence; and the coded bit sequence by performing bit rearrangement, sequence division, and multiplexing on the bit sequence after decimation and the information bit sequence And a bit rearrangement multiplexer for generating the.

  The demodulator according to the present invention receives a modulation symbol to which a coded bit sequence subjected to error correction coding that can be iteratively decoded by the encoder is mapped, and performs iterative decoding and demodulation on the received symbol. In the demodulator, a symbol likelihood calculator that calculates the likelihood of each received symbol from the received symbol sequence, at least two channel value update units that create channel values using the likelihood, and stores the likelihood A symbol likelihood memory, and a likelihood that is read from the symbol likelihood memory to each of the channel value update units according to a usage rule of the channel value update unit, and Corresponding to the bit rearrangement rule in the encoding device for the channel value series provided for each channel value updating unit and created by the channel value updating unit A channel value rearranger for rearranging the channel values, and a channel value sequence created by each of the channel value rearrangers are multiplexed by a method corresponding to a sequence division rule in the encoding device. And an equal interval depuncture unit that interpolates parity bits corresponding to the equal interval decimation rule of the parity bits in the encoding device for the channel value sequence created by the multiplexer. It is characterized by.

  The demodulator according to the present invention receives a modulation symbol to which a coded bit sequence subjected to error correction coding that can be iteratively decoded by the encoder is mapped, and performs iterative decoding and demodulation on the received symbol. In the demodulator, a symbol likelihood calculator that calculates the likelihood of each received symbol from the received symbol sequence, a symbol likelihood memory that is provided corresponding to each of the channel value update units, and stores the likelihood, Using at least two channel value update units that create channel values using the posterior value obtained in the iterative decoding process and the likelihood read from the symbol likelihood memory; and the symbol likelihood computing unit A first allocator that distributes the likelihood of the calculation result to each of the symbol likelihood memories according to a use rule of a channel value update unit corresponding to the symbol likelihood memory; An array of communication channel values corresponding to the bit rearrangement rule in the encoding device with respect to the communication channel value sequence provided for each of the communication channel value updating units and created by the communication channel value updating unit. A channel value rearranger that performs the switching, and a multiplexer that multiplexes the channel value sequences created by each of the channel value rearrangers by a method corresponding to a sequence division rule in the encoding device, An equidistant depuncturing unit for interpolating parity bits corresponding to a regular interval decimation rule of parity bits in the encoding device for a channel value series created by the multiplexer.

  In the demodulating device according to the present invention, the demodulating device performs iterative demodulation, and the channel value update unit performs communication using the posterior value obtained in the iterative decoding process and the likelihood. A second allocator that creates a route value and distributes the posterior value obtained in the process of iterative decoding to each of the channel value update units according to a usage rule of the channel value update unit. Features.

  The demodulation method according to the present invention is a demodulation method for receiving a modulation symbol to which a coded bit sequence subjected to error correction coding capable of iterative decoding is mapped, and performing iterative decoding and iterative demodulation on the received symbol. The process of calculating the likelihood of each received symbol from the received symbol sequence, the process of storing the likelihood in a memory, and the likelihood read from the memory in each of the channel value update process, The first distribution process that distributes according to the usage rule of the channel value update process and the posterior value obtained in the iterative decoding process are assigned to each of the channel value update process according to the usage rule of the channel value update process. A communication path value is created using the second distribution process to be distributed, the likelihood received from the first distribution process, and the posterior value received from the second distribution process. At least two and the signal path value update process, characterized in that it comprises a step of multiplexing the channel value series made by each of the communication path value update process.

  The demodulation method according to the present invention is a demodulation method for receiving a modulation symbol to which a coded bit sequence subjected to error correction coding capable of iterative decoding is mapped, and performing iterative decoding and iterative demodulation on the received symbol. And calculating the likelihood of each received symbol from the received symbol sequence and the likelihood of the calculation result of the symbol likelihood computing unit for each of the memories provided corresponding to each of the channel value updating units. In addition, the first distribution process to be distributed and stored in accordance with the usage rule of the channel value update unit corresponding to the memory, and the posterior value obtained in the iterative decoding process are respectively transmitted to the channel value update process. Using a second distribution process that distributes according to the usage rules of the road value update process, the likelihood read from the memory, and the posterior value received from the second distribution process At least two and a channel value updating process of making channel values, characterized in that it comprises a step of multiplexing the channel value series made by each of the communication path value update process.

  An encoding method according to the present invention is an encoding method for generating an encoded bit sequence from an information bit sequence and a parity bit sequence by error correction encoding capable of iterative decoding, obtained in the encoding process. The process of decimation of parity bits from the parity bit sequence at equal intervals, and the bit sequence after the decimation and the information bit sequence are subjected to bit rearrangement, sequence division and multiplexing to obtain the encoded bit sequence And the process of making.

  The demodulation method according to the present invention receives a modulation symbol to which a coded bit sequence subjected to error correction coding that can be repeatedly decoded by an encoding device is mapped, and repeatedly performs decoding and demodulation on the received symbol. A demodulation method, a process of calculating a likelihood of each received symbol from a received symbol sequence, a process of storing the likelihood in a memory, and a likelihood read from the memory, in a channel value updating process Each of at least two channel value update processes for creating a channel value using the likelihood received from the first distribution process, a first distribution process that distributes according to the usage rules of the channel value update process, A bit rearrangement rule in the encoding device is provided for each of the channel value update processes, and for the channel value sequence created in the channel value update process. A channel value rearrangement process for rearranging the corresponding channel values, and a method corresponding to the sequence division rule in the encoding device for the channel value series created in each of the channel value rearrangement processes And a process of interpolating parity bits corresponding to a regular interval decimation rule of parity bits in the encoding device for the channel value sequence generated in the multiplexing process. And

  The demodulation method according to the present invention receives a modulation symbol to which a coded bit sequence subjected to error correction coding that can be repeatedly decoded by an encoding device is mapped, and repeatedly performs decoding and demodulation on the received symbol. In the demodulation method, the process of calculating the likelihood of each received symbol from the received symbol sequence and the likelihood of the calculation result of the symbol likelihood calculator are provided corresponding to each of the channel value update units A first distribution process in which each of the memories is distributed and stored in accordance with a usage rule of a channel value update unit corresponding to the memory, and a channel value update that creates a channel value using the likelihood read from the memory At least two processes are provided corresponding to each of the channel value update processes, and a bit value in the encoder is set for a channel value sequence created in the channel value update process. A channel value rearrangement process for rearranging the channel values corresponding to the rearrangement rule, and a channel value sequence created in each of the channel value rearrangement processes, and a sequence division rule in the encoding device And a process of interpolating parity bits corresponding to the regular interval decimation rule of the parity bits in the encoding device for the channel value sequence generated in the multiplexing process. It is characterized by including.

  The demodulation method according to the present invention is a demodulation method that performs iterative demodulation, wherein the channel value update process uses a posterior value obtained in the process of iterative decoding and the likelihood to calculate a channel value. And a second distribution process for distributing the posterior value obtained in the iterative decoding process to each of the channel value update processes according to usage rules of the channel value update process.

  According to the present invention, it is possible to shorten the processing time required for updating the channel value in the repeated demodulation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a wireless communication system according to an embodiment of the present invention. In FIG. 1, parts corresponding to those in the conventional radio communication system shown in FIG. In FIG. 1, a receiving device 20 includes a demodulator / decoder 23 as an embodiment of a demodulator according to the present invention.

[First Embodiment]
FIG. 2 is a block diagram showing a configuration of the demodulator / decoder 23 according to the first embodiment of the present invention. This demodulator / decoder 23 is one to which twin turbo decoding is applied. 2, parts corresponding to those of the conventional demodulator / decoder 300 shown in FIG. 13 are assigned the same reference numerals, and descriptions thereof are omitted.

  The demodulator / decoder 23 shown in FIG. 2 includes channel value updaters 50-1 and 50-2 instead of the channel value updaters 301-1 and 301-2 in the demodulator / decoder 300 of FIG. To do. The configuration other than the channel value updaters 50-1 and 50-2 is the same as that of the demodulator / decoder 300 in FIG.

  FIG. 3 is a block diagram showing the configuration of the channel value updaters 50-1 and 50-2 according to the first embodiment of the present invention. In FIG. 3, the channel value updaters 50-1 and 50-2 are not particularly distinguished and will be referred to as the channel value updater 50. Therefore, the posterior value input to the channel value updater 50 is simply referred to as the posterior value 213, and the channel value output from the channel value updater 50 is simply referred to as the channel value 214.

  The communication channel value updater 50 shown in FIG. 3 is different from the conventional communication channel value updater 301 shown in FIG. 14 in that it includes two communication channel value update units 51-1 and 51-2. The update unit is parallelized. In order to realize parallelization of the channel value update unit, two DMUXs 54-1 and 54-2 and a MUX 55 are further provided. Note that the depuncture unit 52 and the channel deinterleave unit 53 are the same as the conventional channel value updater 301 shown in FIG.

  The DMUX 54-1 distributes the likelihood 212 read from the symbol likelihood memory 42 to the channel value update units 51-1 and 51-2. The DMUX 54-2 distributes the posterior value 213 to the channel value update units 51-1 and 51-2. The communication channel value updating units 51-1 and 51-2 create a communication channel value using the likelihood input from the DMUX 54-1 and the posterior value input from the DMUX 54-2. This channel value creation method is the same as the conventional method. The MUX 55 multiplexes the communication channel values created by the communication channel value update units 51-1 and 51-2. The channel value sequence after the output of MUX 55 corresponds to the encoded bit sequence 102 in FIG.

Next, the operation of the DMUXs 54-1 and 54-2 will be described.
The DMUXs 54-1 and 54-2 perform a distribution operation suitable for the channel value update processing in the channel value update units 51-1 and 51-2 in order to realize parallelization of the channel value update units. The communication channel value updating units 51-1 and 51-2 create communication channel values using likelihoods and posterior values corresponding to a predetermined number of received symbols according to predetermined rules. Therefore, assigning the likelihood and the posterior value to the channel value update units 51-1 and 51-2 according to the usage rules is the key to the successful parallelization of the channel value update units.

  FIG. 4 is an explanatory diagram for explaining the operation of the DMUXs 54-1 and 54-2. In FIG. 4, for convenience of explanation, it is assumed that the present demodulator / decoder 23 performs twin turbo decoding using four received symbols. One received symbol (that is, a modulation symbol) is composed of three bits.

  In FIG. 4, the DMUX 54-1 converts the four likelihoods 212 corresponding to the four received symbols A, B, C, and D read from the symbol likelihood memory 42 into the channel value update units 51-1 and 51. -2. Also, DMUX 54-2 has a total of 12 bit likelihoods (posterior values) a1, a2, a3, b1, b2, b3, c1, c2, c3 corresponding to the four received symbols A, B, C, D. , D1, d2, and d3 are distributed to the channel value updating units 51-1 and 51-2. It is assumed that the order of time series of received symbols A, B, C, and D is the order of A, B, C, and D.

  Here, the channel value updating unit 51-1 creates channel values using the likelihood and posterior values corresponding to the received symbols A and C in accordance with a time-series order according to a predetermined rule. On the other hand, the channel value updating unit 51-2 creates channel values using the likelihood and posterior values corresponding to the received symbols B and D in accordance with a time-series order according to a predetermined rule. Accordingly, the DMUX 54-1 outputs the two likelihoods 212 corresponding to the reception symbols A and C to the channel value updating unit 51-1, and communicates the two likelihoods 212 corresponding to the reception symbols B and D. It outputs to the road value update part 51-2. Similarly, DMUX 54-2 outputs likelihoods a1, a2, a3, c1, c2, and c3 of a total of six bits corresponding to received symbols A and C to channel value updating unit 51-1, and receives received symbols. The likelihoods b1, b2, b3, d1, d2, and d3 of a total of six bits corresponding to B and D are output to the channel value updating unit 51-2. Thereby, each of the channel value update units 51-1 and 51-2 can succeed in creating the channel value. Note that the MUX 55 multiplexes the channel values output from each of the channel value update units 51-1 and 51-2 by a method corresponding to the distribution method of the DMUXs 54-1 and 54-2.

  According to the first embodiment described above, since the channel value update unit is parallelized, the processing time required for updating the channel value can be shortened.

[Second Embodiment]
FIG. 5 is a block diagram showing a configuration of the demodulator / decoder 23 according to the second embodiment of the present invention. This demodulator / decoder 23 is one to which twin turbo decoding is applied. In FIG. 5, parts corresponding to those of the conventional demodulator / decoder 300 shown in FIG.

  The demodulator / decoder 23 shown in FIG. 5 includes a symbol likelihood memory unit 61 instead of the symbol likelihood memory 42 in the demodulator / decoder 300 of FIG. Instead of -2, channel value updaters 62-1 and 62-2 are provided. The configuration other than the symbol likelihood memory unit 61 and the channel value updaters 62-1 and 62-2 is the same as that of the demodulator / decoder 300 of FIG.

  FIG. 6 is a block diagram showing configurations of the symbol likelihood memory unit 61 and the channel value updaters 62-1 and 62-2 according to the second embodiment of the present invention. In FIG. 6, the channel value updaters 62-1 and 62-2 are not particularly distinguished, and will be referred to as the channel value updater 62. Therefore, the posterior value input to the channel value updater 62 is simply referred to as the posterior value 213, and the channel value output from the channel value updater 62 is simply referred to as the channel value 214.

  In the second embodiment shown in FIG. 6, the channel value update units are parallelized as in the first embodiment shown in FIG. 3. In the second embodiment, symbol likelihood memories are further parallelized. In FIG. 6, symbol likelihood memories 42-1 and 42-2 are provided corresponding to each of the channel value update units 51-1 and 51-2. The DMUX 54-1 distributes the likelihood 211 output from the symbol likelihood calculator 41 to the symbol likelihood memories 42-1 and 42-2. The likelihood 212a read from the symbol likelihood memories 42-1 and 42-2 is input to the corresponding channel value updating units 51-1 and 51-2, respectively. The DMUX 54-2 distributes the posterior value 213 to the channel value update units 51-1 and 51-2.

  The DMUX 54-1 distributes the likelihood 211 output from the symbol likelihood calculator 41 to the symbol likelihood memories 42-1 and 42-2, and the distribution method is the same as in the first embodiment described with reference to FIG. is there. FIG. 7 illustrates operations of the DMUXs 54-1 and 54-2 according to the second embodiment. As shown in FIG. 7, the DMUX 54-1 gives the likelihood corresponding to the received symbols A and C used in the corresponding channel value updating unit 51-1 to the symbol likelihood memory 42-1. Write. Also, the DMUX 54-1 writes the likelihood corresponding to the received symbols B and D used in the corresponding channel value updating unit 51-2 to the symbol likelihood memory 42-2. The method of distributing the posterior value by the DMUX 54-2 is the same as that of the first embodiment described with reference to FIG. Thereby, each of the channel value update units 51-1 and 51-2 can succeed in creating the channel value. Note that the MUX 55 multiplexes the channel values output from each of the channel value update units 51-1 and 51-2 by a method corresponding to the distribution method of the DMUXs 54-1 and 54-2.

  According to the second embodiment described above, the symbol likelihood memory is further parallelized in addition to the parallelization of the channel value updating unit. As a result, the memory access time can also be shortened, and the processing time required for updating the channel value can be further shortened.

[Third Embodiment]
FIG. 8 is a block diagram showing configurations of the symbol likelihood memory unit 61 and the channel value updater 62a according to the third embodiment of the present invention. In FIG. 8, parts corresponding to those in FIG. 6 are given the same reference numerals, and explanation thereof is omitted.

  In the third embodiment shown in FIG. 8, the channel deinterleave unit is further parallelized from the second embodiment shown in FIG. In FIG. 8, channel deinterleave sections 53a-1 and 53a-2 are provided corresponding to each of communication path value update sections 51-1 and 51-2. The channel deinterleaving unit 53a-1 rearranges the channel value series output from the channel value updating unit 51-1 according to a predetermined rule. The channel deinterleaving unit 53a-2 rearranges the channel value series output from the channel value updating unit 51-2 according to a predetermined rule. The MUX 55a multiplexes the rearranged communication path value series output from the channel deinterleave units 53a-1 and 53a-2 according to a predetermined rule. The equal interval depuncturing unit 52a performs parity bit interpolation on the multiplexed channel value sequence output from the MUX 55a. The equal interval depuncture unit 52a inserts the channel value of the parity bit into the multiplexed channel value sequence according to a predetermined rule. As the communication channel value to be inserted, for example, a likelihood value “0” is used. A sequence after parity bit interpolation by the equal interval depuncture unit 52 a is a sequence of channel values 214.

  As shown in FIG. 8 described above, the third embodiment differs from the second embodiment of FIG. 6 in the processing order of channel deinterleaving, MUX, and depuncture. This is for the purpose of matching the puncture on the transmission side, channel interleaving, and MUX processing in order to realize parallelization of the channel deinterleaving unit.

  FIG. 9 is a block diagram showing a configuration of a turbo encoder 11a according to the third embodiment of the present invention. 9, parts corresponding to those in FIG. 12 are given the same reference numerals, and descriptions thereof are omitted. The turbo encoder 11a shown in FIG. 9 has the puncturing and channel interleaving processing order reversed from the turbo encoder 11 of FIG. This is for the purpose of matching with the processing on the receiving side.

  In FIG. 9, the equally-spaced puncturing unit 37-1 creates a bit sequence 121 by thinning out parity bits from the parity bit sequence 111 output from the element encoder 31-1 according to a predetermined rule. The equally-spaced puncturing unit 37-2 creates a bit sequence 122 by thinning out parity bits from the parity bit sequence 112 output from the element encoder 31-2 according to a predetermined rule. The MUX / channel interleaving unit 38 performs bit rearrangement, sequence division and multiplexing on the transmission information bit sequence 101 and the bit sequences 121 and 122 to create an encoded bit sequence 102.

FIG. 10 is an explanatory diagram for explaining the operation of the turbo encoder 11a shown in FIG. Note that the bit sequence shown in FIG. 10 is for convenience of explanation.
First, FIG. 10 (1) shows a transmission information bit sequence 101 “A0 to A11”, a parity bit sequence 111 “B0 to B11”, and a parity bit sequence 112 “C0 to C11”. The equally spaced puncturing unit 37-1 creates a bit sequence 121 from the parity bit sequence 111 by thinning out parity bits at equal intervals. The equally-spaced puncturing unit 37-2 creates a bit sequence 122 from the parity bit sequence 112 by thinning out parity bits at equal intervals.

  FIG. 10B shows the transmission information bit sequence 101 “A0 to A11”, the bit sequence 121 “B0, B2, B4, B6, B8, B10” and the parity bit sequence 122 “C0, C2, C4, C6, C8”. , C10 ". In this example, the equally-spaced puncturing units 37-1 and 37-2 thin out parity bits every other bit.

  The MUX / channel interleaving unit 38 performs bit rearrangement, sequence division and multiplexing on the transmission information bit sequence 101 and the bit sequences 121 and 122 to create an encoded bit sequence 102. FIG. 10 (3) shows the first encoded bit sequence 102 “A0, A2, A4, A6, A8, A10, B0, B4, B8, C0, C4, C8” and the second encoded bit sequence. 102 "A1, A3, A5, A7, A9, A11, B2, B6, B10, C2, C6, C10" is shown. In this example, the MUX / channel interleaving unit 38 divides each of the transmission information bit sequence 101 and the bit sequences 121 and 122 into two every other bit, multiplexes one of the divided sequences into one sequence, and Each other series after the division is multiplexed into another series. Note that in the example of FIG. 10 (3), the bits are not particularly rearranged.

  Channel deinterleaving sections 53a-1 and 53a-2 shown in FIG. 8 perform rearrangement of channel values corresponding to the bit rearrangement rules of the MUX / channel interleaving section 38 in the turbo encoder 11a of FIG. Further, the MUX 55a performs multiplexing by a method corresponding to the sequence division rule of the MUX / channel interleave unit 38 in the turbo encoder 11a of FIG. Further, the equal interval depuncturing unit 52a performs parity bit interpolation corresponding to the equal interval decimation rule of the parity bits of the equal interval puncturing units 37-1 and 37-2 in the turbo encoder 11a of FIG.

  10, the channel deinterleaving unit 53a-1 processes and outputs the channel value sequence output from the channel value update unit 51-1 corresponding to one of the sequences in FIG. 10 (3). To do. The channel deinterleaving unit 53a-2 processes and outputs the channel value sequence output from the channel value updating unit 51-2 corresponding to the other sequence in FIG. 10 (3). The channel deinterleaving units 53a-1 and 53a-2 perform rearrangement of communication channel values corresponding to the MUX / channel interleaving unit 38 in the turbo encoder 11a of FIG. Note that in the example of FIG. 10 (3), the bits are not particularly rearranged. The MUX 55a multiplexes the channel value series of the outputs from the channel deinterleave units 53a-1 and 53a-2 so as to be one series corresponding to one series shown in FIG. That is, the channel value sequence corresponding to the transmission information bit sequence 101, the channel value sequence corresponding to the bit sequence 121, and the channel value sequence corresponding to the bit sequence 122 are multiplexed every other bit. The equidistant depuncturing unit 52a inserts a channel value of parity bits every other bit into the portion corresponding to the parity bit sequences 111 and 112 with respect to the channel value sequence output from the MUX 55a. As the communication channel value to be inserted, for example, a likelihood value “0” is used.

  Thereby, it is possible to match the parity bit puncturing process, channel interleaving process and multiplexing process on the transmission side with the channel deinterleaving process, multiplexing process and depuncturing process on the reception side.

  According to the third embodiment described above, in addition to the parallelization of the channel value updating unit and the symbol likelihood memory, the channel deinterleaving unit is further parallelized. As a result, the processing time for channel deinterleaving can be shortened, and the processing time for updating the channel value can be further shortened.

  In addition, since parity bits are thinned out at equal intervals on the transmission side, parity bits are not continuously lost in subsequent bit rearrangement, sequence division and multiplexing processing. There are no restrictions on how.

  Note that, according to the third embodiment described above, an effect of shortening the processing time required for updating the communication channel value can be obtained even when iterative demodulation is not applied. When iterative demodulation is not applied, the channel value updating unit creates a channel value using only the likelihood read from the symbol likelihood memory. Therefore, the DMUX 54-2 in FIG. 8 is not necessary when iterative demodulation is not applied.

  In the third embodiment described above, the symbol likelihood memory may not be parallelized. Even in this case, an effect of shortening the processing time required for updating the channel value can be obtained. The effect can be obtained when iterative demodulation is applied or when it is not applied.

  Further, in the third embodiment described above, the present invention is similarly applied to the case where parity bit decimation is not performed, and the effect of shortening the processing time by parallelizing the channel deinterleave unit can be obtained. In this case, the equally spaced puncture units 37-1 and 37-2 in FIG. 9 and the equally spaced puncture unit 52a in FIG. 8 are not provided.

The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes design changes and the like within a scope not departing from the gist of the present invention.
For example, in the above-described embodiment, the channel value update unit, the symbol likelihood memory, or the channel deinterleave unit is parallelized, but the number of parallelisms may be three or more.

  In the above-described embodiment, the turbo code is described as an error correction code capable of iterative decoding. However, as the error correction code capable of iterative decoding, for example, a low density parity check code ( Low-Density Parity-Check Codes (LDPC code). The present invention can apply an LDPC code as an error correction code capable of iterative decoding, and can obtain the same effect as a turbo code.

  In the above-described embodiment, the wireless communication system has been described as an example. However, the transmission form is not limited to wireless, and can be similarly applied to a wired system using a communication cable such as an optical fiber cable. Further, it can be applied to various digital signal transmission systems such as a broadcasting system such as digital broadcasting.

It is a block diagram which shows the structure of the radio | wireless communications system which concerns on one Embodiment of this invention. It is a block diagram which shows the structure of the demodulator / decoder 23 which concerns on 1st Embodiment of this invention. It is a block diagram which shows the structure of the channel value updater 50 which concerns on 1st Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of DMUX54-1, 54-2 shown in FIG. It is a block diagram which shows the structure of the demodulator / decoder 23 which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the structure of the symbol likelihood memory part 61 and the channel value updater 62 which concern on 2nd Embodiment of this invention. It is explanatory drawing for demonstrating operation | movement of DMUX54-1, 54-2 shown in FIG. It is a block diagram which shows the structure of the symbol likelihood memory part 61 and the channel value updater 62a which concern on 3rd Embodiment of this invention. It is a block diagram which shows the structure of the turbo encoder 11a which concerns on 3rd Embodiment of this invention. FIG. 10 is an explanatory diagram for explaining an operation of the turbo encoder 11a illustrated in FIG. 9. It is a block diagram which shows the structure of the conventional radio | wireless communications system. 2 is a block diagram showing a configuration of a turbo encoder 11. FIG. FIG. 10 is a block diagram showing a configuration of a conventional demodulator / decoder 300. It is a block diagram which shows the structure of the conventional channel value updater 301. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 11a ... Turbo encoder, 23 ... Demodulator / decoder (demodulator), 37-1, 37-2 ... Equal interval puncture part, 38 ... MUX and channel interleave part (bit rearrangement multiplexer), 41 ... Symbol likelihood calculator, 42-1, 42-2 ... symbol likelihood memory, 50, 62, 62a ... channel value updater, 51-1, 51-2 ... channel value update unit, 52a ... equidistant depuncture , 53a-1, 53a-2 ... channel deinterleaver (channel value rearranger), 54-1, 54-2 ... DMUX (distributor), 55, 55a ... MUX (multiplexer), 61 ... symbol Likelihood memory section

Claims (12)

In a demodulator that receives a modulation symbol to which a coded bit sequence that has been subjected to repeated decoding and has been subjected to error correction coding is mapped, performs repeated decoding and repeated demodulation on the received symbol,
A symbol likelihood calculator for calculating the likelihood of each received symbol from the received symbol sequence;
At least two channel value update units that create channel values using the posterior value obtained in the iterative decoding process and the likelihood;
A symbol likelihood memory for storing the likelihood;
A first allocator that distributes the likelihood read from the symbol likelihood memory to each of the channel value update units according to a usage rule of the channel value update unit;
A second allocator that distributes the posterior value obtained in the process of iterative decoding to each of the channel value update units according to usage rules of the channel value update unit;
A multiplexer that multiplexes the channel value series created by each of the channel value update units;
A demodulating device comprising: In a demodulator that receives a modulation symbol to which a coded bit sequence that has been subjected to repeated decoding and has been subjected to error correction coding is mapped, performs repeated decoding and repeated demodulation on the received symbol,
A symbol likelihood calculator for calculating the likelihood of each received symbol from the received symbol sequence;
A symbol likelihood memory that is provided corresponding to each of the channel value update units and stores the likelihood;
At least two channel value update units that create channel values using the posterior value obtained in the iterative decoding process and the likelihood read from the symbol likelihood memory;
A first allocator that distributes the likelihood of the calculation result of the symbol likelihood calculator to each of the symbol likelihood memories according to a use rule of a channel value update unit corresponding to the symbol likelihood memory;
A second allocator that distributes the posterior value obtained in the process of iterative decoding to each of the channel value update units according to usage rules of the channel value update unit;
A multiplexer that multiplexes the channel value series created by each of the channel value update units;
A demodulating device comprising: In an encoding device that creates an encoded bit sequence from an information bit sequence and a parity bit sequence by error correction encoding capable of iterative decoding,
An equal interval puncturing unit that thins out parity bits at equal intervals from the parity bit sequence obtained in the encoding process;
A bit rearrangement multiplexer that performs bit reordering, sequence division and multiplexing on the bit sequence after decimation and the information bit sequence to create the encoded bit sequence;
An encoding device comprising: In a demodulator that receives a modulation symbol mapped with an encoded bit sequence that has been subjected to error correction coding that can be repeatedly decoded by an encoder, and that performs iterative decoding and demodulation on the received symbol,
A symbol likelihood calculator for calculating the likelihood of each received symbol from the received symbol sequence;
At least two channel value update units that create channel values using the likelihood, and
A symbol likelihood memory for storing the likelihood;
A first allocator that distributes the likelihood read from the symbol likelihood memory to each of the channel value update units according to a usage rule of the channel value update unit;
An arrangement of communication channel values corresponding to the bit rearrangement rule in the encoding device with respect to the communication channel value sequence provided for each of the communication channel value updating units and created by the communication channel value updating unit. A channel value sorter for performing a change,
A multiplexer that multiplexes the channel value series created by each of the channel value rearrangers by a method corresponding to a sequence division rule in the encoding device;
An equal interval depuncture unit that performs parity bit interpolation corresponding to a parity bit equal interval thinning rule in the encoding device for the channel value series created by the multiplexer,
A demodulating device comprising: In a demodulator that receives a modulation symbol mapped with an encoded bit sequence that has been subjected to error correction coding that can be repeatedly decoded by an encoder, and that performs iterative decoding and demodulation on the received symbol,
A symbol likelihood calculator for calculating the likelihood of each received symbol from the received symbol sequence;
A symbol likelihood memory that is provided corresponding to each of the channel value update units and stores the likelihood;
At least two channel value update units that create channel values using the posterior value obtained in the iterative decoding process and the likelihood read from the symbol likelihood memory;
A first allocator that distributes the likelihood of the calculation result of the symbol likelihood calculator to each of the symbol likelihood memories according to a use rule of a channel value update unit corresponding to the symbol likelihood memory;
An arrangement of communication channel values corresponding to the bit rearrangement rule in the encoding device with respect to the communication channel value sequence provided for each of the communication channel value updating units and created by the communication channel value updating unit. A channel value sorter for performing a change,
A multiplexer that multiplexes the channel value series created by each of the channel value rearrangers by a method corresponding to a sequence division rule in the encoding device;
An equal interval depuncture unit that performs parity bit interpolation corresponding to a parity bit equal interval thinning rule in the encoding device for the channel value series created by the multiplexer,
A demodulating device comprising: The demodulator performs repetitive demodulation, and
The channel value updating unit creates a channel value using the posterior value obtained in the iterative decoding process and the likelihood,
The posterior value obtained in the process of the iterative decoding is further provided with a second allocator that distributes the posterior value to each of the channel value update units according to a usage rule of the channel value update unit. The demodulator according to claim 4 or 5. A demodulation method for receiving a modulation symbol to which a coded bit sequence subjected to error correction coding capable of iterative decoding is mapped, and performing iterative decoding and iterative demodulation on the received symbol,
Calculating the likelihood of each received symbol from the received symbol sequence;
Storing the likelihood in a memory;
A first distribution process of distributing the likelihood read from the memory to each of the channel value update processes according to a usage rule of the channel value update process;
A second distribution process of distributing the posterior value obtained in the iterative decoding process to each of the channel value update processes according to the usage rules of the channel value update process;
At least two channel value update processes for creating a channel value using the likelihood received from the first distribution process and the posterior value received from the second distribution process;
Multiplexing the channel value sequence created in each of the channel value updating steps;
The demodulation method characterized by including. A demodulation method for receiving a modulation symbol to which a coded bit sequence subjected to error correction coding capable of iterative decoding is mapped, and performing iterative decoding and iterative demodulation on the received symbol,
Calculating the likelihood of each received symbol from the received symbol sequence;
The likelihood of the calculation result of the symbol likelihood calculator is distributed and stored in each of the memories provided corresponding to each of the channel value update units according to the usage rule of the channel value update unit corresponding to the memory. The first sorting process,
A second distribution process of distributing the posterior value obtained in the iterative decoding process to each of the channel value update processes according to the usage rules of the channel value update process;
At least two channel value update processes for creating a channel value using the likelihood read from the memory and the posterior value received from the second distribution process;
Multiplexing the channel value sequence created in each of the channel value updating steps;
The demodulation method characterized by including. An encoding method for generating an encoded bit sequence from an information bit sequence and a parity bit sequence by error correction encoding capable of iterative decoding,
From the parity bit sequence obtained in the encoding process, a process of thinning out parity bits at equal intervals;
For the bit sequence after decimation and the information bit sequence, a process of rearranging bits, dividing and multiplexing the sequence to create the encoded bit sequence;
The encoding method characterized by including. A demodulation method for receiving a modulation symbol to which a coded bit sequence subjected to error correction coding that can be repeatedly decoded by an encoding device is mapped, and repeatedly decoding and demodulating the received symbol,
Calculating the likelihood of each received symbol from the received symbol sequence;
Storing the likelihood in a memory;
A first distribution process of distributing the likelihood read from the memory to each of the channel value update processes according to a usage rule of the channel value update process;
At least two channel value update processes for creating a channel value using the likelihood received from the first distribution process;
An array of channel values corresponding to the bit rearrangement rule in the encoding device with respect to the channel value series provided in each of the channel value updating processes and created in the channel value updating process. A channel value rearrangement process for performing the replacement,
Multiplexing process for multiplexing the channel value sequence created in each of the channel value rearrangement processes by a method corresponding to the sequence division rule in the encoding device;
A process of interpolating parity bits corresponding to the equal interval decimation rule of parity bits in the encoding device for the channel value series created in the multiplexing process;
The demodulation method characterized by including. A demodulation method for receiving a modulation symbol to which a coded bit sequence subjected to error correction coding that can be repeatedly decoded by an encoding device is mapped, and repeatedly decoding and demodulating the received symbol,
Calculating the likelihood of each received symbol from the received symbol sequence;
The likelihood of the calculation result of the symbol likelihood calculator is distributed and stored in each of the memories provided corresponding to each of the channel value update units according to the usage rule of the channel value update unit corresponding to the memory. The first sorting process,
At least two channel value update processes for creating a channel value using the likelihood read from the memory;
An array of channel values corresponding to the bit rearrangement rule in the encoding device with respect to the channel value series provided in each of the channel value updating processes and created in the channel value updating process. A channel value rearrangement process for performing the replacement,
Multiplexing process for multiplexing the channel value sequence created in each of the channel value rearrangement processes by a method corresponding to the sequence division rule in the encoding device;
A process of interpolating parity bits corresponding to the equal interval decimation rule of parity bits in the encoding device for the channel value series created in the multiplexing process;
The demodulation method characterized by including. A demodulation method for performing repetitive demodulation,
The channel value update process creates a channel value using the posterior value obtained in the iterative decoding process and the likelihood,
11. The method according to claim 10, further comprising a second distribution step of distributing the posterior value obtained in the iterative decoding process to each of the channel value update processes according to a usage rule of the channel value update process. Alternatively, the demodulation method according to claim 11.

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