JP2008177423A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device reduced in power consumption while reducing an adverse effect on the operating speed. <P>SOLUTION: The semiconductor device has: first layout regions 11a and 11b where a first circuit group for clock generation to which a first power supply (VDD-A) is delivered is arranged along a first direction; and second layout regions 12a and 12b where a second circuit group to which a second power supply (VDD-B) higher than the voltage VDD-A is delivered is arranged along the first direction. Each of the layout regions 11a, 11b, 12a and 12b is alternately arranged along a second direction approximately perpendicular to the first direction with a common ground wire (GND) arranged along the first direction sandwiched therebetween. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a large-scale semiconductor device that requires low power consumption.

  In recent years, the system scale of portable system LSIs has expanded due to higher functionality, and low power consumption design for battery driving is required. Further, even in a large-scale and high-speed high-end system LSI product, the total power becomes too large, and a design for reducing power consumption is required for packaging and reliability. For this reason, a technique called gated clock or Conditional-Clock-Flip Flop (see, for example, “Patent Document 1”) is realized. Also, it is executed that the power supply is shut off when the operation is not performed in units of blocks.

  The gated clock is a technology that stops the operation of the system and saves power consumption when it is not necessary. Also, Conditional-Clock-Flip Flop is different from the data in the flip-flop. This is a technology to reduce power consumption by supplying a clock.

However, conventional semiconductor devices using these technologies have a problem that power consumption cannot be reduced when the system operation is active. Especially for system LSI products that require high-speed operation, the operation speed will be affected, so the method of lowering the power supply voltage that is most effective for reducing power consumption cannot be used, and both high-speed operation and low power consumption are compatible. There was a problem that it was difficult to do.
JP 2005-293372 A

  The present invention provides a semiconductor device capable of reducing power consumption while suppressing the influence on the operation speed.

  According to one aspect of the present invention, a first layout region in which a first power source is supplied and a first circuit group for generating a clock is arranged along a first direction, and the first power source is provided. A second circuit group to which a second power source having a higher voltage is supplied has a second layout region arranged along the first direction, and a plurality of the first and second layout regions Are alternately arranged along a second direction substantially perpendicular to the first direction across a common ground line arranged along the first direction. Is provided.

  According to the present invention, the circuit group for generating the clock is laid out separately from the others, so that it is possible to reduce the power consumption of the semiconductor device while suppressing the influence on the operation speed.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a layout diagram showing a semiconductor device according to Embodiment 1 of the present invention. Here, as an example, the case where the layout areas of the circuit group for clock generation and the other circuit groups are substantially equal is shown.

  The semiconductor device according to the first embodiment of the present invention includes first layout regions 11a and 11b in which circuit groups for generating clocks are arranged, second layout regions 12a and 12b in which other logic circuit groups are arranged, And a common ground wiring GND.

  In the first and second layout regions 11a, 11b and 12a, 12b, the circuits are arranged along the X direction (the left-right direction in the drawing, hereinafter also referred to as the longitudinal direction), and extend along the longitudinal direction. They are alternately arranged along the Y direction (up and down direction in the drawing) across the existing GND wiring.

  That is, as shown in FIG. 1, the first layout area 11a, the GND wiring, the second layout area 12a, the GND wiring, the first layout area 11b, the GND wiring, and the second layout area along the Y direction. They are arranged in the order of 12b.

  The GND wiring is shared by the adjacent first layout region 11a or 11b and the second layout region 12a or 12b, and is used as a common ground wiring.

  In the first layout regions 11a and 11b, first layout columns 13a to 13d including a clock circuit (CLK circuit) and a flip-flop circuit (F / F circuit) for generating a clock signal, and a circuit group thereof A dedicated power supply wiring VDD-A for supplying power to is arranged.

  The first layout region 11a includes two first layout columns 13a and 13b and a VDD-A wiring extending in the longitudinal direction thereof. The first layout columns 13a and 13b include the VDD-A wiring. Are arranged opposite to each other. The VDD-A wiring is shared by the first layout columns 13a and 13b.

  Similarly, the first layout region 11b includes first layout columns 13c and 13d and a VDD-A wiring, and the first layout columns 13c and 13d are arranged to face each other with the VDD-A wiring interposed therebetween. Has been. The VDD-A wiring is shared by the first layout columns 13c and 13d.

  In the second layout regions 12a and 12b, second layout columns 14a to 14d composed of other logic circuits not directly related to the generation of the clock signal, and dedicated power supply wiring VDD− for supplying power to these circuit groups are provided. B is arranged.

  The second layout region 12a is composed of two second layout columns 14a and 14b and a common VDD-B wiring extending in the longitudinal direction, and the second layout columns 14a and 14b are VDD− They are arranged facing each other across the B wiring.

  Similarly, the second layout region 12b is configured by the second layout columns 14c and 14d and the common VDD-B wiring, and the second layout columns 14c and 14d are opposed to each other with the VDD-B wiring interposed therebetween. Are arranged.

  A power supply voltage higher than the voltage supplied to the VDD-A wiring is supplied to the VDD-B wiring.

  In this way, a low power supply voltage is supplied to the first layout regions 11a and 11b, which are related to the generation of the clock signal and have relatively large power consumption, by the VDD-A wiring, and the second layout region is not directly related to the generation of the clock signal. By supplying a higher power supply voltage to the layout regions 12a and 12b through the VDD-B wiring, both low power consumption and high-speed operation are achieved.

  According to the first embodiment, the circuit group for generating the clock is laid out as the layout columns 11a to 11d separately from the other logic circuit groups (layout columns 12a to 12d), thereby suppressing the influence on the operation speed. In addition, the power consumption of the semiconductor device can be reduced.

  FIG. 2 is a layout diagram showing a semiconductor device according to Embodiment 2 of the present invention. In the present embodiment, an example of the layout configuration in the case where the layout area of the circuit group for clock generation is larger than the layout area of the other circuit groups is shown.

  The semiconductor device according to the second embodiment of the present invention includes first layout regions 21a and 21b in which circuit groups for generating clocks are arranged, second layout regions 22a and 22b in which other logic circuit groups are arranged, And a common ground wiring GND.

  In the first and second layout regions 21a, 21b and 22a, 22b, circuits are arranged along the X direction (left and right direction in the drawing, also referred to as the longitudinal direction hereinafter), and extend along the longitudinal direction. They are alternately arranged along the Y direction (up and down direction in the drawing) across the existing GND wiring.

  That is, as shown in FIG. 2, the first layout area 21a, the GND wiring, the second layout area 22a, the GND wiring, the first layout area 21b, the GND wiring, and the second layout area along the Y direction. Arranged in the order of 22b.

  The GND wiring is shared by the adjacent first layout region 21a or 21b and the second layout region 22a or 22b, and is used as a common ground wiring.

  Since the layout configuration of the first layout area 21a and the second layout areas 22a and 22b is the same as that of the first embodiment, detailed description thereof is omitted. The difference between the present embodiment and the first embodiment is that the first layout region 21b is composed of four first layout columns 23c to 23f.

  In the first layout region 21b, first layout columns 23c to 23f including a clock circuit (CLK circuit) and a flip-flop circuit (F / F circuit) for generating a clock signal, and power to these circuit groups are supplied. A dedicated power supply wiring VDD-A to be supplied and a dedicated ground wiring GND-A shared by the first layout columns 23d and 23e are arranged.

  The first layout region 21b includes four first layout columns 23c to 23f, two VDD-A wirings extending in the longitudinal direction, and a dedicated GND-A wiring. 23c and 23d are arranged to face each other across one VDD-A wiring, and the first layout columns 23e and 23f are arranged to face each other across another VDD-A wiring. A GND-A wiring extending in the longitudinal direction is arranged between the rows 23d and 23e.

  As described above, in the second embodiment, the first layout region 21b is configured by the four first layout columns 23c to 23f, so that the layout area of the circuit group for clock generation is the layout area of the other circuit groups. It corresponds to the case of larger.

  According to the second embodiment, the same effect as that of the first embodiment can be obtained even when the layout area of the circuit group for generating the clock is larger than the layout areas of the other circuit groups.

  In the description of the second embodiment, the first layout region 21b has the four first layout columns 23c to 23f. However, the present invention is not limited to this, and many first layout regions are included. A layout column can also be arranged in the first layout region 21b. If necessary, more first layout columns can be arranged in the first layout region 21a.

  FIG. 3 is a layout diagram showing a semiconductor device according to Embodiment 3 of the present invention. In this embodiment, an example of the layout configuration in the case where the layout area of the circuit group for generating the clock is smaller than the layout area of the other circuit groups is shown.

  The semiconductor device according to the third embodiment of the present invention includes first layout regions 31a and 31b in which circuit groups for generating clocks are arranged, second layout regions 32a and 32b in which other logic circuit groups are arranged, And a common ground wiring GND.

  In the first and second layout regions 31a, 31b and 32a, 32b, circuits are arranged along the X direction (left and right direction in the drawing, also referred to as the longitudinal direction hereinafter), and extend along the longitudinal direction. They are alternately arranged along the Y direction (up and down direction in the drawing) across the existing GND wiring.

  That is, as shown in FIG. 3, the first layout region 31a, the GND wiring, the second layout region 32a, the GND wiring, the first layout region 31b, the GND wiring, and the second layout region along the Y direction. They are arranged in the order of 32b.

  The GND wiring is shared by the adjacent first layout region 31a or 31b and the second layout region 32a or 32b, and is used as a common ground wiring.

  Since the layout configurations of the first layout areas 31a and 31b and the second layout area 32b are the same as those in the first embodiment, detailed description thereof is omitted. The difference between the present embodiment and the first embodiment is that the second layout region 32a is composed of four second layout columns 34a to 34d.

  In the second layout region 32a, second layout columns 34a to 34d composed of other clock circuits not directly related to the generation of the clock signal, a dedicated power supply wiring VDD-B for supplying power to these circuit groups, and A dedicated ground wiring GND-B shared by the second layout columns 34b and 34c is arranged.

  The second layout region 32a includes four second layout columns 34a to 34d, two VDD-B wirings extending in the longitudinal direction thereof, and a dedicated GND-B wiring. 34a and 34b are arranged opposite to each other across one VDD-B wiring, and the second layout columns 34c and 34d are arranged opposite to each other across another VDD-B wiring, and the second layout is arranged. A GND-B wiring extending in the longitudinal direction is disposed between the rows 34b and 34c.

  As described above, in the third embodiment, the second layout region 32a is configured by the four second layout columns 34a to 34d, so that the layout area of the circuit group for clock generation is the layout area of the other circuit groups. It corresponds to the case of smaller.

  According to the third embodiment, even when the layout area of the circuit group for generating the clock is smaller than the layout areas of the other circuit groups, the same effect as in the first embodiment can be obtained.

  In the above description of the third embodiment, the second layout region 32a has the four second layout columns 34a to 34d. However, the present invention is not limited to this, and many second layout regions 34a to 34d are provided. The layout column can also be arranged in the second layout area 32a. If necessary, more second layout columns can be arranged in the second layout region 32b.

  Furthermore, in the description of the first to third embodiments, the semiconductor device is provided with four layout regions. However, the present invention is not limited to this, and any two or more layout regions may be used. The same arrangement can be made for a number of layout areas.

  Further, in the above description of the first to third embodiments, the first layout area has a circuit group for generating a clock, and the second layout area has another logic circuit group. For example, any logic circuit that does not affect high-speed operation even when the power supply voltage is lowered can be arranged in the first layout region.

1 is a layout diagram showing a semiconductor device according to Embodiment 1 of the present invention. FIG. 6 is a layout diagram illustrating a semiconductor device according to a second embodiment of the present invention. FIG. 6 is a layout diagram illustrating a semiconductor device according to a third embodiment of the present invention.

Explanation of symbols

11a, 11b, 21a, 21b, 31a, 31b First layout regions 12a, 12b, 22a, 22b, 32a, 32b Second layout regions 13a-13d, 23a-23f, 33a-33d First layout columns 14a- 14d, 24a to 24d, 34a to 34f Second layout column VDD-A, VDD-B Dedicated power supply wiring GND Common ground wiring GND-A, GND-B Dedicated ground wiring

Claims (5)

A first layout region in which a first power supply is supplied and a first circuit group for generating a clock is arranged along a first direction;
A second circuit group to which a second power source having a voltage higher than that of the first power source is supplied has a second layout region arranged along the first direction;
A plurality of the first and second layout regions are alternately arranged along a second direction substantially orthogonal to the first direction across a common ground line disposed along the first direction. A semiconductor device which is arranged. The first layout area is
A first power supply line disposed along the first direction and supplied with the first power;
The first circuit group includes two layout columns arranged along the first direction;
2. The semiconductor device according to claim 1, wherein the two layout columns share the first power supply wiring and are arranged along the second direction with the power supply wiring interposed therebetween. . The second layout area is
A second power supply line disposed along the first direction and supplied with the second power;
The second circuit group includes two layout columns arranged along the first direction;
2. The semiconductor device according to claim 1, wherein the two layout columns share the second power supply wiring and are arranged along the second direction with the power supply wiring interposed therebetween. . The first layout area is
A plurality of first power supply wirings arranged along the first direction and supplied with the first power;
A dedicated ground wiring disposed along the first direction;
The first circuit group includes a plurality of layout columns arranged along the first direction;
The plurality of layout columns share the first power supply wiring and the dedicated ground wiring arranged alternately along the second direction, and the second power supply wiring and the ground wiring are sandwiched between the second power supply wiring and the ground wiring. The semiconductor device according to claim 1, wherein the semiconductor device is disposed along the direction of The second layout area is
A plurality of second power supply wirings arranged along the first direction and supplied with the second power;
A dedicated ground wiring disposed along the first direction;
The second circuit group includes a plurality of layout columns arranged along the first direction;
The plurality of layout columns share the first power supply wiring and the dedicated ground wiring arranged alternately along the second direction, and the second power supply wiring and the ground wiring are sandwiched between the second power supply wiring and the ground wiring. The semiconductor device according to claim 1, wherein the semiconductor device is disposed along the direction of

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