JP2008176060A - Active matrix display device and display method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix display device reduced in display unevenness due to the characteristic variation of a driving thin-film transistor even in the video of a low gradation, and its display method. <P>SOLUTION: The active matrix display device includes: a display section 100 in which pixel sections PX including driving transistors DTr for driving display elements OLED are arranged in a matrix on a substrate; signal lines DL which are disposed for every column and are connected to the respective pixel sections of each column; a gradation signal output section DO which outputs a gradation signal corresponding to the video signal to the pixel section via the signal line; and reset output sections (220, 240, 241, RST) which output reset signals for making the pixel section hold the prescribed gradation voltages via the signal lines. The reset output sections are made to flow two steps of currents to the signal lines as reset signals and make the pixel section hold the gradation voltages reflecting the variation in the characteristics of the driving transistors. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an active matrix display device and a display method thereof, and more particularly to an active matrix display device and a display method thereof that can maintain display quality even if the characteristics of TFTs (thin film transistors) vary.

Active matrix display devices using organic EL elements have been developed. In this apparatus, it is required that the characteristics of a thin film transistor for driving an organic EL element, that is, a drive transistor, be substantially the same between pixels.
However, since the thin film transistor is usually formed on an insulator such as a glass substrate, the characteristics of the drive transistor often vary between pixels.

Patent Document 1 describes an active matrix organic EL display device that employs a current copy type circuit as a pixel circuit. In this display device, a current signal is supplied to each pixel as a video signal, and a driving current having a magnitude corresponding to the current signal is supplied to the organic EL element to cause the organic EL element to emit light. According to this technique, it is possible to reduce the influence of the variation in the characteristics of the drive transistor on the magnitude of the drive current.
US Pat. No. 6,373,454

  By the way, in this current copy type circuit, before the video signal is written to the pixel circuit via the signal line, the potential of the signal line and the gate terminal of the driving thin film transistor of the selected pixel circuit is once set to the reference potential. .

  Normally, the potential of the lowest gradation level is written from the constant voltage source to the signal line and the gate terminal of the driving thin film transistor of the selected pixel circuit regardless of the video signal for each line. The supplied minimum gradation level potential is the same potential in each pixel circuit. That is, the supplied minimum gradation level potential is not a potential obtained by correcting the variation in the threshold value of the driving thin film transistor of each pixel. For this reason, there are variations in the performance of the driving thin film transistor such as threshold value and mobility, so that the brightness of each pixel is different and display unevenness occurs in low gradation raster display.

  The present invention has been made in view of the above problems, and provides an active matrix display device and a display method therefor, which have less display unevenness due to characteristic variations of driving thin film transistors even for low-gradation images. With the goal.

  In order to solve the above problems, an active matrix display device according to the present invention includes a display unit in which a pixel unit including a driving transistor for driving a display element is arranged in a matrix on a substrate, and is provided for each column. A signal line connected to each pixel portion of the column; a gradation signal output portion that outputs a gradation signal corresponding to a video signal to the pixel portion via the signal line; and the pixel portion via the signal line And a reset output unit for outputting a reset signal for holding a predetermined gradation voltage, and the reset output unit applies a two-stage current to the signal line as the reset signal, thereby causing variations in characteristics of the drive transistor. This is an active matrix display device in which a gradation voltage reflecting the above is held in the pixel portion.

  Further, in the display method according to the present invention, pixel portions including driving transistors for driving display elements are arranged in a matrix on a substrate, signal lines are provided for each column, and connected to the respective pixel portions in each column, A gradation signal corresponding to the video signal is output to the pixel portion via the signal line, a reset signal for holding a predetermined gradation voltage is output to the pixel portion via the signal line, and the reset signal is output. In the display method of the active matrix display device, a two-step current is supplied to the signal line as the reset signal, and a gradation voltage reflecting a variation in characteristics of the driving transistor is held in the pixel portion.

  According to the present invention, it is possible to provide an active matrix display device and a display method thereof that can maintain a display quality even if it is a low-gradation image and is affected by variations in characteristics of driving thin film transistors.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same referential mark is attached | subjected to the component which exhibits the same or similar function, and the overlapping description is abbreviate | omitted.
In the following embodiments, an organic EL display device will be described among the active matrix display devices, but the present invention is not limited to the organic EL.

  FIG. 1 is a block diagram schematically showing an active matrix display device according to an embodiment of the present invention. The display device 10 is a bottom emission organic EL display device that employs an active matrix driving method.

On the insulating support substrate 100 such as glass of the display device 10, pixel portions PX (1,1), PX (2,1),..., A plurality of pixel selection scanning lines S1a, S2a,. ..., a plurality of light control scanning lines S1b, S2b, ..., a plurality of signal lines DL1, DL2, ... are provided.
Further, on the insulating support substrate 100, a signal line driving circuit 101, a pixel selection scanning line driving circuit 130, a dimming scanning line driving circuit 140, and a system control unit 120 are provided as driving circuits.

  The pixel unit PX includes an organic EL element and a pixel drive circuit, and is disposed in the vicinity of the intersection of the pixel selection scanning line (dimming scanning line) and the signal line. Details of the configuration of the pixel unit PX will be described later.

  The signal line driver circuit 101 is connected to signal lines DL1, DL2, DL3,... Provided for each pixel column. As shown in FIG. 1, each of the signal lines DL1, DL2,... Extends in the column direction (Y direction) of the pixel portion PX, and is alternately arranged in the pixel portion PX and the row direction (X direction). ing. These signal lines DL1, DL2,... Are connected to the signal line driving circuit 101 and the pixel portion PX in each column.

  The pixel selection scanning line driving circuit 130 is connected to a scanning line provided for each pixel row. Since the configuration of the scanning line corresponding to one pixel row differs depending on the type of the pixel driving circuit, one pixel selection scanning line Sla, S2a,... As shown in FIG. 1, each of the pixel selection scanning lines S1a, S2a,... Extends in the row direction (X direction) of the pixel portion PX, and alternately in the pixel portion PX and the column direction (Y direction). Arranged. These pixel selection scanning lines S1a, S2a,... Are connected to the pixel selection scanning line driving circuit 130 and the pixel portion PX of each row.

  The dimming scanning line driving circuit 140 is connected to a scanning line provided for each row of pixels. Since the configuration of the scanning line corresponding to one pixel row differs depending on the type of the pixel driving circuit, one pixel selection scanning line S1b, S2b,... As shown in FIG. 1, each of the light control scanning lines S1b, S2b,... Extends in the row direction (X direction) of the pixel portion PX, and alternately in the pixel portion PX and the column direction (Y direction). Arranged.

  The signal line driving circuit 101, the pixel selection scanning line driving circuit 130, and the dimming scanning line driving circuit 140 are driven by timing pulses from the system control unit 120. A timing signal and a clock signal synchronized with the video signal are supplied to the system control unit 120 via the input terminals 103 and 104. Therefore, the system control unit 120 can give various timing pulses synchronized with the video signal to the signal line driving circuit 101, the pixel selection scanning line driving circuit 130, and the dimming scanning line driving circuit 140.

  The pixel selection scanning line driving circuit 130 selects a plurality of pixel units PX arranged in the row direction (X direction) in order to store the video signal. When the pixel selection scanning line driving circuit 130 selects any one of the pixel selection scanning lines S1a, S2a,... To be in an active state, a plurality of pixel portions PX connected to the pixel selection scanning line that is in an active state are displayed. The video signal (which may be referred to as image data) can be stored.

The signal line driver circuit 101 takes in a video signal via the input terminal 102. The captured video signal is converted into a video signal current for each pixel unit PX in the row direction (X direction) and output to the corresponding signal lines DL1, DL2,. The pixel portion PX in the active state takes in and stores the video signal current via the corresponding signal lines DL1, DL2,.
When the video signal required for the nth line is supplied to each pixel unit PX of the nth line via the corresponding signal lines DL1, DL2,..., the video required for the next n + 1th line A signal is supplied to each pixel unit PX of the (n + 1) th line via corresponding signal lines DL1, DL2,. The pixel selection scanning lines S1a, S2a,... Are selected by the pixel selection scanning line driving circuit 130.

The dimming scanning line driving circuit 140 designates timing for supplying a light emission current corresponding to the video signal stored in each pixel unit PX to the organic EL element.
A timing signal and a clock signal synchronized with the video signal are supplied to the system control unit 120 via the input terminals 103 and 104. Based on the timing signal and the clock signal, the system control unit 120 performs various timing signals for causing the signal line driving circuit 101, the pixel selection scanning line driving circuit 130, and the dimming scanning line driving circuit 140 to display an image. Is output.

Although not shown, the signal line driving circuit 101, the pixel selection scanning line driving circuit 130, the dimming scanning line driving circuit 140, and the system control unit 120 are also led to a power supply line for supplying power. .
In addition, the signal line driver circuit 101, the pixel selection scanning line driving circuit 130, the dimming scanning line driving circuit 140, and the system control unit 120 may be formed on the substrate 100, and are provided outside the substrate 100 as external ICs. May be.

  FIG. 2 shows a configuration example of the pixel portions PX (1,1), PX (2,1), and PX (3,1) connected to the signal lines DL1, DL2, and DL3. Hereinafter, the pixel portion PX (1, 1) will be described as a representative.

  The OLED 1 is a display element including a photoactive layer between a pair of opposed electrodes. The cathode of the display element OLED1 is connected to the power supply PVSS, and the anode is connected to the power supply line PVDD via a pixel circuit for driving the element. Here, the display element is an organic EL element including at least an organic light emitting layer as a photoactive layer. For example, organic EL elements that emit red, green, and blue light are arranged in a predetermined order on the substrate 100.

  The pixel circuit includes a pixel selection switch SW1, a driving thin film transistor DTr, a correction switch SW2, and an output switch SW3. For example, these are configured by p-channel thin film transistors. Further, a capacitor CO that can hold the gate-source voltage of the driving thin film transistor DTr is provided.

  The organic EL element is connected to the drain of the driving thin film transistor DTr via the output switch SW3, and the source of the driving thin film transistor DTr is connected to the power supply line PVDD. The gate of the driving thin film transistor DTr is connected to the capacitor CO and the drain of the correction switch SW2. The correction switch SW2 is connected between the gate and drain of the driving thin film transistor DTr, and the gate thereof is connected to the pixel selection scanning line Sla. The pixel selection switch SW1 is connected between the signal line and the drain of the driving thin film transistor DTr, and the gate thereof is connected to the pixel selection scanning line Sla. The output switch SW3 is connected between the drain of the driving thin film transistor DTr and the organic EL element, and the gate thereof is connected to the dimming scanning line S1b.

Next, the operation of the pixel unit PX in the video signal writing period and the video display period will be described.
The signal line driver circuit 101 generates a gradation current and supplies it as a video signal current to the signal line DL1. In the pixel PX (1, 1), the pixel selection switch SW1 and the correction switch SW2 are turned on, and the gate-source voltage of the driving thin film transistor DTr is written in the capacitor C0 by the video signal current supplied from the signal line DL1.

FIG. 3 is a diagram showing each circuit of the signal line driver circuit 101 connected to the signal lines.
The signal line drive circuit 101 includes data output units DO1, DO2,..., Signal line reset circuits RST1, RST2,..., A signal line reset control circuit 220, a minimum gradation reset current source 240, and a maximum gradation reset. A current source 241 is provided.

  The data output units DO1, DO2,... Capture the video signal DATA through the input terminals. The captured video signal DATA is converted into a video signal current for each pixel unit PX in the row direction (X direction) in the data output units DO1, DO2,..., And the corresponding signal lines DL1, DL2,. Is output.

The lowest gradation reset current source 240 passes a current for setting the signal line to the lowest gradation voltage (hereinafter referred to as the lowest gradation current Iprst) as a reset current to each of the signal lines DL1, DL2,. Current source. The highest gradation reset current source 241 passes a current for setting the signal line to the highest gradation voltage (hereinafter referred to as the highest gradation current Inrst) as a reset current to the respective signal lines DL1, DL2,. Current source.
The signal line reset circuits RST1, RST2,... Flow the lowest gradation current Iprst or the highest gradation current Inrst through the signal lines DL1, DL2,. The signal line reset control circuit 220 controls the operation of the signal line reset circuits RST1, RST2,.

  First, the configuration and operation of the data output unit DO1 will be described as a representative.

The data output unit DO1 includes a multiplexer 200, switches 201, 202,..., 208, and thin film transistors 211, 212,.
The multiplexer 200 takes in pixel data of a predetermined one pixel unit from one line of image data DATA which is a serial signal supplied from an input terminal. In the example shown in FIG. 3, the multiplexer 200 converts the pixel data into an 8-bit digital signal and outputs the result as the on / off states of the switches 201, 202,. That is, the multiplexer 200 converts a serial signal into a parallel signal.

  One terminal of the switches 201, 202,... Is commonly connected to the signal line DL1, and the other terminal is connected to the sources of the thin film transistors 211, 212,.

The drains of the thin film transistors 211, 212,... Are commonly connected to a ground line (GND), and the gates of the thin film transistors 211, 212,.
On the other hand, the drain of the thin film transistor 219 is connected to the earth line (GND), and the gate and the drain are connected to constitute a constant current source. Further, the source of the thin film transistor 219 is connected to the power supply line PVDD.

  Accordingly, with this configuration, the thin film transistors 211, 212,..., 219 form a current mirror circuit, and the thin film transistors 211, 212,. While in the on state, currents having a magnitude of 1 times, 2 times, 4 times,... Of the reference current Iref flowing through the thin film transistor 219 are output. Thereby, a current corresponding to the gradation of the pixel data flows through the signal line DL1.

  Next, the configuration and operation of the signal line reset circuit RST1 will be described as a representative.

The signal line reset circuit RST1 is provided with a reset switch SWP for resetting the lowest gradation and a reset switch SWN for resetting the highest gradation. These reset switches SWP and SWN are switches that are turned on and off in accordance with a signal from the signal line reset control circuit 220.
When the lowest gradation signal line PRST becomes active and the reset switch SWP is turned on, the lowest gradation current Iprst flows through the signal line DL1. When the highest gradation signal line NRST becomes active and the reset switch SWN is turned on, the highest gradation current Inrst flows through the signal line DL1.

FIG. 4 is a time chart showing a current reset operation of the active matrix display device according to the embodiment of the present invention.
FIG. 4 shows a pixel selection scanning line (S (n) a, S (n + 1) a), a reset switch signal (SWP, SWN), a load signal (LOAD), and a signal line voltage in one horizontal scanning period of the nth row. The waveform is shown.
These operations are controlled by the system control unit 120 in an integrated manner.

  When the nth pixel selection scanning line Sna of the pixel selection scanning line driving circuit 130 is activated, a plurality of pixel units PX connected to the pixel selection scanning line Sna are in a state where they can store reset signals and video signals.

First, when the signal line reset control circuit 220 activates the highest gradation signal line NRST, the reset switch SWN is turned on and the highest gradation current Inrst flows through the signal line DL1.
Here, since the maximum gray-scale current Inrst flows in a direction in which the current is drawn from the pixel circuit, the gate potential of the driving thin film transistor DTr decreases with time, and reflects the variation in characteristics of the driving thin film transistor DTr after a predetermined time elapses. Voltage is maintained.

Next, when the signal line reset control circuit 220 activates the lowest gradation signal line PRST, the reset switch SWP is turned on, and the lowest gradation current Iprst flows through the signal line DL1.
Here, since the lowest gradation current Iprst flows in a direction in which current is added to the pixel circuit, the gate potential of the driving thin film transistor DTr rises with time, and the characteristics of the driving thin film transistor DTr vary after a predetermined time. The reflected black voltage is maintained.

  After the signal reset period has elapsed, a load signal (LOAD) is input to the multiplexer 200. As a result, the signal line is set to a potential corresponding to the gradation of the pixel data by the above-described operation.

  In the embodiment of the present invention, the current reset operation is executed in two stages as shown in FIG. Hereinafter, the basic concept of performing the current reset operation in two stages will be described.

  The above-described two-stage current reset method has been developed with the aim of performing a reset operation using a common current source even when there are variations in the characteristics of the individual driving thin film transistors DTr. The following description is for a P-channel transistor.

  Each pixel before the reset operation is in a state in which one of white and black gradation voltages is held. Therefore, if the current is used to maintain the black gradation voltage, the pixel potential is increased by adding the current from the outside. However, just adding the current for a predetermined time in this manner is the same as that due to the voltage reset, and the variation in the characteristics of the drive transistor cannot be eliminated.

Therefore, the highest gradation current Inrst is first pulled by the highest gradation reset operation. In a state where the voltage of the signal line is stable after a lapse of a predetermined time, the voltage reflecting the variation in characteristics of the driving thin film transistor DTr is held.
Next, the lowest gradation current Iprst is added for a predetermined time by the lowest gradation reset operation. By this lowest gradation reset operation, a predetermined voltage is added to the voltage held in the highest gradation reset operation. As a result, it is possible to generate a black voltage that takes into account variations in the characteristics of the driving thin film transistor DTr.

Here, rewriting of the voltage by the reset current will be described.
In general, the relationship represented by Expression (1) is established between Q: charge, C: capacitance, and V: voltage.
V = Q / C (1)
Therefore, if i is a reset current, Δt is a current duration, and ΔV is a change voltage, the relationship represented by the equation (2) is established.
ΔV = (i × Δt) / C (2)
C represents the total sum of the capacitances of the pixels and signal lines.
Therefore, the amount of voltage change can be controlled by controlling the reset current i and the current duration Δt.

  Since the capacitance C varies depending on the type and size of the panel, an appropriate rewriting time is selected depending on the panel. However, if the voltage of the signal line becomes stable, it is not necessary to continue the current any more. Further, even if i × Δt is the same, if there is a margin in time, the display quality becomes better because ΔV can be controlled with higher accuracy by reducing the current value and increasing the writing time.

  Therefore, in the above-described embodiment, the highest gradation current Inrst and the lowest gradation current Iprst are passed. However, the highest gradation current Inrst and the lowest gradation current Iprst do not need to be sufficient, and it is sufficient in one horizontal scanning period. The reset current may be determined by the time Δt during which the reset operation can be performed. This Δt can be set for each panel in advance for each of the highest gradation reset operation and the lowest gradation reset operation.

  In the highest gradation reset operation, the signal line voltage does not need to be set to the highest gradation voltage, and may be set to a voltage that reflects variations in characteristics of the driving thin film transistor Dtr. Therefore, a voltage having a gradation higher than the minimum gradation voltage may be used. However, in the lowest gradation reset operation, it is necessary to set the voltage to the lowest gradation in order to maintain the black state at the end of the signal line reset period.

  Note that the transistors in each circuit described above may be formed of N channels. At this time, the circuit configuration and the potential are opposite to those in the case of the P channel. Even in this case, the highest gradation reset operation is performed first, and then the lowest gradation reset operation is performed. Are the same.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 is a block diagram schematically showing an active matrix display device according to an embodiment of the present invention. FIG. 9 illustrates a structure of a pixel portion connected to a signal line. FIG. 9 is a diagram illustrating each circuit of a signal line driver circuit connected to a signal line. 4 is a time chart illustrating a current resetting operation of the active matrix display device according to the embodiment of the present invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Display apparatus, 101 ... Signal line drive circuit, 120 ... System control part, 130 ... Pixel selection scanning line drive circuit, 140 ... Dimming scanning line drive circuit, 200 ... Multiplexer, 201 ... Switch, 211 ... Thin-film transistor, 220 ... Signal line reset control circuit, 240 ... lowest gradation reset current source, 241 ... highest gradation reset current source, C0 ... capacitor, DL ... signal line, DTr ... driving thin film transistor, OLED ... display element, OUT01 ... output circuit, PX ... Pixel part, S1a ... Pixel selection scanning line, S1b ... Dimming scanning line, SW1 ... Pixel selection switch, SW2 ... Correction switch, SW3 ... Output switch, SWN ... Reset switch, SWP ... Reset switch.

Claims (8)

A display unit in which pixel units including a driving transistor for driving a display element are arranged in a matrix on a substrate;
A signal line provided for each column and connected to each pixel portion of each column;
A gradation signal output unit that outputs a gradation signal corresponding to a video signal to the pixel unit via the signal line;
A reset output unit that outputs a reset signal for holding a predetermined gradation voltage in the pixel unit via the signal line;
The reset output unit applies a two-step current to the signal line as the reset signal, and holds the gradation voltage reflecting the variation in characteristics of the driving transistor in the pixel unit, Display device. The reset output unit
A first current source for supplying a first reset current to the signal line;
A second current source for passing a second reset current through the signal line;
The first reset current is supplied to the signal line so that the pixel portion holds a voltage of a gray level larger than the lowest gray level, and then the pixel portion holds the voltage of the lowest gray level. The active matrix type display device according to claim 1, further comprising: a reset current control unit configured to control the flow of two reset currents.   3. The active matrix display device according to claim 2, wherein the reset current control unit controls respective times when the first and second reset currents flow.   The active matrix display device according to claim 2, further comprising a drive control unit that operates the grayscale voltage output unit after the reset output unit is operated. A pixel portion including a driving transistor for driving a display element is arranged in a matrix on a substrate,
A signal line is provided for each column and connected to each pixel portion of each column,
A gradation signal corresponding to a video signal is output to the pixel portion via the signal line,
Outputting a reset signal for holding a predetermined gradation voltage in the pixel portion via the signal line;
In the output of the reset signal, an active matrix in which a two-step current is passed through the signal line as the reset signal, and a gradation voltage reflecting variations in characteristics of the driving transistor is held in the pixel portion. Display method of type display device. In the output of the reset signal,
Using the first current source, the first reset current is supplied to the signal line so that the pixel portion holds a voltage of a gray scale larger than the lowest gray scale, and then the second current source is used. 6. The display method of an active matrix display device according to claim 5, wherein the second reset current is controlled to flow so that the pixel portion holds a voltage of the lowest gradation.   7. The display method for an active matrix display device according to claim 6, wherein the respective times for supplying the first and second reset currents are controlled.   The display method of the active matrix display device according to claim 6, wherein the grayscale voltage output operation is executed after the reset signal output operation is executed.

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