JP2008172998A - High-voltage power supply unit, image forming device, and power supply controlling method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect malfunctions and suspension of all outputs of high-voltage power supply, by a single malfunction detection circuit. <P>SOLUTION: A high-voltage power supply unit includes a first output, a second output in which an output voltage different from the first output can be set, and the single protective circuit 50 which suspends a high-voltage power circuit when the malfunctions are caused. The protective circuit 50 detects the malfunctions of the first and the second outputs by a first and a second error detection voltage generating portions (a) and (b). When the malfunctions are caused in one of the outputs, supply of power to a first and a second voltage converting portions 22, 32 is intercepted, and both of the first and the second outputs are suspended. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high-voltage power supply apparatus having a plurality of outputs, a copier equipped with the high-voltage power supply apparatus, a printer, a facsimile, an image forming apparatus such as a digital multifunction peripheral equipped with the functions of these apparatuses, and a power supply control method.

  In an image forming apparatus such as an electronic copying machine or a laser printer, a charging device, a transfer device, a developing device, and the like are incorporated. When these devices are operated, the output of the high-voltage power supply device is used. In the control device of the image forming apparatus, image forming processing is performed while adjusting the output voltage of the high-voltage power supply. In a color image forming apparatus for forming a color image composed of a plurality of colors, in order to form each color, that is, an image of C (cyan), M (magenta), Y (yellow), and K (black). A plurality of charging devices, transfer devices, developing devices and the like corresponding to each color are provided.

  For safety reasons, the high-voltage power supply is often provided with a protection circuit that stops the output of the high-voltage power supply in the event of an abnormality. However, since the high-voltage power supply of the image forming apparatus has multiple outputs, an abnormality detection circuit is provided for each output. The configuration was such that the protective operation was activated.

  As this example, for example, the invention described in Patent Document 1 or 2 is known. Among these, the invention described in Patent Document 1 is a power detection unit that detects output power in an abnormality detection method for a high-voltage power supply device that limits an output voltage or output current to a predetermined value. Detection means for detecting that the range has been exceeded is provided, and the output voltage or output current is limited or stopped by the output of the detection means.

The invention described in Patent Document 2 is a high voltage power supply device that boosts an input voltage and supplies the load to a load. The output current control means for controlling the output current to decrease for a time corresponding to the detected value, and the high voltage output operation is stopped when the repetition of the control for reducing the output current by the means continues for a certain period of time. Means.
Japanese Patent Laid-Open No. 61-210407 Japanese Patent No. 2945710

  For this reason, many parts are used, and the board size increases as the number of outputs increases.

  Therefore, a problem to be solved by the present invention is to enable detection of abnormality and stop of output of all high-voltage power supplies by a single abnormality detection circuit.

  In order to solve the above problem, the first means includes a plurality of outputs capable of setting different output voltages, and a single protection circuit that stops the output when an abnormality occurs, and the protection circuit has an abnormality. A high-voltage power supply device that stops all of the plurality of outputs is characterized.

  According to a second means, in the first means, the plurality of outputs are two outputs of a first output and a second output, and each abnormality of the first output and the second output is determined by a voltage. First and second error detection voltage generators for detection are provided, and voltages from the first and second error detection voltage generators are input to the protection circuit.

  A third means is characterized in that, in the second means, the voltages from the first and second error detection voltage generation units to the protection circuit are inputted via a Zener diode.

  According to a fourth means, in the first means, a Zener diode is provided in an input part to the abnormality detection part in the protection circuit so that the abnormality detection part side is an anode and a signal input side is a cathode. And the second output error detection voltage generator is combined into one through a diode, the cathode side of the diode is connected to the cathode of the Zener diode, and one of the error detection voltage generators exceeds a preset voltage. Then, a signal is input to the abnormality detection unit.

  A fifth means is characterized in that, in any one of the first to fourth means, when the protection circuit stops the output, the control means for controlling the value of the output voltage is turned off.

  The sixth means is characterized in that, in any one of the first to fourth means, the protection circuit drops the high voltage power supply input voltage when stopping the output.

  A seventh means is characterized in that, in any one of the first to sixth means, the protection circuit outputs a signal notifying the CPU simultaneously with the stop of the output.

  The eighth means is characterized in that, in any one of the second to fourth means, the first and second error detection voltage generating sections are arranged on the primary side of the boosting section.

  A ninth means is characterized in that, in any one of the second to fourth means, the first and second error detection voltage generating sections are arranged on the secondary side of the boosting section.

  A tenth means is characterized in that, in the first means, the protection circuit individually outputs each output between the occurrence of the abnormality and the return after stopping all of the plurality of outputs.

  The eleventh means is characterized in that, in the tenth means, when each of the outputs is output individually, the outputs are sequentially output without being individually superimposed.

  The twelfth means is characterized in that, in the tenth means, when the respective outputs are outputted individually, the respective outputs are outputted while being superimposed in order.

  The thirteenth means, in the tenth means, when outputting each of the outputs individually, sequentially outputs the outputs without superimposing them individually, and then outputs the outputs while superimposing the outputs in order. Features.

  The fourteenth means is characterized in that, in any one of the eleventh to thirteenth means, means for controlling each input signal for each output when the respective outputs are outputted individually.

  A fifteenth means is the switch according to any one of the eleventh to thirteenth means, and a switch for opening and closing the power supply to each output, and a means for controlling opening and closing of the switch when outputting each output individually. It is characterized by having.

  A sixteenth means is characterized by an image forming apparatus including the high-voltage power supply device according to any one of the first to fifteenth means.

  The seventeenth means comprises a first output and a second output capable of setting an output voltage different from the first output, and an abnormality occurs in one of the first and second outputs. A power supply control method for stopping both the first and second outputs is characterized.

  In the embodiment described later, the first output is an output applied to the first load 20, the second output is an output applied to the second load 30, the protection circuit is denoted by reference numeral 50, The error detection generator 1 corresponds to the symbol a, the second error detection voltage generator corresponds to the symbol b, the Zener diode corresponds to the symbol 25, and the booster corresponds to the symbols 23 and 33. Detected by the unit 51.

  According to the present invention, it is possible to execute the detection of abnormality and the stop of the output of all high-voltage power supplies with a single abnormality detection circuit.

  Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the same reference numerals are assigned to the common components, and duplicate descriptions are omitted.

  FIG. 1 is a diagram illustrating a schematic configuration of an image forming unit of a generally used secondary transfer type image forming apparatus which is a target in the first embodiment. In this country, the image forming unit of the image forming apparatus includes a photosensitive drum 1, an intermediate transfer belt 3 on which a toner image formed on the photosensitive drum 1 is transferred by a primary transfer device 2, and the intermediate transfer belt 3 is stretched. It is basically composed of a pair of rollers 4 and 5 provided and a secondary transfer device 6 provided to face one of the rollers 4 and 5, for example, the driven roller 5. A charging device 7, a developing device 8, a primary transfer device 2, a cleaning device 9, and a charge eliminating device 10 are provided along the rotation direction on the outer periphery of the photosensitive drum 1, and the secondary transfer device 6, the driven roller 5, and the like. Between them, a paper path 11 extending from a paper feeding device (not shown) is provided.

  In the image forming apparatus generally configured as described above, the surface of the photosensitive drum 1 rotating in the direction of the arrow shown in the figure is charged by the charging device 7, and the surface of the charged photosensitive drum 1 is irradiated with the light beam 12. As a result, an electrostatic latent image is formed on the surface of the photosensitive drum 1. The formed electrostatic latent image is developed with toner by the developing device 8, and a toner image is formed on the surface of the photosensitive drum 1. The intermediate transfer belt 3 is in contact with the surface of the photosensitive drum 1 at the position of the primary transfer device 2. When the toner image reaches the position of the primary transfer device 2, the toner on the surface of the photosensitive drum 1 is transferred by the transfer bias of the primary transfer device 2. The image is transferred onto the intermediate transfer belt 3.

  The image transferred to the intermediate transfer belt 3 reaches the driven roller 5 side by the rotation of the intermediate transfer belt 3 in the direction of the arrow in the drawing, and the sheet conveyed along the sheet path 11 from the sheet feeding device side is positioned at the registration roller 13 position. Are sent out in time with the image leading edge. Then, the leading edge of the image and the leading edge of the paper are aligned at the position of the secondary transfer device 6, and the image on the intermediate transfer belt 3 is transferred onto the paper as the paper is transported. The transferred image is fixed by a fixing device (not shown) and discharged outside the apparatus.

  FIG. 2 is a block diagram showing a schematic configuration of the high-voltage power supply circuit HVP of the image forming apparatus of FIG. In the figure, power is supplied to first and second loads 20 and 30 provided in parallel. The first power supply 20 converts the power supply voltage supplied from the power supply 40 based on the input from the first PWM input unit 21 and the first PWM input unit 21 provided in series. The first voltage converter 22 and the booster 23 that boosts the voltage converted by the first voltage converter 22 and supplies the boosted voltage to the first load. This is performed by the second PWM input unit 31, the second voltage conversion unit 32, and the second boosting unit 33 having the same configuration. The output on the downstream side (secondary side) of the first and second boosting units 23 and 33 is fed back to the first and second boosting conversion units 22 and 23. First and second error detection voltage generators a and b are connected to the upstream side (primary side) of the first and second boosters 23 and 33, respectively, and the first and second error detection voltage generators are connected. Outputs a and b are guided to the protection circuit 50. In this connection circuit, first and second diodes 24 and 34 are respectively provided in parallel, and a Zener in series with the diodes 24 and 34 is provided between the first and second diodes 24 and 34 and the protection circuit 50. A diode 25 is connected. The protection circuit 50 is provided with an abnormality detection unit 51.

  That is, the Zener diode is connected to the signal lines from the first and second output error detection voltage generation units a and b so that the abnormality detection unit side is an anode and the signal input side is a cathode. The output error detection voltage generators a and b of the first and second diodes 24 and 34 combine the cathodes of the first and second diodes 24 and 34 into one, and are connected to the cathode of the Zener diode. The power supply 40 is supplied with power from the external power supply device 41.

  In the high voltage power supply circuit HVP configured as described above, the first and second error detection voltage generators a and b are connected as described above. , B when the voltage becomes 15 V or more, a current flows through the abnormality detection unit 51 in the protection circuit 50. The protection circuit 50 detects an error by this current, turns off the power of the voltage converters 22 and 23 on the high voltage power supply board, and stops the high voltage output even if a PWM signal is input. The voltage conversion units 22 and 23 are constituted by ICs.

  As described above, according to the present embodiment, the error is not observed as a signal, but the error detection voltage generators a and b are combined into one protection circuit by monitoring the voltage under the condition that the voltage is not more than a certain voltage. be able to. As a result, a configuration in which a single protection circuit 50 (abnormality detection unit 51) can detect a plurality of outputs can be obtained, which is advantageous for cost and space saving.

  Further, since the error detection voltage generators a and b are arranged on the primary side of the boosters 23 and 33, it is possible to detect an abnormality with the voltage before the voltage becomes high. As a result, it is not necessary to use a component having a high withstand voltage, which is advantageous in terms of cost.

  FIG. 3 is a block diagram illustrating a schematic configuration of the high-voltage power supply circuit HVP according to the second embodiment. This embodiment is an example in which the first and second error detection voltage generators a and b are arranged on the secondary side of the first and second boosters 23 and 33, respectively, with respect to the first embodiment. The image forming apparatus itself and the high-voltage power supply circuit HVP are configured in the same manner as in the first embodiment except for the arrangement of the first and second error detection voltage generators a and b, and the protection circuit 50 also includes the first and second protection circuits 50. The same operation is performed by the detection outputs of the error detection voltage generators a and b.

  Since the first and second error detection voltage generators a and b detect the boosted voltage, although not shown in the figure, the actual machine divides the voltage with a resistor and protects the voltage dropped to a predetermined voltage. The signal is input to the circuit 50. Other parts not specifically described are configured in the same manner as in the first embodiment and function in the same manner.

  As described above, according to the present embodiment, the first and second error detection voltage generation units a and b are arranged on the secondary side of the first and second boosting units 23 and 33, so that an error in boosting occurs. Regardless of (tolerance of the transformer, etc.), the voltage applied to the load (voltage lowered in the actual machine) can be directly input to the abnormality detection unit 51. Thereby, it is possible to detect the abnormality detection voltage more severely than in the first embodiment.

  FIG. 4 is a block diagram showing a schematic configuration of the high-voltage power supply circuit HVP according to the third embodiment. In this embodiment, in the first embodiment, the protection circuit 50 is configured to turn off the power supplied from the 1C power supply 40 to the voltage converters 22 and 32 when an abnormality occurs. In this configuration, the supplied power is turned off.

  Thus, when an abnormality occurs, the power supplied from the external power supply 60 to the 1C power supply 40 is turned off, and the power supply to the 1C power supply 40 is not performed. As a result, the power supply to the voltage conversion units 22 and 32 is stopped, and the high voltage output from the high voltage power supply circuit HVP is stopped.

  Other parts not specifically described are configured in the same manner as in the first embodiment and function in the same manner.

  FIG. 5 is a block diagram illustrating a schematic configuration of a high-voltage power supply circuit HVP according to the fourth embodiment. This embodiment is an example in which an error signal can be output to the outside, here, the CPU 70 with respect to the first embodiment, and the high-voltage power supply circuit HVP itself is the same as the first embodiment.

  FIG. 6 is a block diagram showing a circuit configuration relating to the external output of the error signal in the protection circuit 50. The protection circuit 50 includes first to third switches 52, 53, and 54. The second and third switches 53 and 54 are connected in parallel to the first switch 52. The second switch 53 is connected to the IC power source Vdd, and the third switch 54 is connected to the control power circuit 26 to the CPU 70 side. It is connected. Other parts not specifically described are configured in the same manner as in the first embodiment and function in the same manner.

  In this embodiment, when a current flows through the Zener diode 25 in the protection circuit 50, the first switch 52 is turned on as shown in FIG. The circuit configuration is such that the switches 53 and 54 are simultaneously turned on. As a result, a signal 27 for notifying the CPU 70 of an error is added simultaneously with the protection operation for stopping the high-voltage output when an abnormality is detected, so that the movement of the entire image forming apparatus can be stopped and the user can be informed accordingly.

  Instead of stopping the movement of the entire image forming apparatus, it is also possible to stop power supply by stopping PWM input to the high voltage substrate.

In the inventions according to the first to fourth embodiments, for a high-voltage power supply having a plurality of loads,
It is advantageous in terms of cost and space by adopting a configuration in which error signals are combined into one regardless of the number of loads instead of the number of loads = error detection unit. However, with only the configuration of the invention described in the first to fourth embodiments, it is not clear in which load an error has occurred when an error occurs because there is only one abnormality detection unit 51. Therefore, when an error occurs, the user or service person has to inspect all the outputs and find the load causing the error.

  Therefore, in this embodiment, it is possible to specify the location where an error has occurred with the configuration of the first to fourth embodiments. FIG. 7 is a flowchart illustrating a processing procedure for specifying an error occurrence location in the fifth embodiment.

  That is, in the configuration shown in FIG. 5 of the fourth embodiment, “only the first output (for example, the first load 20) is turned on” → “the second output (for example, the second load) before the return when an error occurs. By providing a control step of “30) only on”, it is possible to specify which output causes the error.

  Specifically, in FIG. 7, when an error occurs (step S101), all outputs are stopped (step S102), and then the first output (load 20) is turned on (step S103). It is checked whether an error has occurred in this state (step S104). If there is an error, the location where the error occurred is specified (step S105), and the specified error location is displayed to the user (step S106). Next, after the first output (load 20) is turned off and the second output (load 30) is turned on (step S107), whether or not an error has occurred is checked (step S108). On the other hand, if no error has occurred in step S104, the process skips to step S107 and executes the process of step S107.

  If an error has occurred in the check in step S108, the error location is specified (step S109), and the specified error location is displayed to the user (step S110). After that, the second output is turned off, the third output is turned on, and the error position is identified by repeating off and on sequentially for each output. When the output reaches the nth output, the (n−1) th output is turned off, The n-th output is turned on (step S111), and whether or not an error has occurred is checked (step S112). If an error has occurred, the error location is identified (step S113), the identified error location is displayed to the user (step S114), and the process ends. If no error occurs in step S112, the process is finished as it is.

  For example, when an abnormality occurs in the first output (first load 20) as shown in FIG. 8, when the control process as shown in the flowchart of FIG. The high-voltage power supply will be stopped without knowing if it has occurred. However, as shown in the flowchart of FIG. 7, each output is sequentially output individually and an error check is performed, whereby the error location can be specified. Further, even when an abnormality occurs in a plurality of outputs, it is possible to detect an abnormality in all the outputs since the other outputs are checked for abnormality after the first output abnormality is displayed.

  Other parts that are not specifically described are configured in the same way as the fourth embodiment shown in FIG.

  In the usage application of the high-voltage power supply, as shown in FIG. 9, the first output load 20 and the second output load 30 may have a path connected through the load 60 due to the configuration of the entire system. For example, there is a path in which the charging output and the development output in the image forming apparatus are connected to loads of a high-voltage power source through the photosensitive member. In such a configuration, an error does not occur even if each output is output individually, but when there is a connected path and the polarity of the output connected through the load is different, a plurality of outputs are turned on simultaneously. May cause an error. FIG. 9 shows an example in which the first output 20 has a negative polarity and the second output 30 has a positive polarity.

  FIG. 10 is a flowchart showing a processing procedure for specifying the error occurrence portion, which is suitable for a high voltage load in which loads of the high voltage power supply are connected in this way.

  In this flowchart, step S107a is substituted for step S107 in the flowchart of FIG. 7, and step S111a is substituted for step S111. In step S107a, the first output (load 20) is turned on and the second output (load 30) is turned on. In step S111a, the first output on, the second output on. Are overlapped to check the occurrence of an error (step S112), and an error location can be specified even when an error does not occur individually.

  In addition, each part and each step not specifically described are configured in the same manner as in the fifth embodiment and function in the same manner.

  FIG. 11 is a flowchart illustrating a processing procedure for specifying an error occurrence location in the seventh embodiment. This flowchart is a combination of the fifth embodiment and the sixth embodiment. Steps S101 to S114 are processed in the sequential output steps of the fifth embodiment, and then the superimposition of the second embodiment from the step S201 to the step S208 is performed. It is a flowchart processed in the step of output. In this flowchart, each output is sequentially turned on in steps S107 to S111 to detect an error, and each output is superimposed and turned on in steps S201 to S205 to perform error detection.

  In the case of having a plurality of outputs in this way, an error may occur in both the high-voltage power source shown in FIG. 8 and the high-voltage power source shown in FIG. However, by performing the processing as shown in the flowchart of FIG. 11, it is possible to identify the location where the error occurs even in the circuit configuration in which the configurations of FIGS. 8 and 9 are confused. Other parts that are not particularly described are configured in the same manner as the fifth and sixth embodiments and function in the same manner.

  FIG. 12 is a block diagram illustrating a schematic configuration of the high-voltage power supply circuit HVP according to the eighth embodiment. In this embodiment, the CPU 70 of the fourth embodiment is configured so as to output control signals to the PWM input sections 21 and 31, respectively, and to control input signals for the respective outputs. Other parts are configured in the same manner as in the fourth embodiment and function in the same manner.

  Thereby, control of the said Example 5 thru | or 7 is realizable.

  FIG. 13 is a block diagram illustrating a schematic configuration of the high-voltage power supply circuit HVP according to the ninth embodiment. This embodiment is a means for setting on / off of power supply to each of the outputs 20 and 30 immediately before the first output (load 20) and the second output (load 30) of the fourth embodiment. , 37 so that the CPU 70 can set power supply on / off. Other parts are configured in the same manner as in the fourth embodiment and function in the same manner.

  Thereby, control of the said Example 5 thru | or 7 is realizable.

  FIG. 14 is a block diagram illustrating a schematic configuration of the high-voltage power supply circuit HVP according to the tenth embodiment. In this embodiment, the eighth embodiment and the ninth embodiment are combined, and the CPU 70 controls the input signals to the PWM input units 21 and 31 and supplies power to the first output (load 20) and the second output (load 30). It is configured to be able to perform on / off control. Other parts are configured in the same manner as in the fourth embodiment and function in the same manner.

  Thereby, control of the said Example 5 thru | or 7 is realizable.

As described above, according to the above-described embodiment,
1) The protection circuit can be integrated into one by monitoring the voltage under the condition that each error detection voltage generator is not more than a certain voltage, instead of looking at the error as a signal.
2) Since the protection circuit (abnormality detection unit) can be configured in a single configuration even for a plurality of outputs, cost saving and space saving can be achieved.
3) By arranging the first and second error detection voltage generators a and b on the primary sides of the first and second boosters 23 and 33, respectively, abnormality detection is performed with a voltage before the voltage becomes high. Can do.
4) Since abnormality detection can be performed with a voltage before high voltage, it is not necessary to use parts with high withstand voltage, and can be provided at low cost.
5) By arranging the first and second error detection voltage generation units a and b on the secondary side of the first and second boosting units 23 and 33, respectively, errors during boosting (transformer tolerance, etc.) Regardless of whether the voltage applied to the load is directly input to the protection circuit (abnormality detection unit), the abnormal detection voltage can be detected more severely.
6) Since it is possible to add a signal notifying the CPU simultaneously with the high voltage output stop protection operation when an abnormality is detected, it is possible to stop the movement of the entire image forming apparatus and simultaneously notify the user of the abnormality.
7) Since the outputs are sequentially output individually from the occurrence of the error to the return, even if the load of the first output and the load of the second output do not have a path connected through the load, the error detection unit 1 Even in the case of having a single configuration, it is possible to specify the location where the error occurred.
8) Since the output is output in a superimposed manner between the occurrence of the error and the return, even when the load of the first output and the load of the second output have a path connected through the load, only one error detection unit is provided. Even in the case of a combined configuration, it is possible to specify the location where an error occurs. 9) Since the output is output in a superimposed manner after the outputs are output individually and sequentially from the occurrence of the error to the return, a path is provided along which the load of the first output and the load of the second output are connected through the load. Even in the case of the circuit configuration, it is possible to identify the location where the error has occurred even when the error detection unit has a single configuration.
10) Since the output control is performed for each output, it is possible to specify the location where an error has occurred without changing the hardware configuration from the conventional one.
11) A mechanism such as a switch is provided immediately before each output, and by controlling the switch, it is possible to specify the location where an error has occurred even when the error detection unit has a single configuration.
12) Instead of controlling the input signal for each output, a mechanism such as a switch is provided immediately before the input signal for each output and each output, and the switch is controlled so that the location where the abnormality occurs is a load outside the high-voltage power supply. Or the path between the input and output in the high-voltage power supply.
There are effects such as.

1 is a diagram illustrating a schematic configuration of an image forming unit of a generally used secondary transfer type image forming apparatus that is a target in Embodiment 1. FIG. FIG. 2 is a block diagram illustrating a schematic configuration of a high-voltage power supply circuit HVP of the image forming apparatus in FIG. 1. It is a block diagram which shows schematic structure of the high voltage power supply circuit HVP which concerns on Example 2. FIG. FIG. 10 is a block diagram illustrating a schematic configuration of a high-voltage power supply circuit HVP according to a third embodiment. It is a block diagram which shows schematic structure of the high voltage power supply circuit HVP which concerns on Example 4. FIG. FIG. 10 is a block diagram illustrating a circuit configuration related to external output of an error signal in a protection circuit according to a fourth embodiment. 14 is a flowchart illustrating a processing procedure for specifying an error occurrence location in the fifth embodiment. It is a block diagram which shows the state at the time of abnormality generation of the high voltage power supply circuit HVP which concerns on Example 5. FIG. It is a block diagram which shows schematic structure of the high voltage power supply circuit HVP which concerns on Example 6. FIG. 18 is a flowchart illustrating a processing procedure for specifying an error occurrence location in the sixth embodiment. 18 is a flowchart illustrating a processing procedure for specifying an error occurrence location in the seventh embodiment. It is a block diagram which shows schematic structure of the high voltage power supply circuit HVP based on Example 8. FIG. FIG. 10 is a block diagram illustrating a schematic configuration of a high-voltage power supply circuit HVP according to a ninth embodiment. It is a block diagram which shows schematic structure of the high voltage power supply circuit HVP based on Example 10. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photosensitive drum 2 Primary transfer apparatus 3 Intermediate transfer belt 4,5 Roller pair 6 Secondary transfer apparatus 7 Charging apparatus 8 Developing apparatus 9 Cleaning apparatus 10 Static elimination apparatus 11 Paper path 20, 30 Load 21,31 PWM input part 22,32 Voltage converter 23, 33 Booster 24, 34 Diode 25 Zener diode 26 Control power supply circuit 27, 37 Switch 40 Power supply 50 Protection circuit 51 Abnormality detection unit 52, 53, 54 Switch 60 External power supply 70 CPU
a, b Error detection voltage generator HVP High voltage power supply circuit

Claims (17)

Multiple outputs that can be set to different output voltages,
A single protection circuit that stops the output in the event of an abnormality;
With
The protection circuit stops all of the plurality of outputs when an abnormality occurs. The high voltage power supply device according to claim 1,
The plurality of outputs are two outputs of a first output and a second output,
A first and second error detection voltage generator for detecting each abnormality of the first output and the second output by a voltage;
The high-voltage power supply apparatus according to claim 1, wherein voltages from the first and second error detection voltage generators are input to the protection circuit. The high voltage power supply device according to claim 2,
The high-voltage power supply apparatus according to claim 1, wherein voltages from the first and second error detection voltage generation units to the protection circuit are input via a Zener diode. The high voltage power supply device according to claim 1,
In the input part to the abnormality detection unit in the protection circuit, a Zener diode is provided so that the abnormality detection unit side is an anode and the signal input side is a cathode,
The error detection voltage generators of the first and second outputs are combined into one through a diode, the cathode side of the diode is connected to the cathode of the Zener diode, and one of the error detection voltage generators is preset. A high-voltage power supply apparatus, wherein a signal is input to the abnormality detection unit when the voltage exceeds a voltage. In the high voltage power supply device according to any one of claims 1 to 4,
The high-voltage power supply apparatus according to claim 1, wherein when the output is stopped, the protection circuit powers down a control unit that controls a value of the output voltage. In the high voltage power supply device according to any one of claims 1 to 4,
The high-voltage power supply apparatus according to claim 1, wherein the protection circuit drops the high-voltage power supply input voltage when stopping the output. The high voltage power supply device according to any one of claims 1 to 6,
The high-voltage power supply apparatus, wherein the protection circuit outputs a signal notifying the CPU of the abnormality simultaneously with the stop of the output. The high voltage power supply device according to any one of claims 2 to 4,
The high-voltage power supply apparatus according to claim 1, wherein the first and second error detection voltage generation units are arranged on a primary side of the boosting unit. The high voltage power supply device according to any one of claims 2 to 4,
The high-voltage power supply apparatus according to claim 1, wherein the first and second error detection voltage generators are arranged on the secondary side of the booster. The high voltage power supply device according to claim 1,
The high-voltage power supply apparatus according to claim 1, wherein the protection circuit individually outputs each output between the occurrence of the abnormality and the return after stopping all of the plurality of outputs. The high-voltage power supply device according to claim 10,
When outputting each said output separately, each said output is output sequentially, without superimposing separately, The high voltage power supply device characterized by the above-mentioned. The high-voltage power supply device according to claim 10,
When outputting each said output separately, outputting each said output, superimposing each said output in order. The high-voltage power supply device according to claim 10,
When outputting each said output separately, outputting each said output sequentially, without overlapping each other, and then outputting, outputting each said output in order. The high voltage power supply device according to any one of claims 11 to 13,
A high-voltage power supply device comprising means for controlling each input signal for each output when each output is output individually. The high voltage power supply device according to any one of claims 11 to 13,
A switch for opening and closing the power supply to each output;
Means for controlling opening and closing of the switch when outputting each of the outputs individually;
A high-voltage power supply device comprising:   An image forming apparatus comprising the high-voltage power supply device according to claim 1. A first output;
A second output capable of setting an output voltage different from the first output;
With
A power supply control method, comprising: stopping an output of both the first and second outputs when an abnormality occurs in one of the first and second outputs.

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