JP2008172974A - Rectifier circuit and wireless communications device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve input sensitivity of a rectifier circuit by reducing the threshold voltage for conducting the rectifying circuit to execute rectifying operation. <P>SOLUTION: An output voltage of a rectifying circuit is divided so as to supply a divided voltage to a rectifying transistor, and also to reduce the threshold voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a rectifier circuit and a wireless communication apparatus using the rectifier circuit, for example, a rectifier circuit suitable for a wireless tag circuit of a wireless communication system that performs non-contact data communication, and a wireless communication apparatus using the rectifier circuit.

  In recent years, wireless data communication that performs contactless data communication such as contactless IC cards and wireless tags (hereinafter collectively referred to as wireless tags) for entry / exit management of buildings and rooms, package collection management, sensor networks, etc. The system is starting to spread. This wireless system includes a wireless tag and a reader / writer device that is arranged in the vicinity of the wireless tag and performs reading and writing of data.

  In Patent Document 1, a MOS transistor is used as a rectifying element, and the anode side of a transistor diode-connected to the gate of a rectifying transistor of a half-wave rectifier circuit is connected to the source, and the cathode side is connected to the gate. A rectifier circuit is disclosed in which a threshold voltage is applied between a gate and a source of a rectifying transistor so that the threshold voltage of the rectifying transistor is reduced.

  In Patent Document 2, in a rectifier circuit using a MOS transistor, a control signal is generated based on the potential of a capacitor connected to a simulated MOS transistor, thereby canceling the threshold of the rectifier element in a circuit. It is disclosed.

  In FIG. 18 of Patent Document 3, in a rectifier circuit using MOS transistors, capacitors are provided between the control gate terminals and source terminals of the floating gate field effect transistors M71 and M72, respectively, and the holding voltage of the capacitors can be controlled. With this configuration, a configuration that can rectify even a weak AC signal is disclosed.

JP 2006-101670 A JP 2006-166415 A JP 2006-34085 A

  In such a wireless data communication system, one of the problems is to increase the communication distance between the wireless tag and the reader / writer device. In addition, since the purpose is to manage a large number of people and things, there is a demand for cost reduction and miniaturization of the wireless tag.

  First, the communication distance of the wireless tag greatly depends on the threshold voltage of the rectifying element of the rectifying circuit configured in the tag. Since the threshold voltage determines the minimum voltage at which rectification can be performed, the lower the threshold voltage, the rectification operation can be performed from a lower voltage. Therefore, a rectifier circuit having a lower threshold voltage can obtain a higher output voltage even with the same input voltage. . From this point of view, a Schottky diode may be used as a rectifying element.

  In addition, the wireless tag circuit often uses a CMOS process from the viewpoint of cost reduction. Fabricating a Schottky diode by a standard CMOS process has a problem of high costs such as an increase in process steps. In addition, it is difficult to produce a rectifying element having a low threshold voltage such as a Schottky diode by a standard CMOS process.

  In order to solve this problem, Patent Document 1 proposes a method for reducing the threshold voltage of the rectifying element. However, in the method disclosed in Patent Document 1, a voltage for conducting the diode-connected transistor is necessary, and this voltage is a voltage necessary for conducting the output voltage Vb of the rectifier circuit and the diode connection. It can be seen that the sum of the above is necessary. If this voltage is not maintained, the effect of reducing the threshold voltage decreases as the input voltage Va to the rectifier circuit increases, and there is a problem that the output voltage Va decreases. This is because, when the rectifier circuit of Patent Document 1 is used for a wireless tag, if the distance between the wireless tag and the reader / writer is short and the input power Va to the wireless tag is too large, the output voltage Vb decreases sufficiently. This means that the power supply voltage cannot be secured and communication cannot be performed.

  Patent Documents 2 and 3 propose that the threshold value of the rectifying element in the rectifier circuit is canceled by circuit contrivance. However, since the threshold cancellation voltage is generated and supplied to the rectifier element by the control of the logic circuit, the input power is increased and a voltage sufficient to operate the control system such as the logic circuit can be secured. The threshold cannot be canceled unless it becomes. Therefore, this method is effective for a sensor network or the like in which a battery is allowed to be mounted in a wireless tag. However, in a wireless communication system such as a wireless tag that does not allow battery mounting, it is difficult to improve the communication distance by this method.

  In addition, in such a power supply circuit using a rectifier circuit, the need for ensuring a sufficient power supply voltage regardless of the magnitude of input power is not limited to a wireless tag. For example, the power supply electrode is not seen on the mobile phone side and the charger side as in the case of the non-contact charger of the mobile phone. When set to, the coils are close to each other and the voltage is supplied from the charger to the mobile phone by electromagnetic induction and rectified to charge the battery, or the output of the oscillator is rectified to generate positive or negative voltage Even in the case of such a voltage generation circuit, the problem is required when a rectifier circuit using a MOS transistor as a rectifier is used.

  An object of the present invention is to solve the above problems. One of the problems to be solved by the present invention is to improve the communication distance by lowering the threshold voltage of a MOS transistor in a rectifier circuit using a MOS transistor as a rectifier.

  An example of a representative one of the present invention is as follows. That is, a rectifier circuit according to the present invention includes a rectifier circuit unit that obtains an operating voltage from an input signal, and a voltage limiting circuit unit that limits the output voltage of the rectifier circuit unit to a constant value. The element is composed of a field effect transistor, and is configured to divide an operating voltage output from the rectifier circuit unit and supply the divided voltage to the gate terminal of the field effect transistor. Features.

  According to the present invention, in a rectifier circuit using a MOS transistor as a rectifier element, the threshold voltage of the MOS transistor is lowered according to the input power only by the circuit configuration, thereby increasing the input sensitivity of the rectifier circuit regardless of the magnitude of the input power. It is possible to improve the communication distance.

According to a typical embodiment of the present invention, the rectifier circuit includes the field effect transistor and a capacitor, and the gate terminal and the drain terminal of the field effect transistor are connected by a coupling capacitor. . Then, a voltage limiting circuit for limiting the output voltage so as not to exceed a certain value is connected to the rectifying circuit, and the output voltage is divided and supplied to the gates of the rectifying elements.
Embodiments of the present invention will be described below with reference to the drawings.

  First, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a first embodiment in which the present invention is applied to a voltage doubler half-wave rectifier circuit.

  The power supply circuit 1 includes a rectifying circuit unit 2 and a voltage limiting circuit 3, and the output side of the rectifying circuit unit 2 and the voltage limiting circuit 3 are connected. The rectifier circuit unit 2 includes first and second field effect transistors 5 and 6 and first and second capacitors 7 and 8 connected between an input terminal 4 and a reference potential terminal 13 of the power supply circuit. The voltage doubler half-wave rectifier circuit section and the first and second resistance elements 11 and 12 are configured. More specifically, the input terminal 4 is connected to one end of the first capacitor 7. The gate and the drain of the first field effect transistor 5 are connected via a connection first capacitor 9 disposed between the nodes TA and TC, and the source of the first field effect transistor 5 is (at the node TB). ) It is connected to the other end of the first capacitor 7. The source of the second field effect transistor 6 is connected to one end of the second capacitor 8 at the node TE, and the other end of the second capacitor 8 is connected to the reference potential-terminal 13. The gate and drain of the second field effect transistor 6 are connected through a second capacitor 10 for connection disposed between the nodes TB and TD. Further, there is a resistance element between the source of the second field effect transistor 6 (= node TE of the rectifier circuit section 2), the connection portion (TE, TF) of the power supply limiting circuit 3 and the reference potential terminal 13 (node TG). 11 and 12 are provided. An arbitrary intermediate point a of the resistive element 11 and the gate terminal of the field effect transistor 5 are connected, and an arbitrary intermediate point b of the resistive element 12 and the gate terminal of the field effect transistor 6 are connected. The voltage limiting circuit 3 operates so that the output voltage Vout of the output terminal TF of the power supply circuit 1 is maintained within the limiting voltage E. V1 to V3 indicate voltages at the nodes TA, TB, and TD.

  Next, the operation of the power supply circuit 1 when the threshold voltage for the rectifying operation of the field effect transistors 5 and 6 is Vth and the input signal voltage Vin is supplied between the terminal 4 and the terminal 13 will be described. First, the operation principle of threshold cancellation will be described with reference to FIGS.

  FIG. 2 is a circuit diagram schematically showing the relationship between the input terminals (4, 13), the MOS transistor (second field effect transistor 6), and the resistance elements (11, 12) in the power supply circuit 1 of FIG. .

  FIG. 3 is a diagram showing a direct current-voltage characteristic of the MOS transistor circuit shown in FIG.

The circuit of FIG. 2 can perform a rectification operation in two states.
One is a case where the power supply E (= output voltage Vout) is 0 [V], and is hereinafter referred to as [state 1]. The other state is when a voltage higher than 0 [V] is supplied from the power source E and a cancel voltage ΔVth lower than Vth1 is supplied to the gate of the MOS transistor. This is hereinafter referred to as [State 2]. And

  In [State 1], rectification is performed according to Vth1 of the MOS transistor. At this time, when the AC signal voltage Vin is input, as shown in FIG. 3 as the AC characteristics of [State 1], a region where the input voltage amplitude is Vth1 or less (off region) is large and exceeds Vth1. The on-state region (on region) is small. In [State 1], it can be seen that the efficiency of the rectification operation is low due to the voltage drop due to Vth1. In FIG. 3, the voltage waveform is also expressed in the ON region. However, since the MOS transistor actually has a low resistance in the ON state, the voltage waveform is hardly observed and is clamped at Vth1.

  Next, the threshold Vth2 of the MOS transistor in [State 2] becomes (Vth1−ΔVth) due to the effect of the cancel voltage ΔVth, and a threshold lower than Vth1 can be set. When the AC signal voltage Vin is input to this, since the rectification operation can be performed with a threshold voltage (Vth2) lower than the Vth1 by the cancel voltage ΔVth, the OFF region is smaller and the ON region is smaller than the AC characteristics of [State 1]. growing. That is, even in the input signal voltage Vin, in the [state 2], more current flows, the charge charged in the capacitor increases, and a higher voltage can be obtained. This improves the efficiency of the rectifying operation. As in [State 1], the voltage waveform is also expressed in the ON region in FIG. 3, but in reality, the MOS transistor has a low resistance in the ON state, so the voltage waveform is hardly observed and is clamped at Vth2.

  A specific example of setting the cancel voltage for biasing the field effect transistor 5 to the voltage Va [V] and the field effect transistor 6 to the voltage Vb [V] will be described with reference to FIG. The upper limit value (1.65 [V]) of the output voltage Vout [V] obtained by the rectification action becomes a constant value E (rated voltage) by the voltage limiting circuit 3, and each node voltage is relative to the input voltage Vou. The cancel voltage is set in the region where the value is constant. The cancel voltage V1 supplied to the diode-connected MOS transistor 5 is adjusted by the ratio of the resistors R1 and R2 so as to be 0.55 [V] higher than the terminal 13. At this time, the upper limit value of the voltage V2 obtained by the rectification operation of the diode-connected MOS transistor 5 and the capacitor 7 is 0.87 [V] by the voltage limiting circuit 3. Therefore, the ratio of the resistors R3 and R4 is adjusted so that the upper limit value of the cancel voltage V3 supplied to the diode-connected MOS transistor 6 is 1.42 (= 0.87 + 0.55) [V].

  As shown in FIG. 4, since the input power of the rectifier circuit is small in [State 1], the threshold cancellation voltage ΔVth is almost 0 [V]. On the other hand, in [State 2], since the input power of the rectifier circuit is increased, a threshold cancel voltage ΔVth greater than 0 [V] is supplied to the gate.

  The efficiency of the rectifying operation of the rectifier circuit is good when the cancel voltage ΔVth is on the left side of Vth1 in FIG. 3, that is, when the input power is large.

  As the input power increases, the threshold cancellation voltage ΔVth also increases and may be higher than Vth1. Therefore, the voltage limiter 3 for suppressing the voltage of the rectifier circuit is used, and the cancellation voltage ΔVth in the region where the voltage limiter operates. Therefore, the cancel voltage ΔVth does not exceed Vth1 due to the input power.

  If the upper limit of the input power does not change, for example, if the distance between the base station or reader / writer and the wireless circuit on which the circuit of the present invention is mounted is substantially constant, ΔVth is Vth1 even without the voltage limiting circuit 3. Can be set in advance so as not to exceed.

Returning to FIG. 1 again, the overall operation of the power supply circuit 1 will be described.
In the first negative cycle of the input signal voltage Vin, the field effect transistor 5 becomes conductive only when a voltage amplitude Vin larger than Vth is input (the positive and negative cycles are opposite to those in FIG. 2). At this time, a charge corresponding to a voltage of (Vin−Vth) is accumulated in the capacitor 7. At this time, since the voltage input to the field effect transistor 6 is Vth or less, it is in a non-conductive state (see FIG. 2). Next, in the positive cycle, the input voltage signal Vin and (Vin−Vth) accumulated earlier are input to the field effect transistor 6 and are brought into conduction only when the input signal has a voltage amplitude exceeding Vth. The voltage generated at both ends of the capacitor 8, that is, the output voltage Vout of the rectifier circuit unit 2 is
Vout = (Vin + (Vin−Vth)) − Vth = 2 × (Vin−Vth) (1)
It becomes.

Equation (1) is the same as the voltage equation obtained by general voltage doubler half-wave rectification. For this output voltage Vout, the resistance value between the output of the rectifier circuit unit 2 and the point a on the voltage dividing element 11 is R1, the resistance value between the point a and the reference potential 13 is R2, and the resistance value of the rectifier circuit unit 2 When the resistance value between the output and the point b on the voltage dividing element 12 is R3, and the resistance value between the point b and the reference potential 13 is R4, the voltage Va at the point a and the voltage Vb at the point b are
Va = Vout × R2 / (R1 + R2) (2)
Vb = Vout × R4 / (R3 + R4) (3)
(However, Vb> Va)
A voltage is generated. This voltage Va is supplied to the gate of the field effect transistor 5 and the voltage Vb is supplied to the gate of the field effect transistor 6 as a threshold cancel voltage for lowering the respective threshold voltages.

  Therefore, when the present invention is applied, Equation (1) can be rewritten as follows.

Vout = (Vin + (Vin− (Vth−Va))) − (Vin + Vth− (Vin + Vb)) = 2 × (Vin−Vth) + Va + Vb
... (1 ')
Here, assuming that the potential of the gate terminal with respect to the drain terminal of each rectifier element is Vz, Vz = Va = Vb, so (1 ′) can be rewritten as shown in Expression (4).
Vout = 2 × (Vin− (Vth−Vz)) (4)
However, Vin> Vth, Vth> Vz
From the comparison between the formula (1) and the formula (4), as the output voltage obtained even with the same input voltage Vin, the formula (4) to which the present invention is applied can obtain a higher voltage corresponding to Vz. Recognize.

  Here, when Vth = Vz, an on / off ratio, which is a ratio of a conduction state and a non-conduction state as a rectifying element of the field effect transistor, cannot be obtained sufficiently, and the output voltage Vout is significantly deteriorated. Therefore, the threshold cancellation voltage Va and the voltage Vb are preferably lower by about 0.15 to 0.25 [V] than the threshold voltage Vth. However, since this value varies greatly depending on the performance of the device, it cannot be generally stated. It is a guide only.

  When Vth> Vz is not established, the field effect transistors 5 and 6 are applied with a voltage higher than the threshold voltage. At this time, the transistor is always in a conductive state regardless of the input voltage, the rectification operation is not performed, and the output voltage Vout is significantly deteriorated. Since the output voltage Vout is a direct current voltage, the capacitors 9 and 10 prevent the voltages Va and Vb from being supplied to other than the gate. For this reason, the field effect transistor 5 is biased to the voltage Va [V], the field effect transistor 6 is biased to the voltage Vb [V], and the rectification operation is performed according to the magnitude of the AC signal input to the gate via the capacitors 9 and 10.

  By dividing the output voltage obtained by rectifying the input voltage in this way and supplying it as a threshold cancellation voltage to the gate of the field effect transistor that is a rectifying element, the threshold voltage for performing the rectifying operation in a circuit is reduced. Is possible. Further, the resistors R1, R2, R3, and R4 constituting the voltage dividing elements 11 and 12 minimize the potential variation with respect to the AC signal input to the gates of the field effect transistors 5 and 6 via the capacitors 9 and 10, respectively. In order to suppress the limit, the value is set so that the AC signal input to the gate has a sufficiently high impedance.

  Further, since this series of operations is performed regardless of the control system such as a logic circuit, it is not necessary to secure the operating voltage of the control system. Further, based on the limit voltage value determined by the voltage limit circuit 3, the maximum value of the threshold cancellation voltages Va and Vb is set to Vth or less, for example, 0.15 [V] to 0.25 [V] lower than Vth. As described above, if the ratio of R1, R2, R3, and R4 is determined, the output voltage Vout does not decrease even when the input voltage increases.

  Here, an example in which the resistors 11 and 12 are used for the voltage dividing element has been described, but it is needless to say that the present invention is not limited to this example. The voltage dividing element only needs to be an element that has high impedance even at the voltage upper limit determined by the voltage limiting circuit.

  The effect of the present embodiment will be described with reference to FIG. FIG. 5 is a diagram illustrating the input power dependence of the output power of the power supply circuit 1. The horizontal axis shows the power [dBm] input to the circuit, and the vertical axis shows the output voltage Vout [V] of the rectifier circuit. The input power dependence (proposed) of the output power in the voltage doubler half-wave rectifier circuit to which the present invention is applied is indicated by a bold line. As a comparative example, the dependence of output power on input power in a conventional standard voltage doubler half-wave rectifier circuit to which the present invention is not applied is shown (conventional). In addition, a characteristic (ideal) assuming an ideal state in which threshold cancellation operates from the beginning is indicated by a thin line. When the present invention is not applied, the output voltage increases to the limit voltage E by the voltage limit circuit with a substantially constant slope with respect to the input power. On the other hand, according to the present invention, when the rectification operation starts, the voltages Va and Vb at the intermediate points a and b rise to the upper limit value according to the input power, that is, the cancel voltage for canceling the threshold voltage Vth increases. The slope of the output voltage with respect to increases. As a result, it becomes close to ideal characteristics. Note that since the sufficient voltage Vb cannot be supplied to the field effect transistor 6, the sensitivity deteriorates from the time when Va and Vb are saturated. This can be improved by increasing the voltage limit value E of the voltage limit circuit 3.

  In the case where the present invention is applied to the power supply circuit 1 and the case where the present invention is not applied, the output voltage Vout reaches the limit voltage E with respect to the input power, but rises earlier by the amount shown as the improvement amount in FIG.

  According to this embodiment, in a rectifier circuit using a MOS transistor as a rectifier element, the threshold voltage of the MOS transistor is reduced (cancelled) according to the input power in a circuit manner, so that the rectifier circuit of the rectifier circuit can be controlled regardless of the input power. Input sensitivity can be improved and communication distance can be improved. Further, since the voltage limiting circuit 3 is provided, the output voltage does not deteriorate even when the input voltage increases. Furthermore, since the power supply circuit itself can generate a cancel voltage for canceling the threshold without adding a control system such as a logic circuit, a low-cost, high-performance rectifier circuit suitable for a wireless tag or the like is provided. Can be provided.

A second embodiment of the power supply circuit of the present invention will be described with reference to FIG.
FIG. 6 shows an example in which the voltage dividing elements 11 and 12 in the power supply circuit of FIG. 1 are replaced with diode-connected field effect transistors 14 and 15 connected in multiple stages so as not to conduct at the voltage upper limit value. In FIG. 6, the same components as those in FIG. Compared with a general thin film resistor, the resistance in a non-conductive state of the diode has a higher resistance per unit area. Therefore, in the case of FIG. 6, the circuit can be reduced in size by substituting the diode-connected transistors 14 and 15 for the voltage dividing elements 11 and 12.

  Here, for example, the voltage limiting value E of the voltage limiting circuit 3 is 1.65 [V], the threshold voltage Vth capable of performing the rectifying operation of the field effect transistors 5 and 6 is 0.7 [V], and the voltage that can secure the on / off ratio. Assuming that 0.55 [V], the number of diodes required for each of the diode-connected transistors 14 and 15 is 1.65 / 0.55 = 3, which indicates that three or more diodes are required. In this embodiment, considering that the output voltage deteriorates when the current flowing through the voltage dividing element is large, the maximum value of the voltage applied to each diode is set to about 0.3 [V], and the minimum number is 6 here. did.

  In order to supply a voltage of 0.55 [V] to the gate of the field effect transistor 5, the voltage dividing element 14 has a six-stage configuration, the point c between the second stage and the third stage from the bottom, and the field effect Connected to the gate of transistor 5. Thus, the threshold cancellation voltage Vc supplied to the gate of the field effect transistor 5 is 1.65 × (2/6) = 0.55 [V].

  Next, the voltage required for the charge effect transistor 6 is 1.42 [V] from FIG. The voltage dividing element 15 is connected to the point d between the 8th stage and the 9th stage from the bottom of the 10 stage configuration and the gate of the field effect transistor 6. As a result, the threshold cancellation voltage Vd supplied to the gate of the field effect transistor 6 is 1.65 × (8/10) = 1.32 [V]. This makes it possible to obtain a voltage almost as required.

  According to the present embodiment, in the rectifier circuit using a MOS transistor as a rectifier element, the threshold voltage of the MOS transistor is lowered in a circuit according to the input power, so that the input sensitivity of the rectifier circuit is increased regardless of the magnitude of the input power. It is possible to improve the communication distance. Further, even if the input voltage increases, the output voltage does not deteriorate. In addition, a low-cost, high-performance rectifier circuit suitable for a wireless tag or the like can be provided.

  Although the above description has been made in the case of the voltage doubler rectifier circuit, it is effective to apply the present invention by replacing the rectifier circuit 2 with a half-wave rectifier circuit or a full-wave rectifier circuit.

  A third embodiment of the power supply circuit of the present invention will be described with reference to FIG. FIG. 7 is a diagram showing an embodiment in which the present invention is applied to a double voltage half-wave rectifier circuit having a two-stage configuration as an example of multistage connection of rectifier circuits. In FIG. 7, the same components as those in FIG.

  The power supply circuit 16 includes a rectifier circuit unit 17 and a voltage limiting circuit 3. The rectifier circuit unit 17 has a two-stage configuration including the voltage dividing elements 31, 32, 33, and 34, and the output of the rectifier circuit unit 17 and the voltage limiting circuit 3 are connected. The rectifier circuit unit 17 forms a voltage doubler half-wave rectifier circuit with the input terminal 18, the reference potential terminal 13 of this power supply circuit, the field effect transistors 19, 20, 21, 22 and the capacitors 23, 24, 25, 26. . At this time, the gate and drain of the field effect transistor 19 are connected via the capacitor 27, and the gate and drain of the field effect transistor 20 are connected via the capacitor 28. The gate and drain of the field effect transistor 21 are connected via a capacitor 29, and the gate and drain of the field effect transistor 22 are connected via a capacitor 30.

  In addition, voltage dividing elements 31, 32, 33, and 34 are provided between the connection portion of the rectifier circuit unit 17 and the power supply limiting circuit 3 and the reference potential terminal 13. This voltage dividing element may be a resistance element or a diode-connected transistor.

  In this embodiment, the rectifier circuit portion including the field effect transistors 19 and 20 and the capacitors 23 and 24 and the voltage dividing elements 31 and 32 is the first stage rectifier circuit portion, and the field effect transistors 21 and 22 and the capacitors 25 and 26 are included. The rectifier circuit portion including the voltage dividing elements 33 and 34 is a second-stage rectifier circuit portion.

  In this embodiment, the voltage dividing element is a diode-connected transistor. At this time, the minimum number of diode-connected transistors is the same as in the first embodiment, and is set so as not to conduct even with the voltage limit value of the voltage limit circuit. An arbitrary point e of the voltage dividing element 31 and the gate of the field effect transistor 19 are connected, an arbitrary point f of the voltage dividing element 32 and the gate of the field effect transistor 20 are connected, and an arbitrary point g of the voltage dividing element 33 The gate of the field effect transistor 21 is connected, and an arbitrary point h of the voltage dividing element 34 and the gate of the field effect transistor 22 are connected.

  The operation when the input signal voltage Vin is supplied between the terminal 18 and the terminal 13 is described with the threshold voltage for performing the rectifying operation of the field effect transistors 19, 20, 21, and 22 being the same Vth. In the first negative cycle of the input signal, the field effect transistor 19 is turned on only when a voltage amplitude greater than Vth is input. At this time, a charge corresponding to a voltage of (Vin−Vth) is accumulated in the capacitor 23. Naturally, since the voltage input to the field effect transistor 20 is Vth or less, it is in a non-conductive state. Next, in the positive cycle, the input voltage signal Vin and (Vin−Vth) previously stored are input to the field effect transistor 20 and are brought into conduction only when the input signal has a voltage amplitude exceeding Vth.

Therefore, as a result, the voltage generated at both ends of the capacitor 24, that is, the output voltage Vout of the rectifier circuit 17 is expressed by Expression (5).
(2 × Vin−2 × Vth) −Vth + Vin + Vin−Vth = 4 × (Vin−Vth) (5)
If the number of stages of the rectifier circuit is n, the output voltage Vout is
Vout = 2 × n × (Vin−Vth) (6)
It becomes.

Expression (6) is the same as the output voltage expression obtained by a general n-stage voltage doubler rectifier circuit. Based on this voltage, the potentials at arbitrary points e, f, g, and h are determined, and the threshold cancellation voltage and thus the gate voltage of each field effect transistor is determined. When the potential of the gate with respect to the drain of each rectifying element is Vz, the equation (6) is rewritten as the following equation (7).
Vout = 2 × n × (Vin (Vth−Vz)) (7)
However, Vin> Vth, Vth> Vz
Here, if Vth = Vz, the on / off ratio, which is the ratio between the conducting state and the non-conducting state of the field-effect transistor as a rectifying element, cannot be obtained sufficiently, and the output voltage Vout is significantly deteriorated. It should be as low as 15 to 0.25 [V]. However, since this value varies greatly depending on the performance of the device, it cannot be generally stated. It is a guide only.

If Vz = Vth−0.15,
Vout = 2n (Vin (Vth−Vz)) = 2n (Vin− (Vth− (Vth−0.15))
= 2 x n x (Vin-0.15) (8)
It becomes. The output voltage of a general voltage doubler rectifier circuit is as follows from equation (6).
2 × n × (Vin−Vth)
Here, as in the first embodiment, when Vth = 0.55 [V], the output voltage of a general voltage doubler rectifier circuit is as shown in Expression (9).

Vout = 2 × n × (Vin−0.55) (9)
From the output voltage equation (8) of the voltage doubler half wave rectifier circuit obtained by the present invention and the equation (9) of the output voltage of the voltage doubler half wave rectifier circuit to which the present invention is not applied, the present invention provides a higher voltage. It turns out that it is obtained.

  When Vth <Vz, the field effect transistors 19, 20, 21, and 22 are applied with a voltage equal to or higher than the threshold voltage. At this time, the transistor is always in a conductive state regardless of the input voltage, the rectification operation is not performed, and the output voltage Vout is significantly deteriorated. Since the output voltage Vout is a DC voltage, in this embodiment, Ve, Vf, Vg, and Vh are not supplied by the capacitors 27, 28, 29, and 30 except for the gate. Therefore, the field effect transistor 19 is biased to Ve [V], the field effect transistor 20 is biased to Vf [V], the field effect transistor 21 is biased to Vg [V], the field effect transistor 22 is biased to Vh [V], and the capacitors 27 and 28 are biased. , 29 and 30, the rectification operation is performed according to the magnitude of the AC signal input to the gate.

  In this way, the input power is rectified, the voltage is divided and supplied to the gate of the field effect transistor that is a rectifying element, whereby the threshold voltage for performing the rectifying operation can be reduced.

  Since this series of operations is performed independently of the control system such as a logic circuit, it is not necessary to secure the operating voltage of the control system. Further, the maximum value of Ve, Vf, Vg, and Vh is less than Vth, for example, 0.15 [V] to 0.25 [V] lower than Vth based on the limit voltage value determined by the voltage limit circuit. Thus, if the points e, f, g, and h are determined, the output voltage Vout does not decrease even when the input voltage increases.

As for each node voltage, each node voltage maximum value obtained by the circuit of FIG.
Ve = 0.55 [V], Vf = 0.99 [V], Vg = 1.5 [V], Vh = 1.5 [V]
It becomes.

  FIG. 8 shows the input power dependency of the output power of this circuit. The horizontal axis represents power [dBm] input to the circuit, and the vertical axis represents the output voltage [V] of the rectifier circuit. For comparison, the input voltage dependence of the output power in a standard voltage doubling half-wave rectifier circuit to which the present invention is not applied, and the voltage doubling half assuming an ideal state in which threshold cancellation operates from the beginning. The input dependence (ideal) of a wave rectifier circuit is shown. When the present invention is not applied, the output voltage increases to the limit voltage with a substantially constant slope with respect to the input power. On the other hand, in the present invention, the input power exceeds the threshold voltage Vth of the rectifying element, and threshold cancellation voltages Ve, Vf, Vg, and Vh that cancel Vth when the rectifying operation starts rises to the upper limit value according to the input power, The slope of the output voltage with respect to the input power increases. As the number of stages of rectifier circuits increases, the rise time becomes faster. As already described, since a sufficient voltage cannot be supplied to Vh, the sensitivity deteriorates when Ve, Vf, Vg, and Vh are saturated. This point can be improved by increasing the voltage limit value of the voltage limit circuit 3.

  According to the present embodiment, in the rectifier circuit using a MOS transistor as a rectifier element, the threshold voltage of the MOS transistor is lowered in a circuit according to the input power, so that the input sensitivity of the rectifier circuit is increased regardless of the magnitude of the input power. It is possible to improve the communication distance. Further, even if the input voltage increases, the output voltage does not deteriorate. In addition, a low-cost, high-performance rectifier circuit suitable for a wireless tag or the like can be provided.

  As described above, the sensitivity of the input power of the rectifier circuit can be improved by applying the present invention to the multi-stage rectifier circuit. In this embodiment, the voltage doubler half-wave rectifier circuit has been described. However, a half-wave rectifier circuit or a full-wave rectifier circuit may be used.

  FIG. 9 shows an embodiment of a two-stage voltage doubler full-wave rectifier circuit to which the present invention is applied as a fourth embodiment of the power supply circuit of the present invention. 9, the same components as those in FIG. 7 are denoted by the same reference numerals as those in FIG. The power supply circuit 16 includes a rectifier circuit 17 and a voltage limiting circuit 3, and the rectifier circuit 17 includes a negative voltage rectifier circuit. That is, the same reference numerals as those in FIG. 7 and the parts (19 ′ to 34 ′) indicated by the reference numerals with a dash on the right shoulder are negative voltage rectifier circuits. This negative voltage rectifier circuit is a circuit that performs negative voltage rectification on the input signal voltage Vin.

If the same input voltage Vin is obtained as the voltages across the capacitors 23 and 25 and the capacitors 23 'and 24' in FIG. 9, the output voltage Vout is twice that of the double voltage half-wave rectification, as shown in Expression (10). Become.
Vout = 4 × n × (Vin− (Vth−Vz)) (10)
| Vin |> Vth, Vth> Vz
Thus, the effect of the present invention can be obtained in either case of half-wave rectification or full-wave rectification.

  Next, as a fifth embodiment of the present invention, an example applied to a wireless tag will be shown. FIG. 10 shows an example of a so-called wireless tag, which is a wireless communication device equipped with the rectifier circuit of the present invention. This wireless communication apparatus includes a wireless tag 40 and a reader / writer 50. The wireless tag 40 includes a power supply circuit 41 (rectifier circuit 42, voltage limiting circuit 43), an antenna 45, a demodulation circuit 46, a modulation circuit 47, a logic control circuit 48, and a memory 49. The antenna 45 receives a signal from the reader / writer 50 or transmits information on the wireless tag to the reader / writer.

  The reader / writer 50 has a reader / writer antenna 51 and has a function of communicating with the wireless tag 40 and a function of transmitting a command for switching the operation state of the wireless tag 40 to either the normal state or the standby state. . The form of the command for switching the operation state may be any form of signal that can be identified by the wireless tag 40, such as a predetermined signal, waveform, or pulse.

  The logic control circuit 48 of the wireless tag 40 at least (1) functions to read and transmit ID information for identifying itself stored in the memory 49 when detecting predetermined command information transmitted from the reader / writer 50 in a normal state. And (2) a function of switching from a normal state to a standby state when a predetermined communication process with the reader / writer 50 is completed.

  The reader / writer 50 transmits a signal including command information for transmitting ID information for identifying itself to all the wireless tags 40 within the communication range from the reader / writer antenna 51. The wireless tag 40 that has received the signal from the reader / writer 50 transmits ID information in response to the command information. That is, the signal from the reader / writer 50 is detected by the demodulation circuit 46 of the wireless tag 40, and the logic control circuit 48 operates in accordance with the detected signal to read information in the memory 49. The read signal is modulated by the modulation circuit 47 under the control of the logic control circuit 48 and transmitted from the antenna terminal 45 to the reader / writer 50.

  The reader / writer 50 detects whether there is a communicable radio tag 40 by receiving the received ID information of the radio tag. When a communicable wireless tag 40 is detected, predetermined communication processing is sequentially executed with the wireless tag 40. The wireless tag 40 is sequentially switched to a standby state by the logic control circuit 48 at the timing when the communication process is completed. As a result, the operating state of the wireless tag 40 for which the predetermined communication process has been completed is shifted to a standby state, and signal interference with surrounding wireless tags is reduced.

  In addition, the power supply circuit 41 of the wireless tag 40 that has received the signal from the reader / writer 50 from the antenna 45 rectifies the input signal voltage Vin by the rectifier circuit 42, so that the demodulation circuit 46, the modulation circuit 47, and the logic control circuit 48. The power supply voltage Vout necessary for operating the memory 49 is generated.

  If the power supply voltage Vout is too high, each circuit is destroyed by an overvoltage, so that an upper limit value E of a voltage that can be generated by the rectifier circuit 42 is defined in the voltage limiting circuit 43.

  In such wireless communication between the reader / writer 50 and the wireless tag 40, the longer the communication distance, the better. One factor that determines this communication distance is the input sensitivity of the rectifier circuit 42. A higher input sensitivity of the rectifier circuit 42 indicates that the circuit starts to operate at a lower input voltage. In order to obtain a high voltage at a lower voltage in the rectifier circuit 42, it is necessary to make the dead zone of the circuit as small as possible.

  The voltage of a general voltage doubler half-wave rectifier circuit is expressed by equations (1) and (6), and among these, the threshold voltage Vth of the rectifier element represents the dead zone of the circuit. If the input voltage Vin does not exceed the threshold voltage Vth, the circuit does not start the rectification operation.

  As for the voltage obtained by the rectifier circuit 42 to which the present invention is applied, the circuit operates so as to reduce the dead zone as in the equations (4) and (7), so that a higher voltage can be obtained with a lower voltage. Therefore, the communication distance can be increased. As described above, this rectifier circuit 42 is effective even in a full-wave rectifier circuit even in a half-wave rectifier circuit to which the present invention is applied.

  According to the present embodiment, the input sensitivity of the rectifier circuit can be improved regardless of the magnitude of the input power, and the communication distance of the wireless tag can be improved. Further, even if the input voltage increases, the output voltage does not deteriorate. Therefore, a low-cost and high-performance wireless tag can be provided.

  Next, as a sixth embodiment of the present invention, FIG. 11 shows an example applied to a sensor network system for management in product manufacturing process and distribution process. At the stage of product manufacture and distribution, each product is provided with a node with a sensor, and various physical quantities such as position information are measured as needed, and these physical quantities are sent from the node to the host via the network. The host uses the measurement information from the node as input and performs business processing using applications such as production management and inventory management. Thereby, improvement of productivity and improvement of distribution efficiency can be aimed at.

  FIG. 11 shows an example in which the rectifier circuit of the present invention is mounted on a sensor-attached node of such a sensor network system. The sensor network system includes a plurality of sensor-attached nodes 60 (60a, 60b,-,-), a gateway 70 (70a, 70b,-,-), a name server 80, a business server 90, and a network 100.

  Each node 60 (60a, 60b,-,-) has a wireless communication function, measures various information using a built-in sensor, and gateways various electronic data including the measurement information through the wireless communication function. Replace with 70. The gateway 70 is a base station having a wireless communication function and a normal network communication function, and realizes a data conversion processing function between the two different communication protocols. The name server 80 is a normal server computer that manages the relationship between the node identifier, the identifier of the entity to which the node is attached, and the identifier of the base station that communicates with the node, and responds with the related information in response to the inquiry. Implement service functions. The business server (140) executes a business application.

  The sensor-attached node 60 includes a power supply circuit 61 (= rectifier circuit 62), a sensor unit 64, an antenna 65, a demodulation circuit 66, a modulation circuit 67, a logic control circuit 68, and a memory 69. The output of the rectifier circuit 62 is also supplied to the battery. The antenna 65 receives signals such as various command information from the gateway 70, or transmits data measured by the node to the gateway 70. The logic control circuit 68 executes node management and sensing processing. The power supply circuit 61 provides a function of supplying power for driving the sensor-attached node. That is, the rectifier circuit 62 of the node 60 that has received the signal from the gateway 70 is necessary to operate the demodulation circuit 66, the modulation circuit 6, the logic control circuit 68, and the memory 69 by rectifying the input signal voltage Vin. A stable power supply voltage Vout is generated. As the voltage obtained by the rectifier circuit 62 to which the present invention is applied, the circuit operates so as to reduce the dead zone as in the equations (4) and (7), so that a higher voltage can be obtained with a lower voltage. Therefore, the communication distance can be increased.

  The power supply circuit 61 of this embodiment does not have a voltage limiting circuit. As in the system of this embodiment, in a sensor network system for product manufacture and distribution management, the positional relationship between the sensor-attached node and the gateway 70 often varies within a relatively limited range. As described above, when the distance between the node 60 and the gateway 70 is substantially constant, in other words, when the upper limit of the input power from the antenna does not change significantly, ΔVth exceeds Vth1 even if the power supply circuit 61 is not provided with a voltage limiting circuit. I can not.

  According to the present embodiment, the input sensitivity of the rectifier circuit can be improved regardless of the magnitude of the input power, and the communication distance of the sensor-equipped node can be improved. Therefore, a low-cost, high-performance sensor network system can be provided.

  Decreasing the threshold voltage of the field effect transistor used as the rectifying element of the rectifying circuit is directly connected to increasing the minimum input sensitivity of the rectifying circuit. A higher rectified voltage can be obtained with lower input power. Thereby, a wireless tag having a long communication distance can be supplied. This indicates that the distance between the reader / writer and the wireless tag can be increased in an entry / exit management system, a collection management system, etc., and the degree of freedom of installation of the reader / writer is increased. If the communication distance is left as it is, a more stable rectified voltage can be obtained, so that stable wireless communication is possible. Therefore, it is possible to provide a wireless tag system and a sensor network system that are small, high performance, and low power consumption. In addition, a small, high-performance, low-power consumption circuit can be provided as a power supply circuit that can be used for a non-contact charger and a voltage generator.

1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a circuit diagram schematically illustrating a relationship among an input terminal, a MOS transistor, and a resistance element in the power supply circuit of FIG. 1. FIG. 3 is a diagram showing DC current-voltage characteristics of the diode-connected MOS transistor circuit shown in FIG. 2. FIG. 6 is a diagram illustrating a specific example of setting a threshold cancellation voltage for biasing the field effect transistor to the voltage Va [V] and the field effect transistor to the voltage Vb [V] in the first embodiment of the present invention. is there. It is a figure which shows the input power dependence of output power in 1st Example of this invention. It is the figure which replaced the voltage dividing element which shows the 2nd Example of this invention. It is a circuit diagram which shows the 3rd Example of this invention. It is a figure which shows the input power dependence of output power in the 3rd Example of this invention. It is a circuit diagram which shows the 4th Example of this invention. It is a block diagram of the wireless tag which shows the 5th Example of this invention. It is a figure which shows the example of the sensor network system for the management in the manufacture process of a product, and a distribution process as 6th Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,16 ... Power supply circuit, 2,17 ... Rectification circuit, 3 ... Voltage limiting circuit, 4,18 ... Input terminal,
5, 6, 19, 20, 21, 22, 19 ', 20', 21 ', 22' ... field effect transistors,
7, 8, 9, 10, 23, 24, 25, 26, 27, 28, 29, 30, 23 ', 24', 25 ', 26', 27 ', 28', 29 ', 30' ... capacitor,
11, 12, 14, 1531, 32, 33, 34, 31 ', 32', 33 ', 34', 34 '... voltage dividing element,
35 ... Antenna, 36 ... Rectifier circuit, 37 ... Demodulator circuit, 38 ... Modulator circuit, 39 ... Voltage limiting circuit, 40 ... Logic control circuit, 41 ... Memory.

Claims (20)

A rectifier circuit unit that obtains an operating voltage from an input signal, and a voltage limiting circuit unit that limits the output voltage of the rectifier circuit unit to a constant value,
The rectifier element of the rectifier circuit unit is composed of a field effect transistor,
A rectifier circuit configured to divide an operating voltage output from the rectifier circuit unit and supply the divided voltage to a gate terminal of the field effect transistor. In claim 1,
The rectifier circuit unit includes the field effect transistor and a capacitor,
The gate terminal and drain terminal of the field effect transistor are connected by a coupling capacitor,
A rectifier circuit configured to supply the divided voltage to a connection portion between a gate terminal of the field effect transistor and the coupling capacitor. In claim 2,
The divided voltage is 0.15 V to 0. 0 than the threshold voltage of the field effect transistor in a rated voltage state where the output voltage of the rectifier circuit unit is limited to a constant value by the voltage limiting circuit unit. A rectifier circuit that is set to have a voltage lower by 25V. In claim 1,
The rectifier circuit unit includes at least two sets of field effect transistors and capacitors,
The gate terminal and the drain terminal of each field effect transistor of each set are connected by a coupling capacitor,
Each of the operating voltages output from the rectifier circuit unit is divided to generate a threshold cancellation voltage for lowering the threshold voltage of each set of field effect transistors,
2. A rectifier circuit configured to supply the divided voltage to a connection portion between a gate terminal of each field effect transistor of each set and the coupling capacitor. In claim 4,
The operating voltage output from the rectifier circuit unit is divided by resistive elements, and the output voltage of the rectifier circuit unit is in a rated voltage state that is limited to a constant value by the voltage limiting circuit unit. A rectifier circuit characterized by generating a voltage 0.15 V to 0.25 V lower than a threshold voltage of an effect transistor. In claim 4,
The operating voltage output from the rectifier circuit unit is divided by multi-stage diode-connected field effect transistors, and the output voltage of the rectifier circuit unit is a rated voltage that is limited to a constant value by the voltage limiting circuit unit. A rectifier circuit characterized by generating a voltage 0.15 V to 0.25 V lower than the threshold voltage of each group of field effect transistors. In claim 1,
The rectifier circuit unit is constituted by a voltage doubler rectifier circuit, and has a function of detecting the input signal. In claim 1,
Even when the output voltage of the rectifier circuit section is less than the rated voltage limited to a constant value by the voltage limit circuit section, the operating voltage output from the rectifier circuit section is divided, and the field effect transistor A rectifier circuit configured to be supplied to a gate terminal of the rectifier. In claim 1,
The rectifier circuit includes at least a first field effect transistor and a first capacitor, a second field effect transistor and a second capacitor, a first terminal, a second terminal, and a third terminal. And
The first terminal is connected to one end of the first capacitor, and the other end of the first capacitor is a connection portion between the source terminal of the first field effect transistor and the drain terminal of the second field effect transistor. Connected to
The second terminal is connected to a reference potential or ground potential of the rectifier circuit;
A drain terminal of the first field effect transistor is connected to the second terminal;
One end of the second capacitor and the source terminal of the second field effect transistor are connected to the third terminal,
The other end of the second capacitor is connected to the second terminal;
A first resistor element group and a second resistor element group for voltage division are connected between the third terminal and the second terminal,
In the state where the output voltage is a rated voltage controlled by the voltage limiting circuit, a cancel voltage supplied to the gate terminal of the first field effect transistor becomes a voltage higher than the potential of the second terminal, The cancel voltage supplied to the gate terminal of the second field effect transistor is higher than the voltage at the connection between the source terminal of the first field effect transistor and the drain terminal of the second field effect transistor. And a resistance ratio of the first resistance element group and the second resistance element group is set. In claim 1,
The rectifier circuit portion includes at least a first field effect transistor and a first capacitor, a second field effect transistor and a second capacitor, a first terminal, a second terminal, and a third terminal. Comprising
The first terminal is connected to one end of the first capacitor, and the other end of the first capacitor is a connection portion between the source terminal of the first field effect transistor and the drain terminal of the second field effect transistor. Connected to
The second terminal is connected to a reference potential or ground potential of the rectifier circuit;
A drain terminal of the first field effect transistor is connected to the second terminal;
One end of the second capacitor and the source terminal of the second field effect transistor are connected to the third terminal,
The other end of the second capacitor is connected to the second terminal;
Between the third terminal and the second terminal, the first multistage-connected diode-connected field-effect transistor groups and the second multistage-connected diode-connected field effect transistor groups for voltage division are divided. Connected,
In a state where the output voltage is a rated voltage controlled by the voltage limiting circuit, a threshold cancellation voltage supplied to the gate terminal of the first field effect transistor becomes a voltage higher than the potential of the second terminal, A threshold cancellation voltage supplied to a gate terminal of the second field effect transistor is higher than a voltage at a connection portion between a source terminal of the first field effect transistor and a drain terminal of the second field effect transistor; The rectifier circuit is characterized in that a resistance ratio of each of the first and second multistage-connected diode-connected field effect transistor groups is set. In claim 1,
Comprising at least a first field effect transistor and a first capacitor, a second field effect transistor and a second capacitor, a first terminal, a second terminal and a third terminal;
The first terminal is connected to one end of the first capacitor, and the other end of the first capacitor is a connection portion between the source terminal of the first field effect transistor and the drain terminal of the second field effect transistor. Connected to
The second terminal is connected to a reference potential or ground potential of the rectifier circuit;
A drain terminal of the first field effect transistor is connected to the second terminal;
One end of the second capacitor and the source terminal of the second field effect transistor are connected to the third terminal,
The other end of the second capacitor is connected to the second terminal;
A gate terminal and a drain terminal of the first field effect transistor are connected via a first connecting capacitor;
A gate terminal and a drain terminal of the second field effect transistor are connected via a second connection capacitor;
A rectifier circuit configured to divide and supply a voltage between the third terminal and the second terminal to the gate terminal of each field effect transistor. In claim 1,
Including a rectifier circuit portion connected in multiple stages in at least two stages, and having a function of detecting an input signal and obtaining an output voltage for power supply from the input signal;
The rectifying element of the rectifying circuit portion of each stage is composed of a field effect transistor,
A rectifier circuit configured to divide an operating voltage output from the rectifier circuit unit in the final stage and supply the divided voltage to a gate terminal of a field effect transistor in the rectifier circuit unit in each stage. The rectifier element is composed of a field effect transistor,
A function of detecting an input signal, and a function of rectifying the input signal and outputting it as an operating voltage.
A rectifier circuit configured to divide an operation voltage to be output and supply the divided voltage to a gate terminal of the field effect transistor. In claim 13,
Comprising at least two sets of field effect transistors and capacitors;
A rectifier circuit comprising: dividing an operating voltage obtained by rectifying the input signal with a resistance element, and setting the divided voltage as a threshold cancel voltage for lowering a threshold of each field effect transistor. A transmission / reception antenna, a demodulation circuit that demodulates a signal received from the transmission / reception antenna, a logic control circuit that performs signal processing according to the demodulation signal, a storage circuit, and a rectification circuit;
The rectifier circuit has a function of detecting an input signal input from the transmission / reception antenna and obtaining an operating voltage of each circuit from the input signal,
2. A radio communication apparatus according to claim 1, wherein the rectifier element of the rectifier circuit is configured by a field effect transistor, and the operating voltage is divided and supplied to a gate terminal of the field effect transistor. In claim 15,
A wireless communication apparatus comprising a voltage limiting circuit for limiting an output voltage of the rectifier circuit to a constant value. In claim 16,
Even when the output voltage of the rectifier circuit is less than the operating voltage of each circuit of the wireless communication device, the operating voltage output from the rectifier circuit is divided and supplied to the gate terminal of the field effect transistor It is comprised so that it may be comprised, The wireless communication apparatus characterized by the above-mentioned. In claim 16,
The rectifier circuit comprises a field effect transistor and a capacitor,
The first terminal is connected to the input terminal, the second terminal is connected to a reference potential or ground potential common to the rectifier circuit and the previous voltage limit circuit, and the third terminal is connected to the voltage limit circuit as an output terminal And
The first terminal is connected to one end of a first capacitor, the other end of the first capacitor is connected to a drain terminal of the first field effect transistor,
The second terminal is connected to a drain terminal of a second field effect transistor, and a source terminal of the second field effect transistor is connected to a connection portion of the first capacitor and the first field effect transistor;
One end of a second capacitor and a source terminal of a second field effect transistor are connected to the third terminal, and the other end of the second capacitor is connected to the second terminal,
A first capacitor for connection is connected to a gate terminal and a drain terminal of the first field effect transistor;
2. A wireless communication apparatus comprising: a second capacitor for connection connected to a gate terminal and a drain terminal of the second field effect transistor. In claim 18,
The rectifier circuit has a plurality of rectifier circuit sections each having the first input terminal, a second reference potential terminal, and a third output terminal,
A wireless communication apparatus comprising a multistage configuration in which the third terminal of the first rectifier circuit section is connected to the first input terminal of the next stage rectifier circuit section. In claim 18,
A wireless communication apparatus, which is a wireless tag and has a function of receiving a signal from a reader / writer or transmitting information of the wireless tag to the reader / writer.

Images