JP2008164479A - Pulse specification detector - Google Patents

Pulse specification detector Download PDF

Info

Publication number
JP2008164479A
JP2008164479A JP2006355314A JP2006355314A JP2008164479A JP 2008164479 A JP2008164479 A JP 2008164479A JP 2006355314 A JP2006355314 A JP 2006355314A JP 2006355314 A JP2006355314 A JP 2006355314A JP 2008164479 A JP2008164479 A JP 2008164479A
Authority
JP
Japan
Prior art keywords
processing
fft
fft processing
pulse
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006355314A
Other languages
Japanese (ja)
Other versions
JP4682127B2 (en
Inventor
Kazuhide Nomoto
和秀 野本
Takao Yamamoto
敬央 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2006355314A priority Critical patent/JP4682127B2/en
Publication of JP2008164479A publication Critical patent/JP2008164479A/en
Application granted granted Critical
Publication of JP4682127B2 publication Critical patent/JP4682127B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Radar Systems Or Details Thereof (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem wherein, when pulse specification is detected by fast Fourier transform (FFT) processing, increasing the number of sampling times for FFT processing increases the frequency resolution, but increasing the number of sampling times reduces the time resolution. <P>SOLUTION: A pulse specification detector includes a receiving section 3 for frequency-converting the RF signal output from an antenna having received arrival electric wave into an IF signal, an A/D conversion circuit 4 for converting the IF signal into a digital sample signal, an FFT processing circuit 10 for overlapping a processing point of the fast Fourier transform with the digital sample signal and performing the FFT analysis processing, and a specification detecting circuit 6 for detecting the specification of the arrival electric wave from the FFT processing result. The frequency resolution is kept while securing the time resolution, and the pulse specification is detected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

この発明は、パルス状の到来電波の諸元を検出するパルス諸元検出装置に関するもので、特に受信信号を高速フーリエ変換（ＦＦＴ＝Fast Fourier Transform）処理することにより諸元を検出するパルス諸元検出装置に関するものである。   The present invention relates to a pulse specification detection device for detecting specifications of a pulsed incoming radio wave, and in particular, a pulse specification for detecting a specification by performing fast Fourier transform (FFT) processing on a received signal. The present invention relates to a detection device.

アンテナから時系列に入力される高周波（ＲＦ＝RadioFrequency）信号の到来電波を受信して、その受信信号のパルス諸元、例えばパルス到来時刻（ＴＯＡ＝Time of Arrival）、パルス幅（ＰＷ＝Pulse Wide）、パルス振幅（ＰＡ＝Pulse Amplitude）、周波数（Ｆ＝Frequency）などを検出することにより目標識別などを行うことが知られている。
このようなパルス諸元を検出する手段の１つとして、周波数解析手段に高速フーリエ変換（ＦＦＴ）処理と最大エントロピー（ＭＥＭ）処理を併用したものがある。高速フーリエ変換（ＦＦＴ）処理の場合、周波数分解能はビート信号に対するサンプリング数に依存するため、サンプリング数が多いほど周波数分解能は上がるが、サンプリング数が少ないと周波数分解能は下がる。一方、最大エントロピー（ＭＥＭ）処理の場合、周波数分解能はサンプリング数に依存せず、高い分解能が得られるが、スペクトルの強度が忠実に再現されない。したがってＦＦＴ処理のスペクトルの強度の忠実性があるという利点とＭＥＭ処理の高い周波数分解能が得られるという利点を組み合わせて周波数解析を行うようにしたものである。 Receives incoming radio waves of a radio frequency (RF = RadioFrequency) signal input from an antenna in time series, and receives the pulse specifications of the received signal, for example, pulse arrival time (TOA = Time of Arrival), pulse width (PW = Pulse Wide) ), Pulse amplitude (PA = Pulse Amplitude), frequency (F = Frequency), and the like are known to perform target identification and the like.
As one of means for detecting such a pulse specification, there is one in which fast Fourier transform (FFT) processing and maximum entropy (MEM) processing are used in combination with frequency analysis means. In the case of fast Fourier transform (FFT) processing, since the frequency resolution depends on the number of samplings for the beat signal, the frequency resolution increases as the sampling number increases, but the frequency resolution decreases as the sampling number decreases. On the other hand, in the case of maximum entropy (MEM) processing, the frequency resolution does not depend on the number of samplings and high resolution is obtained, but the intensity of the spectrum is not faithfully reproduced. Therefore, the frequency analysis is performed by combining the advantage that the FFT processing spectrum has high fidelity and the advantage that the high frequency resolution of the MEM processing can be obtained.

特に、高速フーリエ変換（ＦＦＴ）処理の場合は、周波数分解能に多少問題はあるものの、複数パルスが重畳した入力波に対しては分離／識別ができる上、目標の有無および強度については忠実であるため、目標識別などの周波数解析にはよく使用されている。（特許文献１参照）
特開２００１−３４９９４１号公報 In particular, in the case of Fast Fourier Transform (FFT) processing, although there is a slight problem in frequency resolution, it is possible to separate / identify an input wave on which a plurality of pulses are superimposed, and the presence / absence and intensity of a target are faithful. Therefore, it is often used for frequency analysis such as target identification. (See Patent Document 1)
JP 2001-349941 A

高速フーリエ変換（ＦＦＴ）処理でパルス諸元を検出する場合、周波数上で処理ができるため、複数パルスが重畳した入力波に対しては分離および識別が可能となるが、高速フーリエ変換（ＦＦＴ）処理の為には、サンプリング数（ポイント数）のデータの纏まりが必要である。したがって、同一サンプリングレートに対して、ＦＦＴ処理のサンプリング数を増加すれば周波数分解能は高くなるが、逆にサンプリング数が増加することで時間分解能が悪化するという課題があった。   In the case of detecting pulse specifications by fast Fourier transform (FFT) processing, since processing can be performed on the frequency, it is possible to separate and identify an input wave on which a plurality of pulses are superimposed, but fast Fourier transform (FFT) For processing, it is necessary to collect data of the number of samplings (number of points). Therefore, if the number of FFT processing samplings is increased for the same sampling rate, the frequency resolution increases, but conversely there is a problem that the time resolution deteriorates as the number of samplings increases.

この発明は、高速フーリエ変換（ＦＦＴ）処理でパルス諸元を検出する場合、時間分解能を確保しながら周波数分解能も維持することにより、高精度のパルス諸元検出装置を得ることを目的とするものである。   An object of the present invention is to obtain a highly accurate pulse specification detection device by maintaining a frequency resolution while ensuring a time resolution when detecting a pulse specification by fast Fourier transform (FFT) processing. It is.

この発明のパルス諸元検出装置は、到来電波を受けたアンテナから出力される高周波信号を中間周波数信号に周波数変換する受信部と、この受信部により変換された中間周波数信号をデジタルのサンプル信号に変換するアナログ／デジタル変換回路と、このアナログ／デジタル変換回路からのデジタルサンプル信号に対して、高速フーリエ変換（ＦＦＴ）の処理ポイントをオーバーラップしてＦＦＴ解析処理を行うＦＦＴ処理回路と、このＦＦＴ処理回路からの出力により到来電波の諸元を検出する諸元検出回路を備えたものである。   The pulse specification detection device of the present invention includes a receiving unit that converts a high-frequency signal output from an antenna that has received an incoming radio wave into an intermediate frequency signal, and the intermediate frequency signal converted by the receiving unit is converted into a digital sample signal. An analog / digital conversion circuit for conversion, an FFT processing circuit for performing FFT analysis processing by overlapping fast Fourier transform (FFT) processing points on the digital sample signal from the analog / digital conversion circuit, and the FFT It is provided with a specification detection circuit for detecting the specification of the incoming radio wave from the output from the processing circuit.

またこの発明のパルス諸元検出装置は、到来電波を受けたアンテナから出力される高周波信号を中間周波数信号に周波数変換する受信部と、この受信部により変換された中間周波数信号をデジタルのサンプル信号に変換するアナログ／デジタル変換回路と、このアナログ／デジタル変換回路からのデジタルサンプル信号に対して、高速フーリエ変換（ＦＦＴ）の処理ポイント数が異なる２種類のＦＦＴ解析を並列処理するＦＦＴ処理回路と、このＦＦＴ処理回路からの出力により到来電波の諸元を検出する諸元検出回路を備えたものである。   In addition, the pulse specification detecting device of the present invention includes a receiving unit that converts a high-frequency signal output from an antenna that has received an incoming radio wave into an intermediate frequency signal, and a digital sample signal from the intermediate frequency signal converted by the receiving unit. An analog / digital conversion circuit that converts the signal into a digital signal, and an FFT processing circuit that performs parallel processing on two types of FFT analysis with different number of processing points of fast Fourier transform (FFT) on the digital sample signal from the analog / digital conversion circuit And a specification detection circuit for detecting the specification of the incoming radio wave from the output from the FFT processing circuit.

この発明によれば、高速フーリエ変換（ＦＦＴ）処理を行うポイントをオーバーラップしてＦＦＴ解析を実行することにより、パルス幅の短い信号の検出にも対応でき、オーバーラップ量が大きいということは、ＦＦＴ処理結果が短時間で出力されることを意味し、検出されるパルス諸元の時間分解能が向上する。
また、ＦＦＴ処理をポイント数Ｍ点とＮ点（Ｍ＜Ｎ）毎に２系統で並列処理を行うことにより、周波数分解能、時間分解能それぞれ最良の諸元が抽出できる。 According to the present invention, by performing FFT analysis by overlapping the points at which fast Fourier transform (FFT) processing is performed, it is possible to cope with detection of a signal with a short pulse width, and the amount of overlap is large. This means that the FFT processing result is output in a short time, and the time resolution of the detected pulse specifications is improved.
In addition, by performing parallel processing in two systems for each M points and N points (M <N) of the FFT processing, the best specifications for frequency resolution and time resolution can be extracted.

発明の基本形態
まず、この発明のパルス諸元検出装置の基本的な形態について説明する。図１はこの発明が適用される基本的な構成図を、図２は高速フーリエ変換（ＦＦＴ）処理を行なった特性図を、図３はＦＦＴ処理結果による時間−周波数成分の特性図をそれぞれ示す。
図２の構成図において、受信アンテナ１は到来電波の高周波（ＲＦ）信号を受信する。アンテナ１から出力されるＲＦ信号は中間周波数（ＩＦ＝Intermediate Frequency）信号へ周波数変換するミキサ２などを有した受信部３に入力される。受信部３で変換された中間周波数信号は、アナログ信号をデジタル信号に変換するアナログ／デジタル（Ａ/Ｄ）変換回路４、高速フーリエ変換（ＦＦＴ）処理を行なうＦＦＴ処理回路５、ＦＦＴ処理結果によりパルス諸元を検出する諸元検出回路６を備えた信号処理回路７に入力され、パルス諸元データを分析する。プロセッサ８は信号処理回路７で分析されたパルス諸元データに基づき、目標識別を行うものである。 Basic form of the invention First, the basic form of the pulse specification detecting apparatus of the present invention will be described. FIG. 1 is a basic configuration diagram to which the present invention is applied, FIG. 2 is a characteristic diagram obtained by performing a fast Fourier transform (FFT) process, and FIG. 3 is a characteristic diagram of a time-frequency component resulting from the FFT process. .
In the configuration diagram of FIG. 2, the receiving antenna 1 receives a radio frequency (RF) signal of an incoming radio wave. An RF signal output from the antenna 1 is input to a receiving unit 3 having a mixer 2 that converts the frequency into an intermediate frequency (IF) signal. The intermediate frequency signal converted by the receiving unit 3 includes an analog / digital (A / D) conversion circuit 4 that converts an analog signal into a digital signal, an FFT processing circuit 5 that performs fast Fourier transform (FFT) processing, and an FFT processing result. The data is input to a signal processing circuit 7 having a specification detection circuit 6 for detecting a pulse specification, and the pulse specification data is analyzed. The processor 8 performs target identification based on the pulse specification data analyzed by the signal processing circuit 7.

図１の構成による動作を図２及び図３に基づき説明する。まず受信部３から出力される中間周波数（ＩＦ）信号をＡ/Ｄ変換回路４にて高速サンプリングし、デジタルサンプル信号とする。ＦＦＴ処理回路５は、デジタルサンプル信号に対して、予め設定されたポイント（サンプル）数のＦＦＴ処理を行い、周波数成分を抽出する。
図２はＦＦＴ処理の各時刻おける周波数成分を示す特性図で、図２（ａ）はＸ回目の処理特性図、図２（ｂ）はＸ＋１回目の処理特性図、図２（ｃ）はＸ＋２回目の処理特性図、図２（ｄ）はＸ＋３回目の処理特性図、図２（ｅ）はＸ＋４回目の処理特性図をそれぞれ示し、ここで予め設定されたスレッショルドレベルを越えた振幅値があればパルスデータを受信したと判断し、その諸元データの検出処理を行う。
この図２では、ＦＦＴ処理のＸ回目からＸ＋４回目まですべてに周波数Ｆ１の信号の振幅値がスレッショルドレベルを越え、ＦＦＴ処理のＸ＋３回目からＸ＋４回目までに周波数Ｆ２の信号の振幅値がスレッショルドレベルを越えていることを示している。 1 will be described with reference to FIGS. 2 and 3. FIG. First, the intermediate frequency (IF) signal output from the receiving unit 3 is sampled at high speed by the A / D conversion circuit 4 to obtain a digital sample signal. The FFT processing circuit 5 performs FFT processing of a preset number of points (samples) on the digital sample signal, and extracts frequency components.
FIG. 2 is a characteristic diagram showing frequency components at each time of FFT processing. FIG. 2 (a) is an Xth processing characteristic diagram, FIG. 2 (b) is an X + 1th processing characteristic diagram, and FIG. 2 (c) is X + 2. FIG. 2 (d) shows an X + 3th processing characteristic diagram, and FIG. 2 (e) shows an X + 4th processing characteristic diagram, where there is an amplitude value exceeding a preset threshold level. For example, it is determined that pulse data has been received, and the specification data is detected.
In FIG. 2, the amplitude value of the signal of frequency F1 exceeds the threshold level from the Xth time to the X + 4th time of the FFT processing, and the amplitude value of the signal of frequency F2 reaches the threshold level from the X + 3th time to the X + 4th time of the FFT processing. It shows that it has exceeded.

図３は、図２によるＦＦＴ処理結果を基に、横軸を時間にスレッショルドレベルを越えた振幅値の周波数データをプロットしたものである。ＦＦＴ処理を行うことで、周波数Ｆ１、Ｆ２がそれぞれ弁別されて検出され、また、それぞれの周波数Ｆ１、Ｆ２に対して到来時刻ＴＯＡはスレッショルドレベル以上になった時刻で検出でき、パルス幅ＰＷは周波数がスレッショルドレベル以上である回数分から検出できる。
この図３では、到来時刻ＴＯＡ（Time of Arrival）１に周波数Ｆ（Frequency）１、パルス幅ＰＷ（Pulse Wide）１の信号が検出され、またパルス到来時刻ＴＯＡ２に周波数Ｆ２、パルス幅ＰＷ２の信号が検出され、２波の信号が重畳した到来電波が分離、検出できることを示している。 FIG. 3 is a plot of frequency data of amplitude values exceeding the threshold level with time on the horizontal axis on the basis of the FFT processing result according to FIG. By performing the FFT processing, the frequencies F1 and F2 are discriminated and detected, and the arrival time TOA can be detected at the time when the frequencies F1 and F2 are equal to or higher than the threshold level, and the pulse width PW is the frequency. Can be detected from the number of times that is equal to or higher than the threshold level.
In FIG. 3, a signal having a frequency F (Frequency) 1 and a pulse width PW (Pulse Wide) 1 is detected at an arrival time TOA (Time of Arrival) 1, and a signal having a frequency F2 and a pulse width PW2 is detected at a pulse arrival time TOA2. Is detected, indicating that the incoming radio wave on which two signals are superimposed can be separated and detected.

こうして中間周波数（ＩＦ）信号をＡ/Ｄ変換したディジタルデータに対してＦＦＴ処理を行うことで、周波数が異なる複数同時入力信号を分離および識別することができ、また、それぞれの周波数に対して到来時刻ＴＯＡ、パルス幅ＰＷ、パルス振幅ＰＡを検出できる。   By performing FFT processing on digital data obtained by A / D-converting intermediate frequency (IF) signals in this way, multiple simultaneous input signals with different frequencies can be separated and identified, and arrive at each frequency. The time TOA, the pulse width PW, and the pulse amplitude PA can be detected.

実施の形態１
次にこの発明の実施の形態１におけるパルス諸元検出装置を図４〜図６について説明する。図４はこの発明の実施の形態１に使用されるＦＦＴ処理回路を示す構成図、図５はＦＦＴ処理の概念図、図６はＦＦＴ処理結果を従来と比較して示す図である。
この発明の実施の形態１は、図１に示す基本構成図のＦＦＴ処理回路５を、この図４に示すような構成のＦＦＴ処理回路１０としたもので、その他の構成は図１の基本構成図と同じに付き、説明を省略する。 Embodiment 1
Next, a pulse specification detection apparatus according to Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 4 is a block diagram showing the FFT processing circuit used in Embodiment 1 of the present invention, FIG. 5 is a conceptual diagram of the FFT processing, and FIG. 6 is a diagram showing the FFT processing result in comparison with the conventional one.
In the first embodiment of the present invention, the FFT processing circuit 5 of the basic configuration diagram shown in FIG. 1 is replaced with an FFT processing circuit 10 of the configuration shown in FIG. 4, and other configurations are the basic configuration of FIG. It is the same as the figure and will not be described.

図４において、ＦＦＴ処理回路１０は、複数のＦＦＴ処理部１０１〜１０４を有し、１サイクルの処理ポイント数Ｎを複数ポイント数Ｍ（但し、ＭはＮ／ｎ、ｎは整数）ずつスライドさせるようにして、オーバーラップしてＦＦＴ処理するようにしている。即ち、各ＦＦＴ処理部１０１〜１０４は、すべて同じ処理ポイント数ＮでＦＦＴ処理を行なうが、処理の開始時間がポイント数Ｍずつずれている。   4, the FFT processing circuit 10 includes a plurality of FFT processing units 101 to 104, and slides the processing point number N in one cycle by a plurality of point numbers M (where M is N / n, n is an integer). In this way, the FFT processing is performed in an overlapping manner. That is, each of the FFT processing units 101 to 104 performs the FFT processing with the same processing point number N, but the processing start time is shifted by the point number M.

図４における構成の動作を図５および図６に基づいて説明する。図４および図５では１サイクルのＦＦＴ処理ポイント数Ｎを１２８とし、１サイクル１２８ポイントを例えばポイント数Ｍを３２ポイントずつスライドさせることを例に説明する。したがってＦＦＴ処理部１０１〜１０４はＮ／Ｍ＝１２８／３２で４個必要となる。
受信部３で中間周波数（ＩＦ）信号に変換されたパルス変調信号はＡ／Ｄ変換回路４でデジタルサンプル信号に変換され、ＦＦＴ処理回路１０の各ＦＦＴ処理部１０１〜１０４に並列に入力される。各ＦＦＴ処理部１０１〜１０４によるＦＦＴ処理の結果、図５に示すように、ＦＦＴ処理部１０１（ＦＦＴ１）の出力は、処理ポイント数１２８毎に出力される出力Ａ、Ｂに相当することになる。またＦＦＴ処理部１０２（ＦＦＴ２）の出力は、出力Ａからポイント数３２ずれた出力ａに相当する。同様にＦＦＴ処理部１０３（ＦＦＴ３）の出力は、出力ｂに、ＦＦＴ処理部１０４（ＦＦＴ４）の出力は、出力ｃに相当することになる。
このように１サイクル１２８ポイントを例えばポイント数を３２ポイントずつスライドさせることによって、１サイクル中で４回のＦＦＴ処理出力（a、ｂ、ｃ、Ｂ）に相当するものが得られることになる。 The operation of the configuration in FIG. 4 will be described with reference to FIGS. 4 and 5, an example will be described in which the number N of FFT processing points in one cycle is 128, and one cycle of 128 points is slid by, for example, 32 points each time. Therefore, four FFT processing units 101 to 104 are required at N / M = 128/32.
The pulse modulation signal converted into the intermediate frequency (IF) signal by the receiving unit 3 is converted into a digital sample signal by the A / D conversion circuit 4 and input in parallel to the FFT processing units 101 to 104 of the FFT processing circuit 10. . As a result of the FFT processing by each of the FFT processing units 101 to 104, as shown in FIG. 5, the output of the FFT processing unit 101 (FFT1) corresponds to outputs A and B output every 128 processing points. . The output of the FFT processing unit 102 (FFT2) corresponds to an output a that is 32 points away from the output A. Similarly, the output of the FFT processing unit 103 (FFT3) corresponds to the output b, and the output of the FFT processing unit 104 (FFT4) corresponds to the output c.
In this way, by sliding 128 points in one cycle, for example, by 32 points each, one corresponding to four FFT processing outputs (a, b, c, B) in one cycle can be obtained.

図６に、到来電波の入力（ＩＦ）信号に対して、処理ポイントをオーバーラップさせてＦＦＴ処理を行った場合と、オーバーラップ無しでＦＦＴ処理を行った場合との検出パルスの分析結果を比較して示す。この図６から明らかなように、処理ポイントをオーバーラップ無しで１２８ポイントＦＦＴ処理をシリーズに実行した時の検出パルスのパルス幅はＰＷ１となる。また処理ポイントをオーバーラップさせて１２８ポイントを３２ポイントずつシフトして４分割でＦＦＴ処理して実行した時の検出パルスのパルス幅はＰＷ２となる。   Fig. 6 compares the analysis results of detected pulses when FFT processing is performed with overlapping processing points on the incoming radio wave input (IF) signal and when FFT processing is performed without overlap. Show. As is apparent from FIG. 6, the pulse width of the detection pulse when the 128-point FFT processing is executed in series without overlapping the processing points is PW1. When the processing points are overlapped and 128 points are shifted by 32 points and FFT processing is performed in four divisions, the pulse width of the detection pulse is PW2.

即ち、ポイント数Ｍ（３２点）毎の出力ａ、ｂ、ｃによるパルス諸元検出で、パルス幅ＰＷとパルス到来時刻ＴＯＡの諸元をとり、ポイント数Ｎ（１２８点）毎の出力Ａ、Ｂによるパルス諸元検出で、周波数Ｆとパルス振幅ＰＡの諸元をとることによって、時間分解能を確保しながら周波数分解能も維持できる。
このように、ＦＦＴ処理を行うポイント数をオーバーラップして、ＦＦＴ解析を実行することにより、パルス諸元のパルス幅ＰＷ、パルス到来時刻ＴＯＡの精度（時間分解能）が向上でき、また周波数分解能も維持して高精度のパルス諸元検出装置を得ることができる。 That is, by detecting the pulse specifications based on the outputs a, b, and c for each point number M (32 points), the pulse width PW and the pulse arrival time TOA are taken, and the output A for each point number N (128 points). By detecting the specifications of the frequency F and the pulse amplitude PA in the pulse specification detection by B, the frequency resolution can be maintained while ensuring the time resolution.
In this way, by performing the FFT analysis by overlapping the number of points for performing the FFT processing, the accuracy (time resolution) of the pulse width PW of the pulse specifications and the pulse arrival time TOA can be improved, and the frequency resolution is also improved. It is possible to obtain a highly accurate pulse specification detection device while maintaining.

実施の形態２
次にこの発明の実施の形態２におけるパルス諸元検出装置を図７、図８について説明する。図７はこの発明の実施の形態２に使用されるＦＦＴ処理回路を示す構成図、図８はＦＦＴ処理の概念図を示す図である。
この発明の実施の形態２は、図１に示す基本構成図のＦＦＴ処理回路５を、この図７に示すような構成のＦＦＴ処理回路１１としたもので、その他の構成は図１の基本構成図と同じに付き、説明を省略する。 Embodiment 2
Next, a pulse specification detection apparatus according to Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 7 is a block diagram showing an FFT processing circuit used in the second embodiment of the present invention, and FIG. 8 is a conceptual diagram of the FFT processing.
In the second embodiment of the present invention, the FFT processing circuit 5 of the basic configuration diagram shown in FIG. 1 is replaced with an FFT processing circuit 11 of the configuration shown in FIG. 7, and the other configuration is the basic configuration of FIG. It is the same as the figure and will not be described.

図７において、ＦＦＴ処理回路１１は、１サイクルの処理ポイント数ＮをＦＦＴ処理するＦＦＴ処理部１１１と、処理ポイント数Ｍ（但し、Ｍ＜Ｎ）をＦＦＴ処理するＦＦＴ処理部１１２の２種類のＦＦＴ処理部で構成されている。即ち、ＦＦＴ処理部１１２は、ＦＦＴ処理部１１１が処理する１サイクルの処理ポイント数Ｎよりも少ない処理ポイント数ＭずつＦＦＴ処理を行なって、１サイクルの処理ポイントをオーバラップしてＦＦＴ処理するようにしている。   In FIG. 7, the FFT processing circuit 11 has two types of processing, that is, an FFT processing unit 111 that performs FFT processing on the number of processing points N in one cycle, and an FFT processing unit 112 that performs FFT processing on the number of processing points M (M <N). It consists of an FFT processing unit. That is, the FFT processing unit 112 performs the FFT processing by the processing point number M smaller than the processing point number N of one cycle processed by the FFT processing unit 111, and performs the FFT processing by overlapping the processing points of one cycle. I have to.

図７における構成の動作を図８に基づいて説明する。図７および図８では、ＦＦＴ処理部１１１が処理する１サイクルのＦＦＴ処理ポイント数Ｎを１２８とし、ＦＦＴ処理部１１２が処理するＦＦＴ処理ポイント数Ｍを３２ポイントとする例について説明する。
受信部３で中間周波数（ＩＦ）信号に変換されたパルス変調信号はＡ／Ｄ変換回路４でデジタルサンプル信号に変換され、ＦＦＴ処理回路１１の処理ポイント数の異なる２種のＦＦＴ処理部１１１、１１２に並列に入力される。各ＦＦＴ処理部１１１、１１２によるＦＦＴ処理の結果、図８のＦＦＴ処理周期に示すように、ＦＦＴ処理部１１１（ＦＦＴ１）の出力は、処理ポイント数１２８毎に出力される出力Ａ、Ｂに相当することになる。またＦＦＴ処理部１１２（ＦＦＴ２）の出力は、ポイント数３２毎に出力される出力ａ、ｂ、ｃ、ｄに相当することになる。 The operation of the configuration in FIG. 7 will be described with reference to FIG. 7 and 8, an example in which the number N of FFT processing points in one cycle processed by the FFT processing unit 111 is 128 and the number M of FFT processing points processed by the FFT processing unit 112 is 32 points will be described.
The pulse modulation signal converted into the intermediate frequency (IF) signal by the receiving unit 3 is converted into a digital sample signal by the A / D conversion circuit 4, and two types of FFT processing units 111 having different numbers of processing points of the FFT processing circuit 11, 112 are input in parallel. As a result of the FFT processing by the FFT processing units 111 and 112, the output of the FFT processing unit 111 (FFT1) corresponds to the outputs A and B output every 128 processing points, as shown in the FFT processing cycle of FIG. Will do. The output of the FFT processing unit 112 (FFT2) corresponds to the outputs a, b, c, and d output for every 32 points.

このようにＦＦＴ処理部１１１で１サイクル１２８ポイントをシリーズにＦＦＴ処理することで周波数データの分解能を維持し、一方ＦＦＴ処理部１１２で１サイクル１２８ポイントの中のポイント数を３２ポイントずつ４分割でＦＦＴ処理を行うことによって、パルス諸元のパルス幅ＰＷ、パルス到来時刻ＴＯＡの精度（時間分解能）が確保できる。
以上のように実施の形態２の発明は、データ点数Ｎとデータ点数Ｍ（ただしＮ＞Ｍ）の２種類のＦＦＴ処理部を並列に構成し、データ点数ＮのＦＦＴ処理で周波数分解能、データ数ＭのＦＦＴ処理で時間分解能を確保している。 In this way, the FFT processing unit 111 performs FFT processing of 128 points per cycle in a series to maintain the frequency data resolution, while the FFT processing unit 112 divides the number of points in one cycle 128 points into 4 points by 32 points. By performing the FFT processing, it is possible to ensure the accuracy (time resolution) of the pulse width PW of the pulse specifications and the pulse arrival time TOA.
As described above, the invention according to the second embodiment has two types of FFT processing units having the number of data points N and the number of data points M (where N> M) configured in parallel. Time resolution is ensured by M FFT processing.

実施の形態３
次にこの発明の実施の形態３におけるパルス諸元検出装置を示す図９について説明する。図９はこの発明の実施の形態３におけるパルス諸元検出装置の構成図を示す図である。
図９に示すように、この発明の実施の形態３は、図１に示す基本構成図のプロセッサ８に再プログラムが可能なデバイスＦＰＧＡ（Field Programmable Gate array）回路９を設け、このＦＰＧＡ回路９により、ＦＦＴ処理回路１２の処理ポイント数を可変するようにしたものである。その他の構成は図１の基本構成図と同じに付き、説明を省略する。
なお、ＦＦＴ処理回路１２は実施の形態１および実施の形態２で説明したＦＦＴ処理回路１０またはＦＦＴ処理回路１１が使用される。 Embodiment 3
Next, FIG. 9 which shows the pulse specification detection apparatus in Embodiment 3 of this invention is demonstrated. FIG. 9 is a diagram showing the configuration of the pulse specification detection apparatus according to Embodiment 3 of the present invention.
As shown in FIG. 9, in the third embodiment of the present invention, a reprogrammable device FPGA (Field Programmable Gate Array) circuit 9 is provided in the processor 8 of the basic configuration shown in FIG. The number of processing points of the FFT processing circuit 12 is variable. Other configurations are the same as those of the basic configuration diagram of FIG.
Note that the FFT processing circuit 12 uses the FFT processing circuit 10 or the FFT processing circuit 11 described in the first and second embodiments.

図９において、プロセッサ８が認識した到来電波の特性、即ちパルス諸元の特性に応じて、ＦＰＧＡ回路９はＦＦＴ処理回路１２の複数のＦＴＴ処理部１０１〜１０４又は１１１、１１２でＦＦＴ処理するポイント数ＮまたはＭを可変にするようにする。
こうして到来電波の特性に応じてＦＴＴ処理ポイント数を変えることで、最適な周波数分解能、時間分解能のパルス諸元検出に柔軟性を持って対応できる。 In FIG. 9, the FPGA circuit 9 performs FFT processing in a plurality of FTT processing units 101 to 104 or 111 and 112 of the FFT processing circuit 12 according to the characteristics of the incoming radio wave recognized by the processor 8, that is, the characteristics of the pulse specifications. The number N or M is made variable.
In this way, by changing the number of FTT processing points in accordance with the characteristics of the incoming radio wave, it is possible to flexibly cope with pulse specification detection with optimal frequency resolution and time resolution.

この発明の基本形態におけるパルス諸元検出装置の全体構成図である。1 is an overall configuration diagram of a pulse specification detection device according to a basic form of the present invention. この発明の基本形態におけるＦＦＴ処理状況を示す特性図である。It is a characteristic view which shows the FFT processing condition in the basic form of this invention. この発明の基本形態におけるＦＦＴ処理結果による時間−周波数成分の特性図である。It is a characteristic figure of the time-frequency component by the FFT processing result in the basic form of this invention. この発明の実施の形態１におけるパルス諸元検出装置に使用されるＦＦＴ処理回路の構成図である。It is a block diagram of the FFT processing circuit used for the pulse specification detection apparatus in Embodiment 1 of this invention. この発明の実施の形態１におけるＦＦＴ処理の概念図である。It is a conceptual diagram of the FFT process in Embodiment 1 of this invention. この発明の実施の形態１におけるＦＦＴ処理結果を従来と比較して示す図である。It is a figure which shows the FFT processing result in Embodiment 1 of this invention compared with the past. この発明の実施の形態２におけるパルス諸元検出装置に使用されるＦＦＴ処理回路の構成図である。It is a block diagram of the FFT processing circuit used for the pulse specification detection apparatus in Embodiment 2 of this invention. この発明の実施の形態２におけるＦＦＴ処理の概念図である。。It is a conceptual diagram of the FFT process in Embodiment 2 of this invention. . この発明の実施の形態３におけるパルス諸元検出装置の全体構成図である。It is a whole block diagram of the pulse specification detection apparatus in Embodiment 3 of this invention.

符号の説明Explanation of symbols

１：アンテナ ２：ミキサ部
３：受信部 ４：Ａ／Ｄ変換回路
５：ＦＦＴ処理回路 ６：諸元検出回路
７：信号処理回路 ８：プロセッサ
９：ＦＰＧＡ回路 １０：ＦＦＴ処理回路
１１：ＦＦＴ処理回路
１０１〜１０４、１１１、１１２：ＦＦＴ処理部 1: Antenna 2: Mixer unit 3: Receiver unit 4: A / D conversion circuit 5: FFT processing circuit 6: Specification detection circuit 7: Signal processing circuit 8: Processor 9: FPGA circuit 10: FFT processing circuit 11: FFT processing Circuits 101-104, 111, 112: FFT processing unit

Claims (5)

到来電波を受けたアンテナから出力される高周波信号を中間周波数信号に周波数変換する受信部、この受信部により変換された中間周波数信号をデジタルのサンプル信号に変換するアナログ／デジタル変換回路、このアナログ／デジタル変換回路からのデジタルサンプル信号に対して、高速フーリエ変換（ＦＦＴ）の処理ポイントをオーバーラップしてＦＦＴ解析処理を行うＦＦＴ処理回路、及びこのＦＦＴ処理回路からの出力により上記到来電波の諸元を検出する諸元検出回路を備えたパルス諸元検出装置。   A receiving unit that converts a high-frequency signal output from an antenna that receives an incoming radio wave into an intermediate frequency signal, an analog / digital conversion circuit that converts the intermediate frequency signal converted by the receiving unit into a digital sample signal, An FFT processing circuit that performs FFT analysis processing by overlapping processing points of Fast Fourier Transform (FFT) with respect to a digital sample signal from the digital conversion circuit, and specifications of the incoming radio wave by output from the FFT processing circuit A pulse specification detection device provided with a specification detection circuit for detecting noise. ＦＦＴ処理回路は、複数のＦＦＴ処理部を有し、１サイクルの処理ポイント数Ｎを複数ポイント数Ｍ（但し、ＭはＮ／ｎ、ｎは整数）ずつスライドさせるようにしてＦＦＴ処理するようにした請求項１に記載のパルス諸元検出装置。   The FFT processing circuit has a plurality of FFT processing units, and performs FFT processing by sliding the processing point number N in one cycle by a plurality of point numbers M (where M is N / n, n is an integer). The pulse specification detection apparatus according to claim 1. 到来電波を受けたアンテナから出力される高周波信号を中間周波数信号に周波数変換する受信部、この受信部により変換された中間周波数信号をデジタルのサンプル信号に変換するアナログ／デジタル変換回路、このアナログ／デジタル変換回路からのデジタルサンプル信号に対して、高速フーリエ変換（ＦＦＴ）の処理ポイント数が異なる２種類のＦＦＴ解析を並列処理するＦＦＴ処理回路、及びこのＦＦＴ処理回路からの出力により上記到来電波の諸元を検出する諸元検出回路を備えたパルス諸元検出装置。   A receiving unit that converts a high-frequency signal output from an antenna that receives an incoming radio wave into an intermediate frequency signal, an analog / digital conversion circuit that converts the intermediate frequency signal converted by the receiving unit into a digital sample signal, An FFT processing circuit that performs parallel processing on two types of FFT analysis with different number of processing points of Fast Fourier Transform (FFT) on the digital sample signal from the digital conversion circuit, and an output from the FFT processing circuit, A pulse specification detection device having a specification detection circuit for detecting specifications. ＦＦＴ処理回路は、１サイクルの処理ポイント数ＮをＦＦＴ処理するＦＦＴ処理部と、処理ポイント数Ｍ（但し、Ｍ＜Ｎ）をＦＦＴ処理するＦＦＴ処理部とから成る請求項３に記載のパルス諸元検出装置。   4. The pulse processing circuit according to claim 3, comprising: an FFT processing unit that performs FFT processing on the number N of processing points in one cycle; and an FFT processing unit that performs FFT processing on the number of processing points M (M <N). Former detection device. 処理ポイント数Ｎ及びＭを到来電波の諸元に応じて可変するようにした請求項２または請求項４に記載のパルス諸元検出装置。   The pulse specification detection device according to claim 2 or 4, wherein the number of processing points N and M is varied according to the specification of the incoming radio wave.
JP2006355314A 2006-12-28 2006-12-28 Pulse specification detector Active JP4682127B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006355314A JP4682127B2 (en) 2006-12-28 2006-12-28 Pulse specification detector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006355314A JP4682127B2 (en) 2006-12-28 2006-12-28 Pulse specification detector

Publications (2)

Publication Number Publication Date
JP2008164479A true JP2008164479A (en) 2008-07-17
JP4682127B2 JP4682127B2 (en) 2011-05-11

Family

ID=39694180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006355314A Active JP4682127B2 (en) 2006-12-28 2006-12-28 Pulse specification detector

Country Status (1)

Country Link
JP (1) JP4682127B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012078131A (en) * 2010-09-30 2012-04-19 Toshiba Corp Radio wave receiver and radio wave receiving method
JP2012512396A (en) * 2008-12-18 2012-05-31 サザン イノヴェーション インターナショナル プロプライアトリー リミテッド Method and apparatus for separating piled-up pulses by using mathematical transformations
JP2012191413A (en) * 2011-03-10 2012-10-04 Toshiba Corp Receiving device and signal determination program
KR20170005483A (en) * 2014-06-03 2017-01-13 레이던 컴퍼니 Analog rf memory system
US10027026B2 (en) 2014-09-18 2018-07-17 Raytheon Company Programmable beamforming system including element-level analog channelizer
US10084587B1 (en) 2017-07-28 2018-09-25 Raytheon Company Multifunction channelizer/DDC architecture for a digital receiver/exciter
US10348338B2 (en) 2016-10-06 2019-07-09 Raytheon Company Adaptive channelizer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375685A (en) * 1986-09-19 1988-04-06 Tech Res & Dev Inst Of Japan Def Agency Synthetic apparatus radar
JPH08327727A (en) * 1995-05-29 1996-12-13 Mitsubishi Electric Corp Radar equipment
JPH09152865A (en) * 1995-11-30 1997-06-10 Sony Corp Automatic voice transcription device
JPH11166973A (en) * 1997-12-03 1999-06-22 Fujitsu Ten Ltd Radar device
JPH11211763A (en) * 1998-01-22 1999-08-06 Mitsubishi Electric Corp Radio wave data measuring apparatus
JP2001349941A (en) * 2000-06-08 2001-12-21 Japan Radio Co Ltd Fm-cw radar device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6375685A (en) * 1986-09-19 1988-04-06 Tech Res & Dev Inst Of Japan Def Agency Synthetic apparatus radar
JPH08327727A (en) * 1995-05-29 1996-12-13 Mitsubishi Electric Corp Radar equipment
JPH09152865A (en) * 1995-11-30 1997-06-10 Sony Corp Automatic voice transcription device
JPH11166973A (en) * 1997-12-03 1999-06-22 Fujitsu Ten Ltd Radar device
JPH11211763A (en) * 1998-01-22 1999-08-06 Mitsubishi Electric Corp Radio wave data measuring apparatus
JP2001349941A (en) * 2000-06-08 2001-12-21 Japan Radio Co Ltd Fm-cw radar device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012512396A (en) * 2008-12-18 2012-05-31 サザン イノヴェーション インターナショナル プロプライアトリー リミテッド Method and apparatus for separating piled-up pulses by using mathematical transformations
JP2012078131A (en) * 2010-09-30 2012-04-19 Toshiba Corp Radio wave receiver and radio wave receiving method
JP2012191413A (en) * 2011-03-10 2012-10-04 Toshiba Corp Receiving device and signal determination program
KR20170005483A (en) * 2014-06-03 2017-01-13 레이던 컴퍼니 Analog rf memory system
JP2017520760A (en) * 2014-06-03 2017-07-27 レイセオン カンパニー Analog RF memory system
KR101896605B1 (en) * 2014-06-03 2018-10-18 레이던 컴퍼니 Analog rf memory system
US10965023B2 (en) 2014-09-18 2021-03-30 Raytheon Company Programmable beamforming system including element-level analog channelizer
US10027026B2 (en) 2014-09-18 2018-07-17 Raytheon Company Programmable beamforming system including element-level analog channelizer
US11664590B2 (en) 2014-09-18 2023-05-30 Raytheon Company Programmable beamforming system including element-level analog channelizer
US10348338B2 (en) 2016-10-06 2019-07-09 Raytheon Company Adaptive channelizer
US10840950B2 (en) 2016-10-06 2020-11-17 Raytheon Company Adaptive channelizer
US10084587B1 (en) 2017-07-28 2018-09-25 Raytheon Company Multifunction channelizer/DDC architecture for a digital receiver/exciter
US10491359B2 (en) 2017-07-28 2019-11-26 Raytheon Company Multifunction channelizer/DDC architecture for a digital receiver/exciter

Also Published As

Publication number Publication date
JP4682127B2 (en) 2011-05-11

Similar Documents

Publication Publication Date Title
JP4682127B2 (en) Pulse specification detector
JP5635059B2 (en) Measurement system and method for monitoring high frequency power
KR101376556B1 (en) Detection of presence of television signals embedded in noise using cyclostationary toolbox
JP4962422B2 (en) Arrival radio direction measurement device, arrival radio direction measurement method, and arrival radio direction measurement program
EP3093794A1 (en) Fingerprint detection device and method
EP2797226B1 (en) Signal playback device and signal playback method
JPWO2018116943A1 (en) Noise suppression device, noise suppression method, and reception device and reception method using the same
US9450598B2 (en) Two-stage digital down-conversion of RF pulses
EP3486678B1 (en) Multi-signal instantaneous frequency measurement system
JP4889662B2 (en) Pulse specification detector
EP3055704B1 (en) Analog to information converter
JP2008249541A (en) Pulse signal detector
WO2016194044A1 (en) Target detection device and target detection method
WO2007034992A3 (en) An apparatus and method for multi-phase digital sampling
WO2018154632A1 (en) Signal detection device and signal detection method
JP2019028048A (en) Information acquisition device based on echo signal, radar device, and pulse compression device
JP2014153206A (en) Signal processing device and signal processing method
JP2019101004A (en) Information acquisition device based on echo signal, rader device and pulse compression device
KR101042029B1 (en) The anticollision scheme of moving target with noise sensor
JP2007212234A (en) Signal detection device
JP5547012B2 (en) Radio wave receiver and signal analysis method
JP5631674B2 (en) Radio wave receiver and signal analysis method
Jawad et al. Common frequency extraction for bandpass sampling based frequency de-hopper
KR101442510B1 (en) Wideband direction finding system and method based on dft polyphase filterbank
JP4999586B2 (en) Radar equipment

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100108

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100312

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101228

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20110201

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110207

R151 Written notification of patent or utility model registration

Ref document number: 4682127

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140210

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250