JP2008161262A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ultrasonic diagnostic apparatus provided with a digital reception beam former inexpensively materializing multi-directional parallel simultaneous reception in order to be adaptive to the organization of a real-time 3D image using a 2D array ultrasonic probe. <P>SOLUTION: A modulator 31 which is a sigma-delta type AD converter converts one reception signal to the digital data of a first cycle T1, and a first decimator 32 decimates the digital data to the data of an N-fold second cycle NT1 (=T2). Thereafter, delay processing by a FIFO memory 33 and channel addition by an adder 34 are performed, and then a second decimator 35 decimates them to the data of an M-fold third cycle NMT1 (=T3). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an ultrasonic diagnostic apparatus for transmitting a ultrasonic wave into a subject, phasing reflected waves received by a plurality of ultrasonic transducers by digital processing (receiving beam forming), and forming a diagnostic image. About.

  The ultrasonic diagnostic apparatus includes an ultrasonic probe having a plurality of ultrasonic transducers and a transmission / reception unit that drives and controls the ultrasonic probe. The transmitter / receiver supplies an electric signal to the ultrasonic transducer to scan the ultrasonic wave beam-formed (transmitted beam form) at a predetermined focal point in the subject, and to transmit the ultrasonic wave reflected in the subject. Receive from the acoustic transducer. At that time, the transmission / reception unit converts the analog reception signal into digital reception data that has been phased (received beam-formed) and outputs it.

  The receive beamformer adds the received signals received at different times in accordance with the distance from the target reflector to each ultrasonic transducer, with their phases (time) aligned and focused. One reception signal (image signal on one scanning line) is generated.

  Conventionally, as shown in FIG. 6, such digital reception beamformers are ADCs ADCs 10a, 10b,..., 10n (hereinafter sometimes referred to as "ADC 10 etc." as representative). FIFO memories 11a, 11b,..., 11n for performing coarse delay (hereinafter sometimes referred to as “FIFO memory 11 etc.” as a representative), and digital delay circuit 12a for adding fine delay , 12b,..., 12n (hereinafter sometimes referred to as “digital delay circuit 12 or the like” as a representative) and an adder 13. The ADC 10 or the like receives an analog reception signal from each ultrasonic transducer (hereinafter, a signal line from each ultrasonic transducer may be referred to as a “channel”), and converts it into digital data with a certain quantization accuracy. . The received signal that has become digital data is temporarily stored in the FIFO memory 11 or the like. By adjusting the phase (delay time) of the timing of reading from the FIFO memory 11 or the like according to the distance from the focal point of each ultrasonic transducer channel, each phase can be adjusted. The amount of time that can be controlled here is limited by the sampling rate of the ADC 10 or the like, but in many cases, the accuracy is insufficient. Therefore, a delay smaller than the sampling rate is added by the digital delay circuit 12 after the FIFO memory 11 or the like. Since the delay due to the FIFO memory 11 or the like adds a “coarse” delay, the delay due to the “Coarse delay” is often referred to as “Fine delay”. As described above, the digital data of each channel to which the delay is added is added by the adder 13 to constitute one reception signal.

  On the other hand, one of the benefits of digitizing the receive beamformer is that so-called parallel simultaneous reception processing can be realized relatively easily. This parallel simultaneous reception technique is a technique for obtaining a plurality of reception signals with different focal points (reception signals on a plurality of image scanning lines) from reception signals of respective channels obtained from one transmission.

  For example, in the diagnosis of the circulatory region where the heart is viewed, it is important to accurately reproduce the movement at a relatively high speed. For example, there may be a case where a necessary and sufficient speed (frame rate) cannot be ensured by repeating <transmission of one ultrasonic wave to one focal point in the subject> → <one signal processing on the image scanning line>. In view of this, a method of obtaining a frame rate by obtaining a plurality of reception signals around the transmission focal point from a single transmission of ultrasonic waves (hereinafter sometimes referred to as “parallel simultaneous reception”) is employed.

  When the receive beamformer was achieved with an analog circuit, the only way to realize this was to prepare a plurality of the same circuits, and this was not a technique that could be easily realized because it affected the cost and mounting area. On the other hand, in recent digital receive beamformers, it is possible to obtain a plurality of received signals with a single circuit by switching the delay parameter from time to time in a time division operation unique to the digital circuit. Further, since digital circuits can be integrated, even if there are a plurality of the same circuits, parallel simultaneous reception processing can be realized without increasing the cost unless the number is too large.

  An example of a reception beamformer for realizing parallel simultaneous reception processing is shown in FIG. FIG. 7 shows a circuit configuration that enables parallel simultaneous reception processing so that reception data of four different focal points around the focal point can be acquired from transmission to one focal point in the form of FIG. In the form shown in FIG. 7, four delay circuits 12a, 12b,..., 12n are provided for each FIFO memory 11a, 11b,..., 11n, and four adders are provided. 13a, 13b, 13c, and 13d are provided. That is, the FIFO memories 11a, 11b,..., 11n are shared by four received data, and circuits such as the subsequent digital delay circuit 12a are prepared for the number of simultaneous receptions, and four adders 13a, 13b, 13c are prepared. , 13d to obtain received data at different focal positions. There is also a method of sharing all the circuits, but in that case, if the processing rate after the FIFO memories 11a, 11b,..., 11n is not made high, the signal band is sacrificed, and if it is made high, power consumption increases. There is a trade-off. On the other hand, the digital delay circuits 12a, 12b,..., 12n for fine delay are often digital filters (for example, Patent Document 1), and the circuit scale is not small. Therefore, as in this example, having a plurality of them is not desirable from the viewpoint of cost, but since the number of parallel simultaneous receptions required by the conventional ultrasonic diagnostic apparatus is at most 4, in view of the above trade-off, In many cases, such a configuration is adopted.

  Here, the problem is how to deal with the increase in the number of parallel simultaneous receptions. In the case of a conventional ultrasonic probe in which ultrasonic transducers are arranged in a single row, that is, only in the lateral (lateral) direction and not arranged in the vertical (elevation) direction, the required number of simultaneous receptions is as described above. Since it was 4 at most, it was possible to keep the influence on the cost within an allowable range even if the circuit was provided for the number of simultaneous receptions. However, recently, a technique for constructing a three-dimensional image in real time using a 2D array ultrasonic probe having ultrasonic transducers arranged in two orthogonal directions has begun to be put into practical use. In the 2D array ultrasonic probe, the number of simultaneous receptions is expected to be 8 and further to 16.

  In order to construct a real-time three-dimensional image using a 2D array ultrasonic probe, it is necessary to acquire and process a large amount of data for three dimensions. Conventionally, if a two-dimensional image composed of N scanning lines on a plane is expanded from a 360 plane rotated by one degree around a predetermined axis to a three-dimensional image, the number of scanning lines is 360. × N. The scanning time is simply 360 times that of the prior art. Although the frame rate drops to 1/360, this is unacceptable in the diagnosis of the circulatory region as described above. Therefore, a measure has been considered in which the decrease in frame rate is suppressed by increasing the number of parallel simultaneous receptions and obtaining a large number of three-dimensional received data.

  The required number of parallel receptions is said to be at least 16. The effect on the circuit scale and thus the cost is enormous. The digital delay circuit for “Fine delay” is composed of many multipliers and adders, and has a large circuit scale as described above. The fact that this is four times that of the prior art means that if we try to cope with the extension of the prior art, the cost must be prepared accordingly.

  In view of this, it is conceivable to use an oversampling AD converter to eliminate the need for a “Fine delay” circuit (digital delay circuit) and to suppress an increase in cost.

  In the first place, the “Fine delay” circuit (digital delay circuit) is required because the upper limit of the sampling frequency of the conventional AD converter is 40 to 60 [MHz]. Because it was insufficient.

  On the other hand, the oversampling AD converter operates at a rate several times the output rate internally. If a signal having a rate sufficient for reception beamforming can be obtained, the “Fine delay” circuit (digital delay circuit) can be dispensed with.

  Here, an outline of the oversampling AD converter is shown in FIG. The AD converter shown in FIG. 8 is one form of a converter called a delta-sigma AD converter. The input analog reception signal is subtracted by the subtractor 311 from the feedback signal from the 1-bit DAC 314 which is a 1-bit DA converter, and then input to the integrator 312. The output of the integrator 312 is input to the comparator 313, and a 1-bit digital signal from “0” to “1” that is delta-sigma modulated like the signal at point (A) in FIG. Converted to a bit string of Thereafter, unnecessary harmonic band signals are removed and decimated by the decimator 100, and finally a digital signal having a bit width of a certain rate is obtained (point (B) in FIG. 8).

  Since the rate of the output of the modulator 31 is sufficiently small from the viewpoint of reception beamforming, the “Fine delay” circuit (digital delay circuit) can be eliminated by performing beamforming on this data.

  There has been a proposal to apply an oversampling AD converter to an ultrasonic diagnostic apparatus in this way (for example, Patent Document 2). FIG. 9 shows an outline of the proposal. FIG. 9 shows one form of a conventional receive beamformer using an oversampling AD converter. This receive beamformer is achieved by the modulator 31, the FIFO memory 11, the adder 13, and the decimator 100. It is assumed that the resolution at the final rate per channel is 8 bits, the rate at the modulator 31 is 1.5625 ns (sampling frequency is 640 MHz), and the final rate is 25 ns (sampling frequency is 40 MHz). The input analog signal is processed by the modulator 31. Thereafter, delay processing is performed on the modulator output at the high sampling frequency by reading control from the FIFO memory 11, and after beam forming addition by the adder 13, the decimator 100 performs decimation to the final rate. Note that N in FIG. 9 represents the number of addition channels.

US Pat. No. 5,345,426 US Pat. No. 5,203,335

  However, the receive beamformer shown in FIG. 9 has the following problems. That is, if a discontinuous point occurs in control data (specifically, a read address to the FIFO memory 11) to the FIFO memory 11 by continuous reception delay control (so-called dynamic focus), unacceptable noise is generated. Although measures to reduce this have been proposed, the modulator 31 is changed and the difficulty is very high. Since the development of a mixed analog / digital IC requires enormous development costs, it is difficult to verify the effects at the design stage.

Considering the conventional receive beamformer shown in FIG. 9 and the performance required for the receive beamformer, the conventional technique has the following problems.
(1) The time accuracy required for receive beamforming does not necessarily match the modulator output rate, and may generally be coarser.
(2) If delay processing is performed at an interval finer than necessary, discontinuous points will be included accordingly. It is not desirable that discontinuities occur frequently at the modulator output point where the pulse density determines the data value after decimation.

  The present invention solves the above-described problems, and includes a digital reception beamformer that realizes multi-directional parallel simultaneous reception at a low cost so as to be compatible with real-time three-dimensional image construction using a 2D array ultrasonic probe. Another object is to provide an ultrasonic diagnostic apparatus.

  The invention according to claim 1 is a delta-sigma type AD conversion means for converting a received signal from an ultrasonic transducer into digital data of a first period T1, and an output of the AD conversion means is a second period. The first decimating means for decimating the data of T2 (T2> T1) and the output from the first decimating means are stored, and at a timing shifted by a delay time determined for each of a plurality of K received signals. The data processing means for outputting the data, and a set including K sets corresponding to the plurality of K received signals, and further adding the data output from the data processing means L reception means are provided, and L addition means and the L second decimation means for decimating the output of the addition means in a third period T3 (T3> T2). An ultrasonic diagnostic apparatus to.

  According to a second aspect of the present invention, there are provided K ultrasonic transducers, transmitting means for irradiating ultrasonic waves to the K ultrasonic transducers so as to have a focal point at a desired distance, and the ultrasonic transducers. A plurality of K received signals acquired by the digital signal are converted to digital data of the first period T1, respectively, and the K AD conversion means of the delta-sigma type and the outputs of the AD conversion means are output in the second period T2 ( The data output from each of the K first decimating means decimating the data of T2> T1) and the K first decimating means are stored, and a delay determined for each of the K received signals At the timing shifted by time, the K data processing means for outputting L data, the L adding means for adding data output from the data processing means, and the output of the adding means 3rd lap T3 (T3> T2) provided with the L second decimating means for decimating the in an ultrasonic diagnostic apparatus characterized by generating a simultaneous reception beam data of the plurality L direction.

  According to the present invention, the delta-sigma type AD conversion means is provided, and further, the first decimating means and the second decimating means are provided, and the decimation is performed in two stages, thereby reducing the cost while suppressing the generation of noise. It is possible to realize suppressed multidirectional parallel simultaneous reception.

[Outline of Embodiment of the Invention]
The embodiment of the present invention is applied to the ultrasonic diagnostic apparatus shown in FIG. The configuration and operation of the ultrasonic diagnostic apparatus will be described later. The main part of the embodiment of the present invention is the receiving unit 3 in FIG. 5, and is particularly characterized in that a receiving beamformer is constructed using an oversampling AD converter and two decimators.

[Configuration of receive beamformer using oversampling AD converter]
First, the configuration of a reception beamformer using an oversampling AD converter will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of a receive beamformer according to an embodiment of the present invention.

  The receive beamformer according to this embodiment includes a modulator 31, a first decimator 32, a FIFO memory 33, an adder 34, and a second decimator 35. Assume that the resolution at the final rate per channel is 8 bits, the rate at the modulator 31 is 1.5625 ns (sampling frequency is 640 MHz), and the final rate is 25 ns (sampling frequency is 40 MHz).

  The input received signal is subtracted by the subtractor 311 from the feedback signal from the 1-bit DAC 314 that is a 1-bit DA converter, and then input to the integrator 312. The output of the integrator 312 is input to the comparator 313, and is converted into a bit string of a 1-bit digital signal of 0 to 1 that is delta-sigma modulated depending on the relationship with the reference voltage.

  Since the delta-sigma type AD converter is based on oversampling, the inside is moving at a rate of 10 times or more. For example, if the Nyquist frequency is 20 MHz and the oversampling ratio is 16, the internal rate is 1.5625 ns. When the accuracy required for the fine delay is 1/16 of the signal wavelength, the rate when the desired ultrasonic signal band is up to 10 MHz is 6.25 ns (>> 1.5625 ns), and the rate 1.5625 ns It can be seen that is sufficient. That is, a conventional digital delay circuit (“Fine delay” circuit) is not required as a configuration in which a wide-band delta-sigma type AD converter is applied to obtain a digital reception signal having a required time accuracy at the time of AD conversion. be able to.

  The signal output from the modulator 31 is reduced by the first decimator 32 to a point necessary and sufficient for beam forming. At this time, the signal changes from pulse density data to one having a certain bit width. In the example of FIG. 1, it is decimated to 4-bit data at a rate of 6.25 ns (a sampling frequency of 160 MHz).

  Next, the signal output from the first decimator 32 is temporarily stored in the FIFO memory 33. Each timing can be adjusted by controlling the phase (delay time) of the timing of reading from the FIFO memory 33 in accordance with the distance from the focal point of each ultrasonic transducer channel. The digital data of each channel to which the delay is added is added by the adder 34 and then converted to data of the final rate by the second decimator 35. In the example of FIG. 1, data is decimated to 25 ns (sampling frequency is 40 MHz). Note that N in FIG. 1 represents the number of addition channels in the adder 34. The FIFO memory 33 corresponds to an example of “data processing means” of the present invention.

  That is, the reception beamformer according to this embodiment is a delta-sigma type AD conversion unit (subtracting in FIG. 1) that converts one reception signal acquired by scanning ultrasonic waves into digital data of the first period T1. The first decimator 32 receiving the output from the integrator 311, the integrator 312, the comparator 313, and the 1-bit DAC 314) decimates the data in the second period NT1 (= T2) N times, and then After the delay process and the channel addition, the second decimator 35 decimates the data of the third period NMT1 (= T3) M times.

  With the above configuration, discontinuous points related to dynamic focus occur, but since the data is already band-limited to some extent, changes between continuous data should be limited. That is, the degree of undesirable phenomena such as noise at discontinuities can be expected to be smaller than in the prior art.

[Reception beamformer simulation]
Next, a delay simulation by the reception beamformer according to this embodiment was performed. For example, as shown in FIG. 2, the ultrasonic transducer P48 located 48th from the center of the beam of the ultrasonic transducers P1, P2,..., P48, P49,. A delay simulation was performed when a continuous wave was received. The simulation was performed for a depth of 10 mm to 20 mm and a carrier frequency of 2 MHz.

  The result of this simulation is shown in FIG. FIG. 3 is a graph showing the result of the delay simulation. In FIG. 3, the horizontal axis represents the depth [mm]. 3 (a), (b), and (c), the vertical axis represents amplitude, and in FIG. 3 (d), the vertical axis represents the difference between the reference ideal signal and the signal obtained by each method. Yes.

  The signal A shown in FIG. 3A is a reference carrier signal, and the signal B is obtained as a result of delaying the signal A according to delay control data determined by the position of the ultrasonic transducer and the focus depth. Signal. Here, the sampling frequency was set to 160 MHz. A signal obtained by re-sampling the signal B is an ideal signal and is a comparison target.

  A signal C shown in FIG. 3B is a signal obtained by re-sampling the signal B to 40 MHz. This signal C is an ideal signal and is to be compared. The signal D is a signal obtained as a result of processing the signal A by the reception beamformer according to this embodiment. That is, the signal D is a signal obtained as a result of performing decimation in two stages by the first decimator 32 and the second decimator 35. In addition, since the signal C and the signal D substantially coincide with each other, they are overlapped in FIG.

  The signal C shown in FIG. 3C is an ideal signal, and the signal E is a signal obtained as a result of processing the signal A by the reception beamformer according to the prior art shown in FIG. That is, the signal E is a signal obtained as a result of decimating by one decimator 100 shown in FIG.

  The difference between the signal C as an ideal signal to be compared, the signal D, and the signal E is obtained, and each difference is shown in FIG. The signal F is the difference between the signal C as the ideal signal and the signal D obtained by the method of this embodiment, and the signal G is the signal C obtained as the ideal signal and the signal E obtained by the prior art method. Is the difference. As shown in FIGS. 3C and 3D, the signal D obtained by the method of this embodiment has less noise than the signal E obtained by the method of the prior art, and is a signal close to the ideal signal. I understand that

  As described above, according to the reception beamformer according to this embodiment, since the “sine delay” circuit (digital delay circuit) can be eliminated by providing the oversampling AD converter, the reception beamforming is performed. The circuit can be made simple and highly integrated. Furthermore, by providing the first decimator 32 and the second decimator 35 and performing decimation in two stages, it is possible to suppress signal degradation.

[Embodiment of Receive Beamformer]
Next, an embodiment in the case of the number of parallel simultaneous receptions in 16 directions is shown in FIG. FIG. 4 is a block diagram showing an embodiment of a receive beamformer that can perform parallel simultaneous reception of 16 channels. The reception beamformer shown in FIG. 4 is an embodiment in which beamforming is performed corresponding to a 2D array ultrasonic probe in which ultrasonic transducers are two-dimensionally arranged.

  Each of the modulators 31a, 31b,..., 31n (hereinafter sometimes referred to as “modulator 31 etc.” as a representative) has the same configuration as the modulator 31 of FIG. One acquired reception signal is converted into a bit string of a 1-bit digital signal. In this embodiment, the modulator 31 or the like converts the received signal into digital data having a first period T1. The modulators 31 and the like are prepared for the number of received signals (number of channels K).

  Each of the first decimators 32a, 32b,..., 32n (hereinafter sometimes referred to as “first decimator 32 etc.” as a representative) has the same configuration as the first decimator 32 of FIG. The data output from the modulator 31 and the like is decimated to N times the data of the second period NT1 (= T2), thereby reducing the rate to a place necessary and sufficient for beam forming. The first decimators 32 and the like are prepared for the number of received signals (number of channels K).

  Each of the FIFO memories 33a, 33b,..., 33n (hereinafter may be referred to as “FIFO memory 33 etc.” as a representative) has the same configuration as the FIFO memory 33 of FIG. Stores output from 32 etc. Then, the reception data is read out based on the reception delay control signal output from the control unit so that the phase of each channel reception signal matches the focal point. The FIFO memory 33 or the like is a type of memory that can read a plurality of ports, and has a read port corresponding to the required number of parallel receptions. In this embodiment, since the number of parallel simultaneous receptions is L = 16, 16 ports are provided. Each port is provided with a read address (reception delay control signal) corresponding to the reception (focus) direction ("Beam") that the port is responsible for. Thus, the data read from the FIFO memory 33 or the like is phase-aligned with necessary and sufficient accuracy. The FIFO memories 33 and the like are prepared for the number of received signals (number of channels K).

  Adders 34a, 34b,..., 34p (hereinafter may be referred to as “adders 34 etc.” as representatives) are connected to the outputs of the FIFO memories 33 etc., respectively. That is, the adder 34 and the like add data corresponding to each simultaneous reception direction (for each “Beam”) output from the different FIFO memories 33 and the like. As a result, reception beam forming is completed. The same number as the number of parallel simultaneous receptions is installed in the adder 34 and the like. In this embodiment, since the number of parallel simultaneous receptions is L = 16, 16 adders 34 and the like are installed. The adder 34 and the like output reception data (16 beam data) in 16 different directions (focal positions).

  Each of the second decimators 35a, 35b,..., 35p (hereinafter sometimes referred to as “second decimator 35 etc.” as a representative) has the same configuration as the second decimator 35 of FIG. The signal output from the adder 34 or the like is converted to data at the final rate by decimating the data in the third period MNT1 (= T3) of M times. The data adjusted to the final rate by the second decimator 35 or the like is then output to the signal processing unit 4 shown in FIG. The second decimator 35 and the like are installed in the same number as the parallel simultaneous reception number. In this embodiment, since the number of parallel simultaneous receptions is L = 16, 16 second decimators 35 and the like are installed.

  In this embodiment, the sampling rate and the resolution (final bit width) of the AD converter have been described using a certain assumed value. However, the value is one example, and the present invention is limited to that example. It is not a thing. Although the description has been made assuming that the modulator output is 1 bit, the present invention can also be applied to a multi-bit type.

  Further, the number of received signals (number of channels K) is not related to the number of beams L (number of parallel simultaneous receptions) to be output after phasing. For example, the number of channels K is assumed to be 128 or 192. The At that time, the modulator 31 and the like, the first decimator 32 and the like, and the FIFO memory 33 and the like of FIG.

  In this embodiment, parallel simultaneous reception in 16 directions has been described. However, parallel reception in 8 directions, 4 directions, or the like is not limited to 16 directions.

[Embodiment of Ultrasonic Diagnostic Apparatus]
Next, the configuration of an ultrasonic diagnostic apparatus to which the above-described reception beamformer is applied will be described with reference to FIG. FIG. 5 is a block diagram showing the configuration of the ultrasonic diagnostic apparatus according to the embodiment of the present invention.

  The ultrasonic diagnostic apparatus according to this embodiment includes an ultrasonic probe 1, a transmission unit 2, a reception unit 3, a signal processing unit 4, an image generation unit 5, a display unit 6, and a control unit 7.

  The ultrasonic probe 1 is a 1D array ultrasonic probe in which a plurality of ultrasonic transducers are arranged in a line in a predetermined direction (scanning direction), or a plurality of ultrasonic transducers arranged in a matrix (lattice). It is composed of a 2D array ultrasonic probe.

  The transmission unit 2 supplies an electric signal to the ultrasonic probe 1 to scan the ultrasonic wave beam-formed (transmitted beam form) at a predetermined focal point. The receiving unit 3 receives the echo signal received by the ultrasonic probe 1, converts the analog received signal into phase-received (received beam-formed) digital received data, and outputs it. The configuration described in the above “embodiment of reception beamformer” is used for the reception unit 3.

  The signal processing unit 4 includes a B mode processing circuit, a Doppler processing circuit, and a color mode processing circuit. The received data output from the receiving unit 3 is processed by one of the processing circuits. The B-mode processing circuit visualizes echo amplitude information and generates B-mode ultrasonic raster data from the echo signal. The Doppler processing circuit extracts the Doppler shift frequency component and further performs FFT processing or the like to generate data having blood flow information. The color mode processing circuit visualizes the moving blood flow information and generates color ultrasonic raster data. Blood flow information includes information such as speed, dispersion, and power, and blood flow information is obtained as binarized information.

  The image generation unit 5 includes a DSC (Digital Scan Converter) and converts ultrasonic raster data into image data represented by orthogonal coordinates (scanning) in order to obtain an image represented by an orthogonal coordinate system (scanning). Conversion process). For example, the DSC generates tomographic image data as two-dimensional information based on the B-mode ultrasonic raster data, and outputs the tomographic image data to the display unit 6. Further, the image generation unit 5 generates voxel data based on a plurality of tomographic image data. Then, the image generation unit 5 performs image processing such as surface rendering processing, volume rendering processing, MPR processing (Multi Planar Reconstruction) on the voxel data, and thereby image data in three-dimensional image data or an arbitrary cross section. Ultrasonic image data such as data (MPR image data) is generated.

  The display unit 6 includes a monitor such as a CRT or a liquid crystal display, and displays a tomographic image, a three-dimensional image, blood flow information, or the like on the screen.

  The control unit 7 is connected to each unit of the ultrasonic diagnostic apparatus and controls the operation of each unit.

  Further, the ultrasonic diagnostic apparatus includes an operation unit (not shown). The operation unit includes a keyboard, a mouse, a trackball, or a TCS (Touch Command Screen), and various settings such as a scan condition and a region of interest (ROI) are performed by an operation of the operator.

  According to the ultrasonic diagnostic apparatus according to this embodiment, a reception beamformer is realized that realizes the number of parallel simultaneous receptions that increase in relation to the construction of a real-time three-dimensional image by a 2D array ultrasonic probe without a significant increase in cost. It becomes possible. Thereby, regarding a real-time three-dimensional ultrasonic diagnostic apparatus, it becomes possible to provide a user with a high-quality image at a reduced cost.

It is a block diagram which shows the structure of the receiving beamformer which concerns on embodiment of this invention. It is a figure for demonstrating the delay simulation by a receiving beamformer. It is a graph which shows the result of a delay simulation. It is a block diagram which shows embodiment of the receiving beamformer which can perform parallel simultaneous reception of 16 channels. 1 is a block diagram showing a schematic configuration of an ultrasonic diagnostic apparatus according to an embodiment of the present invention. It is a lock figure which shows the structure of the receiving beam former which concerns on a prior art. It is a block diagram which shows the structure of the receiving beamformer which concerns on a prior art. It is a block diagram which shows a delta sigma AD converter. It is a block diagram which shows the structure of the receiving beamformer which concerns on a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ultrasonic probe 2 Transmission part 3 Reception part 4 Signal processing part 5 Image generation part 6 Display part 7 Control part 31, 31a-31n Modulator 32, 32a-32n 1st decimator 33, 33a-33n FIFO memory 34, 34a-34p Adder 35, 35a to 35p Second decimator 311 Subtractor 312 Integrator 313 Comparator 314 1-bit DAC

Claims (2)

Delta-sigma type AD conversion means for converting the received signal from the ultrasonic transducer into digital data of the first period T1,
First decimating means for decimating the output of the AD converting means into data of a second period T2 (T2>T1);
Data processing means for storing the output from the first decimating means and outputting L data at a timing shifted by a delay time determined for each of a plurality of K received signals;
Including K sets corresponding to the plurality of K received signals.
Further, the L addition means for adding the data output from the data processing means,
The L second decimating means for decimating the output of the adding means in a third period T3 (T3>T2);
With
An ultrasonic diagnostic apparatus characterized by performing reception beam forming. K ultrasonic transducers,
Transmitting means for irradiating the K ultrasonic transducers with ultrasonic waves so as to have a focal point at a desired distance;
A plurality of K received AD signals obtained by the ultrasonic transducer, each of which is converted into digital data of a first period T1, and the K AD converting means of the delta-sigma type;
The K first decimating means for decimating the output of each AD converting means into data of a second period T2 (T2>T1);
The data output from each of the K first decimating means is stored, and the K data for outputting L data at a timing shifted by a delay time determined for each of the K received signals. Processing means;
The L adding means for adding data output from the data processing means;
The L second decimating means for decimating the output of the adding means in a third period T3 (T3>T2);
With
An ultrasonic diagnostic apparatus that generates simultaneous reception beam data in a plurality of L directions.