JP2008160370A - Data transmission system and method, data transmission device, and data reception device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently transmit a low-speed data signal and a high-speed data signal. <P>SOLUTION: A multiplexer 48 inserts high-speed transmission identification information ID<SB>High</SB>output from a high-speed transmission identification information generator 40, following an IFG (inter-frame gap) after a low-speed down data signal from a buffer 34. The high-speed transmission identification information ID<SB>High</SB>shows a length or a period of a subsequent high-speed down data signal. On reception of the high-speed transmission identification information ID<SB>High</SB>, an ONU 14-1 switches an oscillator 64 from external synchronization to internal synchronization for the period shown by the high-speed transmission identification information ID<SB>High</SB>. The multiplexer 48 multiplexes high-speed down data signal from a buffer 36 followed by the high-speed transmission identification information ID<SB>High</SB>and inserts a high-speed idle signal from a high-speed idle signal generator 39, between frames of the high-speed down data signal as an IFG. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transmission system and method, a data transmission apparatus, and a data reception apparatus that transmit data signals having different transmission rates in a time division multiplexing manner, and more specifically, like GE-PON and 10GE-PON, The present invention relates to a data transmission system and method, a data transmission apparatus, and a data reception apparatus that perform time division multiplexing transmission of downlink data signals having different transmission rates.

  As an access line, a PON (Passive Optical Network) system in which a plurality of users share an optical fiber transmission line is known. Although the data transmission rate was initially about 10 Mbps, it has been gradually increased to 100 Mbps and 1 Gbps. Recently, a system of 10 Gbps is also being studied.

  In the GE-PON system, 8B / 10B conversion is performed internally, and the bit rate of the optical signal is 1.25 Gbps. However, the difference between the rate of the data itself and the rate of the optical signal on the optical transmission path is Since it is not essential for the invention, hereinafter, it will be represented by the rate of the transmission data itself.

  In order to realize flexible band expansion while minimizing the influence on existing users, a method of partially increasing the speed of the 1 Gbps system to 10 Gbps has been studied. Specifically, an ONU (Optical Network Unit), which is an optical terminal device on the user side, can be mixed with one supporting 1 Gbps and one supporting 10 Gbps. An OLT (Optical Line Terminal), which is an optical terminal installed in the center station, examines and stores in advance whether each ONU is compatible with 1 Gbps or 10 Gbps, and a downstream data signal is transmitted at 1 Gbps to an ONU compatible with 1 Gbps. Transmit the downlink data signal at 10 Gbps to the 10 Gbps ONU. The OLT also transmits a multicast or broadcast of a downlink data signal including an ONU corresponding to 1 Gbps as a destination at 1 Gbps, and transmits a downlink data signal at 10 Gbps when all the destinations are ONUs compatible with 10 Gbps.

  In E-PON, each ONU service (for example, VoIP (Voice over IP), VOD (Video On Demand) and the Internet) is managed by logical links, and OLT has one or more logical links in each ONU. Can be set. The OLT confirms whether each ONU is compatible with 1 Gbps or 10 Gbps in the logical link setting protocol.

A conventionally proposed method for multiplexing downlink signals of different speeds in an E-PON system is to transmit a 1 Gbps base preamble, a signal for synchronization to IFG and 10 Gbps as a time axis every time a 10 Gbps base MAC frame is transmitted. Multiplexing above (for example, Non-Patent Document 1).
Mayumi Ishikawa et al., "A Study on PON System with Different Speed Frames", 2006 IEICE Communication Society, p. 180

  However, the conventional method requires a 1 Gbps base preamble, an IFG and a synchronization signal to 10 Gbps every time a 10 Gbps base MAC frame is transmitted, so the transmission time at 10 Gbps is relatively small and overhead is also low. Since it increases, the effective rate of the downstream signal decreases.

  An object of the present invention is to solve such problems and to provide a data transmission system and method, a data transmission device, and a data reception device capable of arranging data signals of different rates with higher density.

  A data transmission system according to the present invention transmits a first data signal having a first data rate and a second data signal having a second data rate faster than the first data rate by time division multiplexing, Data transmission having one or more first communication terminals that can receive the first data signal and cannot receive the second data signal, and one or more second communication terminals that can receive the second data signal The system is characterized in that identification information indicating the length of the second data signal is transmitted prior to the second data signal.

  The data transmission method according to the present invention is capable of receiving a first data signal having a first data rate and not receiving a second data signal having a second data rate higher than the first data rate. In a data transmission system having a first communication terminal and one or more second communication terminals capable of receiving the second data signal, the first data signal and the second data signal are time-division multiplexed. And transmitting the identification information indicating the length of the second data signal prior to the second data signal.

  A data transmission apparatus according to the present invention includes a first buffer that temporarily stores a first data signal having a first data rate, and a second data signal having a second data rate that is faster than the first data rate. A second buffer for temporarily storing the identification information generating device for generating identification information indicating the length of the second data signal, the first data signal from the first buffer, the second A multiplexing device that multiplexes the second data signal from the buffer and the identification information from the identification information generating device, wherein the identification information is between the first data signal and the second data signal. And a multiplexing device arranged.

  A data receiving apparatus according to the present invention transmits a first data signal having a first data rate and a second data signal having a second data rate faster than the first data rate by time division multiplexing, Data transmission having one or more first communication terminals that can receive the first data signal and cannot receive the second data signal, and one or more second communication terminals that can receive the second data signal In the system, a data receiving device included in the first communication terminal, a clock reproducing device for reproducing a clock component corresponding to the first data rate from an input signal, and a first data rate. An oscillator that oscillates at a corresponding frequency and operates in synchronization with the recovered clock of the clock recovery device, and a data recovery device that recovers data from the input signal according to the output of the oscillator When the identification information indicating the transmission period of the second data signal is detected from the reproduction data of the data reproduction device, the oscillator is used as the reproduction clock of the clock reproduction device during the transmission period indicated by the identification information. And a control device for switching from a synchronized state to a self-running state.

  In the present invention, since the identification signal is transmitted prior to the second data signal, the first communication terminal can avoid receiving or mis-synchronizing the second data signal. As a result, the first communication terminal can quickly and correctly receive the first data signal when it is input. That is, the first data signal and the second data signal can be arranged with high density on the time axis, and the effective rate is increased.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration block diagram of an embodiment of the present invention, specifically showing a downstream transmission system portion of a PON system in which a 1 Gbps-based GE-PON system and a 10 Gbps-based 10GE-PON system coexist. It is shown.

  The OLT 10 is connected to the ONUs 14-1 and 14-2 through an optical transmission line 12 composed of passive elements such as optical fibers and optical couplers. The OLT 10 is arranged in the center station, and the ONUs 14-1 and 14-2 are arranged in the user's home. The ONU 14-1 corresponds to GE-PON, and the ONU 12-4 corresponds to 10GE-PON. In addition, one or more ONUs corresponding to GE-PON or one or more ONUs corresponding to 10GE-PON can be connected to the optical transmission line 12, but are omitted in FIG.

  The CPU 20 of the OLT 10 controls the entire OLT 10. Although the transmission system of the upstream signal is omitted, the OLT 10 has one or more logics in the ONUs 14-1 and 14-2 by exchanging messages with the ONUs 14-1 and 14-2 when the ONUs 14-1 and 14-2 are activated. Set the link. The correspondence between the set logical link identifier (LLID) and the ONUs 14-1 and 14-2 is stored in the LLID table 22. At this time, the CPU 20 checks whether each of the ONUs 14-1 and 14-2 is compatible with GE-PON or 10 GE-PON, and stores the information in the table 22. Thereafter, the CPU 20 can identify the high-speed transmission based on 10 Gbps or the low-speed transmission based on 1 Gbps by referring to the LLID table 22.

  Downlink signals are input to the uplink port 24 from an upper network (not shown) in units of transmission frames, usually in units of MAC frames. Downstream signals are temporarily stored in the buffer 26 and sequentially read out to the distribution device 28. The CPU 20 receives the destination information of each frame from the distribution device 28 and supplies the LLID corresponding to the destination of each received frame to the distribution device 28. The distribution device 28 embeds an LLID corresponding to the destination in the header or preamble of each received frame, and then supplies the received frame to queues 30-1 to 30n prepared in advance according to the LLID.

  The OLT 10 transmits a multicast or broadcast of a downlink data signal including an ONU corresponding to 1 Gbps as a destination at 1 Gbps. If all the destinations are ONUs compatible with 10 Gbps, the OLT 10 transmits the multicast or broadcast of the downlink data signal at 10 Gbps. Broadcast and multicast may be transmitted uniformly at 1 Gbps.

  The CPU 20 supplies the low-speed downlink data signal (downlink data signal to the 1 Gbps compatible ONU) stored in the queues 30-1 to 30-n to the low-speed data buffer 34, and is stored in the queues 30-1 to 30-n. The cross-connect device 32 is controlled so that the high-speed downlink data signal (downlink data signal to the 10 Gbps ONU) is supplied to the high-speed data buffer 36. As a result, the low-speed downlink data signals stored in the queues 30-1 to 30-n are written in the low-speed data buffer 34 in units of frames. The high-speed downlink data signals stored in the queues 30-1 to 30-n are written in the high-speed data buffer 36.

  The low-speed idle signal generator 38 generates a low-speed idle signal based on 1 Gbps, which serves as an interframe gap (IFG) that fills between frames of the low-speed downlink signal. The buffer 34 may output the IFG following the payload of the low-speed downlink data signal. In this case, the buffer 34 also serves as the function of the low-speed idle signal generator 38 or the function of the IFG generator.

  The high-speed idle signal generator 39 generates a high-speed idle signal based on 10 Gbps. As will be described in detail later, this high-speed idle signal is used as a filling signal that is filled in when a high-speed downlink data signal is inserted between low-speed downlink data signals, and is used as an IFG between frames of the high-speed downlink data signal. Is also used. The buffer 36 may output a filling signal following the payload of the high-speed downlink signal. In this case, the buffer 36 also functions as a filling signal generator.

  The high-speed transmission identification information generator 40 generates high-speed transmission identification information arranged immediately before the high-speed downlink data signal. Although details will be described later, when receiving the high-speed transmission identification information, the ONU 14-1 compatible with 1 Gbps switches the oscillator for data reproduction from external synchronization to internal synchronization for a period specified by the high-speed transmission identification information.

The oscillator 44 generates a clock having a frequency f _L for internally processing 1 Gbps GE-PON data. The multiplier 46 multiplies the clock of the frequency f _L and generates a clock of the frequency f _H that internally processes 10 Gbps GE-PON data. The low-speed clock f _L is supplied to the low-speed data buffer 34, the high-speed data buffer 36, the low-speed idle signal generator 38, and the high-speed transmission identification information generator 40. The high-speed clock f _H is supplied to the high-speed data buffer 36 and the high-speed idle signal generator 39.

  The multiplexing device 48 sends signals output from the low-speed data buffer 34, the high-speed data buffer 36, the low-speed idle signal generator 38, the high-speed idle signal generator 39, and the high-speed transmission identification information generator 40 on the time axis by the CPU 20. The multiplexed signals are multiplexed in the order instructed, and the multiplexed signals are supplied to the electrical / optical converter 50.

  The CPU 20 sequentially monitors the amount of data stored in the low-speed data buffer 34 and the high-speed data buffer 36, and according to the monitoring result, the low-speed data buffer 34, the high-speed data buffer 36, the low-speed idle signal generator 38, the high-speed idle signal The output timing of the signal generator 39 and the high-speed transmission identification information generator 40 and the multiplexing operation of the multiplexer 48 are controlled.

  When a GE-PON that performs 8B10B conversion with a transmission speed of 1.25 Gbps on the optical transmission line and a 10GE-PON that performs transmission of 64B66B with a transmission speed of 10.3125 Gbps on the optical transmission line are mixed down the 10GE-PON When trying to match the signal length as much as possible to the bit break when the transmission speed of 1.25 Gbps is used as a reference, the period for inserting the downstream signal of 10GE-PON is an integral multiple of 32 ns. This is because the time required to transmit 1.25 Gbps 40 bits and the time required to transmit 10.3125 Gbps 330 bits is 32 ns.

  By the way, when mixing GE-PON having a transmission speed of 1.25 Gbps on the optical transmission path and performing 8B10B conversion and 2GE-PON having a transmission speed of 2.5 Gbps and performing 8B10B conversion on the optical transmission path, 2GE-PON The number of bytes of the signal may be an even number. When the number of bytes of the 2GE-PON signal is an odd number, a 2 Gbps high-speed idle signal for one byte is finally supplemented.

FIG. 2 shows an example of the frame structure of the downlink data signal output from the multiplexing device 48. The multiplexer 48 inserts the high-speed transmission identification information ID _High output from the high-speed transmission identification information generator 40 following the low-speed IFG after the low-speed downlink data signal. The high-speed transmission identification information ID _High indicates the length or period of the subsequent high-speed downlink data signal. As will be described in detail later, when receiving the high-speed transmission identification information ID _High , the ONU 14-1 switches the internal oscillator used for data reproduction from external synchronization to internal synchronization for the period indicated by the high-speed transmission identification information ID _High . Thereby, the ONU 14-1 can eliminate the loss of synchronization between the inputs of the high speed downlink signal, can easily follow the low speed downlink signal input after the high speed downlink signal, and can reproduce the data of the low speed downlink signal.

The multiplexer 48 multiplexes the high-speed downlink data signal from the buffer 36 following the high-speed transmission identification information ID _High , and the high-speed idle signal from the high-speed idle signal generator 39 is IFG between frames of the high-speed downlink data signal. Insert as. If the length of the high-speed downlink data signal immediately before switching to the low-speed downlink data signal is inappropriate for bit synchronization of the low-speed downlink data signal, the multiplexing device 48 multiplexes the filling signal from the high-speed idle signal generating device 39, and then In addition, the low-speed downlink data signal from the buffer 34 is multiplexed.

  The electrical / optical converter 50 converts the downlink data signal from the multiplexer 48 into an optical signal. The optical signal output from the electrical / optical converter 50 is transmitted through the optical transmission line 12 and enters the ONUs 14-1 and 14-2.

In the ONU 14-1, the optical / electrical converter 60 converts the optical signal from the optical transmission line 12 into an electrical signal and supplies the electrical signal to the clock recovery device 62 and the data recovery device 66. The clock recovery device 62 recovers the clock from the low frequency f _L component of the electrical signal from the optical / electrical converter 60. The oscillator 64 that oscillates at the low frequency f _L synchronizes with the recovered clock of the clock recovery device 62. The data reproducing device 66 reproduces the preamble and payload of the low-speed downlink data signal from the electric signal from the optical / electrical converter 60 according to the clock from the oscillator 64. The separation device 68 supplies the preamble of the data reproduced by the data reproduction device 66 to the control device 70, and the control device 70 controls the separation device 68 so as to output only the data signal addressed to itself to the LAN interface 72. . The LAN interface 72 outputs data from the separation device 68 from an output terminal 74 to an external computer or the like (not shown).

The separation device 68 also separates a data portion necessary for control of the ONU 14-1, for example, high-speed transmission identification information ID _High , and supplies it to the control device 70. When receiving the high-speed transmission identification information ID _High from the separation device 68, the control device 70 switches the oscillator 64 from the external synchronization state to the free-running state (internal synchronization state) for the time indicated by the high-speed transmission identification information ID _High . By temporarily controlling the oscillator 64 to the free-running state, the oscillator 64 can be immediately synchronized with the low-speed downlink data signal after the high-speed downlink data signal. This means that the idle period between the high-speed downlink data signal and the subsequent low-speed downlink data signal can be shortened. At the same time, the playback operation of the data playback device 66 may be temporarily stopped.

In the ONU 14-2, the optical / electrical converter 80 converts the optical signal from the optical transmission line 12 into an electrical signal and supplies the electrical signal to the clock recovery device 82 and the data recovery device 86. The clock recovery device 82 recovers the clock from the low frequency f _L component of the electrical signal from the optical / electrical converter 60. The oscillator 84 that oscillates at the low frequency f _L synchronizes with the recovered clock of the clock recovery device 62. Multiplying device 85 multiplies the frequency of the output clock of the oscillator 84 generates a clock of a high frequency f _H.

The data reproduction device 86 receives the preamble and payload of the low-speed downlink data signal and the high-speed downlink signal from the electrical signal from the optical / electrical converter 80 in accordance with the low-speed clock f _L from the oscillator 84 and the high-speed clock f _H from the multiplier 85. Reproduce. The separation device 88 supplies the preamble of the data signal reproduced by the data reproduction device 86 to the control device 90, and the control device 90 controls the separation device 88 so as to output only the data signal addressed to itself to the LAN interface 92. To do. The LAN interface 92 outputs the data from the separation device 88 from the output terminal 94 to an external computer or the like (not shown).

  Since the ONU 14-2 can receive both the low-speed downlink signal and the high-speed downlink signal, it is not necessary to control the external synchronization / self-running of the oscillator 84.

  FIG. 3 shows a schematic block diagram of the second embodiment of the present invention. Constituent elements having the same functions as those in FIG. In this embodiment, a high-speed synchronization signal is transmitted in order to facilitate reception of a high-speed downlink data signal by a high-speed ONU. FIG. 4 shows a transmission frame configuration example according to this embodiment.

  The OLT 110 is changed from the OLT 10 in the following points. That is, the multiplexer 148 multiplexes the high-speed idle signal output from the high-speed idle signal generator 39 as a high-speed synchronization signal after the high-speed transmission identification information, as shown in FIG. 6, in accordance with the switching instruction from the CPU 120. Of course, the time information indicated by the high-speed transmission identification information includes the period of the high-speed synchronization signal.

ONU114-2 is fast to take advantage of synchronization signal, a clock recovery apparatus 182 for extracting play component of the high-speed clock f _H from the high-speed synchronization signal and a high-speed downlink data signal, the oscillator oscillates at a high frequency f _H 184 It comprises. The oscillator 184 supplies the data recovery device 186 with a high-speed clock f _H synchronized with the recovery clock of the clock recovery device 182. The multiplier 85 is deleted. The data reproducing device 186 reproduces the low-speed downlink data signal and the high-speed downlink data signal from the electric signal from the optical / electrical converter 60 according to the low-speed clock f _L from the oscillator 84 and the high-speed clock f _H from the oscillator 184.

  In this embodiment, since the high-speed synchronization signal is transmitted, the ONU 14-2 can receive the high-speed downlink data signal more correctly.

  Although the invention has been described with reference to specific illustrative embodiments, various modifications and alterations may be made to the above-described embodiments without departing from the scope of the invention as defined in the claims. This is obvious to an engineer in the field to which the present invention belongs, and such changes and modifications are also included in the technical scope of the present invention.

It is a schematic block diagram of one Example of this invention. 6 is a schematic diagram illustrating an example of a frame arrangement of low-speed downlink data signals and high-speed downlink data sing multiplexed by a multiplexing device 48. FIG. It is a schematic block diagram of Example 2 of this invention. FIG. 10 is a schematic diagram illustrating an example of a frame arrangement of multiplexed low-speed downlink data signals and high-speed downlink data sing according to the second embodiment.

Explanation of symbols

10, 110: OLT
12: Optical transmission line ONU14-1, 14-2, 114-2: ONU
20, 120: CPU
22: LLID table 24: uplink port 26: buffer 28: distributors 30-1 to 30-n: queue 32: cross-connect device 34: low-speed data buffer 36: high-speed data buffer 38: low-speed idle signal generator 39 : High-speed idle signal generator 40: High-speed transmission identification information generator 44: Oscillator 46: Multiplier 48, 148: Multiplexer 50: Electric / optical converter 60: Optical / electric converter 62: Clock recovery device 64: Oscillator 66 : Data reproduction device 68: Separation device 70: Control device 72: LAN interface 74: Output terminal 80: Optical / electrical converter 82, 182: Clock reproduction device 84, 184: Oscillator 85: Multiplication device 86, 186: Data reproduction device 88: Separation device 90: Control device 92: LAN interface 94: Output terminal

Claims (11)

A first data signal having a first data rate and a second data signal having a second data rate faster than the first data rate can be time-division multiplexed and transmitted to receive the first data signal. Data having one or more first communication terminals (14-1) that cannot receive the second data signal and one or more second communication terminals (14-2) that can receive the second data signal A transmission system,
A data transmission system characterized by transmitting identification information indicating the length of the second data signal prior to the second data signal.   In response to reception of the identification information, the first communication terminal (14-1) switches the oscillator (64) for data reproduction from the external synchronization state to the self-running state for the period indicated by the identification information. The data transmission system according to claim 1, wherein:   The data transmission system according to claim 1 or 2, wherein a synchronization signal corresponding to the second data rate is transmitted between the identification information and the second data signal. One or more first communication terminals (14-1) that can receive a first data signal at a first data rate and cannot receive a second data signal at a second data rate higher than the first data rate. And one or more second communication terminals (14-2) capable of receiving the second data signal, the first data signal and the second data signal are time division multiplexed. Transmission method,
A data transmission method characterized by transmitting identification information indicating the length of the second data signal prior to the second data signal.   In response to the reception of the identification information, the first communication terminal (14-1) switches the oscillator (64) for data reproduction from the external synchronization state to the free-running state for the period indicated by the identification information. The data transmission method according to claim 4, wherein:   6. The data transmission method according to claim 4, wherein a synchronization signal corresponding to the second data rate is transmitted between the identification information and the second data signal. A first buffer (34) for temporarily storing a first data signal of a first data rate;
A second buffer (36) for temporarily storing a second data signal at a second data rate higher than the first data rate;
An identification information generating device (40) for generating identification information indicating the length of the second data signal;
A multiplexing device that multiplexes the first data signal from the first buffer, the second data signal from the second buffer, and the identification information from the identification information generating device; A data transmission device comprising: a multiplexing device that arranges the identification information between one data signal and the second data signal.   8. The multiplexing apparatus according to claim 7, wherein the multiplexing apparatus further multiplexes the filling signal of the second data rate in a remainder when the second data signal is inserted between the first data signals. Data transmission device.   9. The data transmission apparatus according to claim 7, wherein the multiplexing apparatus further multiplexes interframe gaps.   10. The multiplexing device according to claim 7, wherein the multiplexing device multiplexes a synchronization signal corresponding to the second data rate between the identification information and the second data signal. The data transmission device described. A first data signal having a first data rate and a second data signal having a second data rate faster than the first data rate can be time-division multiplexed and transmitted to receive the first data signal. Data having one or more first communication terminals (14-1) that cannot receive the second data signal and one or more second communication terminals (14-2) that can receive the second data signal In the transmission system, a data receiving device included in the first communication terminal,
A clock recovery device (62) for recovering a clock component corresponding to the first data rate from the input signal;
An oscillator (64) that oscillates at a frequency corresponding to the first data rate and operates in synchronization with a recovered clock of the clock recovery device;
A data reproducing device (66) for reproducing data from the input signal in accordance with the output of the oscillator (64);
When the identification information indicating the transmission period of the second data signal is detected from the reproduction data of the data reproduction apparatus, the oscillator is synchronized with the reproduction clock of the clock reproduction apparatus during the transmission period indicated by the identification information. Control device for switching from state to self-running state (70)
A data receiving apparatus comprising:

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