JP2008160037A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device using a stress film which is manufactured by comparatively simple manufacturing processes, and does not reduce stress of a direction in which charge mobility is improved. <P>SOLUTION: The semiconductor device includes a semiconductor substrate, an MISFET which is formed on the semiconductor substrate and isolated by a device isolation region, the stress film, and a stress relaxation structure. The stress film is formed on the semiconductor substrate, and applies the stress to a channel region of the MISFET to change the charge mobility at the channel region. The stress relaxation structure relaxes a component of the direction in which the charge mobility of the stress is reduced, while keeping the component of the direction in which the charge mobility of the stress is improved. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device to which a strained silicon technique using a stress film is applied.

  As a conventional semiconductor device, a first type internal stress film made of a silicon nitride film formed on a source / drain region of an n-channel MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor), and a source of a p-channel MISFET A semiconductor device including a second type internal stress film made of a TEOS (Tetraethoxysilane) film formed on a drain region is known (see, for example, Patent Document 1).

  According to this semiconductor device, the first type internal stress film generates a tensile stress in the direction of electron movement in the channel region of the n-channel type MISFET, thereby increasing the electron mobility. In the channel region of the p-channel type MISFET, compressive stress is generated in the hole movement direction, and the hole mobility is increased.

  However, according to this semiconductor device, it is indispensable to create a stress film separately in the source / drain region of the n-channel type MISFET and the source / drain region of the p-channel type MISFET, which complicates the manufacturing process. There is.

  Further, as a conventional semiconductor device, an element region provided between element isolation regions formed in a semiconductor substrate, a gate electrode, a source region, a drain region formed in the element region, and an element for covering the gate electrode An insulating film formed on the region and the element isolation region, a contact hole electrode provided through the insulating film to be electrically connected to the source region and the drain region in the element region, and the gate electrode in the element region. A semiconductor device is known that includes a dummy contact that is provided through an insulating film at a position that is substantially symmetric to the position of the contact hole electrode (see, for example, Patent Document 2).

  According to this semiconductor device, since the dummy contact is provided through the insulating film at a position substantially symmetrical to the position of the contact hole electrode with respect to the gate electrode in the element region, the gate electrode is the center. Contact holes penetrating the insulating film are arranged almost uniformly around the periphery, and the characteristics of the element can be stabilized by equalizing the stress applied from the insulating film to the channel.

However, according to this semiconductor device, since the formation of the dummy contact is intended to make the stress uniform, there is a possibility that the stress is sometimes reduced to the direction of improving the charge mobility in the channel region.
JP 2005-5633 A JP 2004-342724 A

  An object of the present invention is to provide a semiconductor device using a stress film that can be manufactured by a relatively simple manufacturing process and that does not reduce stress in the direction of improving charge mobility.

  One embodiment of the present invention includes a semiconductor substrate, a MISFET formed over the semiconductor substrate and separated by an element isolation region, and a channel region of the MISFET formed on the semiconductor substrate by applying stress to the channel. A stress film that changes the charge mobility in the region, and a stress relaxation structure that relaxes the component of the stress in the direction of decreasing the charge mobility while maintaining the component of the stress in the direction of improving the charge mobility. A semiconductor device is provided.

  According to the present invention, it is possible to provide a semiconductor device using a stress film that can be manufactured by a relatively simple manufacturing process and that does not reduce stress in the direction of improving the charge mobility.

[First Embodiment]
FIG. 1 is a top view showing the substrate surface of the semiconductor device according to the first embodiment of the present invention. 2 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 1 as viewed in the direction of the arrow in FIG. 1, and FIG. 3 shows the cut surface along the chain line BB ′ in FIG. It is sectional drawing seen in this direction.

  This semiconductor device 1 electrically connects an n-type well 11, a source / drain region 13 and a gate structure 12 formed in a p-type MISFET region 2 of a semiconductor substrate 10 and a p-type MISFET region 2 from a peripheral element region. An element isolation region 15 to be isolated, a compressive stress film 18 covering the source / drain region 13, the gate structure 12, and the element isolation region 15, a source / drain contact 16 formed on the source / drain region 13, and an element isolation And a dummy contact 17 formed on the region 15.

  As the semiconductor substrate 10, a silicon substrate having a {100} plane as a main surface can be used. The {100} plane represents the (100) plane and a plane equivalent to the (100) plane. Further, when the semiconductor substrate 10 is an n-type semiconductor substrate, the n-type well 11 may not be provided.

  Although not shown, the gate structure 12 includes a gate electrode, a gate insulating film, a gate sidewall, and the like.

The source / drain regions 13 are formed, for example, by implanting p-type impurity ions such as B and BF ₂ from the surface of the n-type well 11 in the semiconductor substrate 10.

  There is a channel region 14 between the source / drain regions 13. In the present embodiment, the channel direction is parallel to the <110> axis direction of the semiconductor substrate 10. The <110> axial direction represents the [110] axial direction and an axial direction equivalent to the [110] axial direction.

  The element isolation region 15 has an insulating property and is made of, for example, STI (Shallow Trench Isolation).

  The source / drain contact 16 conducts a wiring (not shown) or the like on the interlayer insulating film 19 and the source / drain region 13, and a metal such as W can be used, for example.

  The dummy contact 17 is formed on the element isolation region 15 and does not have a function as a contact that conducts between the members. The dummy contact 17 can be formed at the same time in the same process as the source / drain contact 16 using the same material as the source / drain contact 16.

The compressive stress film 18 is made of, for example, a silicon nitride film formed using a plasma CVD apparatus. Depending on the operating conditions of the plasma CVD apparatus, the silicon nitride film can be formed in such a film quality that gives compressive stress in a direction parallel to the semiconductor substrate 10 to the channel region 14. For example, the composition Si _x N _y (0 <x <1, y = 1−x) of the silicon nitride film is set by appropriately setting the RF (Radio Frequency) power of the plasma CVD apparatus and the like in the channel region 14. The film is formed so as to give compressive stress. It can also be used as an etching stop film during contact formation.

  When the channel direction in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10 as in the present embodiment, the stress in the direction parallel to the channel direction compresses the channel region 14 inward. When added in the direction, the charge mobility is improved. On the other hand, when a stress in a direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14 outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the channel region 14 in the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the compressive stress film 18, so that the channel region 14 is placed inward. The compressing stress mainly works, and the charge mobility in the direction parallel to the channel direction can be improved. However, on the contrary, the charge mobility in the direction perpendicular to the channel direction decreases.

  The dummy contact 17 is formed in the vicinity of the source / drain region 13 or the region adjacent to the channel region 14 in the direction perpendicular to the channel direction on the element isolation region 15 so as to penetrate the compressive stress film 18 which is a source of stress. Therefore, the stress in the direction perpendicular to the channel direction is relaxed.

Stress vectors F ₁ and F _{21 in} FIG. 1 represent stress parallel to the channel direction generated by the compressive stress film 18 and stress perpendicular to the channel direction, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction that occurs when a dummy contact 17 is not formed.

Since the dummy contact 17 relieves the stress in the direction perpendicular to the channel direction, the magnitude of the stress vector F ₂₁ is smaller than the stress vector F ₂₀ . Note that the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction that occurs when the dummy contact 17 is not formed.

  If the dummy contact 17 is formed in the vicinity of the source / drain region 13 or the region adjacent to the channel region 14 in the direction perpendicular to the channel direction on the element isolation region 15, FIG. The position and number shown in 2 are not limited.

(Effects of the first embodiment)
According to the first embodiment, the stress in the direction perpendicular to the channel direction applied to the channel region 14 in the p-type MISFET region 2 by the compressive stress film 18 is relaxed by the dummy contact 17, and the direction perpendicular to the channel direction is reduced. The reduction in the charge mobility of can be alleviated. Thereby, the effect of improving the charge mobility in the direction parallel to the channel direction can be obtained efficiently.

  In the first embodiment, a case where a stress film that applies compressive stress is applied to the p-type MISFET region 2 in which the channel direction of the channel region 14 is parallel to the <110> axis direction of the semiconductor substrate 10 will be described. However, the present invention is not limited to this, and any structure may be used as long as the dummy contact 17 is formed in a region where the direction of the stress by the stress film is a direction in which the charge mobility in the channel region 14 is reduced.

  Specifically, for example, when a stress film that applies tensile stress is applied to the channel region 14 in the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10, the channel region is mainly used. The stress that pulls 14 outward acts and the charge mobility in the direction perpendicular to the channel direction can be improved. However, since the charge mobility in the direction parallel to the channel direction decreases, the dummy contact 17 is adjacent to the source / drain region 13 and the channel region 14 on the element isolation region 15 in the direction parallel to the channel direction. It is formed in the vicinity of the region to be relieved to relieve stress in the direction parallel to the channel direction.

  In the present embodiment, the channel direction of the channel region in the p-type MISFET region is described as being parallel to the <110> axis direction of the semiconductor substrate. However, the channel direction is in the <100> axis direction of the semiconductor substrate. In the case of a channel region in a parallel p-type MISFET region, charge mobility improves when stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction are applied in the direction compressing the channel region inward.

  In the case of a channel region in an n-type MISFET region whose channel direction is parallel to the <110> axis direction of the semiconductor substrate and a channel region in an n-type MISFET region which is parallel to the <100> axis direction, the channel direction is parallel to the channel direction. When the stress in the normal direction and the stress in the vertical direction are applied in the direction of pulling the channel region outward, the charge mobility is improved.

[Second Embodiment]
The second embodiment of the present invention is different from the first embodiment in that the semiconductor device has a p-type MISFET region and an n-type MISFET region. The channel direction of the channel region in the p-type MISFET region and the n-type MISFET region is parallel to the <100> axis direction, and the channel region receives a stress that is pulled outward by the tensile stress film. Note that the description of the same points as in the first embodiment will be omitted.

  FIG. 4 is a top view showing the substrate surface of the semiconductor device according to the second embodiment of the present invention. FIG. 5 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 4 as viewed in the direction of the arrow in the figure.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically isolated by the element isolation region 15. In addition, the tensile stress film 21 covers the surface of the semiconductor substrate 10 in the p-type MISFET region 2 and the n-type MISFET region 3.

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a dummy contact 17 is formed on the element isolation region 15 around the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  For example, a silicon substrate can be used as the semiconductor substrate 10. When the semiconductor substrate 10 is an n-type semiconductor substrate, the n-type well 11 may not be provided. When the semiconductor substrate 10 is a p-type semiconductor substrate, the p-type well 20 may not be provided.

  Although not shown, the gate structure 12 includes a gate electrode, a gate insulating film, a gate sidewall, and the like. 4 and 5, the gate structure 12 is shown as commonly used in the p-type MISFET region 2 and the n-type MISFET region 3, but in the p-type MISFET region 2 and the n-type MISFET region 3. The structure formed independently may be sufficient.

The source / drain region 13a is formed by implanting p-type impurity ions such as B and BF ₂ from the surface of the n-type well 11 in the semiconductor substrate 10, for example.

  The source / drain region 13b is formed by implanting n-type impurity ions such as As and P from the surface of the p-type well 20 in the semiconductor substrate 10, for example.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <100> axis direction of the semiconductor substrate 10. The <100> axial direction represents the [100] axial direction and an axial direction equivalent to the [100] axial direction.

  The element isolation region 15 is made of, for example, STI (Shallow Trench Isolation).

  The source / drain contacts 16a and 16b are used to connect the wiring and the like on the interlayer insulating film 19 to the source / drain regions 13a and 13b. For example, a metal such as W can be used.

  The dummy contact 17 is formed on the element isolation region 15 made of an insulating material, and does not have a function as a contact that conducts between members. The dummy contact 17 can be formed at the same time using the same material as the source / drain contacts 16a, 16b in the same process as the source / drain contacts 16a, 16b.

The tensile stress film 21 is made of, for example, a silicon nitride film formed using a plasma CVD apparatus. Depending on the operating conditions of the plasma CVD apparatus, the silicon nitride film can be formed in such a film quality that gives tensile stress in the direction parallel to the semiconductor substrate 10 to the channel regions 14a and 14b. For example, the composition Si _x N _y (0 <x <1, y = 1−x) of the silicon nitride film is set by appropriately setting the RF power of the plasma CVD apparatus, and the tensile stress is applied to the channel regions 14a and 14b. It is formed into a film quality that gives It can also be used as an etching stop film during contact formation.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <100> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction and the channel direction When stress in the vertical direction is applied in the direction in which the channel region 14a is compressed inward, the charge mobility in the channel region 14a is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <100> axis direction of the semiconductor substrate 10, and therefore stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction. Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the channel regions 14 a and 14 b in the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10 by the tensile stress film 21. In addition, the stress that pulls the channel regions 14a and 14b outward mainly works. Therefore, the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the channel region 14a of the p-type MISFET region 2 decreases.

  The dummy contact 17 is formed through the tensile stress film 21 in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a on the element isolation region 15, so that the stress applied to the channel region 14a is relieved. .

Stress vectors F ₁₁ and F _{21 in} FIG. 4 represent stress parallel to the channel direction of the channel region 14a generated by the tensile stress film 21 in the p-type MISFET region 2 and stress perpendicular thereto, respectively. The stress vectors F ₁₀ and F ₂₀ represent stress parallel to the channel direction of the channel region 14a that is generated when the dummy contact 17 is not formed, and stress perpendicular to the channel region 14a.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

Since the dummy contact 17 relieves stress in the direction parallel to and perpendicular to the channel direction of the channel region 14a in the p-type MISFET region 2, the magnitudes of the stress vectors F ₁₁ and F ₂₁ are respectively the stress vector F ₁₀ , It is smaller than and _{F 20.} The stress vectors F ₃ and F ₄ have almost the same magnitude as the stress parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 when the dummy contact 17 is not formed, and the stress perpendicular to the channel direction. does not change.

  The dummy contact 17 is not limited to the position and number shown in FIG. 4 as long as it is formed in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a on the element isolation region 15. For example, it may be formed only in the vicinity of the region adjacent to the source / drain region 13a and the channel region 14a in the direction perpendicular to the channel direction on the element isolation region 15.

(Effect of the second embodiment)
According to the second embodiment, the tensile stress applied to the channel region 14a in the p-type MISFET region 2 by the tensile stress film 21 can be relaxed by the dummy contact 17, and the decrease in charge mobility can be mitigated. Thereby, the effect of improving the charge mobility in the channel region 14b of the n-type MISFET region 3 can be obtained efficiently.

  In the second embodiment, the channel region 14a of the p-type MISFET region 2 and the channel region 14b of the n-type MISFET region 3 whose channel directions are parallel to the <100> axis direction of the semiconductor substrate 10 are tensioned. Although the case where the stress film for applying the stress is applied has been described, a structure for applying the stress film for applying the compressive stress may be used. In this case, the charge mobility in the channel region 14a of the p-type MISFET region 2 is improved, and the charge mobility in the channel region 14b of the n-type MISFET region 3 is reduced, so that the periphery of the channel region 14b of the n-type MISFET region 3 is reduced. A dummy contact 17 is formed on the substrate to alleviate the decrease in charge mobility.

[Third Embodiment]
The third embodiment of the present invention is different from the second embodiment in that the channel directions of the channel regions in the p-type MISFET region and the n-type MISFET region are parallel to the <110> axis direction. Note that the description of the same points as in the second embodiment will be omitted.

  FIG. 6 is a top view showing the substrate surface of the semiconductor device according to the third embodiment of the present invention.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically isolated by the element isolation region 15. In addition, the tensile stress film 21 covers the surface of the semiconductor substrate 10 in the p-type MISFET region 2 and the n-type MISFET region 3. Note that a cross-sectional view of the semiconductor device 1 taken along the chain line AA ′ when viewed in the direction of the arrow in the drawing is the same as the cross-sectional view of the semiconductor device 1 according to the second embodiment shown in FIG. .

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a dummy contact 17 is formed on the element isolation region 15 around the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <110> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction causes the channel region 14 to move inward. When added in the direction of compression, the charge mobility is improved. On the other hand, when a stress in a direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14 outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <110> axis direction of the semiconductor substrate 10, and therefore stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction. Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the channel regions 14 a and 14 b in the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the tensile stress film 21. In addition, the stress that pulls the channel regions 14a and 14b outward mainly works. Therefore, the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 decreases.

  Since the dummy contact 17 is formed in the vicinity of a region adjacent to the source / drain region 13a on the element isolation region 15 in a direction parallel to the channel direction, and penetrates the tensile stress film 21 which is a source of stress. Relieve stress in a direction parallel to the direction.

Stress vectors F ₁₁ and F _{2 in} FIG. 6 represent stress parallel to the channel direction and stress perpendicular to the channel direction generated by the tensile stress film 21 in the p-type MISFET region 2, respectively. Further, the stress vector F ₁₀ represents the parallel stress in the channel direction generated when the dummy contact 17 is not formed.

The stress vectors F ₃ and F ₄ represent stress parallel to the channel direction and stress perpendicular to the channel direction generated by the tensile stress film 21 in the n-type MISFET region 3, respectively.

The dummy contact 17, to mitigate a direction parallel stress in the channel direction of the channel region 14a of the p-type MISFET region 2, the magnitude of the stress vector _{F 11} is smaller than the stress vector _{F 10.} Incidentally, the stress vector F ₂ has a vertical stress in the channel direction of the channel region 14a generated in the p-type MISFET region 2 when the dummy contact 17 is not formed, mostly the size does not change. The stress vectors F ₃ and F ₄ have almost the same magnitude as the stress parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 and the stress perpendicular to each other when the dummy contact 17 is not formed. does not change.

  The dummy contact 17 is limited to the position and number shown in FIG. 6 as long as it is formed in the vicinity of the source / drain region 13a in the direction parallel to the channel direction on the element isolation region 15. Absent.

(Effect of the third embodiment)
According to the third embodiment, the stress in the direction parallel to the channel direction applied to the channel region 14a of the p-type MISFET region 2 by the tensile stress film 21 is relaxed by the dummy contact 17, and the direction parallel to the channel direction is reduced. The reduction in the charge mobility of can be alleviated. Thereby, the effect of improving the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be efficiently obtained. .

[Fourth Embodiment]
In the fourth embodiment of the present invention, the channel direction of the channel region in the p-type MISFET region and the n-type MISFET region is parallel to the <110> axis direction, the compressive stress film, and the n-type MISFET region in the p-type MISFET region. The second embodiment is different from the second embodiment in that a tensile stress film is formed. Note that the description of the same points as in the second embodiment will be omitted.

  FIG. 7 is a top view showing a substrate surface of a semiconductor device according to the fourth embodiment of the present invention. FIG. 8 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 7 as viewed in the direction of the arrow in the drawing.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically separated by the element isolation region 15, and the surface of the semiconductor substrate 10 in the p-type MISFET region 2 is a compressive stress film 18, and the semiconductor substrate in the n-type MISFET region 3. 10 is covered with a tensile stress film 21.

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a dummy contact 17 is formed on the element isolation region 15 around the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <110> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction causes the channel region 14a to enter the channel region 14a. When added in the direction of compression, the charge mobility is improved. On the other hand, when the stress in the direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14a outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <110> axis direction of the semiconductor substrate 10, and therefore stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction. Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, since the compressive stress film 18 applies stress to the channel region 14a of the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10, the channel region 14a is placed inward. Compressive stress mainly works. Further, since stress is applied to the channel region 14b of the n-type MISFET region 3 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the tensile stress film 21, the stress that pulls the channel region 14b outward is mainly used. work.

  Therefore, the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 decreases.

  The dummy contact 17 is formed in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a in the direction perpendicular to the channel direction on the element isolation region 15 so as to penetrate the tensile stress film 21 that is a source of stress. Therefore, the stress in the direction perpendicular to the channel direction is relaxed.

Stress vectors F ₁ and F _{21 in} FIG. 7 represent a stress parallel to the channel direction of the channel region 14a generated by the compressive stress film 18 in the p-type MISFET region 2 and a stress perpendicular thereto, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction that occurs when a dummy contact 17 is not formed.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

The dummy contact 17, to mitigate the direction perpendicular stress in the channel direction of the channel region 14a of the p-type MISFET region 2, the magnitude of the stress vector _{F 21} is smaller than the stress vector _{F 20.} Note that the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction of the channel region 14 a generated in the p-type MISFET region 2 when the dummy contact 17 is not formed. The stress vectors F ₃ and F ₄ have almost the same magnitude as the stress parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 and the stress perpendicular to each other when the dummy contact 17 is not formed. does not change.

  If the dummy contact 17 is formed near the source / drain region 13a or the region adjacent to the channel region 14a in the direction perpendicular to the channel direction on the element isolation region 15, the position shown in FIG. It is not limited to numbers.

(Effect of the fourth embodiment)
According to the fourth embodiment, the stress in the direction perpendicular to the channel direction applied to the channel region 14a of the p-type MISFET region 2 by the compressive stress film 18 is relaxed by the dummy contact 17, and the direction perpendicular to the channel direction is reduced. The reduction in the charge mobility of can be alleviated. Thereby, it is possible to efficiently obtain the effect of improving the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3. .

[Fifth Embodiment]
The fifth embodiment of the present invention is different from the first embodiment in that a stress film removing portion is formed instead of a dummy contact. Note that the description of the same points as in the first embodiment, such as the material and the configuration of other parts, is omitted.

  FIG. 9 is a top view showing the substrate surface of the semiconductor device 1 according to the fifth embodiment of the present invention. 10 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 9 as viewed in the direction of the arrow in FIG. 9, and FIG. 11 shows the cut surface along the chain line BB ′ in FIG. It is sectional drawing seen in this direction.

  This semiconductor device 1 electrically connects an n-type well 11, a source / drain region 13 and a gate structure 12 formed in a p-type MISFET region 2 of a semiconductor substrate 10 and a p-type MISFET region 2 from a peripheral element region. The element isolation region 15 to be isolated, the source / drain region 13, the gate structure 12, the compressive stress film 18 having the stress film removing portion 22 covering the element isolation region 15, and the source formed on the source / drain region 13 A drain contact 16 and a general configuration.

  There is a channel region 14 between the source / drain regions 13. In the present embodiment, the channel direction is parallel to the <110> axis direction of the semiconductor substrate 10.

  As in the present embodiment, when the channel direction of the channel region 14 in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, stress in the direction parallel to the channel direction is applied to the channel region 14. When added in the direction of compressing inward, charge mobility is improved. On the other hand, when a stress in a direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14 outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, the stress is applied to the channel region 14 of the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the compressive stress film 18. The compressing stress mainly works, and the charge mobility in the direction parallel to the channel direction can be improved. However, on the contrary, the charge mobility in the direction perpendicular to the channel direction decreases.

  The stress film removing portion 22 is a hole formed in the compressive stress film 18 using a lithography method or the like, and is a direction perpendicular to the source / drain region 13 or the channel region 14 and the channel direction on the element isolation region 15. It is formed in the vicinity of the region adjacent to. In the stress film removing unit 22, since the compressive stress film 18 that is a source of stress is removed, the stress in the direction perpendicular to the channel direction is relaxed.

The stress vectors F ₁ and F _{21 in} FIG. 9 represent the stress parallel to the channel direction generated by the compressive stress film 18 and the stress perpendicular to the channel direction, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction that occurs when stress film removing section 22 is not formed.

Since the stress film removal unit 22 relieves stress in the direction perpendicular to the channel direction, the magnitude of the stress vector F ₂₁ is smaller than the stress vector F ₂₀ . Note that the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction that occurs when the stress film removal portion 22 is not formed.

  If the stress film removing portion 22 is formed in the vicinity of the source / drain region 13 or the region adjacent to the channel region 14 in the direction perpendicular to the channel direction on the element isolation region 15, FIG. 10 and the position and number shown in FIG.

(Effect of 5th Embodiment)
According to the fifth embodiment, the stress in the direction perpendicular to the channel direction applied to the channel region 14 of the p-type MISFET region 2 by the compressive stress film 18 is relaxed by the stress film removal unit 22 and is perpendicular to the channel direction. The decrease in charge mobility in any direction can be mitigated. Thereby, the effect of improving the charge mobility in the direction parallel to the channel direction can be obtained efficiently.

  In the fifth embodiment, a case where a stress film that applies compressive stress is applied to the p-type MISFET region 2 in which the channel direction of the channel region 14 is parallel to the <110> axis direction of the semiconductor substrate 10 will be described. However, the present invention is not limited to this, and any structure may be used as long as the stress film removal portion 22 is formed in a region where the direction of stress by the stress film is a direction in which the charge mobility in the channel region 14 is reduced.

  Specifically, for example, when a stress film that applies tensile stress is applied to the channel region 14 in the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10, the channel region is mainly used. The stress that pulls 14 outward acts and the charge mobility in the direction perpendicular to the channel direction can be improved. However, on the contrary, the charge mobility in the direction parallel to the channel direction is lowered, so that the stress film removal portion 22 is placed on the element isolation region 15 in the direction parallel to the source / drain region 13 and the channel region 14 in the channel direction. It is formed in the vicinity of the region adjacent to, and relieves stress in the direction parallel to the channel direction.

[Sixth Embodiment]
The sixth embodiment of the present invention is different from the fifth embodiment in that the semiconductor device has a p-type MISFET region and an n-type MISFET region. The channel direction of the channel region in the p-type MISFET region and the n-type MISFET region is parallel to the <100> axis direction, and the channel region receives a stress that is pulled outward by the tensile stress film. Note that a description of the same points as in the fifth embodiment will be omitted.

  FIG. 12 is a top view showing a substrate surface of a semiconductor device according to the sixth embodiment of the present invention. FIG. 13 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 12 as viewed in the direction of the arrows in the figure.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically isolated by the element isolation region 15. In addition, the tensile stress film 21 covers the surface of the semiconductor substrate 10 in the p-type MISFET region 2 and the n-type MISFET region 3.

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a stress film removing portion 22 is formed on the element isolation region 15 around the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <100> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <100> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction and the channel direction When stress in the vertical direction is applied in the direction in which the channel region 14a is compressed inward, the charge mobility in the channel region 14a is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <100> axis direction of the semiconductor substrate 10, and therefore stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction. Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the p-type MISFET region 2 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10 and the channel regions 14 a and 14 b of the n-type MISFET region 3 by the tensile stress film 21. In addition, the stress that pulls the channel regions 14a and 14b outward mainly works. Therefore, the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the channel region 14a of the p-type MISFET region 2 decreases.

  The stress film removal portion 22 is a hole formed in the tensile stress film 21 using a lithography method or the like, and is formed in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a on the element isolation region 15. Is done. In the stress film removing unit 22, the tensile stress film 21 that is a source of stress is removed, so that the tensile stress applied to the channel region 14a is relaxed.

Stress vectors F ₁₁ and F _{21 in} FIG. 12 represent a stress parallel to the channel direction of the channel region 14a generated by the tensile stress film 21 in the p-type MISFET region 2 and a stress perpendicular thereto, respectively. The stress vectors F ₁₀ and F ₂₀ represent a stress parallel to the channel direction of the channel region 14a and a stress perpendicular to the channel direction, which are generated when the stress film removal portion 22 is not formed.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

Since the stress film removing unit 22 relieves stress in the direction parallel to and perpendicular to the channel direction of the channel region 14a in the p-type MISFET region 2, the magnitudes of the stress vectors F ₁₁ and F ₂₁ are respectively ₁₀ is smaller than, and _{F 20.} The stress vectors F ₃ and F ₄ are almost as large as stress parallel to and perpendicular to the channel direction of the channel region 14b generated in the n-type MISFET region 3 when the stress film removal portion 22 is not formed. Does not change.

  If the stress film removing portion 22 is formed in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a on the element isolation region 15, the position and number shown in FIGS. Not limited to. For example, it may be formed only in the vicinity of the region adjacent to the source / drain region 13a and the channel region 14a in the direction perpendicular to the channel direction on the element isolation region 15.

(Effect of 6th Embodiment)
According to the sixth embodiment, the tensile stress applied to the channel region 14a of the p-type MISFET region 2 by the tensile stress film 21 can be relaxed by the stress film removal unit 22, and the decrease in charge mobility can be mitigated. . Thereby, the effect of improving the charge mobility in the channel region 14b of the n-type MISFET region 3 can be obtained efficiently.

  In the sixth embodiment, a stress film that applies tensile stress is applied to the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10. Although the case has been described, a configuration in which a stress film that applies compressive stress may be applied. In this case, the charge mobility in the channel region 14a of the p-type MISFET region 2 is improved, and the charge mobility in the channel region 14b of the n-type MISFET region 3 is reduced, so that the periphery of the channel region 14b of the n-type MISFET region 3 is reduced. Then, the stress film removing portion 22 is formed to alleviate the decrease in charge mobility.

[Seventh Embodiment]
The seventh embodiment of the present invention is different from the sixth embodiment in that the channel directions of the channel regions in the p-type MISFET region and the n-type MISFET region are parallel to the <110> axis direction. Note that a description of the same points as in the sixth embodiment will be omitted.

  FIG. 14 is a top view showing the substrate surface of the semiconductor device according to the seventh embodiment of the present invention.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically isolated by the element isolation region 15. In addition, the tensile stress film 21 covers the surface of the semiconductor substrate 10 in the p-type MISFET region 2 and the n-type MISFET region 3. Note that a cross-sectional view of the semiconductor device 1 taken along the chain line AA ′ when viewed in the direction of the arrow in the drawing is the same as the cross-sectional view of the semiconductor device 1 according to the second embodiment shown in FIG. .

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a stress film removing portion 22 is formed on the element isolation region 15 around the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <110> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction causes the channel region 14 to move inward. When added in the direction of compression, the charge mobility is improved. On the other hand, when a stress in a direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14 outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, since the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <110> axis direction of the semiconductor substrate 10, stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 and the channel regions 14 a and 14 b of the n-type MISFET region 3 by the tensile stress film 21. In addition, the stress that pulls the channel regions 14a and 14b outward mainly works. Therefore, the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 decreases.

  The stress film removing portion 22 is a hole formed in the tensile stress film 21 using a lithography method or the like, and in the vicinity of a region adjacent to the source / drain region 13a in the direction parallel to the channel direction on the element isolation region 15. Formed. In the stress film removal unit 22, the tensile stress film 21 that is a source of stress is removed, so that the stress in the direction parallel to the channel direction is relaxed.

Stress vectors F ₁₁ and F _{2 in} FIG. 14 represent stress parallel to the channel direction of the channel region 14a generated by the tensile stress film 21 in the p-type MISFET region 2 and stress perpendicular to the channel direction, respectively. Further, the stress vector F ₁₀ represents the parallel stress in the channel direction generated when the stress film removing section 22 is not formed.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel direction, respectively.

Stress film removing unit 22, to mitigate a direction parallel stress in the channel direction of the channel region 14a of the p-type MISFET region 2, the magnitude of the stress vector _{F 11} is smaller than the stress vector _{F 10.} Incidentally, the stress vector F ₂ has a vertical stress in the channel direction of the channel region 14a generated in the p-type MISFET region 2 when the stress film removing section 22 is not formed, mostly the size does not change. In addition, the stress vectors F ₃ and F ₄ are almost large, that is, stress parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 and stress perpendicular to each other when the stress film removal portion 22 is not formed. Does not change.

  If the stress film removing portion 22 is formed in the vicinity of a region adjacent to the source / drain region 13 in the direction parallel to the channel direction on the element isolation region 15, the stress film removing portion 22 has the position and number shown in FIG. Not limited.

(Effect of 7th Embodiment)
According to the seventh embodiment, the stress in the direction parallel to the channel direction applied to the channel region 14a of the p-type MISFET region 2 by the tensile stress film 21 is relaxed by the stress film removal unit 22 and parallel to the channel direction. The decrease in charge mobility in any direction can be mitigated. Thereby, the effect of improving the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be efficiently obtained. .

[Eighth Embodiment]
In the eighth embodiment of the present invention, the channel direction of the channel region in the p-type MISFET region and the n-type MISFET region is parallel to the <110> axis direction, and the compressive stress film and the n-type MISFET region are formed in the p-type MISFET region. This is different from the sixth embodiment in that a tensile stress film is formed. Note that a description of the same points as in the sixth embodiment will be omitted.

  FIG. 15 is a top view showing the substrate surface of the semiconductor device according to the eighth embodiment of the present invention. FIG. 16 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 15 as viewed in the direction of the arrow in the figure.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically separated by the element isolation region 15, and the surface of the semiconductor substrate 10 in the p-type MISFET region 2 is a compressive stress film 18, and the semiconductor substrate in the n-type MISFET region 3. 10 is covered with a tensile stress film 21.

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a stress film removing portion 22 is formed on the element isolation region 15 around the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <110> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction causes the channel region 14a to enter the channel region 14a. When added in the direction of compression, the charge mobility is improved. On the other hand, when the stress in the direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14a outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <110> axis direction of the semiconductor substrate 10, and therefore stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction. Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, since the compressive stress film 18 applies stress to the channel region 14a of the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10, the channel region 14a is placed inward. Compressive stress mainly works. Further, since stress is applied to the channel region 14b of the n-type MISFET region 3 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the tensile stress film 21, the stress that pulls the channel region 14b outward is mainly used. work.

  Therefore, the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 decreases.

  The stress film removing portion 22 is a hole formed in the compressive stress film 18 using a lithography method or the like, and is a direction perpendicular to the source / drain region 13 or the channel region 14 and the channel direction on the element isolation region 15. It is formed in the vicinity of the region adjacent to. In the stress film removing unit 22, since the compressive stress film 18 that is a source of stress is removed, the stress in the direction perpendicular to the channel direction is relaxed.

Stress vectors F ₁ and F _{21 in} FIG. 15 represent a stress parallel to the channel direction of the channel region 14a generated by the compressive stress film 18 in the p-type MISFET region 2 and a stress perpendicular thereto, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction of the channel region 14a which occurs when the stress film removing section 22 is not formed.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

Stress film removing unit 22, to mitigate the direction perpendicular stress in the channel direction of the channel region 14a of the p-type MISFET region 2, the magnitude of the stress vector _{F 21} is smaller than the stress vector _{F 20.} Note that the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction of the channel region 14 a generated in the p-type MISFET region 2 when the stress film removal portion 22 is not formed. The stress vectors F ₃ and F ₄ are stresses parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 when the stress film removal portion 22 is not formed, and stresses perpendicular to the channel direction, respectively. The size is almost unchanged.

  If the stress film removing portion 22 is formed in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a in the direction perpendicular to the channel direction on the element isolation region 15, as shown in FIG. It is not limited to the position and number shown.

(Effect of 8th Embodiment)
According to the eighth embodiment, the stress in the direction perpendicular to the channel direction applied to the channel region 14a of the p-type MISFET region 2 by the compressive stress film 18 is relaxed by the stress film removal unit 22 and is perpendicular to the channel direction. The decrease in charge mobility in any direction can be mitigated. Thereby, it is possible to efficiently obtain the effect of improving the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3. .

[Ninth Embodiment]
The ninth embodiment of the present invention is different from the first embodiment in that well contacts are formed instead of dummy contacts. Note that the description of the same points as in the first embodiment, such as the material and the configuration of other parts, is omitted.

  FIG. 17 is a top view showing a substrate surface of a semiconductor device according to the ninth embodiment of the present invention. 18 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 17 as viewed in the direction of the arrow in the drawing.

  This semiconductor device 1 electrically connects an n-type well 11, a source / drain region 13 and a gate structure 12 formed in a p-type MISFET region 2 of a semiconductor substrate 10 and a p-type MISFET region 2 from a peripheral element region. An element isolation region 15 to be isolated, a compressive stress film 18 covering the source / drain region 13, the gate structure 12, and the element isolation region 15, a source / drain contact 16 formed on the source / drain region 13, and an n-type And a well contact 23 formed on the well 11.

  There is a channel region 14 between the source / drain regions 13. In the present embodiment, the channel direction is parallel to the <110> axis direction of the semiconductor substrate 10.

  The well contact 23 conducts the wiring on the interlayer insulating film 19 and the source / drain region 13, and is formed at the same time in the same process as the source / drain contact 16 using the same material as the source / drain contact 16. can do.

  As in the present embodiment, when the channel direction of the channel region 14 a in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, stress in the direction parallel to the channel direction is applied to the channel region 14. When added in the direction of compressing inward, charge mobility is improved. On the other hand, when a stress in a direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14 outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, the stress is applied to the channel region 14 of the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the compressive stress film 18. The compressing stress mainly works, and the charge mobility in the direction parallel to the channel direction can be improved. However, on the contrary, the charge mobility in the direction perpendicular to the channel direction decreases.

  The well contact 23 is formed in the vicinity of a region on the n-type well 11 adjacent to the source / drain region 13 and the channel region 14 in a direction perpendicular to the channel direction. Since the well contact 23 is formed through the compressive stress film 18 that is a source of stress, stress in a direction perpendicular to the channel direction is relieved.

Stress vectors F ₁ and F _{21 in} FIG. 17 represent a stress parallel to the channel direction generated by the compressive stress film 18 and a stress perpendicular to the channel direction, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction that occurs when the well contact 23 is not formed.

Since the well contact 23 relieves stress in the direction perpendicular to the channel direction, the magnitude of the stress vector F ₂₁ around the well contact 23 is smaller than the stress vector F ₂₀ . In addition, the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction that occurs when the stress film removal portion 22 is not formed.

  As long as the well contact 23 is formed in the vicinity of the source / drain region 13 or the region adjacent to the channel region 14 in the direction perpendicular to the channel direction on the n-type well 11, FIG. 17 and FIG. The position and number shown in FIG. For example, in FIG. 17 and FIG. 18, the well contact 23 is formed on one side of the source / drain region 13 or the region adjacent to the channel region 14 in the direction perpendicular to the channel direction. It may be. In addition, as the number of well contacts 23 increases, the stress can be effectively relieved. For example, the space between adjacent well contacts 23 can be 0.07 μm or less.

(Effect of 9th Embodiment)
According to the ninth embodiment, the stress in the periphery of the well contact 23 in the direction perpendicular to the channel direction applied to the channel region 14 of the p-type MISFET region 2 by the compressive stress film 18 is relaxed by the well contact 23, A decrease in charge mobility in a direction perpendicular to the channel direction can be mitigated. Thereby, the effect of improving the charge mobility in the direction parallel to the channel direction can be obtained efficiently.

  In the ninth embodiment, a case where a stress film that applies compressive stress is applied to the p-type MISFET region 2 in which the channel direction of the channel region 14 is parallel to the <110> axis direction of the semiconductor substrate 10 will be described. However, the present invention is not limited to this, and any structure may be used as long as the well contact 23 is formed in a region in which the direction of stress by the stress film is a direction in which the charge mobility in the channel region 14 is reduced.

  Specifically, for example, when a stress film that applies tensile stress is applied to the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10, the channel region 14 is mainly outward. The tensile stress acts, and the charge mobility in the direction perpendicular to the channel direction can be improved. However, since the charge mobility in the direction parallel to the channel direction decreases, the well contact 23 is adjacent to the source / drain region 13 and the channel region 14 on the element isolation region 15 in the direction parallel to the channel direction. It is formed in the vicinity of the region to be relieved to relieve stress in the direction parallel to the channel direction.

[Tenth embodiment]
The tenth embodiment of the present invention is different from the ninth embodiment in that the semiconductor device has a p-type MISFET region and an n-type MISFET region. The channel direction of the channel region in the p-type MISFET region and the n-type MISFET region is parallel to the <100> axis direction, and the channel region receives a stress that is pulled outward by the tensile stress film. Note that a description of the same points as in the seventh embodiment will be omitted.

  FIG. 19 is a top view showing the substrate surface of the semiconductor device according to the tenth embodiment of the present invention. 20 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 19 as viewed in the direction of the arrow in the drawing.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically isolated by the element isolation region 15. In addition, the tensile stress film 21 covers the surface of the semiconductor substrate 10 in the p-type MISFET region 2 and the n-type MISFET region 3.

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a well contact 23a is formed on the n-type well 11.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b, and a well contact 23b is formed on the p-type well 20.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <100> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <100> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction and the channel direction When stress in the vertical direction is applied in the direction in which the channel region 14a is compressed inward, the charge mobility in the channel region 14a is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <100> axis direction of the semiconductor substrate 10, and therefore stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction. Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the channel regions 14 a and 14 b of the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10 by the tensile stress film 21. In addition, the stress that pulls the channel regions 14a and 14b outward mainly works. Therefore, the charge mobility of the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility of the channel region 14a of the p-type MISFET region 3 decreases.

  The well contact 23a is formed on the n-type well 11, for example, in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a in the direction perpendicular to the channel direction. The well contact 23b is formed on the p-type well 20, for example, in the vicinity of a region adjacent to the source / drain region 13b or the channel region 14b in a direction perpendicular to the channel direction. The well contacts 23a and 23b are formed through the compressive stress film 18 which is a source of stress.

  Here, since the number of well contacts 23a on the n-type well 11 is large and the number of well contacts 23b on the p-type well 20 is small, the stress applied to the channel region 14a is greatly relaxed, and the stress applied to the channel region 14b is not so much. Not affected. Further, in order to reduce the relaxation of the stress applied to the channel region 14b, the well contact 23b may be formed as far as possible from the channel region 14b.

The stress vectors F ₁ and F _{21 in} FIG. 19 represent stress parallel to the channel direction of the channel region 14a generated by the compressive stress film 18 in the p-type MISFET region 2 and stress perpendicular thereto, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction that occurs when the number of contacts well contact 23a is small.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

Well contact 23a in order to mitigate the vertical direction of the stress in the channel direction of the channel region 14a of the p-type MISFET region 2, the magnitude of the stress vector _{F 21} in the peripheral well contact 23a is smaller than the stress vector _{F 20} ing. Note that the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction of the channel region 14 a generated in the p-type MISFET region 2 when the number of contacts of the well contacts 23 a is small. Further, the stress vectors F ₃ and F ₄ are almost large, that is, a stress parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 when the number of contacts of the well contact 23a is small, and a stress perpendicular to the channel region 14b. Does not change.

  As long as the well contacts 23a and 23b are formed so that there are many well contacts 23a on the n-type well 11 and few well contacts 23b on the p-type well 20, the positions shown in FIGS. It is not limited to numbers. For example, the space between adjacent well contacts 23a can be 0.07 μm or less, and the space between adjacent well contacts 23b can be 0.20 μm or more.

(Effect of 10th Embodiment)
According to the tenth embodiment, the tensile stress around the well contact 23a applied to the channel region 14a of the p-type MISFET region 2 by the tensile stress film 21 is relaxed by the well contact 23a, and the decrease in charge mobility is alleviated. be able to. Thereby, the effect of improving the charge mobility in the channel region 14b of the n-type MISFET region 3 can be obtained efficiently.

  In the tenth embodiment, a stress film that applies tensile stress is applied to the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10. Although the case has been described, a configuration in which a stress film that applies compressive stress may be applied. In this case, the charge mobility in the channel region 14a of the p-type MISFET region 2 is improved, and the charge mobility in the channel region 14b of the n-type MISFET region 3 is reduced, so that the well contact 23a on the n-type well 11 is A small number of well contacts 23b on the p-type well 20 are formed to alleviate a decrease in charge mobility in the channel region 14b of the n-type MISFET region 3.

  Further, as in the third embodiment, the channel directions of the p-type MISFET region 2 and the n-type MISFET region 3 are parallel to the <110> axis direction, and stress is applied to the channel regions 14a and 14b by the tensile stress film 21. In the case of addition, many well contacts 23a are formed on the n-type well 11 in the vicinity of the source / drain regions 13a adjacent to the direction parallel to the channel direction. Thereby, the stress in the direction parallel to the channel direction applied to the channel region 14a of the p-type MISFET region 2 by the tensile stress film 21 is relieved, and the decrease in charge mobility in the direction parallel to the channel direction is relieved.

[Eleventh embodiment]
In the eleventh embodiment of the present invention, the channel direction of the channel region in the p-type MISFET region and the n-type MISFET region is parallel to the <110> axis direction, the compressive stress film, and the n-type MISFET region in the p-type MISFET region. The tenth embodiment differs from the tenth embodiment in that a tensile stress film is formed. Note that the description of the same points as in the tenth embodiment will be omitted.

  FIG. 21 is a top view showing a substrate surface of a semiconductor device according to the eleventh embodiment of the present invention. FIG. 22 is a cross-sectional view of the cut surface taken along the chain line AA ′ in FIG. 21 as viewed in the direction of the arrow in the drawing.

  The semiconductor device 1 has a p-type MISFET region 2 and an n-type MISFET region 3. The p-type MISFET region 2 and the n-type MISFET region 3 are electrically separated by the element isolation region 15, and the surface of the semiconductor substrate 10 in the p-type MISFET region 2 is a compressive stress film 18, and the semiconductor substrate in the n-type MISFET region 3. 10 is covered with a tensile stress film 21.

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a, and a well contact 23a is formed on the n-type well 11.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b, and a well contact 23b is formed on the p-type well 20.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <110> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <110> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction causes the channel region 14a to enter the channel region 14a. When added in the direction of compression, the charge mobility is improved. On the other hand, when the stress in the direction perpendicular to the channel direction is applied in the direction of pulling the channel region 14a outward, the charge mobility is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, since the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <110> axis direction of the semiconductor substrate 10, stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, since the compressive stress film 18 applies stress to the channel region 14a of the p-type MISFET region 2 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10, the channel region 14a is placed inward. Compressive stress mainly works. Further, since stress is applied to the channel region 14b of the n-type MISFET region 3 whose channel direction is parallel to the <110> axis direction of the semiconductor substrate 10 by the tensile stress film 21, the stress that pulls the channel region 14b outward is mainly used. work.

  Therefore, the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility in the direction perpendicular to the channel direction in the channel region 14a of the p-type MISFET region 2 decreases.

  The well contact 23a is formed on the n-type well 11 in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a in the direction perpendicular to the channel direction. The well contact 23b is formed on the p-type well 20, for example, in the vicinity of a region adjacent to the source / drain region 13b or the channel region 14b in a direction perpendicular to the channel direction. The well contacts 23a and 23b are formed through the compressive stress film 18 which is a source of stress.

  Here, since the number of well contacts 23a on the n-type well 11 is large and the number of well contacts 23b on the p-type well 20 is small, the stress applied to the channel region 14a is greatly relaxed, and the stress applied to the channel region 14b is not so much. Not affected. Further, in order to reduce the relaxation of the stress applied to the channel region 14b, the well contact 23b may be formed as far as possible from the channel region 14b.

The stress vectors F ₁ and F _{21 in} FIG. 21 represent stress parallel to the channel direction of the channel region 14a generated by the compressive stress film 18 in the p-type MISFET region 2, and perpendicular stress, respectively. Further, the stress vector F ₂₀ represents a vertical stress in the channel direction that occurs when the number of contacts well contact 23a is small.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

Well contact 23a in order to mitigate the vertical direction of the stress in the channel direction of the channel region 14a of the p-type MISFET region 2, the magnitude of the stress vector _{F 21} in the peripheral well contact 23a is smaller than the stress vector _{F 20} ing. Note that the magnitude of the stress vector F ₁ is almost the same as the stress parallel to the channel direction of the channel region 14 a generated in the p-type MISFET region 2 when the number of contacts of the well contacts 23 a is small. Further, the stress vectors F ₃ and F ₄ are almost large, that is, a stress parallel to the channel direction of the channel region 14b generated in the n-type MISFET region 3 when the number of contacts of the well contact 23a is small, and a stress perpendicular to the channel direction Does not change.

  The well contact 23a is formed in the vicinity of the source / drain region 13a or the region adjacent to the channel region 14a in the direction perpendicular to the channel direction and more than the well contact 23b. 21 and the position and number shown in FIG. Further, the well contact 23 b may be formed at any position on the p-type well 20.

(Effect of 11th Embodiment)
According to the eleventh embodiment, the stress in the direction perpendicular to the channel direction applied to the channel region 14a of the p-type MISFET region 2 by the compressive stress film 18 is relaxed by the well contact 23a, and the direction perpendicular to the channel direction. The reduction in the charge mobility of can be alleviated. Thereby, it is possible to efficiently obtain the effect of improving the charge mobility in the direction parallel to the channel direction in the channel region 14a of the p-type MISFET region 2 and the charge mobility in the channel region 14b of the n-type MISFET region 3. .

[Twelfth embodiment]
The twelfth embodiment of the present invention differs from the second embodiment in that the number of source / drain contacts is increased instead of forming dummy contacts. Note that the description of the same points as in the second embodiment, such as the material and the configuration of other parts, is omitted.

  FIG. 23 is a top view showing the substrate surface of the semiconductor device according to the twelfth embodiment of the present invention. Note that a cross-sectional view of the semiconductor device 1 taken along the chain line AA ′ when viewed in the direction of the arrow in the drawing is the same as the cross-sectional view of the semiconductor device 1 according to the second embodiment shown in FIG. .

  In the p-type MISFET region 2, an n-type well 11, a source / drain region 13a, and a gate structure 12 are formed. A source / drain contact 16a is formed on the source / drain region 13a.

  In the n-type MISFET region 3, a p-type well 20, a source / drain region 13b, and a gate structure 12 are formed. A source / drain contact 16b is formed on the source / drain region 13b.

  Between the source / drain regions 13a and 13b, there are channel regions 14a and 14b, respectively. In the present embodiment, the channel directions of the channel regions 14 a and 14 b are parallel to the <100> axis direction of the semiconductor substrate 10.

  In the present embodiment, since the channel direction of the channel region 14a in the p-type MISFET region 2 is parallel to the <100> axis direction of the semiconductor substrate 10, the stress in the direction parallel to the channel direction and the channel direction When stress in the vertical direction is applied in the direction in which the channel region 14a is compressed inward, the charge mobility in the channel region 14a is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  On the other hand, since the channel direction of the channel region 14b in the n-type MISFET region 3 is parallel to the <100> axis direction of the semiconductor substrate 10, stress in a direction parallel to the channel direction and stress in a direction perpendicular to the channel direction Is added in the direction of pulling the channel region 14b outward, the charge mobility in the channel region 14b is improved. However, when a stress is applied in a direction opposite to the direction in which the charge mobility is improved, the charge mobility is lowered.

  In the present embodiment, stress is applied to the channel regions 14 a and 14 b of the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10 by the tensile stress film 21. In addition, the stress that pulls the channel regions 14a and 14b outward mainly works. Therefore, the charge mobility of the channel region 14b of the n-type MISFET region 3 can be improved. However, on the contrary, the charge mobility of the channel region 14a of the p-type MISFET region 2 decreases.

  The source / drain contacts 16a and 16b are formed through the tensile stress film 21 which is a source of stress. Here, since the source / drain contact 16a on the source / drain region 13a is large and the source / drain contact 16b on the source / drain region 13b is small, the stress applied to the channel region 14a is greatly relaxed. The stress applied to 14b is not significantly affected.

Stress vectors F ₁₁ and F _{21 in} FIG. 23 represent stress parallel to the channel direction of the channel region 14a generated by the tensile stress film 21 in the p-type MISFET region 2 and stress perpendicular to the channel direction, respectively. The stress vectors F ₁₀ and F ₂₀ represent a stress parallel to the channel direction of the channel region 14a and a stress perpendicular to the channel region 14a, which are generated when the stress film removal portion 22 is not formed.

The stress vectors F ₃ and F ₄ represent a stress parallel to the channel direction of the channel region 14b generated by the tensile stress film 21 in the n-type MISFET region 3 and a stress perpendicular to the channel region 14b.

Since the source / drain regions 13a relieve stress in the direction parallel to and perpendicular to the channel direction of the channel region 14a in the p-type MISFET region 2, the magnitudes of the stress vectors F ₁₁ and F ₂₁ are respectively ₁₀ is smaller than, and _{F 20.} The stress vectors F ₃ and F ₄ are almost equal to the stress parallel to the channel direction 14b and perpendicular to the channel direction generated in the n-type MISFET region 3 when the source / drain region 13a is not formed. Does not change.

  It should be noted that the source / drain contacts 16a and 16b may be formed as long as the source / drain contact 16a on the source / drain region 13a is large and the source / drain contact 16b on the source / drain region 13b is small. It is not restricted to the position and number shown in. For example, the space between adjacent source / drain contacts 16a can be 0.07 μm or less, and the space between adjacent source / drain contacts 16b can be 0.20 μm or more.

(Effect of 12th Embodiment)
According to the twelfth embodiment, the tensile stress applied to the channel region 14a of the p-type MISFET region 2 by the tensile stress film 21 can be relaxed by the source / drain contact 16a, and the decrease in charge mobility can be mitigated. . Thereby, the effect of improving the charge mobility in the channel region 14b of the n-type MISFET region 3 can be obtained efficiently.

  In the twelfth embodiment, a stress film that applies tensile stress is applied to the p-type MISFET region 2 and the n-type MISFET region 3 whose channel direction is parallel to the <100> axis direction of the semiconductor substrate 10. Although the case has been described, a configuration in which a stress film that applies compressive stress may be applied. In this case, the charge mobility in the channel region 14a of the p-type MISFET region 2 is improved, and the charge mobility in the channel region 14b of the n-type MISFET region 3 is reduced, so that the source / drain on the source / drain region 13a is reduced. The number of contacts 16a is small, and the number of source / drain contacts 16b on the source / drain region 13b is large, which alleviates the decrease in charge mobility in the channel region 14b of the n-type MISFET region 3.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the relationship between the channel direction of each MISFET and the direction of the semiconductor substrate is not limited to that shown in the above embodiments. In addition, the plane orientation and the axial direction of the semiconductor substrate in each of the above embodiments may not exactly match the numerical values described, for example, a deviation of ± 10 ° or less is included in the scope of application of the present invention. Shall.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

The present invention is also characterized in a method for manufacturing a semiconductor device having the following configuration.
(1) The semiconductor substrate has a {100} plane as a main surface,
The MISFET is a p-type MISFET whose channel direction is parallel to the <110> axis direction of the semiconductor substrate,
The stress film applies compressive stress to the channel region,
The stress relaxation structure is formed in the vicinity of a region adjacent to the source / drain region in a direction perpendicular to the channel direction.
The semiconductor device according to claim 1.
(2) The semiconductor substrate has a {100} plane as a main surface,
A plurality of the MISFETs are formed, and the plurality of MISFETs include a p-type MISFET and an n-type MISFET whose channel direction is parallel to the <100> axis direction of the semiconductor substrate,
The stress film applies tensile stress to the channel regions of the p-type MISFET and the n-type MISFET,
The stress relaxation structure is formed in the vicinity of a region adjacent to the source / drain region of the p-type MISFET perpendicular to the channel direction.
The semiconductor device according to claim 1.
(3) The semiconductor substrate has a {100} plane as a main surface,
A plurality of the MISFETs are formed, and the plurality of MISFETs include a p-type MISFET and an n-type MISFET whose channel direction is parallel to the <100> axis direction of the semiconductor substrate,
The stress film applies compressive stress to the channel regions of the p-type MISFET and the n-type MISFET,
The stress relaxation structure is formed near a region adjacent to the source / drain region of the p-type MISFET.
The semiconductor device according to claim 1.
(4) The semiconductor substrate has a {100} plane as a main surface,
A plurality of the MISFETs are formed, and the plurality of MISFETs include a p-type MISFET and an n-type MISFET whose channel direction is parallel to the <110> axis direction of the semiconductor substrate,
The stress film applies compressive stress to the channel region of the p-type MISFET and tensile stress to the channel region of the n-type MISFET,
The stress relaxation structure is formed in the vicinity of a region adjacent to the source / drain region of the p-type MISFET perpendicular to the channel direction.
The semiconductor device according to claim 1.
(5) The semiconductor substrate has a {100} plane as a main surface,
A plurality of the MISFETs are formed, and the plurality of MISFETs include a p-type MISFET and an n-type MISFET whose channel direction is parallel to the <110> axis direction of the semiconductor substrate,
The stress film applies tensile stress to the channel regions of the p-type MISFET and the n-type MISFET,
The stress relaxation structure is formed near a region adjacent to the source / drain region of the p-type MISFET in parallel with the channel direction.
The semiconductor device according to claim 1.

1 is a top view of a semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is a top view of a semiconductor device concerning a 2nd embodiment of the present invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 6 is a top view of a semiconductor device according to a third embodiment of the present invention. It is a top view of the semiconductor device which concerns on the 4th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 5th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 5th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 6th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 6th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 7th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 8th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 8th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 9th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 9th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 10th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 10th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 11th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 11th Embodiment of this invention. It is a top view of the semiconductor device which concerns on the 12th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 p-type MISFET region 3 n-type MISFET region 10 Semiconductor substrate 11 n-type well 12 Gate structure 13, 13a, 13b Source / drain region 14, 14a, 14b Channel region 15 Element isolation region 16, 16a, 16b Source / source Drain contact 17 Dummy contact 18 Compressive stress film 19 Interlayer insulating film 20 P-type well 21 Tensile stress film 22 Stress film removal part 23, 23a, 23b Well contact

Claims (5)

A semiconductor substrate;
A MISFET formed on the semiconductor substrate and separated by an element isolation region;
A stress film formed on the semiconductor substrate and applying stress to the channel region of the MISFET to change the charge mobility in the channel region;
A stress relaxation structure that relaxes the component of the stress in the direction of decreasing the charge mobility while maintaining the component of the stress in the direction of improving the charge mobility;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the stress relaxation structure is a dummy contact formed through the stress film on the element isolation region.   The semiconductor device according to claim 1, wherein the stress relaxation structure is a hole formed in the stress film. The MISFET is formed on a well formed in the semiconductor substrate,
2. The semiconductor device according to claim 1, wherein the stress relaxation means is a well contact formed through the stress film on the well.   The semiconductor device according to claim 1, wherein the stress relaxation structure is a source / drain contact formed through the stress film on the source / drain region.

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