JP2008158747A - Data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer device, wherein data transfer efficiency is better than the bus structure configured of shared bus connection, and wiring quantity is more reduced than a bus structure configured of cross-bar connection. <P>SOLUTION: This data transfer device configured to transfer data between master circuit blocks 101 and 102 and slave circuit blocks 103 and 104, is provided with: first control circuits 401 and 402 for communicating with the corresponding master circuit blocks; second control circuits 403 and 404 for communicating with the corresponding slave circuits; a shared bus 201 connected to the first control circuit and the second control circuit; and a cross bar part 301 connecting the first control circuit and the second control circuit. The request phase of transaction is executed by a cross bar part 301, and a data phase and a response phase are executed by a shared bus 201. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus.

  Buses that transfer data between a plurality of modules include shared bus connections and crossbar connections. In a bus structure configured by shared bus connection, a plurality of modules are connected to one bus (shared bus). Each module notifies the bus arbiter of a bus request for using the bus, and the bus arbiter issues a bus use permission to a specific module according to the received bus request and the arbitration method (see, for example, Patent Document 1). When a bus request is notified when another module is using the bus, or when multiple modules notify a bus request at the same time, arbitration by the bus arbiter and a waiting time until the bus becomes free are required, and data transfer efficiency is improved. Reduce.

On the other hand, in the bus structure configured by crossbar connection, the modules are connected by signal lines, and the waiting time until the bus becomes free is shorter than in the shared bus connection, and the data transfer efficiency is good. However, since each module has one set of buses, the number of signal lines (wiring amount) increases in proportion to the number of modules, and the circuit area, the amount of heat generation, power consumption, and the like increase.
Japanese Patent Laid-Open No. 10-161973

  It is an object of the present invention to provide a data transfer apparatus that has better data transfer efficiency than a bus structure configured with a shared bus connection and can reduce the amount of wiring as compared with a bus structure configured with a crossbar connection. .

  A data transfer device according to one embodiment of the present invention transfers data between n (n is an integer of 1 or more) master circuit blocks and m (m is an integer of 1 or more) slave circuit blocks. A data transfer device, each of n first control circuits communicating with the corresponding master circuit block, and m second control circuits communicating with the corresponding slave circuit block; , A shared bus connected to the first control circuit and the second control circuit, and crossbars connecting between the n first control circuits and the m second control circuits, respectively. And the first control circuit and the second control circuit include a command signal transmitted from the master circuit block to the slave circuit block, and the slave circuit block receiving the command signal. A command response signal to be transmitted to the star circuit block is transferred via the crossbar unit, and a write data signal to be transmitted to the slave circuit by the master circuit block and a read data signal to be transmitted to the master circuit block by the slave circuit block Are transferred via the shared bus.

  A data transfer device according to one embodiment of the present invention transfers data between n (n is an integer of 1 or more) master circuit blocks and m (m is an integer of 1 or more) slave circuit blocks. And n second control circuits for communicating with the corresponding slave circuit blocks, and n first control circuits for communicating with the corresponding master circuit blocks, respectively. A circuit, a shared bus connected to the first control circuit and the second control circuit, and the n first control circuits and the m second control circuits, respectively. A crossbar unit, wherein the first control circuit and the second control circuit are configured so that the command signal, the write data signal, and the slave circuit block that the master circuit block transmits to the slave circuit block A command response signal to be transmitted to the master circuit block in response to reception of the command signal is transferred through the crossbar unit, and a read data signal to be transmitted from the slave circuit block to the master circuit block is transferred through the shared bus. To do.

  According to the present invention, it is possible to improve the data transfer efficiency as compared with the bus structure configured by the shared bus connection and reduce the wiring amount as compared with the bus structure configured by the crossbar connection.

  Hereinafter, a data transfer apparatus according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a schematic configuration of a data transfer apparatus according to an embodiment of the present invention. The data transfer device performs data transfer between one or more master circuit blocks and one or more slave circuit blocks. Here, as an example, two master circuit blocks 101 and 102 and two slave circuit blocks 103 are used. , 104 is transferred. The master circuit block is, for example, a CPU, and the slave circuit block is, for example, a memory. The data transfer apparatus includes a shared bus 201, a crossbar 301, and control circuits 401 to 404 corresponding to each circuit block. The shared bus 201 has a decoder 202 and a bus arbiter 203.

  A series of data transfer processing (transaction) is divided into a plurality of phases (pipelines), and here, it is assumed that the data transfer processing (transaction) is divided into three phases of request, data, and response. Communication in each phase is performed independently. In the request phase, the master circuit block issues a command (command) and an address, and receives an accept (response) signal from the slave circuit block, thereby completing communication. In the data phase, the master circuit block outputs write data (transmit data to the slave) for each command issued in the request phase, and communication is completed by receiving an accept signal from the slave circuit block. In the response phase, transmission of read data (transmission data to the master) for each command issued in the request phase by the slave circuit and transmission of response information (response signal) for the command issued in the request phase are performed.

  The data transfer apparatus executes a request phase with the crossbar 301 and executes a data phase and a response phase with the shared bus 201.

  The control circuits 401 to 404 will be described. The control circuits 401 to 404 have the same configuration. Here, the control circuit 401 corresponding to the master circuit block 101 will be described as an example. FIG. 2 shows a schematic configuration of the control circuit 401. The control circuit 401 includes ports 501 to 504, a response holding circuit 601, a data holding circuit 602, a request holding circuit 603, a path branch circuit 701, a CB alignment circuit 801, and flip-flops 901 to 907. The port 501 is for connecting the circuit block 101, the port 502 is for connecting the shared bus 201, and the ports 503 and 504 are for connecting the crossbar 301. The port 503 corresponds to the circuit block 103 (control circuit 403), and the port 504 corresponds to the circuit block 104 (control circuit 404).

  The route branch circuit 701 receives a command and an address from the circuit block 101 in the request phase. Based on the received address, it is determined to which of the circuit blocks 103 and 104 the command is to be transmitted, and the command is transmitted via the corresponding port 503 or 504. In the data phase at the time of the write command, a bus use request signal is output to the bus arbiter 203 of the shared bus 201, the bus use permission signal from the bus arbiter 203 is detected, and the data output from the circuit block 101 is sent via the port 502 to the shared bus To 201. Further, a selection control signal sel2 including the order of commands output from the circuit block 101 and information on the destination is output.

  The CB alignment circuit 801 is a circuit for processing the consistency of signals input via the ports 503 and 504. For example, when signals are input simultaneously from the ports 503 and 504, the CB alignment circuit 801 is preset in the CB alignment circuit 801. In accordance with the priority of each crossbar line, simultaneously input signals are sequentially output to the request holding circuit 603 side. In addition, a selection control signal sel1 including information on the port selected for output is output.

  The response holding circuit 601, the data holding circuit 602, and the request holding circuit 603 hold the received signals for each transmission source (slave circuit block), and correspond to the order of commands output from the circuit block 101 based on the selection control signal sel2. Then, the held signal is output.

  FIG. 3 shows a schematic configuration of the path branch circuit 701. The path branch circuit 701 includes bus request control circuits 1101 and 1102, a selector 1103, an address decoder 1104, and a TR table 1105. The address decoder 1104 includes an address table 1106. The address table 1106 stores address information of the master circuit block and the slave circuit block. The address decoder 1104 receives the address transmitted from the circuit block 101 in the request phase, and the selector 1103 receives the command. The address decoder 1104 uses the address table 1106 to determine which of the slave circuit blocks 103 and 104 the received address corresponds to. Based on the determination result, the selector 1103 transmits a command to the port 503 or 504. This determination result is given to the TR table 1105, which stores the destination corresponding to the command issue order and transmits the selection control signal sel2.

  For example, commands are issued in the order of a read command from the master circuit block 101 to the slave circuit block 103 and a read command to the slave circuit block 104, and the read data from the slave circuit block 104 is more than the read data from the slave circuit block 103. When input to the control circuit 401 first, the response holding circuit 601 holds the read data from the slave circuit block 104 based on the selection control signal sel2, and reads the read data from the slave circuit block 103 first to the master circuit block 101. Output to.

  In the data phase when the command is writing, the bus request control circuit 1102 outputs a bus use request signal to the bus arbiter 203 of the shared bus 201, detects the bus use permission signal from the bus arbiter 203, and the circuit block 101 outputs it. Data is output to the shared bus 201 via the port 502.

  FIG. 4 shows a schematic configuration of the request holding circuit 603. The request holding circuit 603 includes selectors 1201 and 1202 and FIFO circuits 1203 and 1204. A FIFO circuit is provided for each crossbar, that is, for each slave circuit block. In the present embodiment, since the two circuit blocks 103 and 104 are provided as slave circuit blocks, two FIFO circuits 1203 and 1204 are provided. For example, the FIFO circuit 1203 corresponds to the port 503, and the FIFO circuit 1204 corresponds to the port 504. The selector 1201 is given a selection control signal sel1 output from the CB alignment circuit 801. The selector 1202 is given a selection control signal sel2 output from the TR table 1105. The accept signal output from the slave circuit block in the request phase is input from the corresponding port 503 or 504 and is supplied to the selector 1201 through the CB alignment circuit. The selector 1201 stores the applied accept signal in the FIFO circuit 1203 or 1204 based on the selection control signal sel1. The selector 1202 extracts a signal from the FIFO circuit 1203 or 1204 based on the selection control signal sel2, and outputs the signal to the circuit block 101 via the port 501.

  A schematic configuration of the response holding circuit 601 is shown in FIG. The response holding circuit 601 includes selectors 1301 and 1302 and FIFO circuits 1303 and 1304. A FIFO circuit is provided for each slave circuit block. In this embodiment, the FIFO circuit includes two slave circuit blocks 103 and 104, and thus has two FIFO circuits 1303 and 1304.

  In the response phase, the response holding circuit 601 receives a signal input from the shared bus 201 via the port 502, that is, a response signal, and stores it in the corresponding FIFO circuit. From the arbiter 202, bus right information including information on the source and destination of data transferred on the shared bus 201 is output, and this bus right information is input to the selector 1301 via the port 502. The selector 1301 selects a FIFO circuit based on the bus right information and outputs a signal. Further, when a read command is transmitted from the circuit block 101 in the request phase of this transaction, a read data signal output from the slave circuit block is also stored. The signal stored in the FIFO circuit is extracted by the selector 1302 based on the selection control signal sel2, and is output to the circuit block 101 via the port 501.

  A schematic configuration of the data holding circuit 602 is shown in FIG. Similar to the response holding circuit 601, the configuration includes two selectors 1401 and 1402, and two FIFO circuits 1403 and 1404. A FIFO circuit is provided for each slave circuit block. In this embodiment, the FIFO circuit includes two slave circuit blocks 103 and 104, and thus has two FIFO circuits 1403 and 1404.

  In the data phase, the data holding circuit 602 receives a signal input from the shared bus 201 via the port 502, that is, an accept signal from the slave circuit block, and stores it in the corresponding FIFO circuit. A selector 1401 selects a FIFO circuit based on the bus right information input via the port 502, and outputs a signal. In the data holding circuit 602 in the control circuit corresponding to the slave circuit block, when a write command is transmitted from the master circuit block in the transaction request phase, the data signal output from the master circuit block is also sent to the corresponding FIFO circuit. Stored. The signal stored in the FIFO circuit is extracted by the selector 1402 based on the selection control signal sel2, and is output to the circuit block via the port 501.

  Each of the flip-flops 901 to 907 is given one of clocks CLK1 to CLK3 that are asynchronous with each other. This is because the flip-flops 901 to 903 are synchronized with the circuit block 101, the flip-flops 904 and 905 are synchronized with the shared bus 201, and the flip-flops 906 and 907 are synchronized with the crossbar 301, respectively.

  In the control circuit corresponding to the master circuit block, such as the control circuit 401 or 402, the only signal received in the transaction request phase is the accept signal. If the setting is made so that the next command is not issued unless the master circuit block receives the accept signal, the request holding circuit 603 may not be provided. Further, only the accept signal is received in the data phase, and the data holding circuit 602 may not be provided. Therefore, the control circuit corresponding to the master circuit block may be configured as shown in FIG.

  In the control circuit corresponding to the slave circuit block such as the control circuits 403 and 404, since there is no signal to be received in the response phase of the transaction, the response holding circuit 601 need not be provided. In the request phase, the CB alignment circuit 801 outputs a signal sel3 including information on which port, that is, from which master circuit block the command is transmitted, to the route branch circuit 701. The route branch circuit 701 receives the information. The destination of the accept signal may be determined based on the above. Therefore, the control circuit corresponding to the slave circuit block may be configured as shown in FIG.

  With this configuration, the data transfer apparatus can execute communication in the request phase with the crossbar 301 and can execute communication in the data phase and response phase with the shared bus 201.

  Since the request phase using the crossbar 301 is executed without a bus access waiting time, the processing efficiency of each master circuit block is improved. Therefore, the data transfer efficiency is improved as compared with the bus structure constituted by the shared bus connection.

  When the request phase, data phase, and response phase signal widths are A (bit), B (bit), and C (bit), respectively, and all phases are executed in a bus structure configured by crossbar connection, (A + B + C) × Signal lines equal to the number of master circuit blocks × the number of slave circuit blocks are required. On the other hand, in the data transfer apparatus according to the present embodiment, since the data phase and the response phase are executed by the shared bus 201, the number of necessary signal lines is A × number of master circuit blocks × number of slave circuit blocks + B + C. Therefore, the number of signal lines can be reduced as compared with the bus structure configured by crossbar connection, the wiring amount can be reduced, and the circuit area, the heat generation amount, the power consumption, and the like can be reduced.

  As described above, the data transfer apparatus according to the present embodiment can improve data transfer efficiency as compared with the bus structure configured by the shared bus connection, and can reduce the wiring amount as compared with the bus structure configured by the crossbar connection.

  An example of data transfer using the data transfer apparatus according to the present embodiment is shown in FIG. Here, it is assumed that the master circuit block 101 writes data D1 to the address Ad1, reads data D2 from the address Ad2, writes data D3 to the address Ad3, and writes data D4 to the address Ad4. Data transfer is divided into three phases, a request phase, a data phase, and a response phase, and the transfer within each phase is assumed to be independent.

  First, the circuit block 101 transmits the write command Write1 to the slave circuit block corresponding to the address Ad1 via the crossbar 301, and receives the accept signal CAc1 from the slave circuit block. In the data phase, the circuit block 101 transmits the data D1 and the data valid (DataValid) signal via the shared bus 201, and receives the accept signal DAc1. With the reception of the accept signal DAc1, the value of the data valid signal is set to zero. Thereafter, the response signal Resp1 is received via the shared bus 201 in the response phase.

  After receiving the accept signal CAc1 for the write command Write1, the circuit block 101 transmits a read command Read1 as the next command to the slave circuit block corresponding to the address Ad2 via the crossbar 301, and the accept signal CAc2 from the slave circuit block. Receive. The corresponding slave circuit block prepares the data D2 to be read and outputs it together with the response signal Resp2 in the response phase.

  After receiving the accept signal CAc2 for the read command Read1, the circuit block 101 transmits the write command Write2 as the next command to the slave circuit block corresponding to the address Ad3 via the crossbar 301, and the accept signal CAc3 from the slave circuit block. Receive. In the data phase, the circuit block 101 transmits the data D3 and the data valid (DataValid) signal via the shared bus 201, and receives the accept signal DAc2. With the reception of the accept signal DAc2, the value of the data valid signal is set to zero. Thereafter, the response signal Resp3 is received through the shared bus 201 in the response phase.

  Similarly, after receiving the accept signal CAc3 for the write command Write2, the circuit block 101 transmits the next command, the write command Write3, to the slave circuit block corresponding to the address Ad4 via the crossbar 301, and from the slave circuit block. An accept signal CAc4 is received. In the data phase, the circuit block 101 transmits the data D4 and the data valid (DataValid) signal via the shared bus 201, and receives the accept signal DAc3. With the reception of the accept signal DAc3, the value of the data valid signal is set to zero. Thereafter, the response signal Resp4 is received via the shared bus 201 in the response phase.

  By transmitting the request phase communication using the crossbar 301 regardless of the progress of the data phase and the response phase, command transmission can be executed without waiting for the bus to be idle. Efficiency is improved. For example, when data is read, the data read by the slave circuit block can be prepared while the data transfer of the previous transaction is performed. Data transfer efficiency is improved.

  In the example shown in FIG. 9, the request phase signal width is 36 bits (command signal is 3 bits, address signal is 32 bits, accept signal is 1 bit), and the data phase signal width is 66 bits (data signal is 64 bits). The data valid signal is 1 bit and the accept signal is 1 bit), and the response phase signal width is 65 bits (the data signal is 64 bits and the response signal is 1 bit). Since the request phase is executed by the crossbar and the data phase and the response phase are executed by the shared bus, the signal width of the data transfer device is 36 × 2 × 2 + 66 + 65 = 275 bits. On the other hand, in the case of a bus structure configured by crossbar connection, (36 + 66 + 65) × 2 × 2 = 668 bits. Accordingly, the amount of wiring can be reduced, and the circuit area, the amount of heat generation, power consumption, and the like can be reduced.

  In the example shown in FIG. 9, the master circuit block 101 performs all four transactions. However, when the master circuit block 102 performs writing of the data D3 to the address Ad3 and writing of the data D4 to the address Ad4. The request phase processing is as shown in FIG. 10, for example.

  In FIG. 11, as a comparative example, in the bus structure constituted by the shared bus connection, the same master circuit block 101 as described above writes the data D1 to the address Ad1, reads the data D2 from the address Ad2, and the master circuit block 102. Data transfer when data D3 is written to address Ad3 and data D4 is written to address Ad4 is shown.

  In the bus structure constituted by the shared bus connection, for example, the command of the second transaction (reading of data D2 from address Ad2) after the completion of the first transaction (writing of data D1 to address Ad1) by master circuit block 101 is completed. The read command Read1 is transmitted. Then, after the completion of the second transaction of the master circuit block 101, a write command Write2 which is a command of the first transaction (writing of data D3 to the address Ad3) of the master circuit block 102 is transmitted, and after the completion of this transaction, the second transaction is transmitted. The write command Write3 which is a command of the transaction (write data D4 to the address Ad4) is transmitted.

  In a bus structure constituted by shared bus connections, processing efficiency is not good because another master circuit block transmits a command after the pipeline processing (transaction) of one master circuit block is completed.

  As described above, the data transfer device according to the present embodiment can improve data transfer efficiency than the bus structure configured by the shared bus connection, and can reduce the wiring amount than the bus structure configured by the crossbar connection. Circuit area, heat generation, power consumption, and the like can be reduced.

  Each of the above-described embodiments is an example and should be considered not restrictive. For example, in the above embodiment, the request phase is executed by the crossbar 301 and the data phase and the response phase are executed by the shared bus 201. However, the request phase and the data phase are executed by the crossbar 301 and the response phase is executed by the shared bus 201. You may make it perform by 201. In that case, the control circuit included in the data transfer apparatus has a configuration as shown in FIG. In the data phase, the path branch circuit 701 transmits the signal received via the port 501 to the port 503 or 504, and the signal received via the port 503 or 504 is connected to the CB alignment circuit 801. To store. Since the data phase is executed by the crossbar, the wiring amount is increased as compared with the data transfer device of the above embodiment, but the transfer efficiency can be improved.

  In the example shown in FIG. 9, the transfer in each phase is assumed to be independent, but the transfer completion condition in the upper phase is not controlled by the transfer status in the lower phase, that is, the data phase lower than the request phase. The protocol may be such that the transfer status in the response phase is not considered in the request phase.

  In the above embodiment, the data transfer is divided into three phases of request phase, data phase, and response phase, but the number of divided phases may not be three. In that case, a holding circuit corresponding to each phase is provided in the control circuit. Whether each phase is executed by the shared bus or the crossbar can be determined from the setting conditions of the processing efficiency and the wiring amount.

  The technical scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic configuration diagram of a data transfer device according to an embodiment of the present invention. It is a schematic block diagram of the control circuit in the data transfer apparatus by the embodiment. It is a schematic block diagram of the path branch circuit in the control circuit included in the data transfer apparatus according to the embodiment. It is a schematic block diagram of the request holding circuit in the control circuit included in the data transfer apparatus according to the embodiment. It is a schematic block diagram of the response holding circuit in the control circuit included in the data transfer apparatus according to the embodiment. It is a schematic block diagram of the data holding circuit in the control circuit included in the data transfer apparatus according to the embodiment. It is a schematic block diagram of the control circuit in the data transfer apparatus by the embodiment. It is a schematic block diagram of the control circuit in the data transfer apparatus by the embodiment. It is a figure which shows the timing chart of the data transfer by the embodiment. It is a figure which shows another example of the timing chart of the data transfer by the embodiment. It is a figure which shows the timing chart of the data transfer by a comparative example. It is a schematic block diagram of the control circuit in the data transfer apparatus by a modification.

Explanation of symbols

101, 102 Master circuit block 103, 104 Slave circuit block 201 Shared bus 301 Crossbar 401-404 Control circuit

Claims (5)

A data transfer device for transferring data between n (n is an integer of 1 or more) master circuit blocks and m (m is an integer of 1 or more) slave circuit blocks,
N first control circuits each communicating with the corresponding master circuit block;
M second control circuits each communicating with the corresponding slave circuit block;
A shared bus connected to the first control circuit and the second control circuit;
a crossbar portion connecting between each of the n first control circuits and the m second control circuits;
With
The first control circuit and the second control circuit include a command signal that the master circuit block transmits to the slave circuit block and a command that the slave circuit block transmits to the master circuit block upon receiving the command signal. A response signal is transferred via the crossbar unit, and a write data signal transmitted from the master circuit block to the slave circuit and a read data signal transmitted from the slave circuit block to the master circuit block are transmitted via the shared bus. A data transfer apparatus for transferring data. The first control circuit includes:
A first port connected to the master circuit block;
A second port connected to the shared bus;
M third ports connected to the crossbar portion;
An address table for storing address information of each of the master circuit block and the slave circuit block; an instruction signal transmitted from the master circuit block; an address signal transmitted from the master circuit block together with the instruction signal; and Transmit to one of the m third ports determined to correspond to the address signal by collating with an address table, and transmit a write data signal transmitted from the master circuit block to the second port A route branch circuit;
A response holding circuit for storing a read data signal received via the second port and transmitting the read data signal to the master circuit block via the first port;
The data transfer apparatus according to claim 1, further comprising: The second control circuit includes:
A first port connected to the slave circuit block;
A second port connected to the shared bus;
N third ports connected to the crossbar portion;
A request holding circuit for storing a command signal received via the third port and transmitting the command signal to the slave circuit block via the first port;
A data holding circuit for storing a write data signal received via the second port and transmitting the write data signal to the slave circuit block via the first port;
The slave circuit block transmits the command response signal transmitted when the command signal is received to the third port to which the command signal is input, and the read data signal transmitted by the slave circuit block is transmitted to the second port. A route branching circuit to transmit to the port;
The data transfer apparatus according to claim 1, further comprising:   4. The data transfer according to claim 3, wherein the request holding circuit has n FIFOs, and each FIFO stores the command signal received through the corresponding n third ports. apparatus. A data transfer device for transferring data between n (n is an integer of 1 or more) master circuit blocks and m (m is an integer of 1 or more) slave circuit blocks,
N first control circuits each communicating with the corresponding master circuit block;
M second control circuits each communicating with the corresponding slave circuit block;
A shared bus connected to the first control circuit and the second control circuit;
a crossbar portion connecting between each of the n first control circuits and the m second control circuits;
With
The first control circuit and the second control circuit are configured such that the master circuit block receives the command signal, the write data signal, and the slave circuit block that the master circuit block transmits to the slave circuit block. A data transfer apparatus, wherein a command response signal to be transmitted to the master circuit block is transferred via the crossbar unit, and a read data signal to be transmitted from the slave circuit block to the master circuit block is transferred via the shared bus.

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