JP2008148327A - Shift register circuit, shift clock generating circuit and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a shift register circuit capable of preventing leakage of data, without the increase in noise-mixing, and of generating selection signals with accurate timing, and to provide a shift clock generating circuit and an image processor. <P>SOLUTION: The shift register circuit comprises a plurality of data transfer elements 81, provided with an input-side transfer gate which is turned on by a first shift clock to fetch the data and an output-side transfer gate which is turned on, after the input-side transfer gate is turned off by a second shift clock and is turned off, before the input-side transfer gate is turned on, to output the data fetched via the input-side transfer gate in the on period; and a means for making the selection signals output from the data transfer elements 81 of respective stages, by cascade-connecting the plurality of data transfer elements 81 and supplying the first and second shift clocks, to the plurality of data transfer elements 81. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a shift register circuit, a shift clock generation circuit, and an image processing apparatus suitable for driving a cell of an image sensor.

  Semiconductor image sensors are used in various image input devices. Recently, the threshold voltage modulation MOS type solid-state imaging device has high performance image quality of CCD (Charge Coupled Device) and low power consumption of CMOS. It is attracting attention as a way to reduce costs.

  A technique of a threshold voltage modulation type MOS solid-state imaging device is disclosed in, for example, Japanese Patent Application Laid-Open No. 11-195778. In a threshold voltage modulation type MOS solid-state imaging device, an image signal based on the photogenerated charges accumulated in the carrier pocket of each pixel is taken out by repeating the three states of initialization, accumulation and readout. The period of the initialization state is a period for discharging residual charges from the carrier pocket. The accumulation state period is a period during which charges are accumulated in the sensor cell. The period of the read state is a period in which the accumulated charge amount is read out by voltage modulation.

  In this type of image sensor, sensor cells are arranged in a matrix, selected for each column, and initialized and read. Then, the pixel information of the read sensor cells for one column is temporarily stored in the line memory, and the image output is obtained by selecting and reading one pixel at a time from the line memory.

  In order to drive the sensor cells arranged in a matrix in the horizontal direction and the vertical direction, and to read from the line memory, a drive sensor column (row) and a shift register for selecting a read memory are employed.

  The shift register is configured by cascading a plurality of DFFs (data flip-flops). The DFF takes in the signal input to the data terminal D by the clock CK input to the clock terminal CK, and outputs it from the output terminals Q and Q1 by the inverted clock XCK input to the inverted clock terminal XCK. By providing the output of the output terminal Q1 to the data terminal D of the next stage DFF, the signal input to the first stage DFF can be taken out as the selection signal output of each stage while being sequentially transferred to the next stage DFF. The selection signal output of each stage is used as a selection signal for sequentially selecting each stage of the drive sensor column (row) and readout memory.

Japanese Patent Laid-Open No. 11-195778

  By the way, as a shift clock for driving the shift register, a one-phase clock of the clock CK and its inverted signal XCK is used.

  Each DFF has CMOS switches on the input side and output side. The CMOS switch on the input side is turned on at the falling edge of the clock CK (the rising edge of the inverted signal XCK) and turned off at the rising edge. The CMOS switch on the output side is turned on at the rising edge of the clock CK (falling edge of the inverted signal XCK) and turned off at the falling edge. When the CMOS switch on the input side is turned on at the falling edge of the clock CK (the rising edge of the inverted signal XCK), data is captured and held. When the CMOS switch on the input side is turned off and the CMOS switch on the output side is turned on at the rising edge of the clock CK (falling edge of the inverted signal XCK), the captured data is transferred to the output side and held, and the output terminal Q , Q1.

  However, the waveform of the clocks CK and XCK may be lost due to the limitation of the transmission band, noise mixing, etc., and the time of the intermediate potential from the start of the waveform rise and fall until the threshold level is exceeded becomes longer. There is. That is, the time required for switching the high (H) level / low (L) level of the shift clock becomes long, and the output side CMOS switch is turned on before the input side CMOS switch is turned off. is there. In other words, all the CMOS switches in the shift register are turned on, and data is sequentially transmitted through the DFF (data cylinder omission) regardless of the clock timing, and a selection signal is output at a normal timing from each stage. It becomes impossible to do.

  Therefore, a method of speeding up the H / L switching of the shift clock (tr / tf (rising / falling) sharply) can be considered. By increasing the driving capability of the clock driver, a shift clock having steep tr / tf characteristics can be generated.

  However, if the driving capability of the clock driver is increased to switch the clock H / L in a short time, the level of noise generated with the shift clock H / L switching also increases. The generated noise has an adverse effect on the pixel readout signal line of the sensor, and there is a problem that a large level of noise is mixed in the output image data.

  SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and a shift register circuit and a shift clock capable of generating a selection signal at an accurate timing by preventing data from being missed without increasing noise contamination. An object is to provide a generation circuit and an image processing apparatus.

  The shift register circuit according to the present invention includes an input-side transfer gate that is turned on by a first shift clock and captures data, and is turned on after the input-side transfer gate is turned off by a second shift clock and the input-side transfer gate. A plurality of data transfer elements comprising: an output-side transfer gate that is turned off before the gate is turned on and outputs data taken in through the input-side transfer gate during the on-period; and And a means for outputting a selection signal from the data transfer elements in each stage by supplying the first and second shift clocks to the plurality of data transfer elements in a cascade connection.

  According to such a configuration, the input-side transfer gate is turned on by the first shift clock and takes in data. After the input side transfer gate is turned off, the output side transfer gate is turned on by the second shift clock, and the data taken in via the input side transfer gate is output. Since the input-side transfer gate and the output-side transfer gate are not turned on at the same time, the data does not pass through a plurality of cascade-connected data transfer elements, and a selection signal is sent from the data transfer element at each stage at a normal timing. Is output. Therefore, it is not necessary to make the switching between the first and second shift clocks steep in order to prevent the data from falling off the cylinder, and it is possible to prevent an increase in noise generated when the clock is generated and to prevent an increase in noise mixing. .

  The input-side transfer gate and the output-side transfer gate are turned on and off by the first shift clock and its inverted signal, and the second shift clock and its inverted signal.

  According to such a configuration, the input-side transfer gate and the output-side transfer gate are turned on and off by the first shift clock and its inverted signal and the second shift clock and its inverted signal. Thereby, reliable data transfer is possible, and a selection signal with an accurate timing can be obtained.

  Further, the first shift clock and the second shift clock are clocks having different phases, and the logic level does not change at the same time.

  According to such a configuration, the input-side transfer gate and the output-side transfer gate are turned on and off when the logic level of the first or second shift clock changes. Since the first and second clocks have different phases and their logic levels do not change at the same time, the input-side transfer gate and the output-side transfer gate cannot be turned on simultaneously. As a result, a selection signal can be obtained from the data transfer element at each stage at a normal timing.

  The input-side and output-side transfer gates are turned on at one polarity logic level of the first and second shift clocks and turned off at the other polarity logic level, and the first and second shift clocks are The other shift clock ends the one-polar logic level period within a period in which the other shift clock is at the other-polar logic level.

  According to such a configuration, the input-side transfer gate is turned on by the one polarity of the first shift clock. When the first shift clock has one polarity, the second shift clock has the other polarity, and one polarity of the first clock ends during the other polarity period of the second shift clock. Therefore, the output side transfer gate is turned on after the input side transfer gate is turned off. Similarly, the input-side transfer gate is turned on after the output-side transfer gate is turned off. In this way, data omission is prevented.

  The shift clock generation circuit according to the present invention is a clock having a phase different from that of the means for generating the first shift clock synchronized with the input clock and the first shift clock, and the logic level does not change at the same time. Means for generating a second shift clock.

  According to such a configuration, the first shift clock is synchronized with the input clock. The second shift clock has a phase different from that of the first shift clock, and the logic level does not change at the same time. Therefore, by supplying these first and second shift clocks to, for example, the input side and output side transfer gates of the data transfer element, the input side and output side transfer gates can be prevented from being turned on simultaneously.

  Further, the first and second shift clocks are characterized in that one shift clock ends a logic level period of one polarity within a period in which one shift clock has a logic level of the other polarity.

  According to such a configuration, since the logic level of one polarity ends in the period of the logic level of the other polarity of the other clock, the action due to the logic level of one polarity and the action due to the logic level of the other polarity are temporally separated. Can be made.

  An image processing apparatus according to the present invention controls driving of image cells arranged in a matrix using a selection signal from the shift register circuit.

  According to such a configuration, since the shift register circuit prevents the data from coming off the cylinder, the image cell can be reliably driven. In addition, the mixing of noise does not increase in order to prevent data loss.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a shift register circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific configuration of the DFF in FIG. FIG. 3 is a circuit diagram showing a shift clock generating circuit for supplying a shift clock to the shift register circuit of FIG. 4 is a circuit diagram showing an image sensor LSI using the shift register circuit of FIG. 1, and FIG. 5 is a block diagram showing an image processing apparatus in which the image sensor of FIG. 4 is incorporated. 6 is a circuit diagram showing the configuration of the drain / gate voltage supply circuit, FIG. 7 is a circuit diagram showing the configuration of the source voltage supply circuit, and FIG. 8 is a diagram for explaining the bias voltage applied to the sensor cell. FIG. 9 is a diagram for explaining the readout line and the clear line of the sensor. FIG. 10 is a timing chart showing the timing of the vertical synchronization signal and the horizontal synchronization signal. FIG. 11 is a timing generator of the image sensor LSI. FIG. 12 is a timing chart for explaining the state of each signal in each state during the H blanking period.

  In this embodiment, as a shift clock of the shift register circuit, a two-phase clock that switches H / L in a complementary manner and an inverted clock thereof, and the clocks of each phase (inverted clocks) are not synchronized with each other. By using a signal that is not switched between H / L, the occurrence of missing data cylinders is prevented.

First, an image sensor and an image processing apparatus using the shift register circuit of FIG. 1 will be described with reference to FIGS.
FIG. 5 is a block diagram showing a configuration of an image processing apparatus including an image sensor LSI (large scale integrated circuit) 1 that is a solid-state imaging device and a signal processing LSI 2 that is a signal processing apparatus. The image sensor LSI 1 is a two-dimensional solid-state imaging device, photoelectrically converts an optical image, and supplies a pixel signal based on the optical image to the signal processing LSI 2.
The signal processing LSI 2 performs predetermined signal processing on each received pixel signal and outputs an image signal.

  The image sensor LSI 1 includes a sensor cell array 3, a clear line shift register 4, a read line shift register 5, a vertical drive circuit 6, a booster circuit 7, a regulator 8, a storage signal line memory 9, and an offset. A signal line memory 10, a horizontal shift register 11, an output amplifier 12, and a timing generator 13 are included. The timing generator 13 includes a register 14 and a 3-wire serial interface 15. In the clear shift register 4, the read line shift register 5, and the horizontal shift register 11, the shift register circuit of FIG. 1 described later is used.

  The sensor cell array 3 of the image sensor LSI 1 is a threshold modulation type solid-state imaging device as described in, for example, Japanese Patent Application Laid-Open No. 11-195778. Various control signals are supplied from the timing generator 13 to each circuit, and based on the various control signals, the sensor cell array 3 outputs a pixel signal corresponding to the amount of light received by each cell. The sensor cell array 3 includes, for example, a 640 × 480 cell and a region (OB region) for optical black (OB). Including the OB region, the sensor array 3 is composed of, for example, 712 × 500 cells. Then, the image sensor LSI 1 supplies the signal processing LSI 2 with two output signals, that is, a voltage output signal VOUTS corresponding to the amount of received light and a voltage output signal VOUTN corresponding to the offset component.

  The vertical drive circuit 6 is a circuit for selecting a read line and a clear line. The read line shift register 5 and the clear line shift register 4 are circuits for designating the read line and the clear line, respectively.

  The regulator 8 is a voltage generation circuit for generating various voltages required in the image sensor LSI 1. As will be described later, the booster circuit 7 is a circuit for boosting the voltage supplied from the regulator 8 in order to give a necessary voltage to the sensor cell array 3. A more detailed description of the image sensor LSI 1 will be described later with reference to FIG.

  The signal processing LSI 2 includes a differential amplifier circuit 16, an optical black (hereinafter abbreviated as OB) clamp circuit 17, a programmable gain amplifier circuit (PGA) 18, an analog-digital conversion circuit (ADC) 19, and an OB control logic circuit. 20, a luminance control logic circuit 21, a luminance photometry logic circuit 22, a register 23, an image processor 24, a sequencer 25, and a timing generator 26. The register 23 stores data such as shutter speed data.

Two analog signals VOUTS and VOUTN from the image sensor LSI 1 are input to the differential amplifier circuit 16. The differential amplifier circuit 16 of the signal processing LSI 2 amplifies the difference between the voltage value of the signal component and the offset component, and outputs the differential voltage to the OB clamp circuit 17.
The OB clamp circuit 17 is a circuit for setting the black level of the input pixel signal to an appropriate level of black. Cells for a predetermined number of pixels in the sensor cell array 3, that is, the OB region, are shielded by a light shielding plate or the like. Based on the signal level of the shielded cell, an appropriate pixel signal for the effective pixel region is appropriately selected. Black level adjustment is performed.

The PGA 18 is an amplifier for adjusting the gain in units of 1 decibel, for example. The signal amplified by the PGA 18 is supplied to the ADC 19. The ADC 19 converts the output of the PGA 18 into a digital signal.
For the pixels in the OB area, luminance data of the pixels is supplied from the ADC 19 to the OB control logic circuit 20 as a digital signal. The OB control logic circuit 20 receives a signal from the ADC 19 based on a control signal from the timing generator 26, and outputs a control signal to the OB clamp circuit 17 in order to adjust the black level.

Similarly, the luminance photometry logic circuit 22 measures luminance based on, for example, data of all green (G) pixels in one frame supplied from the ADC 19 and supplies the luminance data to the luminance control logic 21. .
The luminance control logic circuit 21 adjusts the brightness of the image by supplying a gain control signal to the PGA 18 based on the luminance data supplied from the luminance photometry logic circuit 22. Further, the luminance control logic circuit 21 writes the shutter speed data to the register 23.

  Since the register 14 and the register 23 store the same data, when the contents of one register are changed, the contents of the other register are also changed via the 3-wire serial interface 15. The Therefore, when the shutter speed data is written in the register 23 in the signal processing LSI 2, the data is further transferred to and written in the register 14 in the image sensor LSI 1 via the 3-wire serial interface 15. In the image sensor LSI 1, a focal plane shutter is set based on shutter speed data. The function of the focal plane shutter will be described later.

  For example, the image sensor LSI 1 controls the focal plane read line and clear line width dl based on shutter speed data. When the exposure time is shortened as in the case where the image is bright, the control is performed so that the width dl is narrowed, that is, the number of lines between the readout line and the clear line is decreased. Further, when the exposure time is increased as in the case where the image is dark, the control is performed so as to increase the width dl, that is, increase the number of lines between the readout line and the clear line. Further, when the exposure is not appropriate only by controlling the shutter speed, the luminance control logic circuit 21 controls the signal amount to be appropriate by adjusting the signal gain.

  A system clock signal CLKIN is supplied to the signal processing LSI 2, and the timing generator 26 generates various timing signals based on the system clock signal CLKIN. The signal processing LSI 2 supplies various synchronization signals from various timing signals to the image sensor LSI 1. As the synchronization signals, there are a sensor drive clock signal SCLK, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HSYNC. The image sensor LSI 1 synchronizes based on these synchronization signals and supplies the image signal to the signal processing LSI 2. Accordingly, the SCLK, VSYNC, and HSYNC signals depend on the system clock signal CLKIN.

Various parameters, for example, parameters for making the whole or part bright, etc., are input to the register 23 of the signal processing LSI ² via an I ² C-Bus (Isquare Seabus) I / F and stored. The
In the signal processing LSI 2, the image processor 24 is a circuit for generating an image based on RGB signals, and the sequencer 25 is a circuit for driving the image processor 24.

  A clock designation signal CLK_SEL is further input to the timing generator 13 of the image sensor LSI 1. CLK_SEL is a signal for explicitly instructing the image sensor LSI 1 to specify the clock frequency at which the image sensor LSI 1 is operated, that is, inputting a clock high / low instruction to the image sensor LSI 1 as a control signal. Based on CLK_SEL, the timing generator 13 changes the output timing of various control signals. Further, the standby signal STANDBY is input to the timing generator 13.

Data such as shutter speed, regulator voltage setting, and scan direction designation are input to the register 14 of the image sensor LSI 1 via the 3-wire serial interface 15 and stored.
Further, the image sensor LSI 1 supplies a valid signal VALID as one control signal to the timing generator 26 of the signal processing LSI 2. VALID is a signal indicating that valid image data is output from the image sensor LSI 1. When this signal is active, the signal processing LSI 2 can know that valid image data is output from the image sensor LSI 1 and can be used for photometry.

Next, the configuration of the image sensor LSI 1 will be described. FIG. 4 is a circuit diagram showing a configuration of the image sensor LSI 1.
The sensor cell array 3 is a matrix solid-state imaging device composed of m × n (m rows and n columns) cells S11 to Smn. One cell corresponds to one unit pixel. Each cell corresponding to each unit pixel includes a photodiode PDS and a MOS transistor PDTr which is an insulated gate field effect transistor for detecting an optical signal.
The photodiode PDS includes an impurity diffusion region and a well region, and holes are generated in the well region in response to incident light. The well region is shared with the optical signal detection MOS transistor PDTr, and constitutes the gate region of the optical signal detection MOS transistor PDTr. The impurity diffusion region of the photodiode PDS and the drain diffusion region of the optical signal detection MOS transistor PDTr are integrally formed on the surface layer of the well region. The drain diffusion region is formed so as to surround the outer periphery of the ring-shaped gate electrode. A source diffusion region is formed at the center of the ring-shaped gate electrode. A carrier pocket is formed in the well region under the gate electrode and around the source diffusion region so as to surround the source diffusion region. Details of the sensor structure are described in JP-A-11-195778.

  In order to obtain a signal corresponding to the amount of light from the sensor cell array 3, by applying a predetermined bias voltage to the gate, source, and drain of each cell in each of the three states of accumulation, reading, and clear, the amount corresponding to the amount of light A signal can be obtained. In short, in the accumulation state, holes generated according to the amount of light incident on the photodiode PDS are accumulated in the carrier pocket. In the read state, the signal voltage is read based on the accumulated holes. The read signal voltage is a voltage signal corresponding to the difference between the gate voltage and the threshold value that changes according to the amount of received light. In the clear state, the booster circuit 7 boosts the source voltage of the optical signal detection MOS transistor PDTr to a predetermined value, and the gate voltage is also boosted to a predetermined value by the coupling capacitance between the ring gate and the source. The signal detection MOS transistor PDTr is turned on, and a channel is formed under the ring gate. Therefore, the drain voltage becomes substantially equal to the source voltage (when the drain voltage VD = VG−Vth and the gate voltage VG is sufficiently higher than the source voltage), and the drain voltage is accumulated by spreading the depletion layer under the source, channel, and drain. The holes are swept toward the substrate, and residual charges such as holes are discharged. After clearing, the image signal can be obtained by reading the offset voltage including the noise component and taking the difference between the signal voltage and the offset voltage. A two-dimensional image signal can be obtained by performing the above-described operation for each cell and obtaining an image signal. The bias conditions, that is, the bias voltages of the gate, source, and drain of each cell in each state will be described later.

  The clear line shift register 4 is a circuit for designating a line to be cleared. The clear line shift register 4 receives the clear line shift data AV, the clear line shift clock signal VCLK_ASR, and the clear line shift register reset signal VSFRA_RST. The clear line shift register 4 outputs clear line selection signals VSA1 to VSAm for selecting a line for clearing accumulated charges in the matrix sensor cell array 3.

  The read line shift register 5 is a circuit for designating a read line. Read line shift register 5 receives read line shift data BV, read line shift clock signal VCLK_BSR, and read line shift register reset signal VSFRB_RST. The read line shift register 5 outputs read line selection signals VSB1 to VSBm for selecting a line from which a signal voltage is read out in the matrix sensor cell array 3.

  When the clear line shift data AV and the read line shift data BV are given at the output timing determined based on the shutter speed data, the clear line shift register 4 and the read line shift register 5 are selected in order. Output a signal. That is, the read line shift data BV is generated at a predetermined timing with respect to the vertical synchronization signal VSYNC, but the phase relationship between the read line shift data BV and the clear line shift data AV is determined by the shutter speed. The clear line shift register 4 and the read line shift register 5 sequentially output selection signals while maintaining the phase relationship. As will be described later, when a readout line and a clear line exist in one frame, two lines in the sensor array are designated and selected.

  The vertical drive circuit 6 includes, for each line, two AND circuits 31, 32, an OR circuit 33, a buffer circuit 34, and a drain / gate voltage supply circuit VC1i (i is any one of 1 to m. The same). One AND circuit 31 receives a clear line selection signal VSAi and a clear line selection enable signal CLS as inputs. The other AND circuit 32 receives a read line selection signal VSBi and a read line selection enable signal VSM for three operations of signal read, clear, and noise read. The OR circuit 33 receives the output signals of the AND circuits 31 and 32 and the all-line selection signal VGUP during storage. The buffer circuit 34 receives the output signal from the OR circuit 33 as an input. The output signal of each buffer circuit 34 is supplied as a line selection signal VSCi to the drain / gate voltage supply circuit VC1i.

  In addition to the line selection signal VSCi, an accumulation enable signal SDI, a read enable signal SDR2, and a clear pulse signal CL are input to the drain / gate voltage supply circuit VC1i. The drain / gate voltage supply circuit VC1i selects and outputs a voltage to be applied to the gates and drains of all cells in the corresponding line. That is, the drain / gate voltage supply circuit VC1i supplies the drain voltage VPDi and the gate voltage VPGi to each cell of each line. Details of the drain-gate voltage supply circuit VC1i will be described later.

  A source voltage supply circuit VC2h (h is any one of 1 to n, hereinafter the same) is provided for each column of the matrix. A clear pulse signal CL and a pre-clear gate preset signal PR are input to the source voltage supply circuit VC2h. The source voltage supply circuit VC2h supplies the source voltage VPSh to the sources of all the cells in each column. Details of the source voltage supply circuit VC2h will be described later.

A source line corresponding to each column is connected to the storage signal line memory 9 and the offset signal line memory 10 via a switch SW1h to which a line memory data load signal LOAD is input.
The accumulation signal line memory 9 includes a selection circuit HSh corresponding to each column. Each selection circuit HSh includes a charge storage capacitor C2, a read switch SW21, a reset switch SW22, and an output switch SW23.

  The offset signal line memory 10 includes a selection circuit HNh corresponding to each column. Each selection circuit HNh includes a charge storage capacitor C3, a read switch SW31, a reset switch SW32, and an output switch SW33. When the storage signal line memory data load signal LOADS is input to the storage signal line memory 9, the SW21 is turned on, and a voltage corresponding to the amount of light is applied from each source line to the capacitor C2, and the capacitor C2 receives the voltage. Charges corresponding to the voltage are accumulated. The pixel signals for one line selected by the read line shift register 5 are stored in the accumulation signal line memory 9 in accordance with LOADS.

  The accumulated signal line memory reset signal RESS to the accumulated signal line memory 9 is a signal for setting the capacitor C2 to a predetermined voltage VMPR immediately before signal reading. The voltage VMPR is supplied from the power source 35 generated by the regulator 8 to the capacitor C2 by turning on the reset switch SW22.

  Then, according to the selection signal HSCANh from the horizontal shift register 11, the switches SW23 of the selection circuits HSh of the storage signal line memory 9 are sequentially turned on. Since the turned-on SW 23 outputs a voltage corresponding to the electric charge accumulated in the capacitor C2, one line of pixel signals selected by the read line shift register 5 is sequentially output as a VOUTS signal via the output amplifier 36. Is output.

  When the offset component accumulation signal line memory data load signal LOADN is input to the offset signal line memory 10, the switch SW31 is turned on, and a voltage corresponding to the offset component is applied from each source line, and the capacitor C3 is supplied. Charges corresponding to the voltage are accumulated. The pixel signals for one line selected by the read line shift register 5 are stored in the offset signal line memory 10 in accordance with the offset component accumulation signal line memory data load signal LOADN. The offset signal line memory reset signal RESN to the offset signal line memory 10 is a signal for setting the capacitor C3 to a predetermined voltage VMPR immediately before reading the offset component signal. The voltage VMPR is supplied from the power source 37 generated by the regulator 8 to the capacitor C3 by turning on the reset switch SW32.

  The horizontal shift register 11 sequentially turns on the switches SW33 of the selection circuits HNh of the offset signal line memory 10. Since the turned-on SW 33 outputs a voltage corresponding to the electric charge accumulated in the capacitor C3, an offset component signal of the pixel signal of one line selected by the read line shift register 5 is sequentially output as a VOUTN signal. It is output via the amplifier 38. Two voltage analog signals VOUTS and VOUTN from the image sensor LSI 1 are input to the differential amplifier circuit 16 of the signal processing LSI 2.

  FIG. 6 is a circuit diagram showing the configuration of the drain / gate voltage supply circuits VC11 to VC1m of FIG. The drain / gate voltage supply circuit VC1i includes a NAND circuit, an inverter circuit, and a transistor, and outputs a drain voltage VPD and a gate voltage VPG according to various input signals.

  Each drain / gate voltage supply circuit VC1i receives a clear pulse signal CL, an accumulation enable signal SDI and a read enable signal SDR2, and uses the supplied voltages of VCCSGHR, VCCSGHI, VCCSDR and VCCSDI, which will be described later. Are applied to the drain and gate of each sensor cell.

  The sensor cell array 3 has the following state. Each of these states is specifically “accumulation”, “reset (S)”, “modulation (S)”, “preset”, “clear”, “reset (N)” and “modulation (N)”. Each state is included, and an optical image is converted into an electrical signal and output by repeating these states. The accumulation enable signal SDI is a low active signal and is a signal indicating an accumulation period. The read enable signal SDR2 is a signal generated based on the signal SDR indicating a period other than the accumulation period, and is a signal that becomes low active during modulation, offset modulation, and clearing. The line selection signal VSCi is used to select a read line and a clear line, and the clear pulse signal CL is set to a period for discharging residual charges such as accumulated holes.

  In FIG. 6, it is assumed that the clear pulse signal CL is at L level and the line selection signal VSCi is at H level. In this case, the PMOS transistor T1 and the NMOS transistor T2 are turned on, and the PMOS transistor T3 is turned off. Then, the gate voltage VPGi becomes the voltage VCCSGHI or the voltage VCCSGHR. The PMOS transistor T1 is an enhanced type and the NMOS transistor T2 is a depletion type MOS transistor.

  Conversely, when the clear pulse signal CL is at the H level and the line selection signal VSC is at the L level, the transistors T1 and T2 are turned off and the transistor T3 is turned on. In this case, the gate voltage VPGi is a low level voltage. When the clear pulse signal CL and the line selection signal VSCi are at the H level, the transistors T1, T2, and T3 are turned off and the gate is in a floating state.

  When the clear pulse signal CL is at L level or the line selection signal VSC is at L level, the NMOS transistor T5 is turned on. The sources of the transistors T5 in each line are commonly connected to form a COM node. When the transistor T5 is on, the drain of each line is connected to the COM node and enters a floating state. When the transistor T5 is on and the accumulation enable signal SDI is at the L level, the PMOS transistor T6 and the NMOS transistor T7 are also turned on, and the drain voltage VPDi becomes the voltage VCCSDI. When the transistor T5 is on and the read enable signal SDR2 becomes L level, the PMOS transistor T4 is also turned on and the drain voltage VPDi becomes the voltage VCCSDR. Further, when only the transistor T5 is in the on state among the transistors T4 to T7, all the drains are connected to the floating COM node and become HiZ.

  The transistor T1 is supplied with the voltage VCCSGHI when the accumulation enable signal SDI is at the L level, and is supplied with the voltage VCCSGHR when the signal SDR is at the L level.

That is, the circuit of FIG. Table 1 shows only the H level and L level of the signal of interest.
(Table 1)
VSCi CL SDI SDR2 VPGi
L L L (GND)
L H L (GND)
H L L VCCSGHI
H L L VCCSGHR
H H Floating VSCi CL SDI SDR2 VPDi
L L VCCSDI
L L VCCSDI
L L VCCSDR
L L VCCSDR
L H H HiZ
FIG. 7A is a circuit diagram showing a configuration of the source voltage supply circuits VC21 to VC2n of FIG. The source voltage supply circuit VC2h includes a capacitor and a transistor, and outputs a source voltage VPSh according to various input signals.
FIG. 7B shows a circuit for generating the signals S1, S2, S3 and S4 in FIG.
Each source voltage supply circuit VC2h receives the inverted signals S1 to S3 of the clear pulse signal CL and the normal rotation signal S4 of the preset signal PR, and uses the supplied VCCCSDB and VCCVPS to generate the SOURCE bias voltage of FIG. Is applied to the source of each sensor cell.

  In FIG. 7B, signals S1 to S3 are inverted signals of the clear pulse signal CL, and the normal rotation signal S4 of the preset signal PR is a signal having the same logic level as the pre-clear gate preset signal PR. When the clear pulse signal CL and the pre-clear gate preset signal PR are both at the L level, the inverted signals S1 to S3 are at the H level, and the normal rotation signal S4 of the preset signal PR is at the L level. Therefore, the NMOS transistors T11 and T13 are on, the PMOS transistors T12 and T14 are off, and the NMOS transistor T15 is off. That is, in this case, since the transistors T14 and T15 are off, the source voltage supply circuit VC2h does not supply the source voltage. At this time, the voltage value at the ND1 point is the ground level (GND), and the voltage value at the ND2 point is VCCSDB.

  When the clear pulse signal CL is at L level and the pre-clear gate preset signal PR is at H level, the inverted signals S1 to S3 and the normal signal S4 of the preset signal PR are at H level. Therefore, the transistors T11, T13, T15 are on, and the transistors T12, T14 are off. That is, in this case, the source voltage VPSh is the voltage VCCVPS, the voltage value at the ND1 point is the ground level (GND), and the voltage value at the ND2 point is VCCSDB. During this time, therefore, the capacitor C1 is charged to the voltage VCCSDB.

  When the clear pulse signal CL is at the H level and the pre-clear gate preset signal PR is at the L level, the inverted signals S1 to S3 and the normal signal S4 of the preset signal PR are at the L level. Therefore, the transistors T11, T13, T15 are off, and the transistors T12, T14 are on. That is, in this case, the voltage at the point ND2 becomes the source voltage VPSh. If the voltage of the capacitor C1 is charged to VCCSDB immediately before this case, the ND1 point becomes the voltage VCCCSDB by turning on the transistor T12, and the voltage value at the ND2 point becomes VCCSDB × 2.

That is, the circuit of FIG.
(Table 2)
CL PR VPSh
(1) Do not supply L L voltage (2) L H VCCVPS
(3) VCCSDB × 2 immediately after the state of H L (2)
FIG. 8 is a diagram for explaining the bias voltage applied to the sensor cell.
FIG. 8 shows voltage values of the gate voltage, the source voltage, and the drain voltage of each cell in each state. In FIG. 5, from the viewpoint of the bias voltage, “accumulation”, “reset (S)”, “modulation (S)”, “preset”, “clear”, “reset (N)”, and “modulation (N)”. Each state is shown separately.

  In FIG. 8, GATE is the gate voltage of the cell and has two states, a selected state and a non-selected state. SOURCE is the cell source voltage. DRAIN is a cell drain voltage and has two states, a selected state and a non-selected state.

First, the case of the accumulation state will be described.
In the “accumulation” state (hereinafter referred to as the accumulation state), all cells in the cell array are selected, and a voltage having a voltage value of VCCSGHI is applied to the gate. When stored, there are no unselected cells. In the accumulation state, the source is not supplied with the bias voltage from the source voltage supply circuit VC2h, but the VCCSGHI voltage is applied to the gate, and the optical signal detection MOS transistor PDTr is turned on. In the accumulation state, the source becomes equal to the drain voltage (VCCSDI).

Next, the case of the “reset (S)” state (hereinafter abbreviated as RESS state) will be described.
In the case of a cell in a selected state, a voltage having a voltage value of Lo (L level) is applied to the gate in the RESS state. In the RESS state, a voltage having a voltage value VMPR is applied to the source. In the case of the cell in the selected state, in the RESS state, the Lo voltage is applied to the gate and the optical signal detection MOS transistor PDTr is turned off, so that the source and the drain become non-conductive, and the drain has a high impedance. (HiZ).

In the case of a non-selected cell, in the RESS state, a voltage having a voltage value of Lo (L level) is applied to the gate. When a cell is in a non-selected state and in a RESS state, the drain becomes HiZ.
In the “modulation (S)” state (hereinafter abbreviated as the LOADS state), in the case of a selected cell, a voltage having a voltage value of VCCSGHR is applied to the gate. In the case of a selected cell, a voltage having a voltage value of VCCSDR is applied to the drain, and a voltage having a voltage value of (VCCSGHR−VthS) is output to the source.
In the LOADS state, it is necessary to apply a bias voltage that satisfies the relationship (VCCSGHR <VCCSDR).

In the case of a non-selected cell, in the LOADS state, a voltage having a voltage value of Lo is applied to the gate, and a voltage having a voltage value of VCCSDR is applied to the drain.
Next, the case of the “preset” state (hereinafter abbreviated as the PR state) will be described.
In the case of the cell in the selected state, a voltage having a voltage value of VCCSGHR is applied to the gate in the PR state. In the PR state, a voltage whose voltage value is VCCVPS is applied to the source. In the case of the cell in the selected state, in the PR state, since the optical signal detection MOS transistor PDTr is turned on, the drain has the same voltage as the source.

  In the case of a non-selected cell, in the PR state, a voltage having a voltage value of Lo is applied to the gate, and the drain becomes VCCVPS. The line VSCi is at Lo level (= non-selected line) is turned on by T5, and each line is connected to the common node (COM node) and the COM node becomes HiZ.

  In the “clear” state (hereinafter abbreviated as the CL state), in the case of a selected cell, a voltage having a voltage value of (VCCCSDB × 2) is applied to the source, and the optical signal detection MOS transistor PDTr is turned on. Therefore, the drain has the same voltage as the source. As a result, a voltage having a voltage value of (VCCSGHR + VCCCSDB × 2) is applied to the gate.

In the case of a non-selected cell, in the CL state, a voltage having a voltage value of Lo is applied to the gate, and a voltage having a voltage value of VCCSDR is applied to the drain.
Next, the case of the “reset (N)” state (hereinafter abbreviated as the RESN state) will be described.
In the case of the cell in the selected state, in the RESN state, a voltage having a voltage value of Lo is applied to the gate. In the RESN state, a voltage whose voltage value is VMPR is applied to the source. In the case of a selected cell, the drain is HiZ when in the RESN state.

In the case of a non-selected cell, a voltage having a voltage value of Lo is applied to the gate in the RESN state. In the case of a non-selected cell, the drain is HiZ when in the RESN state.
Note that the NMOS transistor T5 of FIG. 6 is turned on during the period when the clear pulse signal CL is at the L level. Therefore, even in the RESS state, the NMOS transistor T5 is turned on and the drain is connected to the COM node. Since the read enable signal SDR2 becomes H level in the RESS state and the RESN state, the PMOS transistor T4 is turned off and the COM node becomes floating.

  In the “modulation (N)” state (hereinafter abbreviated as the LOADN state), in the case of a selected cell, a voltage having a voltage value of VCCSGHR is applied to the gate. In the LOADN state, a voltage whose voltage value is VCCSDR is applied to the drain, and a voltage whose voltage value is (VCCSGHR−VthN) is output to the source.

In the case of a non-selected cell, in the LOADN state, a voltage having a voltage value of Lo is applied to the gate, and a voltage having a voltage value of VCCSDR is applied to the drain.
Similar to the LOADS state, T5 in FIG. 6 is turned on also in LOADN, so that the drain is connected to the COM node (= HiZ).

  FIG. 9 is a diagram for explaining the readout line and the clear line of the sensor.

  As shown in FIG. 9, in the m × n pixel matrix, each line is scanned in order from the first line to the m-th line. The read line is a line from which a signal corresponding to the amount of light is read, and the clear line is a line from which charges accumulated in each cell are cleared. Since scanning is sequentially performed from the first line, a hole is generated in each cell of the line cleared based on the clear selection signal according to the amount of light received thereafter. The exposure time is the time until the read line selection signal VSBi is read after clearing. The exposure time is proportional to the number of lines dl between the readout line and the clear line, and the shutter speed setting, that is, the range from 1H (H is the number of horizontal lines; the same applies hereinafter) to mH (or (1 frame + 1H or more). However, it can be changed by setting.

FIG. 10 is a timing chart showing the timing of the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC.
The vertical synchronizing signal VSYNC is a timing pulse having a length of t2 generated every period t1. The horizontal synchronization signal HSYNC is a timing pulse having a length of t4, which is generated every period t3. The vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC are supplied from the timing generator 26 of the signal processing LSI 2 to the image sensor LSI 1.

  When the vertical synchronization signal VSYNC is supplied, the read line shift register 5 sequentially outputs the selection signal VSBi. The horizontal synchronization signal HSYNC is output by the number of lines (= m) of the sensor cell array 3 within the period t1 after the supply of the vertical synchronization signal VSYNC. In the period t4 during which the horizontal synchronization signal HSYNC is output and VGUP is L, there is a period during which the above-described signal component reading, clearing, and offset component reading operations are performed. The period during which VGUP is L is set to a predetermined period during the H blanking period. The H blanking period will be described in detail later with reference to FIG.

Analog signals VOUTS and VOUTN of n signal components and offset components are output in a period t5 after a period t4 in the period t3.
Next, the circuit configuration of the timing generator (hereinafter referred to as TG) 13 of the image sensor LSI 1 will be described with reference to FIG.
FIG. 11 is a circuit block diagram showing a configuration of the TG 13 of the image sensor LSI 1 of FIG.

  TG includes serial control block 71, master timing control block 72, sensor register block 73, shutter control unit (shutter speed upper limit control unit) 74, frame control unit 75, H / V counter 76, vertical scan control block 77, horizontal scan. A control block 78 and an analog control block 79 are included.

The serial control block 71 receives and inputs a 3-wire serial I / F signal that is an interface signal between the serial control block 71 and the register 14 of the signal processing LSI 2.
The master timing control block 72 receives the sensor drive clock SCLK, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC from the TG 26 of the signal processing LSI 2. In addition, the clock designation signal CLK_SEL from the signal processing LSI 2 and the standby signal STANDBY are input to the TG 13.

  The serial control block 71 inputs shutter speed setting data, regulator 8 setting data, system clock information, and the like written in the register 23 of the signal processing LSI 2 as serial I / F signals. The write address and write strobe signal WR are output and supplied to the sensor register block 73.

In response to the input signal, the sensor register block 73 includes a line shutter speed setting signal, a frame shutter speed setting signal, a frame mode setting signal, a clear pulse width control setting signal, a clear pulse application count setting signal, a gain setting signal, Outputs the regulator voltage setting signal.
On the other hand, the master timing control block 72 outputs a pixel clock, a horizontal reset pulse, a vertical reset pulse, and a reset signal based on the various input signals described above.

  The shutter control unit (shutter speed upper limit control unit) 74 receives a line shutter speed setting signal and a frame shutter speed setting signal from the sensor register block 73, and outputs line shutter speed data and frame shutter speed data as outputs.

The frame control unit 75 receives the pixel clock, vertical reset pulse and reset signal from the master timing control block 72 and the standby signal STANDBY, and outputs the frame count value, frame control data and valid (VALID) control. Output a signal.
The HV counter 76 receives the pixel clock, horizontal reset pulse, vertical reset pulse, and reset signal from the master timing control block 72, and outputs a line count value and a pixel count value as outputs.

  The vertical scan control block 77 has, as inputs, line shutter speed data and frame shutter speed data from the shutter control unit 74, frame count value, frame control data and valid (VALID) control signal from the frame control unit 75, Clear pulse width control setting signal and clear pulse application count setting signal from the sensor register block 73, pixel clock and reset signal from the master timing control block 72, clock designation signal CLK_SEL, line count from the H / V counter 76 A value and a pixel count value are input.

  The vertical scan control block 77 outputs clear line shift data AV, clear line shift clock VCLK_ASR, clear line shift register reset signal VSFRA_RST, clear line selection enable signal CLS, read line shift data BV, and read line shift. Output clock VCLK_BSR, read line shift register reset signal VSFRB_RST, read line selection enable signal VSM, all line selection signal VGUP during accumulation, accumulation enable signal SDI, read enable signal SDR, pre-clear gate preset signal PR, and clear pulse CL .

  The horizontal scan control block 78 has as inputs a valid (VALID) control signal from the frame control unit 75, a line count value and a pixel count value from the H / V counter 76, and a clear pulse from the sensor register block 73. A width control setting signal, a pixel clock and reset signal from the master timing control block 72, and a clock designation signal CLK_SEL are input.

  The horizontal scan control block 78 outputs line memory selection shift data AH, line memory selection shift clock CIN, line memory selection enable signal HSC_CK, storage signal line memory reset signal RESS, and storage signal line memory data load signal LOADS as outputs. , The offset line memory reset signal RESN and the offset line memory data load signal LOADN are output.

  The clock designation signal CLK_SEL is a signal indicating the frequency level of the system clock signal CLKIN. This CLK_SEL is supplied to the vertical scan control block 77 and the horizontal scan control block 78. The control blocks 77 and 78 can control the output timing of various sensor drive signals output from the blocks 77 and 78 according to the H and L levels of the clock designation signal CLK_SEL.

  The analog control block 79 includes a valid (VALID) control signal from the frame control unit 75, a line count value and a pixel count value from the H / V counter 76, a gain setting signal from the sensor register block 73, and a standby signal. STANDBY is input, and an analog amplifier gain control signal, amplifier drive clock CDL, and standby control signal are output as outputs.

A valid (VALID) control signal from the frame control unit 75 is output from the TG 13 to the signal processing LSI 2 as a VALID signal.
The regulator voltage setting signal from the sensor register block 73 and the standby control signal from the analog control block 79 are input to the sensor drive bias generation regulator 8 of the image sensor LSI 1 in FIG.

  The analog amplifier gain control signal and the amplifier drive clock CDL from the analog control block 79 become control signals for the output amplifier 12 of the image sensor LSI 1 in FIG.

  FIG. 12 is a timing chart showing signals for controlling photoelectric conversion of the sensor cell array 3. The sensor cell array 3 repeats each state of “accumulation”, “reset (S)”, “modulation (S)”, “preset”, “clear”, “reset (N)”, and “modulation (N)”. The optical image is converted into an electrical signal and output. FIG. 12 shows the state of signals in each of these states. The sensor cell array 3 operates at a predetermined frame rate with the vertical synchronization signal VSNYC and the horizontal synchronization signal HSYNC in FIG. 10 as unit time.

  In the example of FIG. 12, in a certain line count signal ROWCT, HSYNC is an L level from 1 to 80 for the pixel clock signal PXLCT, and LOADS (reset (S) + modulation (S)) is from 5 to 22 for PXLCT. In the state, PXLCT from 27 to 44 is assigned to the CL (preset + clear) state, and PXLCT from 45 to 63 is assigned to the LOADN (reset (N) + modulation (N)) state.

  Each control signal is generated and output by the TG 13. The TG 13 is configured by a logic circuit. The logic circuit can be automatically designed by using a design system using HDL (Hardware Description Language) such as Verilog-HDL and VHDL.

First, the accumulation state will be described.
A period other than the predetermined period (the fifth pixel to the 63rd pixel in FIG. 12) in the H blanking period shown in FIG. 10 is the accumulation period. During the accumulation period, all the pixels are in the accumulation state. During this period, all line selection signal VGUP during accumulation is at H level, and accumulation enable signal SDI and clear pulse signal CL are at L level. As shown in FIG. 4, as shown in Table 1 above, the operation of the drain / gate voltage supply circuit VC1i is performed when all the line selection signals VGUP at the time of accumulation become H level and all the line selection signals VSCi become H level. The gate voltage VPGi becomes VCCSGHI. Further, the drain voltage VPDi becomes the voltage VCCSDI. Further, during this period, the pre-clear gate preset signal PR is also at the L level, and the source voltage supply circuit VC2h does not supply the source voltage as shown in Table 2 showing the operation of the source voltage supply circuit VC2h. In this case, the optical signal detection MOS transistor PDTr is turned on and the source of all cells in the cell array matches the drain voltage.

  At the fifth pixel in the H blanking period, the accumulation period ends and signal readout is started. In the period for reading signals (LOADS, CL, and LOADN periods), hole accumulation based on the amount of received light is continued, but each cell is set to a setting value different from the accumulation period. In the period for signal readout, each cell is set to an individual set value in the clear line, readout line, or non-selected line.

First, the reset (s) state will be described. As shown in FIG. 12, common settings are made for all cells even during this period.
As shown in FIG. 12, the clear pulse signal CL and the pre-clear gate preset signal PR are at the L level, and the source voltage supply circuit VC2h does not supply the source voltage. During this period, the accumulated signal line memory reset signal RESS is active high, the switch SW22 in FIG. 4 is turned on, and the terminal voltage of the capacitor C2 constituting the line memory is charged to VMPR. Further, the storage signal line memory data load signal LOADS and the line memory data load signal LOAD also become high active, the switches SW21 and SW11 are turned on, and the source line is initialized with the voltage VMPR.

  On the other hand, during storage, all line selection signals VGUP change from H to L, and all line selection signals VSCi change to L level. Therefore, as shown in Table 1, all the gate voltages VPSGi are at the L (GND) level. Further, since the accumulation enable signal SDI is at the H level and SDR2 is also at the H level, as shown in Table 1, since T5 in FIG. 6 is turned on, the drains of all the cells are commonly connected ( COM node), the COM node is in the Hiz state.

Next, the modulation (s) state will be described.
As shown in FIG. 12, CL and PR maintain L level, and the source voltage supply circuit VC2h does not supply voltage to the source line. An output corresponding to the voltage value set for each cell is output via the source line. That is, for the clear line and the non-selected line, the line selection signal VSCi remains at the L level, and the gate voltage is at the L (GND) level. Further, since the read enable signal SDR2 is also at the L level, the drain voltage VPDi becomes VCCSDR.

  For the read line, the line selection signal VSCi is at the H level. Since the clear pulse signal CL and the signal SDR are at the L level, the gate voltage VPGi is VCCSGHR. The drain voltage VPDi is VCCSDR. As a result, a voltage (VCCSGHR−VthS) appears in the source voltage VPSi. Note that VthS varies depending on the accumulated holes. The source line voltage (VCCSGHR-VthS) is stored in each capacitor C2 constituting the line memory via the switch SW21.

Next, for the correlated double sampling process, a CL state for removing (clearing) holes accumulated in each cell of the readout line is set. In order to remove holes, it is necessary to apply a very high voltage to the gate. A preset state is set before the clear state, and a high voltage is obtained using a voltage doubler circuit.
Note that each cell of the clear line is cleared simultaneously with the clearing of the read line.

  First, in the preset state, the line selection signal VSCi is at the H level for the read line and the clear line. Since the clear pulse signal CL and the signal SDR are at the L level, the gate voltage VPGi is VCCSGHR. For the non-selected line, since the line selection signal VSCi is at L level, the gate voltage is at L (GND) level.

  Further, since the clear pulse signal CL is at L level and the pre-clear gate preset signal PR is H, as shown in Table 2, the voltages VPSh of all the source lines are reset to the voltage VCCVPS (for example, 0 V). 7 is charged with the voltage VCCSDB, and the point ND2 becomes the voltage VCCSDB. Since the accumulation enable signal SDI and the read enable signal SDR2 are at the H level, the optical signal detection MOS transistor PDTr is turned on at the drain, and becomes the same potential as the source.

  Next, in the clear state, the pre-clear gate preset signal PR changes from H level to L level, and the clear pulse signal CL changes from L level to H level. In this case, as shown in Table 2, the source line changes to the voltage VCCCSDB × 2. For the readout line and the clear line, the clear pulse signal CL and the line selection signal VSCi are at the H level, so that the gates are in a floating state as shown in Table 1. Therefore, the gate voltage VPGi becomes (VCCCSDB × 2 + VCCSGHR) due to the coupling capacitance between the source and the gate. Similarly to the preset state, the drain has the same potential as the source when the optical signal detection MOS transistor PDTr is turned on.

  On the other hand, for the non-selected line, the gate voltage VPGI remains at L (GND) level, and the drain voltage VPDi becomes VCCSDR because the transistor T4 is turned on.

  Next, the state shifts to the modulation (N) state through the reset (N) state. In these reset (N) state and modulation (N) state, substantially the same signals as the reset (s) state and modulation (s) state are set, respectively. That is, in the reset (N) state, the offset line memory reset signal RESN and the offset line memory data load signal LOADN are high instead of the accumulated signal line memory reset signal RESS and the accumulated signal line memory data load signal LOADS, respectively. Become active. As a result, the switch SW32 is turned on, and the capacitor C3 constituting the noise reading line memory is charged to the VMPR. Further, the switch SW31 and the switch SW11 are turned on, and the source line is initialized with the voltage VMPR.

  In the modulation (N) state, the clear pulse signal CL and the pre-clear gate preset signal PR are at the L level, and the source voltage supply circuit VC2h does not supply a voltage to the source line. For the clear line and the non-selected line, the line selection signal VSCi is at the L level, and the gate voltage VPGi is L (GND). Further, since the read enable signal SDR2 is also at the L level, the drain voltage VPDi becomes VCCSDR.

  For the read line, the line selection signal VSCi is at the H level. Since the clear pulse signal CL and the signal SDR are at the L level, the gate voltage VPGi is VCCSGHR. The drain voltage VPDi is VCCSDR. As a result, a voltage (VCCSGHR−VthN) appears in the source voltage VPSh. Since the voltage appearing at the source is set to the clear state immediately before, the voltage corresponds to the offset component. The source line voltage (VCCSGHR-VthN) is stored in each capacitor C3 constituting the line memory via the switch SW31.

  Thus, the signal component is accumulated in the capacitor C2, and the offset component is accumulated in the capacitor C3. When the switches SW23 and SW33 are sequentially turned on by the selection signal HSCANh from the horizontal shift register 11, the voltages stored in the capacitors C2 and C3 are output as VOUTS and VOUTN via the output amplifiers 36 and 38, respectively. .

Next, shift register circuits applicable to the clear line shift register 4, the read line shift register 5, and the horizontal shift register 11 will be described.
In FIG. 1, the shift register circuit is configured by cascading a plurality of DFFs 81 (four stages of DFFs 81-1 to DFF81-4 in FIG. 1). Obviously, the number of stages is not limited to four. The DFF 81 has a data terminal D to which data is input, a clock terminal CK1 to which a clock CK1 is input, a clock terminal XCK1 to which an inverted clock XCK1 is input, and a reset terminal XR to which a reset signal XR is input. Furthermore, the DFF 81 in this embodiment also has a clock end CK2 to which the clock CK2 is input and a clock end XCK2 to which the inverted clock XCK2 is input.

  The DFF 81 captures and holds the data input to the data terminal D in synchronization with the clocks CK1 and XCK1, transfers the captured data to the output side in synchronization with the clocks CK2 and XCK2, holds the data, and outputs The signals are output from the ends Q and Q1. The DFF 81 can reliably insert a hold period, which is a time for holding data, between a setup period for taking in data and preparing for transfer and an output period for transferring and holding the data. It can be done.

  Input data Din is given to the data end of the first stage DFF 81-1. The output terminal Q of each stage DFF 81 is connected to the data terminal D of the next stage DFF 81, and each stage DFF 81 outputs a selection signal of each stage from each output terminal Q 1.

FIG. 2 shows a specific configuration of such a DFF 81.
The input side transfer gates are constituted by the input side MOS transistors T21 and T22 connected to the complementary. The common input terminals of the transistors T21 and T22 are connected to the data terminal D, and the common output terminal is connected to the output terminal of the inverter I21 and one input terminal of the NAND circuit N21. The clock CK1 is supplied to the gate of the Pch transistor T21, and the clock XCK1 is supplied to the gate of the Nch transistor T22. A reset signal XR is applied to the other input terminal of the NAND circuit N21. The transistors T21 and T22 are turned on at L of the clock CK1 (H of the clock XCK1) and take in the data input to the data terminal D.

  An output side transfer gate is constituted by the output side MOS transistors T31 and T32 connected to the complementary. The common input terminals of the transistors T31 and T32 are connected to the input terminal of the inverter I21 and the output terminal of the NAND circuit N21, and the common output terminal is connected to the input terminals of the inverters I31 and I32 and the output terminal of the NAND circuit N31. The output terminal of the inverter I31 is connected to one input terminal of the NAND circuit N31 and also to the output terminal Q. The output terminal of the inverter I32 is connected to the output terminal Q1. A reset signal XR is applied to the other input terminal of the NAND circuit N31.

  The inverted clock XCK2 is supplied to the gate of the Pch transistor T31, and the clock CK2 is supplied to the gate of the Nch transistor T32. The transistors T31 and T32 are turned on at H of the clock CK2 (L of the clock XCK2) and take in data at the output terminal of the NAND circuit N21.

  The NAND circuits N21 and N31 invert the data of one input terminal by being supplied with the H reset signal XR to the other input terminal, and the output terminal by supplying the L reset signal XR to the other input terminal. Reset to H.

  FIG. 3 is a circuit diagram showing a specific configuration of a shift clock generation circuit that generates the clocks CK1, XCK1, CK2, and XCK2 of FIGS.

  A predetermined clock CLKin is input to the inverter I41. The output terminal of the inverter I41 is connected to one input terminal of the NAND circuit N41, and is connected to one input terminal of the NAND circuit N42 via the inverter I42. The output terminal of NAND circuit N41 is connected to the other input terminal of NAND circuit N42 via inverters I45 and I46, and the output terminal of NAND circuit N42 is connected to the other input terminal of NAND circuit N41 via inverters I47 and I48. . Outputs from the output terminals of the NAND circuits N41 and N42 are output as outputs DCLXOUT and DCLOUT via inverters I43 and I44, respectively.

  The output terminal of the inverter I43 is connected to the output terminal XCK1 through the buffers A1 and A2, and is connected to one input terminal of the NAND circuit N43. The output terminal of the inverter I44 is connected to the output terminal CK2 via the buffers A3 and A4, and is connected to one input terminal of the NAND circuit N44. A signal SFR_P for determining whether or not to use the Pch gate is applied to the other input terminals of the NAND circuits N43 and N44. Output terminals of NAND circuits N43 and N44 are connected to output terminals CK1 and XCK2 via buffers A5 and A6, respectively.

  Next, the operation of the shift register circuit configured as described above will be described with reference to the timing chart of FIG. FIG. 13 shows clocks CK1, XCK1, CK2, and XCK2 generated by the shift clock generation circuit.

  In FIG. 3, it is assumed that the clock CLKin is at the H level for a predetermined period. In this case, one input terminal of the NAND circuit N41 is at L level, and its output is always at H level. One input terminal of the NAND circuit N42 is at H level, and the other input terminal is at H level by the output of the NAND circuit N41. Accordingly, the other input terminal of the NAND circuit N41 is at the L level due to the output of the NAND circuit N41. That is, in the NAND circuit N41, both the two inputs are at the L level and the output is at the H level. On the other hand, the NAND circuit N42 has both two inputs at the H level and the output at the L level. As a result, DCLXOUT is at L level and DCLOUT is at H level.

  Here, it is assumed that the clock CLKin changes from H to L level. As a result, one input terminal of the NAND circuit N41 changes to H, and one input terminal of the NAND circuit N42 changes to L level. Immediately after the input changes, the output of the NAND circuit N42 switches from L to H, but the output of the NAND circuit N41 remains H. The output H of the NAND circuit N42 is delayed by the inverters I47 and I48 and supplied to the other input terminal of the NAND circuit N41, and the output of the NAND circuit N41 is switched from H to L level. That is, DCLXOUT changes from L to H after a predetermined time delay after DCLOUT changes from H to L level.

  Next, it is assumed that the clock CLKin changes from L to H. As a result, one input terminal of the NAND circuit N41 changes to L level, and one input terminal of the NAND circuit N42 changes to H. Immediately after the input changes, the output of the NAND circuit N41 switches from L to H, but the output of the NAND circuit N42 remains H. The output H of the NAND circuit N41 is delayed by the inverters I45 and I46 and supplied to the other input terminal of the NAND circuit N42, and the output of the NAND circuit N42 is switched from H to L level. That is, DCLOUT changes from L to H after a predetermined time delay after DCLXOUT changes from H to L level.

  Thereafter, the same operation is repeated. For example, assuming that the duty of the input clock CLKin is 50%, DCLOUT and DCLXOUT are signals in which the timing of transition from L to H is always delayed from the timing of transition from H to L level. That is, DCLOUT and DCLXOUT are signals whose falling timing is substantially synchronized with the falling and falling of the input clock CLKin, and whose rising timing is delayed from the falling and falling of the input clock CLKin.

DCLOUT and DCLXOUT are output as the clock CK2 or the inverted clock XCK1 via the buffers A1 and A2 or the buffers A3 and A4, respectively.
As is clear from the comparison of the clocks CK2 and XCK1 in FIG. 13, these clocks are signals whose rising timings are delayed from each other's falling timings.
As a result, the two-phase clocks CK2 and XCK1 have an L period longer than the H period, and the H period is reliably terminated within the mutual L period.

  NAND circuits N43 and N44 invert and output the signal inputted with the H level of signal SFR_P. That is, when the signal SFR_P is H, DCLOUT and DCLXOUT are inverted by the NAND circuits N44 and N43 and output as the clocks XCK2 and CK1 via the buffers A6 and A5, respectively. That is, the clocks CK1 and XCK2 are inverted signals of the clocks XCK1 and CK2, respectively.

  It is also possible to use only Nch transistors T22 and T32 among the input side transfer gate constituted by the transistors T21 and T22 and the output side transfer gate constituted by the transistors T31 and T32 in FIG. In this case, the clocks CK1 and XCK2 supplied to the Pch side transistors T21 and T31 are not necessary. Therefore, the signal SFR_P is set to L level. Thereby, the shift clock generation circuit of FIG. 3 does not need to generate the clocks CK1 and XCK2, and the generation of noise can be further suppressed.

  The clocks CK1, XCK1, CK2, and XCK2 shown in FIG. 13 are supplied to the transistors T21, T22, T32, and T31 of each shift register circuit constituting the DFF 81, respectively. The input-side transfer gate composed of the transistors T21 and T22 is turned on during the L period of CK1 (H period of XCK1) in FIG. The fetched data is supplied to the inverter I21 via the NAND circuit N21 and further supplied to the NAND circuit N21. Then, the transistors T31 and T32 constituting the output side transfer gate are turned on when the clock CK2 becomes H (XCK2 is L), and the output of the NAND circuit N21 is supplied to the output side inverters I31 and I32. .

  In this embodiment, since the clock CK1 is set to H (XCK1 is set to L) before the clock CK2 is set to H (SCK2 is set to L) by the shift clock generation circuit, the setup is performed by turning on the input-side transfer gate. Between the period and the transfer period by the output-side transfer gate, the data hold period by the input-side inverter I21 and the NAND circuit N21 is reliably set.

  That is, as shown in FIG. 13, after the clock CK1 becomes H (XCK1 is L) and the input-side transfer gate is surely turned off, the clock CK2 becomes H (XCK2 is L). As a result, the output-side transfer gate is turned on, and the data held in the inverter I21 and the NAND circuit N21 is transferred to the output side. During the ON period of the output side transfer gate, the data transferred to the output side is held in the inverter I31 and the NAND circuit N31 and is output via the inverter I32. The output of the inverter I31 is supplied as the Q output to the data terminal D of the next stage DFF.

  1 sequentially outputs the selection signal from the output terminal Q1 at the clock cycle of the clock CK2, that is, the clock cycle of the clock CLKin from each of the DFFs 81-1, 81-2,.

  As described above, in this embodiment, by using a two-phase clock, that is, a clock for controlling on / off of the input-side transfer gate and a clock for controlling on / off of the output-side transfer gate, as the shift clock, the input is performed. The on-period of the transfer gate on the side does not overlap the on-period of the output transfer gate. As a result, it is possible to prevent the fetched data from being sequentially transferred to the shift register at each stage regardless of the shift clock due to the missing data cylinder.

  Further, in the present embodiment, it is not necessary to make the switching of the first and second shift clocks steep in order to prevent data loss. Therefore, it is not necessary to increase the driving force of the clock driver in order to make the switching of the shift clock steep, and it is possible to prevent an increase in noise caused by this and prevent an increase in noise mixing.

FIG. 14 is a circuit diagram showing a modification of the first embodiment.
The DFF in FIG. 2 can reset the circuit by a reset signal XR. On the other hand, the present invention can also be applied to a DFF that does not have a reset mechanism. FIG. 14 is obtained by removing the reset mechanism.

  That is, it differs from the DFF of FIG. 2 in that inverters I35 and I36 are employed in place of the NAND circuits N21 and N31, respectively. That is, the input terminal of the inverter I35 is connected to the output terminal of the input side transfer gate, and the data that has passed through the input side transfer gate is output to the inverter I21. The output terminal of the inverter I36 is connected to the output terminal of the output side transfer gate, and the output of the inverter I31 is given to output the inverted signal to the inverter I31.

  Even in such a configuration, it is possible to prevent the input-side transfer gate and the output-side transfer gate from being turned on at the same time, and prevent data from being missed without steep switching of the shift clock, thereby introducing noise. Therefore, it is possible to generate an accurate selection signal output while preventing an increase in the number of signals.

  15 and 16 show a second embodiment of the present invention. FIG. 15 is a circuit diagram showing a shift register circuit according to the second embodiment, and FIG. 16 is a circuit diagram showing a specific configuration of the DFF in FIG.

In FIG. 15 and FIG. 16, the same components as those in FIG. 1 and FIG.
FIG. 15 shows a DFF reset mechanism using a NOR circuit. 15 differs from FIG. 1 in that each DFF 85 has a reset terminal R instead of the reset terminal XR. 16 is different from the DFF of FIG. 2 in that NOR circuits NR1 and NR2 are used instead of the NAND circuits N21 and N31, respectively, and an inverter I38 is added.

  The NOR circuits NR1 and NR2 receive the L reset signal R at the other input terminal, invert the output of the input side transfer gate input at one input terminal, and the H reset signal XR at the other input terminal. Is supplied, the output terminal is reset to the L level. Inverter I38 inverts and outputs the output of inverter I31.

  Even in the shift register circuit configured in this way, in each DFF, it is possible to prevent the input-side transfer gate and the output-side transfer gate from being turned on at the same time, and data can be transferred without steep switching of the shift clock. It is possible to prevent the cylinder from coming off and generate an accurate selection signal output from each stage while preventing an increase in noise mixing.

  FIG. 17 shows a timing chart when the shift register circuit of FIG. 1 or FIG. 15 is applied to the horizontal shift register 11 of FIG.

  The shift clock generation circuit of FIG. 3 receives a line memory selection shift clock CIN2 as an input clock CLKin. As described above, the falling timing of the clock CK2 and the clock XCK1 from the shift clock generating circuit is substantially synchronized with the falling and falling of the input clock CLKin, and the rising timing is delayed from the falling and falling of the input clock CLKin. Signal. Clocks XCK2 and CK1 are inverted signals of clocks CK2 and XCK1, respectively. In this way, clocks CK1, XCK1, CK2, and XCK2 shown in FIG. 17 are obtained.

The first stage DFF 81-1 or 85-1 receives the line memory selection shift data AH as the input Din. The shift data AH passes through the input side transfer gate of the first stage DFF during the L period of the clock CK1 (H period of XCK1).
After the input side transfer gate is turned off, the output side transfer gate is turned on, and the shift data AH is transferred to the output side and output as the output AH1 of the first stage DFF.

Further, the output AH1 is taken in the next L period of the clock CK1 (H period of XCK1) via the input side transfer gate of the DFF 81-2 or 85-2 at the next stage.
Further, after the L period of the clock CK1 (H period of XCK1) ends, it is transferred to the output side via the output side transfer gate by the clock CK2 which becomes H level, and is output from the next stage DFF as the output AH2. Thereafter, the same operation is repeated, and the selection signal output of each stage is obtained from the DFF of each stage.

  As described above, the line memory selection shift data AH is accurately transferred at each stage in accordance with the clock CIN2 without causing data loss even if the shift clock is not sharply switched.

  18 shows a timing chart when the shift register circuit of FIG. 1 or FIG. 15 is applied to vertical shift registers such as the clear line shift register 4 and the read line shift register 5 of FIG.

  The shift clock generation circuit of FIG. 3 receives the read line shift clock VCLK_BSR as the clock CLKin. In this case, clocks CK1, XCK1, CK2, and XCK2 shown in FIG. 18 are obtained by the shift clock generation circuit.

  Read line shift data BV is input as input Din to DFF 81-1 or 85-1. This shift data BV passes through the input side transfer gate of the first stage DFF during the L period of the clock CK1 (H period of XCK1). After the input side transfer gate is turned off, it is transferred by the output side transfer gate and output as the output VSB1 of the first stage DFF.

  Furthermore, VSB1 is taken in via the input side transfer gate of the DFF in the next stage in the next L period of clock CK1 (H period of XCK1). Further, after the L period of the clock CK1 (H period of XCK1) ends, it is transferred to the output side via the output side transfer gate by the clock CK2 that becomes H level, and is output from the next stage DFF as the output VSB2. Thereafter, the same operation is repeated, and the selection signal output of each stage is obtained from the DFF of each stage.

In this way, the read line shift clock VCLK_BSR is accurately transferred at each stage in accordance with the clock CIN2 without causing data loss. Moreover, noise contamination does not increase.
In the above embodiment, the MOS image sensor of the threshold voltage modulation system is described as an example of the solid-state imaging device, but the present invention is not limited to the MOS image sensor of the threshold voltage modulation system, and an image of another system is used. Needless to say, the sensor can also be applied.

1 is a circuit diagram showing a shift register circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a specific configuration of a DFF in FIG. 1. FIG. 2 is a circuit diagram showing a shift clock generation circuit that supplies a shift clock to the shift register circuit of FIG. 1. FIG. 2 is a circuit diagram showing an image sensor LSI using the shift register circuit of FIG. 1. FIG. 5 is a block diagram showing an image processing apparatus in which the image sensor of FIG. 4 is incorporated. The circuit diagram which shows the structure of the drain gate voltage supply circuit concerning embodiment of this invention. The circuit diagram which shows the structure of the source voltage supply circuit concerning embodiment of this invention. The figure for demonstrating the bias voltage applied to the sensor cell concerning embodiment of this invention. The figure for demonstrating the read-out line and clear line of a sensor concerning embodiment of this invention. 3 is a timing chart showing timings of a vertical synchronizing signal and a horizontal synchronizing signal according to the embodiment of the present invention. 1 is a circuit block diagram showing a configuration of a timing generator of an image sensor LSI according to an embodiment of the present invention. The timing chart for demonstrating the state of each signal in each state in the H blanking period concerning embodiment of this invention. 6 is a timing chart for explaining the operation of the first embodiment. The circuit diagram which shows the modification of 1st Embodiment. A circuit diagram showing a shift register circuit of a 2nd embodiment. The circuit diagram which shows the specific structure of DFF in FIG. The timing chart at the time of applying the shift register circuit of FIG. 1 or FIG. 15 to the horizontal shift register 11 of FIG. 16 is a timing chart when the shift register circuit of FIG. 1 or FIG. 15 is applied to vertical shift registers such as the clear line shift register 4 and the read line shift register 5 of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Image sensor LSI, 2 ... Signal processing LSI, 3 ... Sensor cell array, 6 ... Vertical drive circuit, 9 ... Line memory for accumulation signals, 10 ... Line memory for offset signals, 13 ... Timing generator, 81-1 to 81- 4 ... DFF, T21, T22, T31, T32 ... transistor, I21, I31, I32 ... inverter, N21, N31 ... NAND circuit.

Claims (7)

First means for generating a first shift clock synchronized with an input clock;
And a second means for generating a second shift clock having a phase different from that of the first shift clock.   2. The shift clock circuit according to claim 1, wherein the first shift clock and the second shift clock do not change in logic level at the same time.   2. The first and second shift clocks according to claim 1, wherein one shift clock ends a logic level period of one polarity within a period in which one shift clock is a logic level of the other polarity. Shift clock generation circuit. A first means for inputting a first clock signal and outputting a first shift clock;
After the first clock signal changes from the first level to the second level, a second clock signal that changes from the second level to the first level is input after a lapse of a predetermined time, A second means for outputting two shift clocks;
Third means for inputting the first clock signal and the first signal;
A fourth means for inputting the second clock signal and the first signal;
Including
If the first signal is active,
The third means outputs a third shift clock which is an inverted signal of the first shift clock;
The fourth means outputs a fourth shift clock which is an inverted signal of the second shift clock;
If the first signal is inactive,
The shift clock generation circuit, wherein the third means and the fourth means output a third level signal. A shift clock generation circuit according to any one of claims 1 to 4,
Including a plurality of data transfer elements connected in cascade, and a shift register circuit to which the first shift clock and the second shift clock are supplied to each of the plurality of data transfer elements. An image processing apparatus. Each of the plurality of data transfer elements includes:
An input-side transfer gate which is controlled by the first shift clock and inputs data to the data transfer element when turned on;
6. The image processing apparatus according to claim 5, further comprising: an output-side transfer gate that is controlled by the second shift clock and outputs data from the data transfer element when turned on. The input-side transfer gate is
A first Pch transistor controlled by the first shift clock;
A first Nch transistor controlled by the third shift clock,
The output side transfer gate is:
A second Pch transistor controlled by the second shift clock;
The image processing apparatus according to claim 6, further comprising: a second Nch transistor controlled by the fourth shift clock.

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